| blob | 44000b9925574990e43fa2305bfc2df6eb47e251 |
1 /* Target-dependent code for the IA-64 for GDB, the GNU debugger.
3 Copyright (C) 1999-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
43 #ifdef HAVE_LIBUNWIND_IA64_H
47 /* Note: KERNEL_START is supposed to be an address which is not going
48 to ever contain any valid unwind info. For ia64 linux, the choice
49 of 0xc000000000000000 is fairly safe since that's uncached space.
51 We use KERNEL_START as follows: after obtaining the kernel's
52 unwind table via getunwind(), we project its unwind data into
53 address-range KERNEL_START-(KERNEL_START+ktab_size) and then
54 when ia64_access_mem() sees a memory access to this
55 address-range, we redirect it to ktab instead.
57 None of this hackery is needed with a modern kernel/libcs
58 which uses the kernel virtual DSO to provide access to the
59 kernel's unwind info. In that case, ktab_size remains 0 and
60 hence the value of KERNEL_START doesn't matter. */
62 #define KERNEL_START 0xc000000000000000ULL
65 struct ia64_table_entry
66 {
70 };
74 #endif
76 /* An enumeration of the different IA-64 instruction types. */
79 {
87 undefined /* undefined or reserved */
90 /* We represent IA-64 PC addresses as the value of the instruction
91 pointer or'd with some bit combination in the low nibble which
92 represents the slot number in the bundle addressed by the
93 instruction pointer. The problem is that the Linux kernel
94 multiplies its slot numbers (for exceptions) by one while the
95 disassembler multiplies its slot numbers by 6. In addition, I've
96 heard it said that the simulator uses 1 as the multiplier.
98 I've fixed the disassembler so that the bytes_per_line field will
99 be the slot multiplier. If bytes_per_line comes in as zero, it
100 is set to six (which is how it was set up initially). -- objdump
101 displays pretty disassembly dumps with this value. For our purposes,
102 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
103 never want to also display the raw bytes the way objdump does. */
105 #define SLOT_MULTIPLIER 1
107 /* Length in bytes of an instruction bundle. */
109 #define BUNDLE_LEN 16
111 /* See the saved memory layout comment for ia64_memory_insert_breakpoint. */
113 #if BREAKPOINT_MAX < BUNDLE_LEN - 2
115 #endif
125 CORE_ADDR faddr);
127 #define NUM_IA64_RAW_REGS 462
133 /* NOTE: we treat the register stack registers r32-r127 as
134 pseudo-registers because they may not be accessible via the ptrace
135 register get/set interfaces. */
143 /* Array of register names; There should be ia64_num_regs strings in
144 the initializer. */
253 };
255 struct ia64_frame_cache
256 {
267 cfm value). */
268 CORE_ADDR after_prologue;
269 /* Address of first instruction after the last
270 prologue instruction; Note that there may
271 be instructions from the function's body
272 intermingled with the prologue. */
274 /* Size of the memory stack frame (may be zero),
275 or -1 if it has not been determined yet. */
277 for this frame. 0 if no register is being used
278 as the frame pointer. */
280 /* Saved registers. */
283 };
285 static int
287 {
289 }
292 {
295 };
298 {
301 };
304 {
306 &floatformat_ia64_ext_little
307 };
311 {
315 tdep->ia64_ext_type
317 floatformats_ia64_ext);
320 }
322 static int
325 {
343 }
347 {
349 }
353 {
356 else
358 }
360 static int
362 {
366 }
369 /* Extract ``len'' bits from an instruction bundle starting at
370 bit ``from''. */
372 static long long
374 {
391 {
394 }
397 {
401 }
404 }
406 /* Replace the specified bits in an instruction bundle. */
408 static void
410 {
418 {
427 }
428 else
429 {
438 {
442 }
445 {
451 }
452 }
453 }
455 /* Return the contents of slot N (for N = 0, 1, or 2) in
456 and instruction bundle. */
458 static long long
460 {
462 }
464 /* Store an instruction in an instruction bundle. */
466 static void
468 {
470 }
473 {
506 };
508 /* Fetch and (partially) decode an instruction at ADDR and return the
509 address of the next instruction to fetch. */
511 static CORE_ADDR
513 {
519 /* Warn about slot numbers greater than 2. We used to generate
520 an error here on the assumption that the user entered an invalid
521 address. But, sometimes GDB itself requests an invalid address.
522 This can (easily) happen when execution stops in a function for
523 which there are no symbols. The prologue scanner will attempt to
524 find the beginning of the function - if the nearest symbol
525 happens to not be aligned on a bundle boundary (16 bytes), the
526 resulting starting address will cause GDB to think that the slot
527 number is too large.
529 So we warn about it and set the slot number to zero. It is
530 not necessarily a fatal condition, particularly if debugging
531 at the assembly language level. */
533 {
537 }
552 else
556 }
558 /* There are 5 different break instructions (break.i, break.b,
559 break.m, break.f, and break.x), but they all have the same
560 encoding. (The five bit template in the low five bits of the
561 instruction bundle distinguishes one from another.)
563 The runtime architecture manual specifies that break instructions
564 used for debugging purposes must have the upper two bits of the 21
565 bit immediate set to a 0 and a 1 respectively. A breakpoint
566 instruction encodes the most significant bit of its 21 bit
567 immediate at bit 36 of the 41 bit instruction. The penultimate msb
568 is at bit 25 which leads to the pattern below.
570 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
571 it turns out that 0x80000 was used as the syscall break in the early
572 simulators. So I changed the pattern slightly to do "break.i 0x080001"
573 instead. But that didn't work either (I later found out that this
574 pattern was used by the simulator that I was using.) So I ended up
575 using the pattern seen below.
577 SHADOW_CONTENTS has byte-based addressing (PLACED_ADDRESS and SHADOW_LEN)
578 while we need bit-based addressing as the instructions length is 41 bits and
579 we must not modify/corrupt the adjacent slots in the same bundle.
580 Fortunately we may store larger memory incl. the adjacent bits with the
581 original memory content (not the possibly already stored breakpoints there).
582 We need to be careful in ia64_memory_remove_breakpoint to always restore
583 only the specific bits of this instruction ignoring any adjacent stored
584 bits.
586 We use the original addressing with the low nibble in the range <0..2> which
587 gets incorrectly interpreted by generic non-ia64 breakpoint_restore_shadows
588 as the direct byte offset of SHADOW_CONTENTS. We store whole BUNDLE_LEN
589 bytes just without these two possibly skipped bytes to not to exceed to the
590 next bundle.
592 If we would like to store the whole bundle to SHADOW_CONTENTS we would have
593 to store already the base address (`address & ~0x0f') into PLACED_ADDRESS.
594 In such case there is no other place where to store
595 SLOTNUM (`adress & 0x0f', value in the range <0..2>). We need to know
596 SLOTNUM in ia64_memory_remove_breakpoint.
598 There is one special case where we need to be extra careful:
599 L-X instructions, which are instructions that occupy 2 slots
600 (The L part is always in slot 1, and the X part is always in
601 slot 2). We must refuse to insert breakpoints for an address
602 that points at slot 2 of a bundle where an L-X instruction is
603 present, since there is logically no instruction at that address.
604 However, to make things more interesting, the opcode of L-X
605 instructions is located in slot 2. This means that, to insert
606 a breakpoint at an address that points to slot 1, we actually
607 need to write the breakpoint in slot 2! Slot 1 is actually
608 the extended operand, so writing the breakpoint there would not
609 have the desired effect. Another side-effect of this issue
610 is that we need to make sure that the shadow contents buffer
611 does save byte 15 of our instruction bundle (this is the tail
612 end of slot 2, which wouldn't be saved if we were to insert
613 the breakpoint in slot 1).
615 ia64 16-byte bundle layout:
616 | 5 bits | slot 0 with 41 bits | slot 1 with 41 bits | slot 2 with 41 bits |
618 The current addressing used by the code below:
619 original PC placed_address placed_size required covered
620 == bp_tgt->shadow_len reqd \subset covered
621 0xABCDE0 0xABCDE0 0x10 <0x0...0x5> <0x0..0xF>
622 0xABCDE1 0xABCDE1 0xF <0x5...0xA> <0x1..0xF>
623 0xABCDE2 0xABCDE2 0xE <0xA...0xF> <0x2..0xF>
625 L-X instructions are treated a little specially, as explained above:
626 0xABCDE1 0xABCDE1 0xF <0xA...0xF> <0x1..0xF>
628 `objdump -d' and some other tools show a bit unjustified offsets:
629 original PC byte where starts the instruction objdump offset
630 0xABCDE0 0xABCDE0 0xABCDE0
631 0xABCDE1 0xABCDE5 0xABCDE6
632 0xABCDE2 0xABCDEA 0xABCDEC
633 */
635 #define IA64_BREAKPOINT 0x00003333300LL
637 static int
640 {
654 /* Enable the automatic memory restoration from breakpoints while
655 we read our instruction bundle for the purpose of SHADOW_CONTENTS.
656 Otherwise, we could possibly store into the shadow parts of the adjacent
657 placed breakpoints. It is due to our SHADOW_CONTENTS overlapping the real
658 breakpoint instruction bits region. */
662 {
665 }
667 /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
668 for addressing the SHADOW_CONTENTS placement. */
671 /* Always cover the last byte of the bundle in case we are inserting
672 a breakpoint on an L-X instruction. */
677 {
678 /* X unit types can only be used in slot 2, and are actually
679 part of a 2-slot L-X instruction. We cannot break at this
680 address, as this is the second half of an instruction that
681 lives in slot 1 of that bundle. */
684 }
686 {
687 /* L unit types can only be used in slot 1. But the associated
688 opcode for that instruction is in slot 2, so bump the slot number
689 accordingly. */
692 }
694 /* Store the whole bundle, except for the initial skipped bytes by the slot
695 number interpreted as bytes offset in PLACED_ADDRESS. */
699 /* Re-read the same bundle as above except that, this time, read it in order
700 to compute the new bundle inside which we will be inserting the
701 breakpoint. Therefore, disable the automatic memory restoration from
702 breakpoints while we read our instruction bundle. Otherwise, the general
703 restoration mechanism kicks in and we would possibly remove parts of the
704 adjacent placed breakpoints. It is due to our SHADOW_CONTENTS overlapping
705 the real breakpoint instruction bits region. */
709 {
712 }
714 /* Breakpoints already present in the code will get deteacted and not get
715 reinserted by bp_loc_is_permanent. Multiple breakpoints at the same
716 location cannot induce the internal error as they are optimized into
717 a single instance by update_global_location_list. */
732 }
734 static int
737 {
748 /* Disable the automatic memory restoration from breakpoints while
749 we read our instruction bundle. Otherwise, the general restoration
750 mechanism kicks in and we would possibly remove parts of the adjacent
751 placed breakpoints. It is due to our SHADOW_CONTENTS overlapping the real
752 breakpoint instruction bits region. */
756 {
759 }
761 /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
762 for addressing the SHADOW_CONTENTS placement. */
767 {
768 /* X unit types can only be used in slot 2, and are actually
769 part of a 2-slot L-X instruction. We refuse to insert
770 breakpoints at this address, so there should be no reason
771 for us attempting to remove one there, except if the program's
772 code somehow got modified in memory. */
779 }
781 {
782 /* L unit types can only be used in slot 1. But the breakpoint
783 was actually saved using slot 2, so update the slot number
784 accordingly. */
787 }
794 {
800 }
802 /* Extract the original saved instruction from SLOTNUM normalizing its
803 bit-shift for INSTR_SAVED. */
809 /* In BUNDLE_MEM, be careful to modify only the bits belonging to SLOTNUM
810 and not any of the other ones that are stored in SHADOW_CONTENTS. */
816 }
818 /* As gdbarch_breakpoint_from_pc ranges have byte granularity and ia64
819 instruction slots ranges are bit-granular (41 bits) we have to provide an
820 extended range as described for ia64_memory_insert_breakpoint. We also take
821 care of preserving the `break' instruction 21-bit (or 62-bit) parameter to
822 make a match for permanent breakpoints. */
827 {
841 /* Enable the automatic memory restoration from breakpoints while
842 we read our instruction bundle to match bp_loc_is_permanent. */
847 /* The memory might be unreachable. This can happen, for instance,
848 when the user inserts a breakpoint at an invalid address. */
852 /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
853 for addressing the SHADOW_CONTENTS placement. */
856 /* Cover always the last byte of the bundle for the L-X slot case. */
859 /* Check for L type instruction in slot 1, if present then bump up the slot
860 number to the slot 2. */
863 {
866 }
868 {
871 }
873 /* A break instruction has its all its opcode bits cleared except for
874 the parameter value. For L+X slot pair we are at the X slot (slot 2) so
875 we should not touch the L slot - the upper 41 bits of the parameter. */
881 }
883 static CORE_ADDR
885 {
894 }
896 void
898 {
900 ULONGEST psr_value;
910 }
912 #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
914 /* Returns the address of the slot that's NSLOTS slots away from
915 the address ADDR. NSLOTS may be positive or negative. */
916 static CORE_ADDR
918 {
919 CORE_ADDR new_addr;
932 }
934 static enum register_status
937 {
942 {
943 #ifdef HAVE_LIBUNWIND_IA64_H
944 /* First try and use the libunwind special reg accessor,
945 otherwise fallback to standard logic. */
948 #endif
949 {
950 /* The fallback position is to assume that r32-r127 are
951 found sequentially in memory starting at $bof. This
952 isn't always true, but without libunwind, this is the
953 best we can do. */
955 ULONGEST cfm;
956 ULONGEST bsp;
957 CORE_ADDR reg;
969 /* The bsp points at the end of the register frame so we
970 subtract the size of frame from it to get start of
971 register frame. */
975 {
980 }
981 else
984 }
985 }
987 {
988 ULONGEST unatN_val;
989 ULONGEST unat;
996 }
998 {
1000 ULONGEST bsp;
1001 ULONGEST cfm;
1010 /* The bsp points at the end of the register frame so we
1011 subtract the size of frame from it to get start of register frame. */
1018 {
1019 /* Compute address of nat collection bits. */
1021 CORE_ADDR nat_collection;
1023 /* If our nat collection address is bigger than bsp, we have to get
1024 the nat collection from rnat. Otherwise, we fetch the nat
1025 collection from the computed address. */
1029 else
1033 }
1037 }
1039 {
1040 /* A virtual register frame start is provided for user convenience.
1041 It can be calculated as the bsp - sof (sizeof frame). */
1043 ULONGEST cfm;
1051 /* The bsp points at the end of the register frame so we
1052 subtract the size of frame from it to get beginning of frame. */
1056 }
1058 {
1059 ULONGEST pr;
1060 ULONGEST cfm;
1061 ULONGEST prN_val;
1070 {
1071 /* Fetch predicate register rename base from current frame
1072 marker for this frame. */
1075 /* Adjust the register number to account for register rotation. */
1076 regnum = VP16_REGNUM
1078 }
1082 }
1083 else
1087 }
1089 static void
1092 {
1096 {
1097 ULONGEST bsp;
1098 ULONGEST cfm;
1105 {
1108 }
1109 }
1111 {
1115 regnum),
1116 byte_order);
1123 }
1125 {
1126 ULONGEST natN_val;
1127 ULONGEST bsp;
1128 ULONGEST cfm;
1133 /* The bsp points at the end of the register frame so we
1134 subtract the size of frame from it to get start of register frame. */
1141 regnum),
1142 byte_order);
1145 {
1146 /* Compute address of nat collection bits. */
1148 CORE_ADDR nat_collection;
1151 /* If our nat collection address is bigger than bsp, we have to get
1152 the nat collection from rnat. Otherwise, we fetch the nat
1153 collection from the computed address. */
1155 {
1157 IA64_RNAT_REGNUM,
1161 else
1164 nat_collection);
1165 }
1166 else
1167 {
1172 else
1177 }
1178 }
1179 }
1181 {
1182 ULONGEST pr;
1183 ULONGEST cfm;
1184 ULONGEST prN_val;
1185 ULONGEST prN_mask;
1191 {
1192 /* Fetch predicate register rename base from current frame
1193 marker for this frame. */
1196 /* Adjust the register number to account for register rotation. */
1197 regnum = VP16_REGNUM
1199 }
1201 byte_order);
1208 }
1209 }
1211 /* The ia64 needs to convert between various ieee floating-point formats
1212 and the special ia64 floating point register format. */
1214 static int
1216 {
1219 }
1221 static int
1225 {
1229 /* Convert to TYPE. */
1238 }
1240 static void
1243 {
1248 }
1251 /* Limit the number of skipped non-prologue instructions since examining
1252 of the prologue is expensive. */
1255 /* Given PC representing the starting address of a function, and
1256 LIM_PC which is the (sloppy) limit to which to scan when looking
1257 for a prologue, attempt to further refine this limit by using
1258 the line data in the symbol table. If successful, a better guess
1259 on where the prologue ends is returned, otherwise the previous
1260 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
1261 which will be set to indicate whether the returned limit may be
1262 used with no further scanning in the event that the function is
1263 frameless. */
1265 /* FIXME: cagney/2004-02-14: This function and logic have largely been
1266 superseded by skip_prologue_using_sal. */
1268 static CORE_ADDR
1270 {
1273 CORE_ADDR end_pc;
1275 /* The prologue can not possibly go past the function end itself,
1276 so we can already adjust LIM_PC accordingly. */
1280 /* Start off not trusting the limit. */
1285 {
1289 /* Handle the case in which compiler's optimizer/scheduler
1290 has moved instructions into the prologue. We scan ahead
1291 in the function looking for address ranges whose corresponding
1292 line number is less than or equal to the first one that we
1293 found for the function. (It can be less than when the
1294 scheduler puts a body instruction before the first prologue
1295 instruction.) */
1298 i--)
1299 {
1307 {
1309 }
1311 }
1314 {
1318 }
1319 }
1321 }
1323 #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1324 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1325 || (14 <= (_regnum_) && (_regnum_) <= 31))
1326 #define imm9(_instr_) \
1327 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1328 | (((_instr_) & 0x00008000000LL) >> 20) \
1329 | (((_instr_) & 0x00000001fc0LL) >> 6))
1331 /* Allocate and initialize a frame cache. */
1335 {
1341 /* Base address. */
1357 }
1359 static CORE_ADDR
1363 {
1364 CORE_ADDR next_pc;
1366 instruction_type it;
1382 CORE_ADDR addr;
1397 /* We want to check if we have a recognizable function start before we
1398 look ahead for a prologue. */
1401 {
1402 /* alloc - start of a regular function. */
1408 /* Verify that the current cfm matches what we think is the
1409 function start. If we have somehow jumped within a function,
1410 we do not want to interpret the prologue and calculate the
1411 addresses of various registers such as the return address.
1412 We will instead treat the frame as frameless. */
1421 }
1422 else
1423 {
1424 /* Look for a leaf routine. */
1428 {
1429 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1437 {
1438 /* mov r2, r12 - beginning of leaf routine. */
1441 }
1442 }
1444 /* If we don't recognize a regular function or leaf routine, we are
1445 done. */
1447 {
1451 }
1452 }
1454 /* Loop, looking for prologue instructions, keeping track of
1455 where preserved registers were spilled. */
1457 {
1463 {
1464 /* Exit loop upon hitting a non-nop branch instruction. */
1468 }
1471 {
1472 /* Exit loop upon hitting a predicated instruction if
1473 we already have the return register or if we are frameless. */
1477 }
1479 {
1480 /* Move from BR */
1486 {
1489 }
1490 }
1493 {
1494 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1503 {
1504 /* mov rN, r12 */
1507 }
1509 {
1510 /* adds r12, -mem_stack_frame_size, r12 */
1513 }
1516 {
1519 /* adds r2, spilloffset, rFramePointer
1520 or
1521 adds r2, spilloffset, r12
1523 Get ready for stf.spill or st8.spill instructions.
1524 The address to start spilling at is loaded into r2.
1525 FIXME: Why r2? That's what gcc currently uses; it
1526 could well be different for other compilers. */
1528 /* Hmm... whether or not this will work will depend on
1529 where the pc is. If it's still early in the prologue
1530 this'll be wrong. FIXME */
1532 {
1537 }
1538 spill_addr = saved_sp
1543 }
1546 {
1547 /* mov rN, rM where rM is an input register. */
1550 }
1553 {
1554 /* mov r12, r2 */
1557 }
1558 }
1562 {
1563 /* stf.spill [rN] = fM, imm9
1564 or
1565 stf.spill [rN] = fM */
1573 {
1578 else
1581 }
1582 }
1585 {
1586 /* mov.m rN = arM
1587 or
1588 mov.i rN = arM */
1594 {
1595 /* We have something like "mov.m r3 = ar.unat". Remember the
1596 r3 (or whatever) and watch for a store of this register... */
1599 }
1600 }
1602 {
1603 /* mov rN = pr */
1607 {
1610 }
1611 }
1615 {
1616 /* st8 [rN] = rM
1617 or
1618 st8 [rN] = rM, imm9 */
1625 {
1626 /* We've found a spill of either the UNAT register or the PR
1627 register. (Well, not exactly; what we've actually found is
1628 a spill of the register that UNAT or PR was moved to).
1629 Record that fact and move on... */
1631 {
1632 /* Track UNAT register. */
1635 }
1636 else
1637 {
1638 /* Track PR register. */
1641 }
1643 /* st8 [rN] = rM, imm9 */
1645 else
1648 }
1650 {
1651 /* Allow up to one store of each input register. */
1654 }
1657 {
1658 /* Allow an indirect store of an input register. */
1661 }
1662 }
1664 {
1665 /* One of
1666 st1 [rN] = rM
1667 st2 [rN] = rM
1668 st4 [rN] = rM
1669 st8 [rN] = rM
1670 Note that the st8 case is handled in the clause above.
1672 Advance over stores of input registers. One store per input
1673 register is permitted. */
1678 {
1681 }
1684 {
1685 /* Allow an indirect store of an input register. */
1688 }
1689 }
1691 {
1692 /* Either
1693 stfs [rN] = fM
1694 or
1695 stfd [rN] = fM
1697 Advance over stores of floating point input registers. Again
1698 one store per register is permitted. */
1702 {
1705 }
1706 }
1710 {
1711 /* st8.spill [rN] = rM
1712 or
1713 st8.spill [rN] = rM, imm9 */
1718 {
1719 /* We've found a spill of one of the preserved general purpose
1720 regs. Record the spill address and advance the spill
1721 register if appropriate. */
1724 /* st8.spill [rN] = rM, imm9 */
1726 else
1729 }
1730 }
1733 }
1735 /* If not frameless and we aren't called by skip_prologue, then we need
1736 to calculate registers for the previous frame which will be needed
1737 later. */
1740 {
1744 /* Extract the size of the rotating portion of the stack
1745 frame and the register rename base from the current
1746 frame marker. */
1753 /* Find the bof (beginning of frame). */
1759 {
1761 {
1763 }
1770 }
1772 /* For the previous argument registers we require the previous bof.
1773 If we can't find the previous cfm, then we can do nothing. */
1776 {
1779 }
1781 {
1784 }
1788 {
1794 /* The previous bof only requires subtraction of the sol (size of
1795 locals) due to the overlap between output and input of
1796 subsequent frames. */
1802 {
1804 {
1806 }
1811 else
1813 }
1815 }
1816 }
1818 /* Try and trust the lim_pc value whenever possible. */
1828 }
1830 CORE_ADDR
1832 {
1839 /* Call examine_prologue with - as third argument since we don't
1840 have a next frame pointer to send. */
1842 }
1845 /* Normal frames. */
1849 {
1865 /* We always want the bsp to point to the end of frame.
1866 This way, we can always get the beginning of frame (bof)
1867 by subtracting frame size. */
1891 }
1893 static void
1896 {
1901 /* If outermost frame, mark with null frame id. */
1906 "regular frame id: code %s, stack %s, "
1912 }
1917 {
1932 {
1936 /* We want to calculate the previous bsp as the end of the previous
1937 register stack frame. This corresponds to what the hardware bsp
1938 register will be if we pop the frame back which is why we might
1939 have been called. We know the beginning of the current frame is
1940 cache->bsp - cache->sof. This value in the previous frame points
1941 to the start of the output registers. We can calculate the end of
1942 that frame by adding the size of output:
1943 (sof (size of frame) - sol (size of locals)). */
1948 prev_bsp =
1952 }
1955 {
1966 IA64_PFS_REGNUM);
1968 }
1971 {
1972 /* If the function in question uses an automatic register (r32-r127)
1973 for the frame pointer, it'll be found by ia64_find_saved_register()
1974 above. If the function lacks one of these frame pointers, we can
1975 still provide a value since we know the size of the frame. */
1977 }
1980 {
1982 ULONGEST prN;
1985 IA64_PR_REGNUM);
1987 {
1988 /* Fetch predicate register rename base from current frame
1989 marker for this frame. */
1992 /* Adjust the register number to account for register rotation. */
1994 }
1998 }
2001 {
2003 ULONGEST unatN;
2005 IA64_UNAT_REGNUM);
2009 }
2012 {
2014 /* Find address of general register corresponding to nat bit we're
2015 interested in. */
2016 CORE_ADDR gr_addr;
2021 {
2022 /* Compute address of nat collection bits. */
2024 CORE_ADDR bsp;
2025 CORE_ADDR nat_collection;
2028 /* If our nat collection address is bigger than bsp, we have to get
2029 the nat collection from rnat. Otherwise, we fetch the nat
2030 collection from the computed address. */
2034 {
2037 }
2038 else
2042 }
2045 }
2048 {
2053 {
2056 }
2058 {
2061 }
2064 }
2067 {
2068 /* We don't know how to get the complete previous PSR, but we need it
2069 for the slot information when we unwind the pc (pc is formed of IP
2070 register plus slot information from PSR). To get the previous
2071 slot information, we mask it off the return address. */
2081 {
2084 }
2086 {
2089 }
2094 }
2097 {
2104 }
2108 {
2118 {
2122 /* FIXME: brobecker/2008-05-01: Doesn't this seem redundant
2123 with the same code above? */
2127 IA64_CFM_REGNUM);
2131 IA64_BSP_REGNUM);
2138 }
2141 }
2144 {
2148 {
2149 /* Fetch floating point register rename base from current
2150 frame marker for this frame. */
2153 /* Adjust the floating point register number to account for
2154 register rotation. */
2155 regnum = IA64_FR32_REGNUM
2157 }
2159 /* If we have stored a memory address, access the register. */
2163 /* Otherwise, punt and get the current value of the register. */
2164 else
2166 }
2167 }
2170 {
2171 NORMAL_FRAME,
2172 default_frame_unwind_stop_reason,
2175 NULL,
2176 default_frame_sniffer
2177 };
2179 /* Signal trampolines. */
2181 static void
2184 {
2189 {
2194 IA64_IP_REGNUM);
2197 IA64_CFM_REGNUM);
2200 IA64_PSR_REGNUM);
2203 IA64_BSP_REGNUM);
2206 IA64_RNAT_REGNUM);
2209 IA64_CCV_REGNUM);
2212 IA64_UNAT_REGNUM);
2215 IA64_FPSR_REGNUM);
2218 IA64_PFS_REGNUM);
2221 IA64_LC_REGNUM);
2232 }
2233 }
2237 {
2249 /* Note that frame size is hard-coded below. We cannot calculate it
2250 via prologue examination. */
2264 }
2266 static void
2269 {
2279 "sigtramp frame id: code %s, stack %s, "
2285 }
2290 {
2304 {
2309 {
2312 }
2315 }
2319 {
2329 }
2332 {
2339 }
2340 }
2342 static int
2346 {
2349 {
2354 }
2357 }
2360 {
2361 SIGTRAMP_FRAME,
2362 default_frame_unwind_stop_reason,
2363 ia64_sigtramp_frame_this_id,
2364 ia64_sigtramp_frame_prev_register,
2365 NULL,
2366 ia64_sigtramp_frame_sniffer
2367 };
2369 \f
2371 static CORE_ADDR
2373 {
2377 }
2380 {
2382 ia64_frame_base_address,
2383 ia64_frame_base_address,
2384 ia64_frame_base_address
2385 };
2387 #ifdef HAVE_LIBUNWIND_IA64_H
2389 struct ia64_unwind_table_entry
2390 {
2391 unw_word_t start_offset;
2392 unw_word_t end_offset;
2393 unw_word_t info_offset;
2394 };
2398 {
2400 }
2402 /* Skip over a designated number of registers in the backing
2403 store, remembering every 64th position is for NAT. */
2406 {
2412 }
2414 /* Gdb ia64-libunwind-tdep callback function to convert from an ia64 gdb
2415 register number to a libunwind register number. */
2416 static int
2418 {
2443 else
2445 }
2447 /* Gdb ia64-libunwind-tdep callback function to convert from a libunwind
2448 register number to a ia64 gdb register number. */
2449 static int
2451 {
2474 else
2476 }
2478 /* Gdb ia64-libunwind-tdep callback function to reveal if register is
2479 a float register or not. */
2480 static int
2482 {
2484 }
2486 /* Libunwind callback accessor function for general registers. */
2487 static int
2490 {
2499 /* We never call any libunwind routines that need to write registers. */
2503 {
2505 /* Libunwind expects to see the pc value which means the slot number
2506 from the psr must be merged with the ip word address. */
2515 /* Libunwind expects to see the beginning of the current
2516 register frame so we must account for the fact that
2517 ptrace() will return a value for bsp that points *after*
2518 the current register frame. */
2528 /* Libunwind wants bspstore to be after the current register frame.
2529 This is what ptrace() and gdb treats as the regular bsp value. */
2535 /* For all other registers, just unwind the value directly. */
2539 }
2548 }
2550 /* Libunwind callback accessor function for floating-point registers. */
2551 static int
2554 {
2558 /* We never call any libunwind routines that need to write registers. */
2564 }
2566 /* Libunwind callback accessor function for top-level rse registers. */
2567 static int
2570 {
2579 /* We never call any libunwind routines that need to write registers. */
2583 {
2585 /* Libunwind expects to see the pc value which means the slot number
2586 from the psr must be merged with the ip word address. */
2595 /* Libunwind expects to see the beginning of the current
2596 register frame so we must account for the fact that
2597 ptrace() will return a value for bsp that points *after*
2598 the current register frame. */
2608 /* Libunwind wants bspstore to be after the current register frame.
2609 This is what ptrace() and gdb treats as the regular bsp value. */
2615 /* For all other registers, just unwind the value directly. */
2619 }
2629 }
2631 /* Libunwind callback accessor function for top-level fp registers. */
2632 static int
2635 {
2639 /* We never call any libunwind routines that need to write registers. */
2645 }
2647 /* Libunwind callback accessor function for accessing memory. */
2648 static int
2652 {
2654 {
2660 else
2663 }
2665 /* XXX do we need to normalize byte-order here? */
2668 else
2670 }
2672 /* Call low-level function to access the kernel unwind table. */
2673 static LONGEST
2675 {
2676 LONGEST x;
2678 /* FIXME drow/2005-09-10: This code used to call
2679 ia64_linux_xfer_unwind_table directly to fetch the unwind table
2680 for the currently running ia64-linux kernel. That data should
2681 come from the core file and be accessed via the auxv vector; if
2682 we want to preserve fall back to the running kernel's table, then
2683 we should find a way to override the corefile layer's
2684 xfer_partial method. */
2690 }
2692 /* Get the kernel unwind table. */
2693 static int
2695 {
2699 {
2701 LONGEST size;
2712 }
2734 }
2736 /* Find the unwind table entry for a specified address. */
2737 static int
2740 {
2744 CORE_ADDR load_base;
2756 {
2758 {
2771 }
2772 }
2777 /* Verify that the segment that contains the IP also contains
2778 the static unwind table. If not, we may be in the Linux kernel's
2779 DSO gate page in which case the unwind table is another segment.
2780 Otherwise, we are dealing with runtime-generated code, for which we
2781 have no info here. */
2785 {
2788 {
2791 {
2793 /* Get the segbase from the section containing the
2794 libunwind table. */
2796 }
2797 }
2800 }
2812 }
2814 /* Libunwind callback accessor function to acquire procedure unwind-info. */
2815 static int
2818 {
2820 unw_dyn_info_t di;
2825 {
2826 /* XXX This only works if the host and the target architecture are
2827 both ia64 and if the have (more or less) the same kernel
2828 version. */
2834 "(name=`%s',segbase=%s,start=%s,end=%s,gp=%s,"
2842 }
2843 else
2844 {
2851 "(name=`%s',segbase=%s,start=%s,end=%s,gp=%s,"
2859 }
2862 arg);
2864 /* We no longer need the dyn info storage so free it. */
2868 }
2870 /* Libunwind callback accessor function for cleanup. */
2871 static void
2874 {
2875 /* Nothing required for now. */
2876 }
2878 /* Libunwind callback accessor function to get head of the dynamic
2879 unwind-info registration list. */
2880 static int
2883 {
2887 unw_dyn_info_t di;
2894 {
2901 {
2903 /* We no longer need the dyn info storage so free it. */
2907 {
2910 "dynamic unwind table in objfile %s "
2916 }
2917 }
2918 }
2920 }
2923 /* Frame interface functions for libunwind. */
2925 static void
2928 {
2933 CORE_ADDR bsp;
2937 {
2940 }
2942 /* We must add the bsp as the special address for frame comparison
2943 purposes. */
2951 "libunwind frame id: code %s, stack %s, "
2957 }
2962 {
2973 /* Let libunwind do most of the work. */
2977 {
2978 ULONGEST prN_val;
2981 {
2983 ULONGEST cfm;
2986 /* Fetch predicate register rename base from current frame
2987 marker for this frame. */
2992 /* Adjust the register number to account for register rotation. */
2994 }
2998 }
3001 {
3002 ULONGEST unatN_val;
3007 }
3010 {
3014 /* We want to calculate the previous bsp as the end of the previous
3015 register stack frame. This corresponds to what the hardware bsp
3016 register will be if we pop the frame back which is why we might
3017 have been called. We know that libunwind will pass us back the
3018 beginning of the current frame so we should just add sof to it. */
3022 IA64_CFM_REGNUM);
3028 }
3029 else
3031 }
3033 static int
3037 {
3043 }
3046 {
3047 NORMAL_FRAME,
3048 default_frame_unwind_stop_reason,
3049 ia64_libunwind_frame_this_id,
3050 ia64_libunwind_frame_prev_register,
3051 NULL,
3052 ia64_libunwind_frame_sniffer,
3053 libunwind_frame_dealloc_cache
3054 };
3056 static void
3060 {
3064 CORE_ADDR bsp;
3066 CORE_ADDR prev_ip;
3070 {
3073 }
3075 /* We must add the bsp as the special address for frame comparison
3076 purposes. */
3080 /* For a sigtramp frame, we don't make the check for previous ip being 0. */
3085 "libunwind sigtramp frame id: code %s, "
3091 }
3096 {
3100 CORE_ADDR prev_ip;
3102 /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT
3103 method of getting previous registers. */
3105 IA64_IP_REGNUM);
3110 {
3113 regnum);
3114 }
3115 else
3117 }
3119 static int
3123 {
3125 {
3129 }
3130 else
3132 }
3135 {
3136 SIGTRAMP_FRAME,
3137 default_frame_unwind_stop_reason,
3138 ia64_libunwind_sigtramp_frame_this_id,
3139 ia64_libunwind_sigtramp_frame_prev_register,
3140 NULL,
3141 ia64_libunwind_sigtramp_frame_sniffer
3142 };
3144 /* Set of libunwind callback acccessor functions. */
3145 unw_accessors_t ia64_unw_accessors =
3146 {
3147 ia64_find_proc_info_x,
3148 ia64_put_unwind_info,
3149 ia64_get_dyn_info_list,
3150 ia64_access_mem,
3151 ia64_access_reg,
3152 ia64_access_fpreg,
3153 /* resume */
3154 /* get_proc_name */
3155 };
3157 /* Set of special libunwind callback acccessor functions specific for accessing
3158 the rse registers. At the top of the stack, we want libunwind to figure out
3159 how to read r32 - r127. Though usually they are found sequentially in
3160 memory starting from $bof, this is not always true. */
3161 unw_accessors_t ia64_unw_rse_accessors =
3162 {
3163 ia64_find_proc_info_x,
3164 ia64_put_unwind_info,
3165 ia64_get_dyn_info_list,
3166 ia64_access_mem,
3167 ia64_access_rse_reg,
3168 ia64_access_rse_fpreg,
3169 /* resume */
3170 /* get_proc_name */
3171 };
3173 /* Set of ia64-libunwind-tdep gdb callbacks and data for generic
3174 ia64-libunwind-tdep code to use. */
3176 {
3177 ia64_gdb2uw_regnum,
3178 ia64_uw2gdb_regnum,
3179 ia64_is_fpreg,
3182 };
3186 static int
3188 {
3191 /* Don't use the struct convention for anything but structure,
3192 union, or array types. */
3198 /* HFAs are structures (or arrays) consisting entirely of floating
3199 point values of the same length. Up to 8 of these are returned
3200 in registers. Don't use the struct convention when this is the
3201 case. */
3207 /* Other structs of length 32 or less are returned in r8-r11.
3208 Don't use the struct convention for those either. */
3210 }
3212 /* Return non-zero if TYPE is a structure or union type. */
3214 static int
3216 {
3219 }
3221 static void
3224 {
3230 {
3237 {
3242 regnum++;
3243 }
3244 }
3246 {
3247 /* This is an integral value, and its size is less than 8 bytes.
3248 These values are LSB-aligned, so extract the relevant bytes,
3249 and copy them into VALBUF. */
3250 /* brobecker/2005-12-30: Actually, all integral values are LSB aligned,
3251 so I suppose we should also add handling here for integral values
3252 whose size is greater than 8. But I wasn't able to create such
3253 a type, neither in C nor in Ada, so not worrying about these yet. */
3255 ULONGEST val;
3259 }
3260 else
3261 {
3262 ULONGEST val;
3270 {
3271 ULONGEST val;
3275 regnum++;
3276 }
3279 {
3282 }
3283 }
3284 }
3286 static void
3289 {
3295 {
3302 {
3307 regnum++;
3308 }
3309 }
3310 else
3311 {
3312 ULONGEST val;
3320 {
3321 ULONGEST val;
3325 regnum++;
3326 }
3329 {
3332 }
3333 }
3334 }
3336 static enum return_value_convention
3340 {
3344 {
3347 }
3350 {
3353 }
3357 else
3359 }
3361 static int
3363 {
3365 {
3369 else
3370 {
3373 }
3376 return
3378 etp);
3381 {
3389 }
3394 }
3395 }
3397 /* Determine if the given type is one of the floating point types or
3398 and HFA (which is a struct, array, or combination thereof whose
3399 bottom-most elements are all of the same floating point type). */
3403 {
3407 }
3410 /* Return 1 if the alignment of T is such that the next even slot
3411 should be used. Return 0, if the next available slot should
3412 be used. (See section 8.5.1 of the IA-64 Software Conventions
3413 and Runtime manual). */
3415 static int
3417 {
3419 {
3424 else
3427 return
3430 {
3438 }
3441 }
3442 }
3444 /* Attempt to find (and return) the global pointer for the given
3445 function.
3447 This is a rather nasty bit of code searchs for the .dynamic section
3448 in the objfile corresponding to the pc of the function we're trying
3449 to call. Once it finds the addresses at which the .dynamic section
3450 lives in the child process, it scans the Elf64_Dyn entries for a
3451 DT_PLTGOT tag. If it finds one of these, the corresponding
3452 d_un.d_ptr value is the global pointer. */
3454 static CORE_ADDR
3456 CORE_ADDR faddr)
3457 {
3463 {
3467 {
3470 }
3473 {
3480 {
3482 LONGEST tag;
3491 {
3492 CORE_ADDR global_pointer;
3498 byte_order);
3500 /* The payoff... */
3502 }
3508 }
3509 }
3510 }
3512 }
3514 /* Attempt to find (and return) the global pointer for the given
3515 function. We first try the find_global_pointer_from_solib routine
3516 from the gdbarch tdep vector, if provided. And if that does not
3517 work, then we try ia64_find_global_pointer_from_dynamic_section. */
3519 static CORE_ADDR
3521 {
3530 }
3532 /* Given a function's address, attempt to find (and return) the
3533 corresponding (canonical) function descriptor. Return 0 if
3534 not found. */
3535 static CORE_ADDR
3537 {
3541 /* Return early if faddr is already a function descriptor. */
3547 {
3550 {
3553 }
3556 {
3563 {
3565 LONGEST faddr2;
3577 }
3578 }
3579 }
3581 }
3583 /* Attempt to find a function descriptor corresponding to the
3584 given address. If none is found, construct one on the
3585 stack using the address at fdaptr. */
3587 static CORE_ADDR
3589 {
3592 CORE_ADDR fdesc;
3597 {
3598 ULONGEST global_pointer;
3614 }
3617 }
3619 /* Use the following routine when printing out function pointers
3620 so the user can see the function address rather than just the
3621 function descriptor. */
3622 static CORE_ADDR
3625 {
3632 /* check if ADDR points to a function descriptor. */
3636 /* Normally, functions live inside a section that is executable.
3637 So, if ADDR points to a non-executable section, then treat it
3638 as a function descriptor and return the target address iff
3639 the target address itself points to a section that is executable.
3640 Check first the memory of the whole length of 8 bytes is readable. */
3643 {
3649 }
3651 /* There are also descriptors embedded in vtables. */
3653 {
3660 }
3663 }
3665 static CORE_ADDR
3667 {
3669 }
3671 /* The default "allocate_new_rse_frame" ia64_infcall_ops routine for ia64. */
3673 static void
3675 {
3691 }
3693 /* The default "store_argument_in_slot" ia64_infcall_ops routine for
3694 ia64. */
3696 static void
3699 {
3701 }
3703 /* The default "set_function_addr" ia64_infcall_ops routine for ia64. */
3705 static void
3707 {
3708 /* Nothing needed. */
3709 }
3711 static CORE_ADDR
3716 {
3725 ULONGEST bsp;
3731 /* Count the number of slots needed for the arguments. */
3733 {
3739 nslots++;
3742 nfuncargs++;
3745 }
3747 /* Divvy up the slots between the RSE and the memory stack. */
3751 /* Allocate a new RSE frame. */
3755 /* We will attempt to find function descriptors in the .opd segment,
3756 but if we can't we'll construct them ourselves. That being the
3757 case, we'll need to reserve space on the stack for them. */
3761 /* Adjust the stack pointer to it's new value. The calling conventions
3762 require us to have 16 bytes of scratch, plus whatever space is
3763 necessary for the memory slots and our function descriptors. */
3767 /* Place the arguments where they belong. The arguments will be
3768 either placed in the RSE backing store or on the memory stack.
3769 In addition, floating point arguments or HFAs are placed in
3770 floating point registers. */
3774 {
3781 /* Special handling for function parameters. */
3785 {
3795 else
3797 slotnum++;
3799 }
3801 /* Normal slots. */
3803 /* Skip odd slot if necessary... */
3805 slotnum++;
3809 {
3814 {
3815 /* Integral types are LSB-aligned, so we have to be careful
3816 to insert the argument on the correct side of the buffer.
3817 This is why we use store_unsigned_integer. */
3818 store_unsigned_integer
3821 byte_order));
3822 }
3823 else
3824 {
3825 /* This is either an 8bit integral type, or an aggregate.
3826 For 8bit integral type, there is no problem, we just
3827 copy the value over.
3829 For aggregates, the only potentially tricky portion
3830 is to write the last one if it is less than 8 bytes.
3831 In this case, the data is Byte0-aligned. Happy news,
3832 this means that we don't need to differentiate the
3833 handling of 8byte blocks and less-than-8bytes blocks. */
3836 }
3841 else
3846 slotnum++;
3847 }
3849 /* Handle floating point types (including HFAs). */
3852 {
3856 {
3862 floatreg++;
3865 }
3866 }
3867 }
3869 /* Store the struct return value in r8 if necessary. */
3871 {
3874 }
3881 /* The following is not necessary on HP-UX, because we're using
3882 a dummy code sequence pushed on the stack to make the call, and
3883 this sequence doesn't need b0 to be set in order for our dummy
3884 breakpoint to be hit. Nonetheless, this doesn't interfere, and
3885 it's needed for other OSes, so we do this unconditionaly. */
3893 }
3896 {
3897 ia64_allocate_new_rse_frame,
3898 ia64_store_argument_in_slot,
3899 ia64_set_function_addr
3900 };
3902 static struct frame_id
3904 {
3922 }
3924 static CORE_ADDR
3926 {
3938 }
3940 static int
3942 {
3945 }
3947 /* The default "size_of_register_frame" gdbarch_tdep routine for ia64. */
3949 static int
3951 {
3953 }
3957 {
3961 /* If there is already a candidate, use it. */
3971 /* According to the ia64 specs, instructions that store long double
3972 floats in memory use a long-double format different than that
3973 used in the floating registers. The memory format matches the
3974 x86 extended float format which is 80 bits. An OS may choose to
3975 use this format (e.g. GNU/Linux) or choose to use a different
3976 format for storing long doubles (e.g. HPUX). In the latter case,
3977 the setting of the format may be moved/overridden in an
3978 OS-specific tdep file. */
4012 ia64_memory_insert_breakpoint);
4014 ia64_memory_remove_breakpoint);
4019 /* Settings for calling functions in the inferior. */
4026 #ifdef HAVE_LIBUNWIND_IA64_H
4032 #else
4034 #endif
4038 /* Settings that should be unnecessary. */
4043 ia64_convert_from_func_ptr_addr);
4045 /* The virtual table contains 16-byte descriptors, not pointers to
4046 descriptors. */
4049 /* Hook in ABI-specific overrides, if they have been registered. */
4053 }
4057 void
4059 {
4061 }