| blob | 5af1643bf506870e741ee4da7bd645083619e16d |
1 /* 32-bit ELF support for ARM
2 Copyright 1998-2013 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 #include <limits.h>
33 /* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35 #define RELOC_SECTION(HTAB, NAME) \
38 /* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40 #define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
45 /* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47 #define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
52 /* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54 #define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
59 #define elf_info_to_howto 0
60 #define elf_info_to_howto_rel elf32_arm_info_to_howto
62 #define ARM_ELF_ABI_VERSION 0
63 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65 /* The Adjusted Place, as defined by AAELF. */
66 #define Pa(X) ((X) & 0xfffffffc)
73 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
78 {
79 /* No relocation. */
108 /* 32 bit absolute */
123 /* standard 32bit pc-relative reloc */
138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
153 /* 16 bit absolute */
168 /* 12 bit absolute */
197 /* 8 bit absolute */
296 /* BLX instruction for the ARM. */
311 /* BLX instruction for the Thumb. */
326 /* Dynamic TLS relocations. */
370 /* Relocs used in ARM Linux */
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
893 /* Group relocations. */
1273 /* End of group relocations. */
1487 /* GNU extension to record C++ vtable member usage */
1502 /* GNU extension to record C++ vtable hierarchy */
1545 /* TLS relocations */
1658 /* 112-127 private relocations. */
1676 /* R_ARM_ME_TOO, obsolete. */
1692 };
1694 /* 160 onwards: */
1696 {
1710 };
1712 /* 249-255 extended, currently unused, relocations: */
1714 {
1770 };
1774 {
1786 }
1788 static void
1791 {
1796 }
1798 struct elf32_arm_reloc_map
1799 {
1800 bfd_reloc_code_real_type bfd_reloc_val;
1802 };
1804 /* All entries in this list must also be present in elf32_arm_howto_table. */
1806 {
1893 };
1897 bfd_reloc_code_real_type code)
1898 {
1906 }
1911 {
1930 }
1932 /* Support for core dump NOTE sections. */
1934 static bfd_boolean
1936 {
1941 {
1946 /* pr_cursig */
1949 /* pr_pid */
1952 /* pr_reg */
1957 }
1959 /* Make a ".reg/999" section. */
1962 }
1964 static bfd_boolean
1966 {
1968 {
1979 }
1981 /* Note that for some reason, a spurious space is tacked
1982 onto the end of the args in some (at least one anyway)
1983 implementations, so strip it off if it exists. */
1984 {
1990 }
1993 }
1998 {
2000 {
2005 {
2017 }
2020 {
2039 }
2040 }
2041 }
2043 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vec
2045 #define TARGET_BIG_SYM bfd_elf32_bigarm_vec
2048 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2049 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2050 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2055 /* In lieu of proper flags, assume all EABIv4 or later objects are
2056 interworkable. */
2057 #define INTERWORK_FLAG(abfd) \
2058 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2059 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2060 || ((abfd)->flags & BFD_LINKER_CREATED))
2062 /* The linker script knows the section names for placement.
2063 The entry_names are used to do simple name mangling on the stubs.
2064 Given a function name, and its type, the stub can be found. The
2065 name can be changed. The only requirement is the %s be present. */
2080 /* The name of the dynamic interpreter. This is put in the .interp
2081 section. */
2085 {
2089 };
2092 {
2100 + dl_tlsdesc_lazy_resolver(GOT) */
2102 };
2104 #ifdef FOUR_WORD_PLT
2106 /* The first entry in a procedure linkage table looks like
2107 this. It is set up so that any shared library function that is
2108 called before the relocation has been set up calls the dynamic
2109 linker first. */
2111 {
2116 };
2118 /* Subsequent entries in a procedure linkage table look like
2119 this. */
2121 {
2126 };
2128 #else
2130 /* The first entry in a procedure linkage table looks like
2131 this. It is set up so that any shared library function that is
2132 called before the relocation has been set up calls the dynamic
2133 linker first. */
2135 {
2141 };
2143 /* Subsequent entries in a procedure linkage table look like
2144 this. */
2146 {
2150 };
2152 #endif
2154 /* The format of the first entry in the procedure linkage table
2155 for a VxWorks executable. */
2157 {
2162 };
2164 /* The format of subsequent entries in a VxWorks executable. */
2166 {
2173 };
2175 /* The format of entries in a VxWorks shared library. */
2177 {
2184 };
2186 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2187 #define PLT_THUMB_STUB_SIZE 4
2189 {
2192 };
2194 /* The entries in a PLT when using a DLL-based target with multiple
2195 address spaces. */
2197 {
2200 };
2202 /* The first entry in a procedure linkage table looks like
2203 this. It is set up so that any shared library function that is
2204 called before the relocation has been set up calls the dynamic
2205 linker first. */
2207 {
2208 /* First bundle: */
2213 /* Second bundle: */
2218 /* Third bundle: */
2222 /* .Lplt_tail: */
2224 /* Fourth bundle: */
2229 };
2230 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2232 /* Subsequent entries in a procedure linkage table look like this. */
2234 {
2239 };
2241 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2242 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2243 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2244 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2245 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2246 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2248 enum stub_insn_type
2249 {
2251 THUMB32_TYPE,
2252 ARM_TYPE,
2253 DATA_TYPE
2254 };
2256 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2257 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2258 is inserted in arm_build_one_stub(). */
2259 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2260 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2261 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2262 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2263 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2264 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2267 {
2268 bfd_vma data;
2274 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2275 to reach the stub if necessary. */
2277 {
2280 };
2282 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2283 available. */
2285 {
2289 };
2291 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2293 {
2301 };
2303 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2304 allowed. */
2306 {
2312 };
2314 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2315 available. */
2317 {
2322 };
2324 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2325 one, when the destination is close enough. */
2327 {
2331 };
2333 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2334 blx to reach the stub if necessary. */
2336 {
2340 };
2342 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2343 blx to reach the stub if necessary. We can not add into pc;
2344 it is not guaranteed to mode switch (different in ARMv6 and
2345 ARMv7). */
2347 {
2352 };
2354 /* V4T ARM -> ARM long branch stub, PIC. */
2356 {
2361 };
2363 /* V4T Thumb -> ARM long branch stub, PIC. */
2365 {
2371 };
2373 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2374 architectures. */
2376 {
2384 };
2386 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2387 allowed. */
2389 {
2396 };
2398 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2399 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2401 {
2405 };
2407 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2408 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2410 {
2416 };
2418 /* NaCl ARM -> ARM long branch stub. */
2420 {
2429 };
2431 /* NaCl ARM -> ARM long branch stub, PIC. */
2433 {
2442 };
2445 /* Cortex-A8 erratum-workaround stubs. */
2447 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2448 can't use a conditional branch to reach this stub). */
2451 {
2455 };
2457 /* Stub used for b.w and bl.w instructions. */
2460 {
2462 };
2465 {
2467 };
2469 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2470 instruction (which switches to ARM mode) to point to this stub. Jump to the
2471 real destination using an ARM-mode branch. */
2474 {
2476 };
2478 /* For each section group there can be a specially created linker section
2479 to hold the stubs for that group. The name of the stub section is based
2480 upon the name of another section within that group with the suffix below
2481 applied.
2483 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2484 create what appeared to be a linker stub section when it actually
2485 contained user code/data. For example, consider this fragment:
2487 const char * stubborn_problems[] = { "np" };
2489 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2490 section called:
2492 .data.rel.local.stubborn_problems
2494 This then causes problems in arm32_arm_build_stubs() as it triggers:
2496 // Ignore non-stub sections.
2497 if (!strstr (stub_sec->name, STUB_SUFFIX))
2498 continue;
2500 And so the section would be ignored instead of being processed. Hence
2501 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2502 C identifier. */
2505 /* One entry per long/short branch stub defined above. */
2506 #define DEF_STUBS \
2507 DEF_STUB(long_branch_any_any) \
2508 DEF_STUB(long_branch_v4t_arm_thumb) \
2509 DEF_STUB(long_branch_thumb_only) \
2510 DEF_STUB(long_branch_v4t_thumb_thumb) \
2511 DEF_STUB(long_branch_v4t_thumb_arm) \
2512 DEF_STUB(short_branch_v4t_thumb_arm) \
2513 DEF_STUB(long_branch_any_arm_pic) \
2514 DEF_STUB(long_branch_any_thumb_pic) \
2515 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2516 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2517 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
2518 DEF_STUB(long_branch_thumb_only_pic) \
2519 DEF_STUB(long_branch_any_tls_pic) \
2520 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
2521 DEF_STUB(long_branch_arm_nacl) \
2522 DEF_STUB(long_branch_arm_nacl_pic) \
2523 DEF_STUB(a8_veneer_b_cond) \
2524 DEF_STUB(a8_veneer_b) \
2525 DEF_STUB(a8_veneer_bl) \
2526 DEF_STUB(a8_veneer_blx)
2528 #define DEF_STUB(x) arm_stub_##x,
2529 enum elf32_arm_stub_type
2530 {
2531 arm_stub_none,
2532 DEF_STUBS
2533 /* Note the first a8_veneer type */
2534 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
2535 };
2536 #undef DEF_STUB
2539 {
2544 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2546 {
2548 DEF_STUBS
2549 };
2551 struct elf32_arm_stub_hash_entry
2552 {
2553 /* Base hash table entry structure. */
2556 /* The stub section. */
2559 /* Offset within stub_sec of the beginning of this stub. */
2560 bfd_vma stub_offset;
2562 /* Given the symbol's value and its section we can determine its final
2563 value when building the stubs (so the stub knows where to jump). */
2564 bfd_vma target_value;
2567 /* Offset to apply to relocation referencing target_value. */
2568 bfd_vma target_addend;
2570 /* The instruction which caused this stub to be generated (only valid for
2571 Cortex-A8 erratum workaround stubs at present). */
2574 /* The stub type. */
2576 /* Its encoding size in bytes. */
2578 /* Its template. */
2580 /* The size of the template (number of entries). */
2583 /* The symbol table entry, if any, that this was derived from. */
2586 /* Type of branch. */
2589 /* Where this stub is being called from, or, in the case of combined
2590 stub sections, the first input section in the group. */
2593 /* The name for the local symbol at the start of this stub. The
2594 stub name in the hash table has to be unique; this does not, so
2595 it can be friendlier. */
2597 };
2599 /* Used to build a map of a section. This is required for mixed-endian
2600 code/data. */
2603 {
2604 bfd_vma vma;
2606 }
2607 elf32_arm_section_map;
2609 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2612 {
2613 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2614 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2615 VFP11_ERRATUM_ARM_VENEER,
2616 VFP11_ERRATUM_THUMB_VENEER
2617 }
2618 elf32_vfp11_erratum_type;
2621 {
2623 bfd_vma vma;
2624 union
2625 {
2626 struct
2627 {
2631 struct
2632 {
2637 elf32_vfp11_erratum_type type;
2638 }
2639 elf32_vfp11_erratum_list;
2642 {
2643 DELETE_EXIDX_ENTRY,
2644 INSERT_EXIDX_CANTUNWIND_AT_END
2645 }
2646 arm_unwind_edit_type;
2648 /* A (sorted) list of edits to apply to an unwind table. */
2650 {
2651 arm_unwind_edit_type type;
2652 /* Note: we sometimes want to insert an unwind entry corresponding to a
2653 section different from the one we're currently writing out, so record the
2654 (text) section this edit relates to here. */
2658 }
2659 arm_unwind_table_edit;
2662 {
2663 /* Information about mapping symbols. */
2668 /* Information about CPU errata. */
2671 /* Information about unwind tables. */
2672 union
2673 {
2674 /* Unwind info attached to a text section. */
2675 struct
2676 {
2680 /* Unwind info attached to an .ARM.exidx section. */
2681 struct
2682 {
2687 }
2688 _arm_elf_section_data;
2690 #define elf32_arm_section_data(sec) \
2691 ((_arm_elf_section_data *) elf_section_data (sec))
2693 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2694 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2695 so may be created multiple times: we use an array of these entries whilst
2696 relaxing which we can refresh easily, then create stubs for each potentially
2697 erratum-triggering instruction once we've settled on a solution. */
2699 struct a8_erratum_fix
2700 {
2703 bfd_vma offset;
2704 bfd_vma addend;
2709 };
2711 /* A table of relocs applied to branches which might trigger Cortex-A8
2712 erratum. */
2714 struct a8_erratum_reloc
2715 {
2716 bfd_vma from;
2717 bfd_vma destination;
2722 bfd_boolean non_a8_stub;
2723 };
2725 /* The size of the thread control block. */
2726 #define TCB_SIZE 8
2728 /* ARM-specific information about a PLT entry, over and above the usual
2729 gotplt_union. */
2730 struct arm_plt_info
2731 {
2732 /* We reference count Thumb references to a PLT entry separately,
2733 so that we can emit the Thumb trampoline only if needed. */
2734 bfd_signed_vma thumb_refcount;
2736 /* Some references from Thumb code may be eliminated by BL->BLX
2737 conversion, so record them separately. */
2738 bfd_signed_vma maybe_thumb_refcount;
2740 /* How many of the recorded PLT accesses were from non-call relocations.
2741 This information is useful when deciding whether anything takes the
2742 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2743 non-call references to the function should resolve directly to the
2744 real runtime target. */
2747 /* Since PLT entries have variable size if the Thumb prologue is
2748 used, we need to record the index into .got.plt instead of
2749 recomputing it from the PLT offset. */
2750 bfd_signed_vma got_offset;
2751 };
2753 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
2754 struct arm_local_iplt_info
2755 {
2756 /* The information that is usually found in the generic ELF part of
2757 the hash table entry. */
2760 /* The information that is usually found in the ARM-specific part of
2761 the hash table entry. */
2764 /* A list of all potential dynamic relocations against this symbol. */
2766 };
2768 struct elf_arm_obj_tdata
2769 {
2772 /* tls_type for each local got entry. */
2775 /* GOTPLT entries for TLS descriptors. */
2778 /* Information for local symbols that need entries in .iplt. */
2781 /* Zero to warn when linking objects with incompatible enum sizes. */
2784 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2786 };
2788 #define elf_arm_tdata(bfd) \
2789 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
2791 #define elf32_arm_local_got_tls_type(bfd) \
2792 (elf_arm_tdata (bfd)->local_got_tls_type)
2794 #define elf32_arm_local_tlsdesc_gotent(bfd) \
2795 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2797 #define elf32_arm_local_iplt(bfd) \
2798 (elf_arm_tdata (bfd)->local_iplt)
2800 #define is_arm_elf(bfd) \
2801 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2802 && elf_tdata (bfd) != NULL \
2803 && elf_object_id (bfd) == ARM_ELF_DATA)
2805 static bfd_boolean
2807 {
2809 ARM_ELF_DATA);
2810 }
2812 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2814 /* Arm ELF linker hash entry. */
2815 struct elf32_arm_link_hash_entry
2816 {
2819 /* Track dynamic relocs copied for this symbol. */
2822 /* ARM-specific PLT information. */
2825 #define GOT_UNKNOWN 0
2826 #define GOT_NORMAL 1
2827 #define GOT_TLS_GD 2
2828 #define GOT_TLS_IE 4
2829 #define GOT_TLS_GDESC 8
2830 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
2833 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2838 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2839 starting at the end of the jump table. */
2840 bfd_vma tlsdesc_got;
2842 /* The symbol marking the real symbol location for exported thumb
2843 symbols with Arm stubs. */
2846 /* A pointer to the most recently used stub hash entry against this
2847 symbol. */
2849 };
2851 /* Traverse an arm ELF linker hash table. */
2852 #define elf32_arm_link_hash_traverse(table, func, info) \
2853 (elf_link_hash_traverse \
2854 (&(table)->root, \
2855 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
2856 (info)))
2858 /* Get the ARM elf linker hash table from a link_info structure. */
2859 #define elf32_arm_hash_table(info) \
2860 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2861 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
2863 #define arm_stub_hash_lookup(table, string, create, copy) \
2864 ((struct elf32_arm_stub_hash_entry *) \
2865 bfd_hash_lookup ((table), (string), (create), (copy)))
2867 /* Array to keep track of which stub sections have been created, and
2868 information on stub grouping. */
2869 struct map_stub
2870 {
2871 /* This is the section to which stubs in the group will be
2872 attached. */
2874 /* The stub section. */
2876 };
2878 #define elf32_arm_compute_jump_table_size(htab) \
2879 ((htab)->next_tls_desc_index * 4)
2881 /* ARM ELF linker hash table. */
2882 struct elf32_arm_link_hash_table
2883 {
2884 /* The main hash table. */
2887 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
2888 bfd_size_type thumb_glue_size;
2890 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
2891 bfd_size_type arm_glue_size;
2893 /* The size in bytes of section containing the ARMv4 BX veneers. */
2894 bfd_size_type bx_glue_size;
2896 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
2897 veneer has been populated. */
2900 /* The size in bytes of the section containing glue for VFP11 erratum
2901 veneers. */
2902 bfd_size_type vfp11_erratum_glue_size;
2904 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
2905 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
2906 elf32_arm_write_section(). */
2910 /* An arbitrary input BFD chosen to hold the glue sections. */
2913 /* Nonzero to output a BE8 image. */
2916 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
2917 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
2920 /* The relocation to use for R_ARM_TARGET2 relocations. */
2923 /* 0 = Ignore R_ARM_V4BX.
2924 1 = Convert BX to MOV PC.
2925 2 = Generate v4 interworing stubs. */
2928 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
2931 /* Whether we should fix the ARM1176 BLX immediate issue. */
2934 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
2937 /* What sort of code sequences we should look for which may trigger the
2938 VFP11 denorm erratum. */
2939 bfd_arm_vfp11_fix vfp11_fix;
2941 /* Global counter for the number of fixes we have emitted. */
2944 /* Nonzero to force PIC branch veneers. */
2947 /* The number of bytes in the initial entry in the PLT. */
2948 bfd_size_type plt_header_size;
2950 /* The number of bytes in the subsequent PLT etries. */
2951 bfd_size_type plt_entry_size;
2953 /* True if the target system is VxWorks. */
2956 /* True if the target system is Symbian OS. */
2959 /* True if the target system is Native Client. */
2962 /* True if the target uses REL relocations. */
2965 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
2966 bfd_vma next_tls_desc_index;
2968 /* How many R_ARM_TLS_DESC relocations were generated so far. */
2969 bfd_vma num_tls_desc;
2971 /* Short-cuts to get to dynamic linker sections. */
2975 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
2978 /* The offset into splt of the PLT entry for the TLS descriptor
2979 resolver. Special values are 0, if not necessary (or not found
2980 to be necessary yet), and -1 if needed but not determined
2981 yet. */
2982 bfd_vma dt_tlsdesc_plt;
2984 /* The offset into sgot of the GOT entry used by the PLT entry
2985 above. */
2986 bfd_vma dt_tlsdesc_got;
2988 /* Offset in .plt section of tls_arm_trampoline. */
2989 bfd_vma tls_trampoline;
2991 /* Data for R_ARM_TLS_LDM32 relocations. */
2992 union
2993 {
2994 bfd_signed_vma refcount;
2995 bfd_vma offset;
2998 /* Small local sym cache. */
3001 /* For convenience in allocate_dynrelocs. */
3004 /* The amount of space used by the reserved portion of the sgotplt
3005 section, plus whatever space is used by the jump slots. */
3006 bfd_vma sgotplt_jump_table_size;
3008 /* The stub hash table. */
3011 /* Linker stub bfd. */
3014 /* Linker call-backs. */
3018 /* Array to keep track of which stub sections have been created, and
3019 information on stub grouping. */
3022 /* Number of elements in stub_group. */
3025 /* Assorted information used by elf32_arm_size_stubs. */
3029 };
3031 /* Create an entry in an ARM ELF linker hash table. */
3037 {
3041 /* Allocate the structure if it has not already been allocated by a
3042 subclass. */
3049 /* Call the allocation method of the superclass. */
3054 {
3066 }
3069 }
3071 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3072 symbols. */
3074 static bfd_boolean
3076 {
3078 {
3079 bfd_size_type num_syms;
3080 bfd_size_type size;
3102 }
3104 }
3106 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3107 to input bfd ABFD. Create the information if it doesn't already exist.
3108 Return null if an allocation fails. */
3112 {
3123 }
3125 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3126 in ABFD's symbol table. If the symbol is global, H points to its
3127 hash table entry, otherwise H is null.
3129 Return true if the symbol does have PLT information. When returning
3130 true, point *ROOT_PLT at the target-independent reference count/offset
3131 union and *ARM_PLT at the ARM-specific information. */
3133 static bfd_boolean
3137 {
3141 {
3145 }
3157 }
3159 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3160 before it. */
3162 static bfd_boolean
3165 {
3171 }
3173 /* Return a pointer to the head of the dynamic reloc list that should
3174 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3175 ABFD's symbol table. Return null if an error occurs. */
3180 {
3182 {
3189 }
3190 else
3191 {
3192 /* Track dynamic relocs needed for local syms too.
3193 We really need local syms available to do this
3194 easily. Oh well. */
3204 }
3205 }
3207 /* Initialize an entry in the stub hash table. */
3213 {
3214 /* Allocate the structure if it has not already been allocated by a
3215 subclass. */
3217 {
3222 }
3224 /* Call the allocation method of the superclass. */
3227 {
3230 /* Initialize the local fields. */
3245 }
3248 }
3250 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3251 shortcuts to them in our hash table. */
3253 static bfd_boolean
3255 {
3262 /* BPABI objects never have a GOT, or associated sections. */
3270 }
3272 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3274 static bfd_boolean
3276 {
3281 flagword flags;
3289 {
3296 }
3299 {
3307 }
3310 {
3316 }
3318 }
3320 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3321 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3322 hash table. */
3324 static bfd_boolean
3326 {
3345 {
3350 {
3352 htab->plt_entry_size
3354 }
3355 else
3356 {
3357 htab->plt_header_size
3359 htab->plt_entry_size
3361 }
3362 }
3371 }
3373 /* Copy the extra info we tack onto an elf_link_hash_entry. */
3375 static void
3379 {
3386 {
3388 {
3392 /* Add reloc counts against the indirect sym to the direct sym
3393 list. Merge any entries against the same section. */
3395 {
3400 {
3405 }
3408 }
3410 }
3414 }
3417 {
3418 /* Copy over PLT info. */
3426 /* We should only allocate a function to .iplt once the final
3427 symbol information is known. */
3431 {
3434 }
3435 }
3438 }
3440 /* Create an ARM elf linker hash table. */
3444 {
3453 elf32_arm_link_hash_newfunc,
3455 ARM_ELF_DATA))
3456 {
3459 }
3462 #ifdef FOUR_WORD_PLT
3465 #else
3468 #endif
3474 {
3477 }
3480 }
3482 /* Free the derived linker hash table. */
3484 static void
3486 {
3492 }
3494 /* Determine if we're dealing with a Thumb only architecture. */
3496 static bfd_boolean
3498 {
3500 Tag_CPU_arch);
3510 Tag_CPU_arch_profile);
3513 }
3515 /* Determine if we're dealing with a Thumb-2 object. */
3517 static bfd_boolean
3519 {
3521 Tag_CPU_arch);
3523 }
3525 /* Determine what kind of NOPs are available. */
3527 static bfd_boolean
3529 {
3531 Tag_CPU_arch);
3536 }
3538 static bfd_boolean
3540 {
3542 Tag_CPU_arch);
3545 }
3547 static bfd_boolean
3549 {
3551 {
3565 }
3566 }
3568 /* Determine the type of stub needed, if any, for a call. */
3570 static enum elf32_arm_stub_type
3577 bfd_vma destination,
3581 {
3582 bfd_vma location;
3583 bfd_signed_vma branch_offset;
3605 /* Determine where the call point is. */
3612 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3613 are considering a function call relocation. */
3618 /* For TLS call relocs, it is the caller's responsibility to provide
3619 the address of the appropriate trampoline. */
3625 {
3630 else
3633 {
3636 /* Note when dealing with PLT entries: the main PLT stub is in
3637 ARM mode, so if the branch is in Thumb mode, another
3638 Thumb->ARM stub will be inserted later just before the ARM
3639 PLT stub. We don't take this extra distance into account
3640 here, because if a long branch stub is needed, we'll add a
3641 Thumb->Arm one and branch directly to the ARM PLT entry
3642 because it avoids spreading offset corrections in several
3643 places. */
3650 }
3651 }
3652 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3659 {
3660 /* Handle cases where:
3661 - this call goes too far (different Thumb/Thumb2 max
3662 distance)
3663 - it's a Thumb->Arm call and blx is not available, or it's a
3664 Thumb->Arm branch (not bl). A stub is needed in this case,
3665 but only if this call is not through a PLT entry. Indeed,
3666 PLT stubs handle mode switching already.
3667 */
3671 || (thumb2
3679 {
3681 {
3682 /* Thumb to thumb. */
3684 {
3686 /* PIC stubs. */
3689 /* V5T and above. Stub starts with ARM code, so
3690 we must be able to switch mode before
3691 reaching it, which is only possible for 'bl'
3692 (ie R_ARM_THM_CALL relocation). */
3693 ? arm_stub_long_branch_any_thumb_pic
3694 /* On V4T, use Thumb code only. */
3697 /* non-PIC stubs. */
3700 /* V5T and above. */
3701 ? arm_stub_long_branch_any_any
3702 /* V4T. */
3704 }
3705 else
3706 {
3708 /* PIC stub. */
3709 ? arm_stub_long_branch_thumb_only_pic
3710 /* non-PIC stub. */
3712 }
3713 }
3714 else
3715 {
3716 /* Thumb to arm. */
3720 {
3725 }
3727 stub_type =
3729 /* PIC stubs. */
3731 /* TLS PIC stubs */
3735 /* V5T PIC and above. */
3736 ? arm_stub_long_branch_any_arm_pic
3737 /* V4T PIC stub. */
3740 /* non-PIC stubs. */
3742 /* V5T and above. */
3743 ? arm_stub_long_branch_any_any
3744 /* V4T. */
3747 /* Handle v4t short branches. */
3752 }
3753 }
3754 }
3759 {
3761 {
3762 /* Arm to thumb. */
3767 {
3772 }
3774 /* We have an extra 2-bytes reach because of
3775 the mode change (bit 24 (H) of BLX encoding). */
3781 {
3783 /* PIC stubs. */
3785 /* V5T and above. */
3786 ? arm_stub_long_branch_any_thumb_pic
3787 /* V4T stub. */
3790 /* non-PIC stubs. */
3792 /* V5T and above. */
3793 ? arm_stub_long_branch_any_any
3794 /* V4T. */
3796 }
3797 }
3798 else
3799 {
3800 /* Arm to arm. */
3803 {
3804 stub_type =
3806 /* PIC stubs. */
3808 /* TLS PIC Stub */
3809 ? arm_stub_long_branch_any_tls_pic
3811 ? arm_stub_long_branch_arm_nacl_pic
3813 /* non-PIC stubs. */
3815 ? arm_stub_long_branch_arm_nacl
3817 }
3818 }
3819 }
3821 /* If a stub is needed, record the actual destination type. */
3826 }
3828 /* Build a name for an entry in the stub hash table. */
3836 {
3838 bfd_size_type len;
3841 {
3850 }
3851 else
3852 {
3864 }
3867 }
3869 /* Look up an entry in the stub hash. Stub entries are cached because
3870 creating the stub name takes a bit of time. */
3879 {
3887 /* If this input section is part of a group of sections sharing one
3888 stub section, then use the id of the first section in the group.
3889 Stub names need to include a section id, as there may well be
3890 more than one stub used to reach say, printf, and we need to
3891 distinguish between them. */
3898 {
3900 }
3901 else
3902 {
3915 }
3918 }
3920 /* Find or create a stub section. Returns a pointer to the stub section, and
3921 the section to which the stub section will be attached (in *LINK_SEC_P).
3922 LINK_SEC_P may be NULL. */
3927 {
3936 {
3939 {
3941 bfd_size_type len;
3957 }
3959 }
3965 }
3967 /* Add a new stub entry to the stub hash. Not all fields of the new
3968 stub entry are initialised. */
3974 {
3983 /* Enter this entry into the linker stub hash table. */
3987 {
3990 stub_name);
3992 }
3999 }
4001 /* Store an Arm insn into an output section not processed by
4002 elf32_arm_write_section. */
4004 static void
4007 {
4010 else
4012 }
4014 /* Store a 16-bit Thumb insn into an output section not processed by
4015 elf32_arm_write_section. */
4017 static void
4020 {
4023 else
4025 }
4027 /* If it's possible to change R_TYPE to a more efficient access
4028 model, return the new reloc type. */
4030 static unsigned
4033 {
4039 /* We do not support relaxations for Old TLS models. */
4041 {
4048 }
4051 }
4053 static bfd_reloc_status_type elf32_arm_final_link_relocate
4059 static unsigned int
4061 {
4063 {
4092 }
4093 }
4095 static bfd_boolean
4098 {
4099 #define MAXRELOCS 3
4106 bfd_vma sym_value;
4115 /* Massage our args to the form they really have. */
4127 /* We have to do less-strictly-aligned fixes last. */
4130 /* Make a note of the offset within the stubs for this entry. */
4136 /* This is the address of the stub destination. */
4146 {
4148 {
4150 {
4153 {
4154 /* We've borrowed the reloc_addend field to mean we should
4155 insert a condition code into this (Thumb-1 branch)
4156 instruction. See THUMB16_BCOND_INSN. */
4159 }
4162 }
4172 {
4175 }
4182 /* Handle cases where the target is encoded within the
4183 instruction. */
4185 {
4188 }
4202 }
4203 }
4207 /* Stub size has already been computed in arm_size_one_stub. Check
4208 consistency. */
4211 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
4215 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4216 in each stub. */
4224 {
4225 Elf_Internal_Rela rel;
4226 bfd_boolean unresolved_reloc;
4228 enum arm_st_branch_type branch_type
4239 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4240 template should refer back to the instruction after the original
4241 branch. */
4244 /* There may be unintended consequences if this is not true. */
4247 /* Note: _bfd_final_link_relocate doesn't handle these relocations
4248 properly. We should probably use this function unconditionally,
4249 rather than only for certain relocations listed in the enclosing
4250 conditional, for the sake of consistency. */
4257 }
4258 else
4259 {
4260 Elf_Internal_Rela rel;
4261 bfd_boolean unresolved_reloc;
4278 }
4281 #undef MAXRELOCS
4282 }
4284 /* Calculate the template, template size and instruction size for a stub.
4285 Return value is the instruction size. */
4287 static unsigned int
4291 {
4306 {
4308 {
4322 }
4323 }
4326 }
4328 /* As above, but don't actually build the stub. Just bump offset so
4329 we know stub section sizes. */
4331 static bfd_boolean
4334 {
4339 /* Massage our args to the form they really have. */
4356 }
4358 /* External entry points for sizing and building linker stubs. */
4360 /* Set up various things so that we can make a list of input sections
4361 for each output section included in the link. Returns -1 on error,
4362 0 when no stubs will be needed, and 1 on success. */
4364 int
4367 {
4373 bfd_size_type amt;
4381 /* Count the number of input BFDs and find the top input section id. */
4385 {
4390 {
4393 }
4394 }
4403 /* We can't use output_bfd->section_count here to find the top output
4404 section index as some sections may have been removed, and
4405 _bfd_strip_section_from_output doesn't renumber the indices. */
4409 {
4412 }
4421 /* For sections we aren't interested in, mark their entries with a
4422 value we can check later. */
4424 do
4431 {
4434 }
4437 }
4439 /* The linker repeatedly calls this function for each input section,
4440 in the order that input sections are linked into output sections.
4441 Build lists of input sections to determine groupings between which
4442 we may insert linker stubs. */
4444 void
4447 {
4454 {
4458 {
4459 /* Steal the link_sec pointer for our list. */
4460 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4461 /* This happens to make the list in reverse order,
4462 which we reverse later. */
4465 }
4466 }
4467 }
4469 /* See whether we can group stub sections together. Grouping stub
4470 sections may result in fewer stubs. More importantly, we need to
4471 put all .init* and .fini* stubs at the end of the .init or
4472 .fini output sections respectively, because glibc splits the
4473 _init and _fini functions into multiple parts. Putting a stub in
4474 the middle of a function is not a good idea. */
4476 static void
4478 bfd_size_type stub_group_size,
4479 bfd_boolean stubs_always_after_branch)
4480 {
4483 do
4484 {
4491 /* Reverse the list: we must avoid placing stubs at the
4492 beginning of the section because the beginning of the text
4493 section may be required for an interrupt vector in bare metal
4494 code. */
4495 #define NEXT_SEC PREV_SEC
4498 {
4499 /* Pop from tail. */
4503 /* Push on head. */
4506 }
4509 {
4513 bfd_vma end_of_next;
4517 {
4521 /* End of NEXT is too far from start, so stop. */
4523 /* Add NEXT to the group. */
4525 }
4527 /* OK, the size from the start to the start of CURR is less
4528 than stub_group_size and thus can be handled by one stub
4529 section. (Or the head section is itself larger than
4530 stub_group_size, in which case we may be toast.)
4531 We should really be keeping track of the total size of
4532 stubs added here, as stubs contribute to the final output
4533 section size. */
4534 do
4535 {
4537 /* Set up this stub group. */
4539 }
4542 /* But wait, there's more! Input sections up to stub_group_size
4543 bytes after the stub section can be handled by it too. */
4545 {
4549 {
4552 /* End of NEXT is too far from stubs, so stop. */
4554 /* Add NEXT to the stub group. */
4558 }
4559 }
4561 }
4562 }
4566 #undef PREV_SEC
4567 #undef NEXT_SEC
4568 }
4570 /* Comparison function for sorting/searching relocations relating to Cortex-A8
4571 erratum fix. */
4573 static int
4575 {
4583 else
4585 }
4590 /* Helper function to scan code for sequences which might trigger the Cortex-A8
4591 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
4592 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
4593 otherwise. */
4595 static bfd_boolean
4605 {
4618 {
4622 bfd_vma base_vma;
4641 {
4652 /* Span is entirely within a single 4KB region: skip scanning. */
4657 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4659 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4660 * The branch target is in the same 4KB region as the
4661 first half of the branch.
4662 * The instruction before the branch is a 32-bit
4663 length non-branch instruction. */
4665 {
4674 {
4675 /* Load the rest of the insn (in manual-friendly order). */
4678 /* Encoding T4: B<c>.W. */
4680 /* Encoding T1: BL<c>.W. */
4682 /* Encoding T2: BLX<c>.W. */
4684 /* Encoding T3: B<c>.W (not permitted in IT block). */
4687 }
4692 && insn_32bit
4693 && is_32bit_branch
4694 && last_was_32bit
4696 {
4700 bfd_vma target;
4712 {
4716 /* We don't care about the error returned from this
4717 function, only if there is glue or not. */
4724 /* Keep a simpler condition, for the sake of clarity. */
4730 {
4734 else
4736 }
4737 }
4739 /* Check if we have an offending branch instruction. */
4742 /* We've already made a stub for this instruction, e.g.
4743 it's a long branch or a Thumb->ARM stub. Assume that
4744 stub will suffice to work around the A8 erratum (see
4745 setting of always_after_branch above). */
4746 ;
4748 {
4757 }
4759 {
4779 }
4782 {
4785 /* The original instruction is a BL, but the target is
4786 an ARM instruction. If we were not making a stub,
4787 the BL would have been converted to a BLX. Use the
4788 BLX stub instead in that case. */
4791 {
4795 }
4796 /* Conversely, if the original instruction was
4797 BLX but the target is Thumb mode, use the BL
4798 stub. */
4801 {
4805 }
4810 /* If we found a relocation, use the proper destination,
4811 not the offset in the (unrelocated) instruction.
4812 Note this is always done if we switched the stub type
4813 above. */
4815 offset =
4818 /* If the stub will use a Thumb-mode branch to a
4819 PLT target, redirect it to the preceding Thumb
4820 entry point. */
4826 /* The BLX stub is ARM-mode code. Adjust the offset to
4827 take the different PC value (+8 instead of +4) into
4828 account. */
4833 {
4837 {
4843 }
4846 {
4847 /* If we're doing a subsequent scan,
4848 check if we've found the same fix as
4849 before, and try and reuse the stub
4850 name. */
4854 {
4858 }
4859 }
4862 {
4866 }
4878 num_a8_fixes++;
4879 }
4880 }
4881 }
4886 }
4887 }
4891 }
4898 }
4900 /* Determine and set the size of the stub section for a final link.
4902 The basic idea here is to examine all the relocations looking for
4903 PC-relative calls to a target that is unreachable with a "bl"
4904 instruction. */
4906 bfd_boolean
4910 bfd_signed_vma group_size,
4914 {
4915 bfd_size_type stub_group_size;
4916 bfd_boolean stubs_always_after_branch;
4927 {
4932 }
4934 /* Propagate mach to stub bfd, because it may not have been
4935 finalized when we created stub_bfd. */
4939 /* Stash our params away. */
4945 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
4946 as the first half of a 32-bit branch straddling two 4K pages. This is a
4947 crude way of enforcing that. */
4953 else
4957 {
4958 /* Default values. */
4959 /* Thumb branch range is +-4MB has to be used as the default
4960 maximum size (a given section can contain both ARM and Thumb
4961 code, so the worst case has to be taken into account).
4963 This value is 24K less than that, which allows for 2025
4964 12-byte stubs. If we exceed that, then we will fail to link.
4965 The user will have to relink with an explicit group size
4966 option. */
4968 }
4972 /* If we're applying the cortex A8 fix, we need to determine the
4973 program header size now, because we cannot change it later --
4974 that could alter section placements. Notice the A8 erratum fix
4975 ends up requiring the section addresses to remain unchanged
4976 modulo the page size. That's something we cannot represent
4977 inside BFD, and we don't want to force the section alignment to
4978 be the page size. */
4983 {
4994 {
5004 /* We'll need the symbol table in a second. */
5009 /* Walk over each section attached to the input bfd. */
5013 {
5016 /* If there aren't any relocs, then there's nothing more
5017 to do. */
5023 /* If this section is a link-once section that will be
5024 discarded, then don't create any stubs. */
5029 /* Get the relocs. */
5030 internal_relocs
5036 /* Now examine each relocation. */
5040 {
5045 bfd_vma sym_value;
5046 bfd_vma destination;
5059 {
5061 error_ret_free_internal:
5065 }
5069 hash = elf32_arm_hash_entry
5073 /* Only look for stubs on branch instructions, or
5074 non-relaxed TLSCALL */
5087 : (elf32_arm_local_got_tls_type
5092 /* Now determine the call target, its name, value,
5093 section. */
5101 {
5102 /* A non-relaxed TLS call. The target is the
5103 plt-resident trampoline and nothing to do
5104 with the symbol. */
5111 }
5113 {
5114 /* It's a local symbol. */
5118 {
5119 local_syms
5122 local_syms
5128 }
5137 else
5138 sym_sec =
5142 /* This is an undefined symbol. It can never
5143 be resolved. */
5153 sym_name
5157 }
5158 else
5159 {
5160 /* It's an external symbol. */
5168 {
5175 /* For a destination in a shared library,
5176 use the PLT stub as target address to
5177 decide whether a branch stub is
5178 needed. */
5183 {
5187 destination = (sym_value
5190 }
5195 }
5198 {
5199 /* For a shared library, use the PLT stub as
5200 target address to decide whether a long
5201 branch stub is needed.
5202 For absolute code, they cannot be handled. */
5210 {
5214 destination = (sym_value
5217 }
5218 else
5220 }
5221 else
5222 {
5225 }
5229 }
5231 do
5232 {
5233 /* Determine what (if any) linker stub is needed. */
5241 /* Support for grouping stub sections. */
5244 /* Get the name of this stub. */
5250 /* We've either created a stub for this reloc already,
5251 or we are about to. */
5254 stub_entry = arm_stub_hash_lookup
5258 {
5259 /* The proper stub has already been created. */
5263 }
5266 htab);
5268 {
5271 }
5286 {
5289 }
5291 /* For historical reasons, use the existing names for
5292 ARM-to-Thumb and Thumb-to-ARM stubs. */
5303 else
5305 sym_name);
5308 }
5311 /* Look for relocations which might trigger Cortex-A8
5312 erratum. */
5318 {
5324 {
5325 /* Found a candidate. Note we haven't checked the
5326 destination is within 4K here: if we do so (and
5327 don't create an entry in a8_relocs) we can't tell
5328 that a branch should have been relocated when
5329 scanning later. */
5331 {
5337 }
5347 num_a8_relocs++;
5348 }
5349 }
5350 }
5352 /* We're done with the internal relocs, free them. */
5355 }
5358 {
5359 /* Sort relocs which might apply to Cortex-A8 erratum. */
5364 /* Scan for branches which might trigger Cortex-A8 erratum. */
5371 }
5372 }
5380 /* OK, we've added some stubs. Find out the new size of the
5381 stub sections. */
5385 {
5386 /* Ignore non-stub sections. */
5391 }
5395 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5398 {
5405 stub_sec->size
5407 NULL);
5408 }
5411 /* Ask the linker to do its stuff. */
5413 }
5415 /* Add stubs for Cortex-A8 erratum fixes now. */
5417 {
5419 {
5432 {
5435 stub_name);
5437 }
5456 }
5458 /* Stash the Cortex-A8 erratum fix array for use later in
5459 elf32_arm_write_section(). */
5462 }
5463 else
5464 {
5467 }
5470 error_ret_free_local:
5472 }
5474 /* Build all the stubs associated with the current output file. The
5475 stubs are kept in a hash table attached to the main linker hash
5476 table. We also set up the .plt entries for statically linked PIC
5477 functions here. This function is called via arm_elf_finish in the
5478 linker. */
5480 bfd_boolean
5482 {
5494 {
5495 bfd_size_type size;
5497 /* Ignore non-stub sections. */
5501 /* Allocate memory to hold the linker stubs. */
5507 }
5509 /* Build the stubs as directed by the stub hash table. */
5513 {
5514 /* Place the cortex a8 stubs last. */
5517 }
5520 }
5522 /* Locate the Thumb encoded calling stub for NAME. */
5528 {
5533 /* We need a pointer to the armelf specific hash table. */
5545 hash = elf_link_hash_lookup
5556 }
5558 /* Locate the ARM encoded calling stub for NAME. */
5564 {
5569 /* We need a pointer to the elfarm specific hash table. */
5581 myh = elf_link_hash_lookup
5592 }
5594 /* ARM->Thumb glue (static images):
5596 .arm
5597 __func_from_arm:
5598 ldr r12, __func_addr
5599 bx r12
5600 __func_addr:
5601 .word func @ behave as if you saw a ARM_32 reloc.
5603 (v5t static images)
5604 .arm
5605 __func_from_arm:
5606 ldr pc, __func_addr
5607 __func_addr:
5608 .word func @ behave as if you saw a ARM_32 reloc.
5610 (relocatable images)
5611 .arm
5612 __func_from_arm:
5613 ldr r12, __func_offset
5614 add r12, r12, pc
5615 bx r12
5616 __func_offset:
5617 .word func - . */
5619 #define ARM2THUMB_STATIC_GLUE_SIZE 12
5624 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5628 #define ARM2THUMB_PIC_GLUE_SIZE 16
5633 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
5635 .thumb .thumb
5636 .align 2 .align 2
5637 __func_from_thumb: __func_from_thumb:
5638 bx pc push {r6, lr}
5639 nop ldr r6, __func_addr
5640 .arm mov lr, pc
5641 b func bx r6
5642 .arm
5643 ;; back_to_thumb
5644 ldmia r13! {r6, lr}
5645 bx lr
5646 __func_addr:
5647 .word func */
5649 #define THUMB2ARM_GLUE_SIZE 8
5654 #define VFP11_ERRATUM_VENEER_SIZE 8
5656 #define ARM_BX_VENEER_SIZE 12
5661 #ifndef ELFARM_NABI_C_INCLUDED
5662 static void
5664 {
5669 {
5670 /* Do not include empty glue sections in the output. */
5672 {
5676 }
5678 }
5689 }
5691 bfd_boolean
5693 {
5701 ARM2THUMB_GLUE_SECTION_NAME);
5705 THUMB2ARM_GLUE_SECTION_NAME);
5709 VFP11_ERRATUM_VENEER_SECTION_NAME);
5713 ARM_BX_GLUE_SECTION_NAME);
5716 }
5718 /* Allocate space and symbols for calling a Thumb function from Arm mode.
5719 returns the symbol identifying the stub. */
5724 {
5731 bfd_vma val;
5732 bfd_size_type size;
5738 s = bfd_get_linker_section
5750 myh = elf_link_hash_lookup
5754 {
5755 /* We've already seen this guy. */
5758 }
5760 /* The only trick here is using hash_table->arm_glue_size as the value.
5761 Even though the section isn't allocated yet, this is where we will be
5762 putting it. The +1 on the value marks that the stub has not been
5763 output yet - not that it is a Thumb function. */
5781 else
5788 }
5790 /* Allocate space for ARMv4 BX veneers. */
5792 static void
5794 {
5800 bfd_vma val;
5802 /* BX PC does not need a veneer. */
5810 /* Check if this veneer has already been allocated. */
5814 s = bfd_get_linker_section
5819 /* Add symbol for veneer. */
5827 myh = elf_link_hash_lookup
5845 }
5848 /* Add an entry to the code/data map for section SEC. */
5850 static void
5852 {
5857 {
5862 }
5867 {
5872 }
5875 {
5878 }
5879 }
5882 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
5883 veneers are handled for now. */
5885 static bfd_vma
5891 {
5897 bfd_vma val;
5905 s = bfd_get_linker_section
5920 myh = elf_link_hash_lookup
5935 /* Link veneer back to calling location. */
5949 /* A symbol for the return from the veneer. */
5953 myh = elf_link_hash_lookup
5970 /* Generate a mapping symbol for the veneer section, and explicitly add an
5971 entry for that symbol to the code/data map for the section. */
5973 {
5975 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
5976 ever requires this erratum fix. */
5986 /* The elf32_arm_init_maps function only cares about symbols from input
5987 BFDs. We must make a note of this generated mapping symbol
5988 ourselves so that code byteswapping works properly in
5989 elf32_arm_write_section. */
5991 }
5997 /* The offset of the veneer. */
5999 }
6001 #define ARM_GLUE_SECTION_FLAGS \
6002 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6003 | SEC_READONLY | SEC_LINKER_CREATED)
6005 /* Create a fake section for use by the ARM backend of the linker. */
6007 static bfd_boolean
6009 {
6014 /* Already made. */
6023 /* Set the gc mark to prevent the section from being removed by garbage
6024 collection, despite the fact that no relocs refer to this section. */
6028 }
6030 /* Add the glue sections to ABFD. This function is called from the
6031 linker scripts in ld/emultempl/{armelf}.em. */
6033 bfd_boolean
6036 {
6037 /* If we are only performing a partial
6038 link do not bother adding the glue. */
6046 }
6048 /* Select a BFD to be used to hold the sections used by the glue code.
6049 This function is called from the linker scripts in ld/emultempl/
6050 {armelf/pe}.em. */
6052 bfd_boolean
6054 {
6057 /* If we are only performing a partial link
6058 do not bother getting a bfd to hold the glue. */
6062 /* Make sure we don't attach the glue sections to a dynamic object. */
6071 /* Save the bfd for later use. */
6075 }
6077 static void
6079 {
6083 Tag_CPU_arch);
6086 {
6089 }
6090 else
6091 {
6094 }
6095 }
6097 bfd_boolean
6100 {
6109 /* If we are only performing a partial link do not bother
6110 to construct any glue. */
6114 /* Here we have a bfd that is to be included on the link. We have a
6115 hook to do reloc rummaging, before section sizes are nailed down. */
6122 {
6124 abfd);
6126 }
6128 /* PR 5398: If we have not decided to include any loadable sections in
6129 the output then we will not have a glue owner bfd. This is OK, it
6130 just means that there is nothing else for us to do here. */
6134 /* Rummage around all the relocs and map the glue vectors. */
6141 {
6150 /* Load the relocs. */
6151 internal_relocs
6159 {
6168 /* These are the only relocation types we care about. */
6173 /* Get the section contents if we haven't done so already. */
6175 {
6176 /* Get cached copy if it exists. */
6179 else
6180 {
6181 /* Go get them off disk. */
6184 }
6185 }
6188 {
6194 }
6196 /* If the relocation is not against a symbol it cannot concern us. */
6199 /* We don't care about local symbols. */
6203 /* This is an external symbol. */
6208 /* If the relocation is against a static symbol it must be within
6209 the current section and so cannot be a cross ARM/Thumb relocation. */
6213 /* If the call will go through a PLT entry then we do not need
6214 glue. */
6219 {
6221 /* This one is a call from arm code. We need to look up
6222 the target of the call. If it is a thumb target, we
6223 insert glue. */
6230 }
6231 }
6242 }
6246 error_return:
6255 }
6256 #endif
6259 /* Initialise maps of ARM/Thumb/data for input BFDs. */
6261 void
6263 {
6268 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6278 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6279 should contain the number of local symbols, which should come before any
6280 global symbols. Mapping symbols are always local. */
6282 NULL);
6284 /* No internal symbols read? Skip this BFD. */
6289 {
6296 {
6301 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
6303 }
6304 }
6305 }
6308 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6309 say what they wanted. */
6311 void
6313 {
6321 {
6322 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6327 else
6329 }
6330 }
6333 void
6335 {
6341 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6343 {
6345 {
6352 /* Give a warning, but do as the user requests anyway. */
6355 }
6356 }
6358 /* For earlier architectures, we might need the workaround, but do not
6359 enable it by default. If users is running with broken hardware, they
6360 must enable the erratum fix explicitly. */
6362 }
6365 enum bfd_arm_vfp11_pipe
6366 {
6367 VFP11_FMAC,
6368 VFP11_LS,
6369 VFP11_DS,
6370 VFP11_BAD
6371 };
6373 /* Return a VFP register number. This is encoded as RX:X for single-precision
6374 registers, or X:RX for double-precision registers, where RX is the group of
6375 four bits in the instruction encoding and X is the single extension bit.
6376 RX and X fields are specified using their lowest (starting) bit. The return
6377 value is:
6379 0...31: single-precision registers s0...s31
6380 32...63: double-precision registers d0...d31.
6382 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6383 encounter VFP3 instructions, so we allow the full range for DP registers. */
6385 static unsigned int
6388 {
6391 else
6393 }
6395 /* Set bits in *WMASK according to a register number REG as encoded by
6396 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6398 static void
6400 {
6405 }
6407 /* Return TRUE if WMASK overwrites anything in REGS. */
6409 static bfd_boolean
6411 {
6415 {
6428 }
6431 }
6433 /* In this function, we're interested in two things: finding input registers
6434 for VFP data-processing instructions, and finding the set of registers which
6435 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6436 hold the written set, so FLDM etc. are easy to deal with (we're only
6437 interested in 32 SP registers or 16 dp registers, due to the VFP version
6438 implemented by the chip in question). DP registers are marked by setting
6439 both SP registers in the write mask). */
6441 static enum bfd_arm_vfp11_pipe
6444 {
6449 {
6459 {
6481 vfp_binop:
6489 {
6494 {
6508 /* These instructions will not bounce due to underflow. */
6514 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6515 registers to cause the erratum in previous instructions. */
6521 {
6526 /* Only FCVTSD can underflow. */
6533 }
6538 }
6539 }
6544 }
6545 }
6546 /* Two-register transfer. */
6548 {
6552 {
6555 else
6556 {
6559 }
6560 }
6563 }
6565 {
6570 {
6577 {
6585 }
6595 }
6598 }
6599 /* Single-register transfer. Note L==0. */
6601 {
6606 {
6609 /* Mark fmdhr and fmdlr as writing to the whole of the DP
6610 destination register. I don't know if this is exactly right,
6611 but it is the conservative choice. */
6617 }
6620 }
6623 }
6629 /* Look for potentially-troublesome code sequences which might trigger the
6630 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
6631 (available from ARM) for details of the erratum. A short version is
6632 described in ld.texinfo. */
6634 bfd_boolean
6636 {
6647 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
6648 The states transition as follows:
6650 0 -> 1 (vector) or 0 -> 2 (scalar)
6651 A VFP FMAC-pipeline instruction has been seen. Fill
6652 regs[0]..regs[numregs-1] with its input operands. Remember this
6653 instruction in 'first_fmac'.
6655 1 -> 2
6656 Any instruction, except for a VFP instruction which overwrites
6657 regs[*].
6659 1 -> 3 [ -> 0 ] or
6660 2 -> 3 [ -> 0 ]
6661 A VFP instruction has been seen which overwrites any of regs[*].
6662 We must make a veneer! Reset state to 0 before examining next
6663 instruction.
6665 2 -> 0
6666 If we fail to match anything in state 2, reset to state 0 and reset
6667 the instruction pointer to the instruction after 'first_fmac'.
6669 If the VFP11 vector mode is in use, there must be at least two unrelated
6670 instructions between anti-dependent VFP11 instructions to properly avoid
6671 triggering the erratum, hence the use of the extra state 1. */
6673 /* If we are only performing a partial link do not bother
6674 to construct any glue. */
6678 /* Skip if this bfd does not correspond to an ELF image. */
6682 /* We should have chosen a fix type by the time we get here. */
6688 /* Skip this BFD if it corresponds to an executable or dynamic object. */
6693 {
6697 /* If we don't have executable progbits, we're not interested in this
6698 section. Also skip if section is to be excluded. */
6718 elf32_arm_compare_mapping);
6721 {
6727 /* FIXME: Only ARM mode is supported at present. We may need to
6728 support Thumb-2 mode also at some point. */
6733 {
6748 {
6752 /* I'm assuming the VFP11 erratum can trigger with denorm
6753 operands on either the FMAC or the DS pipeline. This might
6754 lead to slightly overenthusiastic veneer insertion. */
6756 {
6760 }
6764 {
6767 other_regs,
6771 numregs))
6773 else
6775 }
6779 {
6782 other_regs,
6786 numregs))
6788 else
6789 {
6792 }
6793 }
6798 }
6801 {
6810 {
6817 }
6820 first_fmac);
6828 }
6831 }
6832 }
6838 }
6842 error_return:
6848 }
6850 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
6851 after sections have been laid out, using specially-named symbols. */
6853 void
6856 {
6864 /* Skip if this bfd does not correspond to an ELF image. */
6876 {
6881 {
6883 bfd_vma vma;
6886 {
6889 /* Find veneer symbol. */
6893 myh = elf_link_hash_lookup
6909 /* Find return location. */
6913 myh = elf_link_hash_lookup
6929 }
6930 }
6931 }
6934 }
6937 /* Set target relocation values needed during linking. */
6939 void
6946 bfd_arm_vfp11_fix vfp11_fix,
6950 {
6964 else
6965 {
6967 target2_type);
6968 }
6979 }
6981 /* Replace the target offset of a Thumb bl or b.w instruction. */
6983 static void
6985 {
6986 bfd_vma upper;
6987 bfd_vma lower;
7004 }
7006 /* Thumb code calling an ARM function. */
7008 static int
7016 bfd_vma offset,
7017 bfd_signed_vma addend,
7018 bfd_vma val,
7020 {
7022 bfd_vma my_offset;
7038 THUMB2ARM_GLUE_SECTION_NAME);
7045 {
7049 {
7056 }
7067 ret_offset =
7068 /* Address of destination of the stub. */
7071 /* Offset from the start of the current section
7072 to the start of the stubs. */
7074 /* Offset of the start of this stub from the start of the stubs. */
7075 + my_offset
7076 /* Address of the start of the current section. */
7078 /* The branch instruction is 4 bytes into the stub. */
7080 /* ARM branches work from the pc of the instruction + 8. */
7086 }
7090 /* Now go back and fix up the original BL insn to point to here. */
7091 ret_offset =
7092 /* Address of where the stub is located. */
7094 /* Address of where the BL is located. */
7097 /* Addend in the relocation. */
7098 - addend
7099 /* Biassing for PC-relative addressing. */
7105 }
7107 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
7115 bfd_vma val,
7118 {
7119 bfd_vma my_offset;
7135 {
7139 {
7144 }
7151 {
7152 /* For relocatable objects we can't use absolute addresses,
7153 so construct the address from a relative offset. */
7154 /* TODO: If the offset is small it's probably worth
7155 constructing the address with adds. */
7162 /* Adjust the offset by 4 for the position of the add,
7163 and 8 for the pipeline offset. */
7170 }
7172 {
7176 /* It's a thumb address. Add the low order bit. */
7179 }
7180 else
7181 {
7188 /* It's a thumb address. Add the low order bit. */
7193 }
7194 }
7199 }
7201 /* Arm code calling a Thumb function. */
7203 static int
7211 bfd_vma offset,
7212 bfd_signed_vma addend,
7213 bfd_vma val,
7215 {
7217 bfd_vma my_offset;
7228 ARM2THUMB_GLUE_SECTION_NAME);
7242 /* Somehow these are both 4 too far, so subtract 8. */
7244 + my_offset
7256 }
7258 /* Populate Arm stub for an exported Thumb function. */
7260 static bfd_boolean
7262 {
7269 bfd_vma val;
7273 /* Allocate stubs for exported Thumb functions on v4t. */
7282 ARM2THUMB_GLUE_SECTION_NAME);
7300 }
7302 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
7304 static bfd_vma
7306 {
7308 bfd_vma glue_addr;
7317 ARM_BX_GLUE_SECTION_NAME);
7327 {
7333 }
7336 }
7338 /* Generate Arm stubs for exported Thumb symbols. */
7339 static void
7342 {
7346 /* Ignore this if we are not called by the ELF backend linker. */
7353 /* If blx is available then exported Thumb symbols are OK and there is
7354 nothing to do. */
7359 link_info);
7360 }
7362 /* Reserve space for COUNT dynamic relocations in relocation selection
7363 SRELOC. */
7365 static void
7367 bfd_size_type count)
7368 {
7376 }
7378 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
7379 dynamic, the relocations should go in SRELOC, otherwise they should
7380 go in the special .rel.iplt section. */
7382 static void
7384 bfd_size_type count)
7385 {
7391 else
7392 {
7395 }
7396 }
7398 /* Add relocation REL to the end of relocation section SRELOC. */
7400 static void
7403 {
7418 }
7420 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
7421 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
7422 to .plt. */
7424 static void
7426 bfd_boolean is_iplt_entry,
7429 {
7437 {
7441 /* NaCl uses a special first entry in .iplt too. */
7445 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
7447 }
7448 else
7449 {
7453 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
7456 /* If this is the first .plt entry, make room for the special
7457 first entry. */
7460 }
7462 /* Allocate the PLT entry itself, including any leading Thumb stub. */
7469 {
7470 /* We also need to make an entry in the .got.plt section, which
7471 will be placed in the .got section by the linker script. */
7474 }
7475 }
7477 static bfd_vma
7479 {
7481 }
7483 static bfd_vma
7485 {
7487 }
7489 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
7490 the entry lives in .iplt and resolves to (*SYM_VALUE)().
7491 Otherwise, DYNINDX is the index of the symbol in the dynamic
7492 symbol table and SYM_VALUE is undefined.
7494 ROOT_PLT points to the offset of the PLT entry from the start of its
7495 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
7496 bookkeeping information. */
7498 static void
7503 {
7509 bfd_vma plt_index;
7510 Elf_Internal_Rela rel;
7511 bfd_vma plt_header_size;
7512 bfd_vma got_header_size;
7516 /* Pick the appropriate sections and sizes. */
7518 {
7523 /* There are no reserved entries in .igot.plt, and no special
7524 first entry in .iplt. */
7527 }
7528 else
7529 {
7536 }
7539 /* Fill in the entry in the procedure linkage table. */
7541 {
7550 /* Fill in the entry in the .rel.plt section. */
7556 /* Get the index in the procedure linkage table which
7557 corresponds to this symbol. This is the index of this symbol
7558 in all the symbols for which we are making plt entries. The
7559 first entry in the procedure linkage table is reserved. */
7562 }
7563 else
7564 {
7571 /* Get the offset into the .(i)got.plt table of the entry that
7572 corresponds to this function. */
7575 /* Get the index in the procedure linkage table which
7576 corresponds to this symbol. This is the index of this symbol
7577 in all the symbols for which we are making plt entries.
7578 After the reserved .got.plt entries, all symbols appear in
7579 the same order as in .plt. */
7582 /* Calculate the address of the GOT entry. */
7587 /* ...and the address of the PLT entry. */
7594 {
7596 bfd_vma val;
7599 {
7607 else
7609 }
7610 }
7612 {
7614 bfd_vma val;
7617 {
7627 else
7629 }
7634 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
7635 referencing the GOT for this PLT entry. */
7642 /* Create the R_ARM_ABS32 relocation referencing the
7643 beginning of the PLT for this GOT entry. */
7648 }
7650 {
7651 /* Calculate the displacement between the PLT slot and the
7652 common tail that's part of the special initial PLT slot. */
7653 int32_t tail_displacement
7663 /* Calculate the displacement between the PLT slot and the entry
7664 in the GOT. The offset accounts for the value produced by
7665 adding to pc in the penultimate instruction of the PLT stub. */
7666 got_displacement = (got_address
7669 /* NaCl does not support interworking at all. */
7687 }
7688 else
7689 {
7690 /* Calculate the displacement between the PLT slot and the
7691 entry in the GOT. The eight-byte offset accounts for the
7692 value produced by adding to pc in the first instruction
7693 of the PLT stub. */
7699 {
7704 }
7718 #ifdef FOUR_WORD_PLT
7720 #endif
7721 }
7723 /* Fill in the entry in the .rel(a).(i)plt section. */
7727 {
7728 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
7729 The dynamic linker or static executable then calls SYM_VALUE
7730 to determine the correct run-time value of the .igot.plt entry. */
7733 }
7734 else
7735 {
7739 }
7741 /* Fill in the entry in the global offset table. */
7744 }
7748 else
7749 {
7752 }
7753 }
7755 /* Some relocations map to different relocations depending on the
7756 target. Return the real relocation. */
7758 static int
7761 {
7763 {
7767 else
7775 }
7776 }
7778 /* Return the base VMA address which should be subtracted from real addresses
7779 when resolving @dtpoff relocation.
7780 This is PT_TLS segment p_vaddr. */
7782 static bfd_vma
7784 {
7785 /* If tls_sec is NULL, we should have signalled an error already. */
7789 }
7791 /* Return the relocation value for @tpoff relocation
7792 if STT_TLS virtual address is ADDRESS. */
7794 static bfd_vma
7796 {
7798 bfd_vma base;
7800 /* If tls_sec is NULL, we should have signalled an error already. */
7805 }
7807 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
7808 VALUE is the relocation value. */
7810 static bfd_reloc_status_type
7812 {
7819 }
7821 /* Handle TLS relaxations. Relaxing is possible for symbols that use
7822 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
7823 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
7825 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
7826 is to then call final_link_relocate. Return other values in the
7827 case of error.
7829 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
7830 the pre-relaxed code. It would be nice if the relocs were updated
7831 to match the optimization. */
7833 static bfd_reloc_status_type
7837 {
7841 {
7848 else
7849 {
7853 else
7855 }
7860 /* Thumb insn. */
7863 {
7865 /* nop */
7867 }
7869 {
7871 /* nop */
7873 else
7874 /* ldr rx,[ry] */
7876 }
7878 {
7880 /* nop */
7882 else
7883 /* mov r0, rx */
7886 }
7887 else
7888 {
7890 /* It's a 32 bit instruction, fetch the rest of it for
7891 error generation. */
7898 }
7902 /* arm insn. */
7905 {
7907 /* mov rx, ry */
7910 }
7912 {
7914 /* nop */
7916 else
7917 /* ldr rx,[ry] */
7920 }
7922 {
7924 /* nop */
7926 else
7927 /* mov r0, rx */
7930 }
7931 else
7932 {
7937 }
7941 /* GD->IE relaxation, turn the instruction into 'nop' or
7942 'ldr r0, [pc,r0]' */
7948 /* GD->IE relaxation */
7950 /* add r0,pc; ldr r0, [r0] */
7953 /* nop.w */
7955 else
7956 /* nop; nop */
7962 }
7964 }
7966 /* For a given value of n, calculate the value of G_n as required to
7967 deal with group relocations. We return it in the form of an
7968 encoded constant-and-rotation, together with the final residual. If n is
7969 specified as less than zero, then final_residual is filled with the
7970 input value and no further action is performed. */
7972 static bfd_vma
7974 {
7976 bfd_vma g_n;
7981 {
7984 /* Calculate which part of the value to mask. */
7987 else
7988 {
7991 /* Determine the most significant bit in the residual and
7992 align the resulting value to a 2-bit boundary. */
7997 /* The desired shift is now (msb - 6), or zero, whichever
7998 is the greater. */
8002 }
8004 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
8009 /* Calculate the residual for the next time around. */
8011 }
8016 }
8018 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
8019 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
8021 static int
8023 {
8033 }
8035 /* Perform a relocation as part of a final link. */
8037 static bfd_reloc_status_type
8044 bfd_vma value,
8053 {
8063 bfd_vma addend;
8064 bfd_signed_vma signed_addend;
8066 bfd_vma dynreloc_value;
8071 bfd_vma plt_offset;
8072 bfd_vma gotplt_offset;
8073 bfd_boolean has_iplt_entry;
8081 /* Some relocation types map to different relocations depending on the
8082 target. We pick the right one here. */
8085 /* It is possible to have linker relaxations on some TLS access
8086 models. Update our information here. */
8092 /* If the start address has been set, then set the EF_ARM_HASENTRY
8093 flag. Setting this more than once is redundant, but the cost is
8094 not too high, and it keeps the code simple.
8096 The test is done here, rather than somewhere else, because the
8097 start address is only set just before the final link commences.
8099 Note - if the user deliberately sets a start address of 0, the
8100 flag will not be set. */
8111 else
8117 {
8121 {
8125 }
8126 else
8128 }
8129 else
8132 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
8133 are resolving a function call relocation. */
8140 /* Record the symbol information that should be used in dynamic
8141 relocations. */
8147 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
8148 VALUE appropriately for relocations that we resolve at link time. */
8152 {
8157 {
8161 /* Populate .iplt entries here, because not all of them will
8162 be seen by finish_dynamic_symbol. The lower bit is set if
8163 we have already populated the entry. */
8165 plt_offset--;
8166 else
8167 {
8171 }
8173 /* Static relocations always resolve to the .iplt entry. */
8180 /* If there are non-call relocations that resolve to the .iplt
8181 entry, then all dynamic ones must too. */
8183 {
8186 }
8187 }
8188 else
8189 /* We populate the .plt entry in finish_dynamic_symbol. */
8191 }
8192 else
8193 {
8197 }
8200 {
8202 /* We don't need to find a value for this symbol. It's just a
8203 marker. */
8221 /* Handle relocations which should use the PLT entry. ABS32/REL32
8222 will use the symbol's value, which may point to a PLT entry, but we
8223 don't need to handle that here. If we created a PLT entry, all
8224 branches in this object should go to it, except if the PLT is too
8225 far away, in which case a long branch stub should be inserted. */
8232 {
8233 /* If we've created a .plt section, and assigned a PLT entry
8234 to this function, it must either be a STT_GNU_IFUNC reference
8235 or not be known to bind locally. In other cases, we should
8236 have cleared the PLT entry by now. */
8246 }
8248 /* When generating a shared object or relocatable executable, these
8249 relocations are copied into the output file to be resolved at
8250 run time. */
8268 {
8269 Elf_Internal_Rela outrel;
8275 {
8281 }
8305 else
8306 {
8309 /* This symbol is local, or marked to become local. */
8312 {
8315 /* On Symbian OS, the data segment and text segement
8316 can be relocated independently. Therefore, we
8317 must indicate the segment to which this
8318 relocation is relative. The BPABI allows us to
8319 use any symbol in the right segment; we just use
8320 the section symbol as it is convenient. (We
8321 cannot use the symbol given by "h" directly as it
8322 will not appear in the dynamic symbol table.)
8324 Note that the dynamic linker ignores the section
8325 symbol value, so we don't subtract osec->vma
8326 from the emitted reloc addend. */
8329 else
8333 {
8339 else
8342 }
8344 }
8345 else
8346 /* On SVR4-ish systems, the dynamic loader cannot
8347 relocate the text and data segments independently,
8348 so the symbol does not matter. */
8351 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
8352 to the .iplt entry. Instead, every non-call reference
8353 must use an R_ARM_IRELATIVE relocation to obtain the
8354 correct run-time address. */
8356 else
8360 else
8362 }
8366 /* If this reloc is against an external symbol, we do not want to
8367 fiddle with the addend. Otherwise, we need to include the symbol
8368 value so that it becomes an addend for the dynamic reloc. */
8375 }
8377 {
8386 {
8390 {
8391 /* Check for Arm calling Arm function. */
8392 /* FIXME: Should we translate the instruction into a BL
8393 instruction instead ? */
8397 input_bfd,
8399 }
8401 {
8402 /* Check for Arm calling Thumb function. */
8404 {
8409 error_message))
8411 else
8413 }
8414 }
8416 /* Check if a stub has to be inserted because the
8417 destination is too far or we are changing mode. */
8421 {
8432 {
8433 /* The target is out of reach, so redirect the
8434 branch to the local stub for this function. */
8438 stub_type);
8439 {
8447 }
8448 }
8449 else
8450 {
8451 /* If the call goes through a PLT entry, make sure to
8452 check distance to the right destination address. */
8454 {
8459 /* The PLT entry is in ARM mode, regardless of the
8460 target function. */
8462 }
8463 }
8464 }
8466 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
8467 where:
8468 S is the address of the symbol in the relocation.
8469 P is address of the instruction being relocated.
8470 A is the addend (extracted from the instruction) in bytes.
8472 S is held in 'value'.
8473 P is the base address of the section containing the
8474 instruction plus the offset of the reloc into that
8475 section, ie:
8476 (input_section->output_section->vma +
8477 input_section->output_offset +
8478 rel->r_offset).
8479 A is the addend, converted into bytes, ie:
8480 (signed_addend * 4)
8482 Note: None of these operations have knowledge of the pipeline
8483 size of the processor, thus it is up to the assembler to
8484 encode this information into the addend. */
8490 else
8491 /* RELA addends do not have to be adjusted by howto->size. */
8497 /* A branch to an undefined weak symbol is turned into a jump to
8498 the next instruction unless a PLT entry will be created.
8499 Do the same for local undefined symbols (but not for STN_UNDEF).
8500 The jump to the next instruction is optimized as a NOP depending
8501 on the architecture. */
8505 {
8510 else
8512 }
8513 else
8514 {
8515 /* Perform a signed range check. */
8526 {
8527 /* Set the H bit in the BLX instruction. */
8529 {
8532 else
8534 }
8536 /* Select the correct instruction (BL or BLX). */
8537 /* Only if we are not handling a BL to a stub. In this
8538 case, mode switching is performed by the stub. */
8542 {
8545 }
8546 }
8547 }
8548 }
8580 {
8581 /* Check for overflow. */
8584 }
8590 }
8598 /* There is no way to tell whether the user intended to use a signed or
8599 unsigned addend. When checking for overflow we accept either,
8600 as specified by the AAELF. */
8610 /* See comment for R_ARM_ABS8. */
8618 /* Support ldr and str instructions for the thumb. */
8620 {
8621 /* Need to refetch addend. */
8623 /* ??? Need to determine shift amount from operand size. */
8625 }
8628 /* ??? Isn't value unsigned? */
8632 /* ??? Value needs to be properly shifted into place first. */
8638 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
8639 {
8640 bfd_vma insn;
8641 bfd_signed_vma relocation;
8647 {
8652 }
8674 }
8677 /* PR 10073: This reloc is not generated by the GNU toolchain,
8678 but it is supported for compatibility with third party libraries
8679 generated by other compilers, specifically the ARM/IAR. */
8680 {
8681 bfd_vma insn;
8682 bfd_signed_vma relocation;
8696 /* We do not check for overflow of this reloc. Although strictly
8697 speaking this is incorrect, it appears to be necessary in order
8698 to work with IAR generated relocs. Since GCC and GAS do not
8699 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
8700 a problem for them. */
8708 }
8711 /* Corresponds to: ldr.w reg, [pc, #offset]. */
8712 {
8713 bfd_vma insn;
8714 bfd_signed_vma relocation;
8720 {
8724 }
8744 }
8749 /* Thumb BL (branch long instruction). */
8750 {
8751 bfd_vma relocation;
8752 bfd_vma reloc_sign;
8756 bfd_signed_vma reloc_signed_max;
8757 bfd_signed_vma reloc_signed_min;
8758 bfd_vma check;
8759 bfd_signed_vma signed_check;
8763 /* A branch to an undefined weak symbol is turned into a jump to
8764 the next instruction unless a PLT entry will be created.
8765 The jump to the next instruction is optimized as a NOP.W for
8766 Thumb-2 enabled architectures. */
8769 {
8771 {
8774 }
8775 else
8776 {
8779 }
8781 }
8783 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
8784 with Thumb-1) involving the J1 and J2 bits. */
8786 {
8796 /* Sign extend. */
8800 }
8803 {
8804 /* Check for Thumb to Thumb call. */
8805 /* FIXME: Should we translate the instruction into a BL
8806 instruction instead ? */
8810 input_bfd,
8812 }
8813 else
8814 {
8815 /* If it is not a call to Thumb, assume call to Arm.
8816 If it is a call relative to a section name, then it is not a
8817 function call at all, but rather a long jump. Calls through
8818 the PLT do not require stubs. */
8820 {
8822 {
8823 /* Convert BL to BLX. */
8825 }
8828 {
8832 error_message))
8834 else
8836 }
8837 }
8841 {
8842 /* Make sure this is a BL. */
8844 }
8845 }
8849 {
8850 /* Check if a stub has to be inserted because the destination
8851 is too far. */
8863 {
8864 /* The target is out of reach or we are changing modes, so
8865 redirect the branch to the local stub for this
8866 function. */
8870 stub_type);
8872 {
8879 }
8881 /* If this call becomes a call to Arm, force BLX. */
8883 {
8888 }
8889 }
8890 }
8892 /* Handle calls via the PLT. */
8894 {
8900 {
8901 /* If the Thumb BLX instruction is available, convert
8902 the BL to a BLX instruction to call the ARM-mode
8903 PLT entry. */
8906 }
8907 else
8908 {
8909 /* Target the Thumb stub before the ARM PLT entry. */
8912 }
8914 }
8924 /* If this is a signed value, the rightshift just dropped
8925 leading 1 bits (assuming twos complement). */
8928 else
8931 /* Calculate the permissable maximum and minimum values for
8932 this relocation according to whether we're relocating for
8933 Thumb-2 or not. */
8940 /* Assumes two's complement. */
8945 /* For a BLX instruction, make sure that the relocation is rounded up
8946 to a word boundary. This follows the semantics of the instruction
8947 which specifies that bit 1 of the target address will come from bit
8948 1 of the base address. */
8951 /* Put RELOCATION back into the insn. Assumes two's complement.
8952 We use the Thumb-2 encoding, which is safe even if dealing with
8953 a Thumb-1 instruction by virtue of our overflow check above. */
8963 /* Put the relocated value back in the object file: */
8968 }
8972 /* Thumb32 conditional branch instruction. */
8973 {
8974 bfd_vma relocation;
8980 bfd_signed_vma signed_check;
8982 /* Need to refetch the addend, reconstruct the top three bits,
8983 and squish the two 11 bit pieces together. */
8985 {
8999 }
9001 /* Handle calls via the PLT. */
9003 {
9007 /* Target the Thumb stub before the ARM PLT entry. */
9010 }
9012 /* ??? Should handle interworking? GCC might someday try to
9013 use this for tail calls. */
9024 /* Put RELOCATION back into the insn. */
9025 {
9034 }
9036 /* Put the relocated value back in the object file: */
9041 }
9046 /* Thumb B (branch) instruction). */
9047 {
9048 bfd_signed_vma relocation;
9051 bfd_signed_vma signed_check;
9053 /* CZB cannot jump backward. */
9058 {
9059 /* Need to refetch addend. */
9062 {
9066 }
9067 else
9069 /* The value in the insn has been right shifted. We need to
9070 undo this, so that we can perform the address calculation
9071 in terms of bytes. */
9073 }
9085 else
9091 /* Assumes two's complement. */
9096 }
9101 {
9102 bfd_vma insn;
9103 bfd_vma relocation;
9107 {
9108 /* Extract the addend. */
9111 }
9121 }
9129 /* Relocation is relative to the start of the
9130 global offset table. */
9136 /* If we are addressing a Thumb function, we need to adjust the
9137 address by one, so that attempts to call the function pointer will
9138 correctly interpret it as Thumb code. */
9142 /* Note that sgot->output_offset is not involved in this
9143 calculation. We always want the start of .got. If we
9144 define _GLOBAL_OFFSET_TABLE in a different way, as is
9145 permitted by the ABI, we might have to change this
9146 calculation. */
9153 /* Use global offset table as symbol value. */
9167 /* Relocation is to the entry for this symbol in the
9168 global offset table. */
9175 {
9176 /* We have a relocation against a locally-binding STT_GNU_IFUNC
9177 symbol, and the relocation resolves directly to the runtime
9178 target rather than to the .iplt entry. This means that any
9179 .got entry would be the same value as the .igot.plt entry,
9180 so there's no point creating both. */
9183 }
9185 {
9186 bfd_vma off;
9191 {
9192 /* We have already processsed one GOT relocation against
9193 this symbol. */
9198 }
9199 else
9200 {
9201 Elf_Internal_Rela outrel;
9204 {
9205 /* If the symbol doesn't resolve locally in a static
9206 object, we have an undefined reference. If the
9207 symbol doesn't resolve locally in a dynamic object,
9208 it should be resolved by the dynamic linker. */
9210 {
9213 }
9214 else
9217 }
9218 else
9219 {
9226 else
9229 }
9231 /* The GOT entry is initialized to zero by default.
9232 See if we should install a different value. */
9235 {
9239 }
9242 {
9247 }
9249 }
9251 }
9252 else
9253 {
9254 bfd_vma off;
9261 /* The offset must always be a multiple of 4. We use the
9262 least significant bit to record whether we have already
9263 generated the necessary reloc. */
9266 else
9267 {
9272 {
9273 Elf_Internal_Rela outrel;
9281 else
9284 }
9287 }
9290 }
9306 {
9307 bfd_vma off;
9316 else
9317 {
9318 /* If we don't know the module number, create a relocation
9319 for it. */
9321 {
9322 Elf_Internal_Rela outrel;
9337 }
9338 else
9342 }
9350 }
9359 {
9367 {
9368 bfd_boolean dyn;
9373 {
9376 }
9380 }
9381 else
9382 {
9387 }
9389 /* Linker relaxations happens from one of the
9390 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
9398 else
9399 {
9401 Elf_Internal_Rela outrel;
9404 /* The GOT entries have not been initialized yet. Do it
9405 now, and emit any relocations. If both an IE GOT and a
9406 GD GOT are necessary, we emit the GD first. */
9412 {
9415 }
9418 {
9421 /* We should have relaxed, unless this is an undefined
9422 weak symbol. */
9431 + offplt
9443 /* For globals, the first word in the relocation gets
9444 the relocation index and the top bit set, or zero,
9445 if we're binding now. For locals, it gets the
9446 symbol's offset in the tls section. */
9454 /* Second word in the relocation is always zero. */
9458 }
9460 {
9462 {
9478 else
9479 {
9482 R_ARM_TLS_DTPOFF32);
9491 }
9492 }
9493 else
9494 {
9495 /* If we are not emitting relocations for a
9496 general dynamic reference, then we must be in a
9497 static link or an executable link with the
9498 symbol binding locally. Mark it as belonging
9499 to module 1, the executable. */
9504 }
9507 }
9510 {
9512 {
9515 else
9527 }
9528 else
9532 }
9536 else
9538 }
9547 {
9548 bfd_signed_vma offset;
9549 /* TLS stubs are arm mode. The original symbol is a
9550 data object, so branch_type is bogus. */
9552 enum elf32_arm_stub_type stub_type
9560 {
9562 = elf32_arm_get_stub_entry
9568 }
9569 else
9575 {
9585 }
9586 else
9587 {
9588 /* Thumb blx encodes the offset in a complicated
9589 fashion. */
9599 {
9601 }
9602 else
9603 {
9605 /* Round up the offset to a word boundary */
9607 }
9619 }
9620 }
9621 /* These relocations needs special care, as besides the fact
9622 they point somewhere in .gotplt, the addend must be
9623 adjusted accordingly depending on the type of instruction
9624 we refer to */
9626 {
9635 {
9642 /* bl/blx */
9645 /* add */
9647 else
9648 {
9654 }
9655 }
9656 else
9657 {
9661 {
9677 }
9678 }
9686 }
9687 else
9696 }
9700 {
9706 }
9707 else
9716 {
9719 /* Ensure that we have a BX instruction. */
9723 {
9724 /* Branch to veneer. */
9725 bfd_vma glue_addr;
9732 }
9733 else
9734 {
9735 /* Preserve Rm (lowest four bits) and the condition code
9736 (highest four bits). Other bits encode MOV PC,Rm. */
9738 }
9741 }
9748 /* Until we properly support segment-base-relative addressing then
9749 we assume the segment base to be zero, as for the group relocations.
9750 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
9751 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
9755 {
9759 {
9762 }
9784 }
9791 /* Until we properly support segment-base-relative addressing then
9792 we assume the segment base to be zero, as for the above relocations.
9793 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
9794 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
9795 as R_ARM_THM_MOVT_ABS. */
9799 {
9800 bfd_vma insn;
9806 {
9812 }
9838 }
9851 {
9855 /* sb is the origin of the *segment* containing the symbol. */
9857 bfd_vma residual;
9858 bfd_vma g_n;
9859 bfd_signed_vma signed_value;
9862 /* Determine which group of bits to select. */
9864 {
9886 }
9888 /* If REL, extract the addend from the insn. If RELA, it will
9889 have already been fetched for us. */
9891 {
9898 else
9899 {
9900 /* Compensate for the fact that in the instruction, the
9901 rotation is stored in multiples of 2 bits. */
9904 /* Rotate "constant" right by "rotation" bits. */
9907 }
9909 /* Determine if the instruction is an ADD or a SUB.
9910 (For REL, this determines the sign of the addend.) */
9913 {
9919 }
9922 }
9924 /* Compute the value (X) to go in the place. */
9930 /* PC relative. */
9932 else
9933 /* Section base relative. */
9936 /* If the target symbol is a Thumb function, then set the
9937 Thumb bit in the address. */
9941 /* Calculate the value of the relevant G_n, in encoded
9942 constant-with-rotation format. */
9946 /* Check for overflow if required. */
9953 {
9959 }
9961 /* Mask out the value and the ADD/SUB part of the opcode; take care
9962 not to destroy the S bit. */
9965 /* Set the opcode according to whether the value to go in the
9966 place is negative. */
9969 else
9972 /* Encode the offset. */
9976 }
9985 {
9989 /* sb is the origin of the *segment* containing the symbol. */
9991 bfd_vma residual;
9992 bfd_signed_vma signed_value;
9995 /* Determine which groups of bits to calculate. */
9997 {
10015 }
10017 /* If REL, extract the addend from the insn. If RELA, it will
10018 have already been fetched for us. */
10020 {
10023 }
10025 /* Compute the value (X) to go in the place. */
10029 /* PC relative. */
10031 else
10032 /* Section base relative. */
10035 /* Calculate the value of the relevant G_{n-1} to obtain
10036 the residual at that stage. */
10039 /* Check for overflow. */
10041 {
10047 }
10049 /* Mask out the value and U bit. */
10052 /* Set the U bit if the value to go in the place is non-negative. */
10056 /* Encode the offset. */
10060 }
10069 {
10073 /* sb is the origin of the *segment* containing the symbol. */
10075 bfd_vma residual;
10076 bfd_signed_vma signed_value;
10079 /* Determine which groups of bits to calculate. */
10081 {
10099 }
10101 /* If REL, extract the addend from the insn. If RELA, it will
10102 have already been fetched for us. */
10104 {
10107 }
10109 /* Compute the value (X) to go in the place. */
10113 /* PC relative. */
10115 else
10116 /* Section base relative. */
10119 /* Calculate the value of the relevant G_{n-1} to obtain
10120 the residual at that stage. */
10123 /* Check for overflow. */
10125 {
10131 }
10133 /* Mask out the value and U bit. */
10136 /* Set the U bit if the value to go in the place is non-negative. */
10140 /* Encode the offset. */
10144 }
10153 {
10157 /* sb is the origin of the *segment* containing the symbol. */
10159 bfd_vma residual;
10160 bfd_signed_vma signed_value;
10163 /* Determine which groups of bits to calculate. */
10165 {
10183 }
10185 /* If REL, extract the addend from the insn. If RELA, it will
10186 have already been fetched for us. */
10188 {
10191 }
10193 /* Compute the value (X) to go in the place. */
10197 /* PC relative. */
10199 else
10200 /* Section base relative. */
10203 /* Calculate the value of the relevant G_{n-1} to obtain
10204 the residual at that stage. */
10207 /* Check for overflow. (The absolute value to go in the place must be
10208 divisible by four and, after having been divided by four, must
10209 fit in eight bits.) */
10211 {
10217 }
10219 /* Mask out the value and U bit. */
10222 /* Set the U bit if the value to go in the place is non-negative. */
10226 /* Encode the offset. */
10230 }
10235 }
10236 }
10238 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
10239 static void
10243 bfd_signed_vma increment)
10244 {
10245 bfd_signed_vma addend;
10249 {
10267 }
10268 else
10269 {
10270 bfd_vma contents;
10274 /* Get the (signed) value from the instruction. */
10277 {
10278 bfd_signed_vma mask;
10283 }
10285 /* Add in the increment, (which is a byte value). */
10287 {
10299 /* Should we check for overflow here ? */
10301 /* Drop any undesired bits. */
10304 }
10309 }
10310 }
10312 #define IS_ARM_TLS_RELOC(R_TYPE) \
10313 ((R_TYPE) == R_ARM_TLS_GD32 \
10314 || (R_TYPE) == R_ARM_TLS_LDO32 \
10315 || (R_TYPE) == R_ARM_TLS_LDM32 \
10316 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
10317 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
10318 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
10319 || (R_TYPE) == R_ARM_TLS_LE32 \
10320 || (R_TYPE) == R_ARM_TLS_IE32 \
10321 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
10323 /* Specific set of relocations for the gnu tls dialect. */
10324 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
10325 ((R_TYPE) == R_ARM_TLS_GOTDESC \
10326 || (R_TYPE) == R_ARM_TLS_CALL \
10327 || (R_TYPE) == R_ARM_THM_TLS_CALL \
10328 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
10329 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
10331 /* Relocate an ARM ELF section. */
10333 static bfd_boolean
10342 {
10360 {
10367 bfd_vma relocation;
10368 bfd_reloc_status_type r;
10369 arelent bfd_reloc;
10390 {
10395 /* An object file might have a reference to a local
10396 undefined symbol. This is a daft object file, but we
10397 should at least do something about it. V4BX & NONE
10398 relocations do not use the symbol and are explicitly
10399 allowed to use the undefined symbol, so allow those.
10400 Likewise for relocations against STN_UNDEF. */
10406 {
10413 }
10416 {
10423 {
10428 {
10450 {
10456 }
10460 /* Get the (signed) value from the instruction. */
10463 {
10464 bfd_signed_vma mask;
10469 }
10471 }
10474 addend =
10479 /* Cases here must match those in the preceding
10480 switch statement. */
10482 {
10505 }
10506 }
10507 }
10508 else
10510 }
10511 else
10512 {
10513 bfd_boolean warned;
10521 }
10528 {
10529 /* This is a relocatable link. We don't have to change
10530 anything, unless the reloc is against a section symbol,
10531 in which case we have to adjust according to where the
10532 section symbol winds up in the output section. */
10534 {
10538 else
10540 }
10542 }
10546 else
10547 {
10548 name = (bfd_elf_string_from_elf_section
10552 }
10560 {
10565 input_bfd,
10566 input_section,
10569 name);
10570 }
10572 /* We call elf32_arm_final_link_relocate unless we're completely
10573 done, i.e., the relaxation produced the final output we want,
10574 and we won't let anybody mess with it. Also, we have to do
10575 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
10576 both in relaxed and non-relaxed cases */
10582 {
10585 /* This may have been marked unresolved because it came from
10586 a shared library. But we've just dealt with that. */
10588 }
10589 else
10600 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
10601 because such sections are not SEC_ALLOC and thus ld.so will
10602 not process them. */
10608 {
10611 input_bfd,
10612 input_section,
10617 }
10620 {
10622 {
10624 /* If the overflowing reloc was to an undefined symbol,
10625 we have already printed one error message and there
10626 is no point complaining again. */
10652 /* error_message should already be set. */
10657 /* Fall through. */
10659 common_error:
10666 }
10667 }
10668 }
10671 }
10673 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
10674 adds the edit to the start of the list. (The list must be built in order of
10675 ascending TINDEX: the function's callers are primarily responsible for
10676 maintaining that condition). */
10678 static void
10681 arm_unwind_edit_type type,
10684 {
10693 {
10703 }
10704 else
10705 {
10712 }
10713 }
10717 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
10718 static void
10720 {
10728 /* Adjust size of output section. */
10730 }
10732 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
10733 static void
10735 {
10745 }
10747 /* Scan .ARM.exidx tables, and create a list describing edits which should be
10748 made to those tables, such that:
10750 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
10751 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
10752 codes which have been inlined into the index).
10754 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
10756 The edits are applied when the tables are written
10757 (in elf32_arm_write_section). */
10759 bfd_boolean
10763 bfd_boolean merge_exidx_entries)
10764 {
10771 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
10772 text sections. */
10774 {
10778 {
10786 {
10787 Elf_Internal_Shdr *linked_hdr
10795 /* Link this .ARM.exidx section back from the text section it
10796 describes. */
10798 }
10799 }
10800 }
10802 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
10803 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
10804 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
10807 {
10814 bfd_vma j;
10825 {
10826 /* Section has no unwind data. */
10830 /* Ignore zero sized sections. */
10837 }
10839 /* Skip /DISCARD/ sections. */
10856 /* An error? */
10860 {
10865 /* An EXIDX_CANTUNWIND entry. */
10867 {
10871 }
10872 /* Inlined unwinding data. Merge if equal to previous. */
10874 {
10880 }
10881 /* Normal table entry. In theory we could merge these too,
10882 but duplicate entries are likely to be much less common. */
10883 else
10887 {
10892 }
10895 }
10897 /* Free contents if we allocated it ourselves. */
10901 /* Record edits to be applied later (in elf32_arm_write_section). */
10910 }
10912 /* Add terminating CANTUNWIND entry. */
10917 }
10919 static bfd_boolean
10922 {
10938 }
10940 static bfd_boolean
10942 {
10949 /* Invoke the regular ELF backend linker to do all the work. */
10953 /* Process stub sections (eg BE8 encoding, ...). */
10957 {
10959 /* Only process it once, in its link_sec slot. */
10961 {
10967 }
10968 }
10970 /* Write out any glue sections now that we have created all the
10971 stubs. */
10973 {
10976 ARM2THUMB_GLUE_SECTION_NAME))
10981 THUMB2ARM_GLUE_SECTION_NAME))
10986 VFP11_ERRATUM_VENEER_SECTION_NAME))
10991 ARM_BX_GLUE_SECTION_NAME))
10993 }
10996 }
10998 /* Return a best guess for the machine number based on the attributes. */
11000 static unsigned int
11002 {
11006 {
11012 {
11019 {
11027 {
11033 {
11037 }
11038 }
11039 }
11042 }
11046 }
11047 }
11049 /* Set the right machine number. */
11051 static bfd_boolean
11053 {
11059 {
11062 else
11064 }
11068 }
11070 /* Function to keep ARM specific flags in the ELF header. */
11072 static bfd_boolean
11074 {
11077 {
11079 {
11082 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
11083 abfd);
11084 else
11085 _bfd_error_handler
11087 abfd);
11088 }
11089 }
11090 else
11091 {
11094 }
11097 }
11099 /* Copy backend specific data from one object module to another. */
11101 static bfd_boolean
11103 {
11104 flagword in_flags;
11105 flagword out_flags;
11116 {
11117 /* Cannot mix APCS26 and APCS32 code. */
11121 /* Cannot mix float APCS and non-float APCS code. */
11125 /* If the src and dest have different interworking flags
11126 then turn off the interworking bit. */
11128 {
11130 _bfd_error_handler
11131 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
11135 }
11137 /* Likewise for PIC, though don't warn for this case. */
11140 }
11145 /* Also copy the EI_OSABI field. */
11149 /* Copy object attributes. */
11153 }
11155 /* Values for Tag_ABI_PCS_R9_use. */
11156 enum
11157 {
11158 AEABI_R9_V6,
11159 AEABI_R9_SB,
11160 AEABI_R9_TLS,
11161 AEABI_R9_unused
11162 };
11164 /* Values for Tag_ABI_PCS_RW_data. */
11165 enum
11166 {
11167 AEABI_PCS_RW_data_absolute,
11168 AEABI_PCS_RW_data_PCrel,
11169 AEABI_PCS_RW_data_SBrel,
11170 AEABI_PCS_RW_data_unused
11171 };
11173 /* Values for Tag_ABI_enum_size. */
11174 enum
11175 {
11176 AEABI_enum_unused,
11177 AEABI_enum_short,
11178 AEABI_enum_wide,
11179 AEABI_enum_forced_wide
11180 };
11182 /* Determine whether an object attribute tag takes an integer, a
11183 string or both. */
11185 static int
11187 {
11196 else
11198 }
11200 /* The ABI defines that Tag_conformance should be emitted first, and that
11201 Tag_nodefaults should be second (if either is defined). This sets those
11202 two positions, and bumps up the position of all the remaining tags to
11203 compensate. */
11204 static int
11206 {
11216 }
11218 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
11219 static bfd_boolean
11221 {
11223 {
11224 _bfd_error_handler
11229 }
11230 else
11231 {
11232 _bfd_error_handler
11236 }
11237 }
11239 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
11240 Returns -1 if no architecture could be read. */
11242 static int
11244 {
11248 /* Note: the tag and its argument below are uleb128 values, though
11249 currently-defined values fit in one byte for each. */
11256 /* This tag is "safely ignorable", so don't complain if it looks funny. */
11258 }
11260 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
11261 The tag is removed if ARCH is -1. */
11263 static void
11265 {
11270 {
11273 }
11275 /* Note: the tag and its argument below are uleb128 values, though
11276 currently-defined values fit in one byte for each. */
11282 }
11284 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
11285 into account. */
11287 static int
11290 {
11291 #define T(X) TAG_CPU_ARCH_##X
11294 {
11304 };
11306 {
11317 };
11319 {
11331 };
11333 {
11346 };
11348 {
11362 };
11364 {
11379 };
11381 {
11397 };
11399 {
11416 };
11418 {
11419 v6t2,
11420 v6k,
11421 v7,
11422 v6_m,
11423 v6s_m,
11424 v7e_m,
11425 v8,
11426 /* Pseudo-architecture. */
11427 v4t_plus_v6_m
11428 };
11430 /* Check we've not got a higher architecture than we know about. */
11433 {
11436 }
11438 /* Override old tag if we have a Tag_also_compatible_with on the output. */
11444 /* And override the new tag if we have a Tag_also_compatible_with on the
11445 input. */
11454 /* Architectures before V6KZ add features monotonically. */
11460 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
11461 as the canonical version. */
11463 {
11466 }
11467 else
11471 {
11475 }
11478 #undef T
11479 }
11481 /* Query attributes object to see if integer divide instructions may be
11482 present in an object. */
11483 static bfd_boolean
11485 {
11490 {
11492 /* Integer divide allowed if instruction contained in archetecture. */
11497 else
11501 /* Integer divide explicitly prohibited. */
11505 /* Unrecognised case - treat as allowing divide everywhere. */
11507 /* Integer divide allowed in ARM state. */
11509 }
11510 }
11512 /* Query attributes object to see if integer divide instructions are
11513 forbidden to be in the object. This is not the inverse of
11514 elf32_arm_attributes_accept_div. */
11515 static bfd_boolean
11517 {
11519 }
11521 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
11522 are conflicting attributes. */
11524 static bfd_boolean
11526 {
11529 /* Some tags have 0 = don't care, 1 = strong requirement,
11530 2 = weak requirement. */
11535 /* Skip the linker stubs file. This preserves previous behavior
11536 of accepting unknown attributes in the first input file - but
11537 is that a bug? */
11542 {
11543 /* This is the first object. Copy the attributes. */
11548 /* Use the Tag_null value to indicate the attributes have been
11549 initialized. */
11552 /* We do not output objects with Tag_MPextension_use_legacy - we move
11553 the attribute's value to Tag_MPextension_use. */
11555 {
11559 {
11560 _bfd_error_handler
11564 }
11570 }
11573 }
11577 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
11579 {
11580 /* Ignore mismatches if the object doesn't use floating point. */
11584 {
11585 _bfd_error_handler
11590 }
11591 }
11594 {
11595 /* Merge this attribute with existing attributes. */
11597 {
11600 /* These are merged after Tag_CPU_arch. */
11605 /* Use the first value seen. */
11609 {
11613 /* These aren't real CPU names, but we can't guess
11614 that from the architecture version alone. */
11628 "ARM v8"
11629 };
11631 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
11637 secondary_compat);
11640 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
11644 {
11645 /* The output architecture has been changed to match the
11646 input architecture. Use the input names. */
11653 }
11654 else
11655 {
11658 }
11660 /* If we still don't have a value for Tag_CPU_name,
11661 make one up now. Tag_CPU_raw_name remains blank. */
11666 }
11673 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
11682 /* Use the largest value specified. */
11689 /* Use the smallest value specified. */
11698 {
11699 /* This error message should be enabled once all non-conformant
11700 binaries in the toolchain have had the attributes set
11701 properly.
11702 _bfd_error_handler
11703 (_("error: %B: 8-byte data alignment conflicts with %B"),
11704 obfd, ibfd);
11705 result = FALSE; */
11706 }
11707 /* Fall through. */
11710 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
11711 value if greater than 2 (for future-proofing). */
11719 /* The virtualization tag effectively stores two bits of
11720 information: the intended use of TrustZone (in bit 0), and the
11721 intended use of Virtualization (in bit 1). */
11726 {
11729 else
11730 {
11731 _bfd_error_handler
11736 }
11737 }
11742 {
11743 /* 0 will merge with anything.
11744 'A' and 'S' merge to 'A'.
11745 'R' and 'S' merge to 'R'.
11746 'M' and 'A|R|S' is an error. */
11755 else
11756 {
11757 _bfd_error_handler
11759 ibfd,
11763 }
11764 }
11767 {
11768 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
11769 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
11770 when it's 0. It might mean absence of FP hardware if
11771 Tag_FP_arch is zero, otherwise it is effectively SP + DP. */
11773 #define VFP_VERSION_COUNT 8
11774 static const struct
11775 {
11779 {
11788 };
11793 /* If the output has no requirement about FP hardware,
11794 follow the requirement of the input. */
11796 {
11802 }
11803 /* If the input has no requirement about FP hardware, do
11804 nothing. */
11806 {
11809 }
11811 /* Both the input and the output have nonzero Tag_FP_arch.
11812 So Tag_ABI_HardFP_use is (SP & DP) when it's zero. */
11814 /* If both the input and the output have zero Tag_ABI_HardFP_use,
11815 do nothing. */
11818 ;
11819 /* If the input and the output have different Tag_ABI_HardFP_use,
11820 the combination of them is 3 (SP & DP). */
11825 /* Now we can handle Tag_FP_arch. */
11827 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
11828 pick the biggest. */
11831 {
11834 }
11835 /* The output uses the superset of input features
11836 (ISA version) and registers. */
11843 /* This assumes all possible supersets are also a valid
11844 options. */
11846 {
11850 }
11852 }
11858 {
11859 /* It's sometimes ok to mix different configs, so this is only
11860 a warning. */
11861 _bfd_error_handler
11863 }
11869 {
11870 _bfd_error_handler
11873 }
11881 {
11882 _bfd_error_handler
11884 ibfd);
11886 }
11887 /* Use the smallest value specified. */
11894 {
11895 _bfd_error_handler
11896 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
11898 }
11904 {
11907 {
11908 /* The existing object is compatible with anything.
11909 Use whatever requirements the new object has. */
11911 }
11915 {
11926 _bfd_error_handler
11927 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
11929 }
11930 }
11933 /* Aready done. */
11937 {
11938 _bfd_error_handler
11942 }
11945 /* Merged in target-independent code. */
11948 /* This is handled along with Tag_FP_arch. */
11952 {
11954 {
11955 _bfd_error_handler
11959 }
11960 }
11966 /* A value of zero on input means that the divide instruction may
11967 be used if available in the base architecture as specified via
11968 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
11969 the user did not want divide instructions. A value of 2
11970 explicitly means that divide instructions were allowed in ARM
11971 and Thumb state. */
11985 /* We don't output objects with Tag_MPextension_use_legacy - we
11986 move the value to Tag_MPextension_use. */
11988 {
11990 {
11991 _bfd_error_handler
11994 ibfd);
11996 }
11997 }
12005 /* This tag is set if it exists, but the value is unused (and is
12006 typically zero). We don't actually need to do anything here -
12007 the merge happens automatically when the type flags are merged
12008 below. */
12011 /* Already done in Tag_CPU_arch. */
12014 /* Keep the attribute if it matches. Throw it away otherwise.
12015 No attribute means no claim to conform. */
12022 result
12024 }
12026 /* If out_attr was copied from in_attr then it won't have a type yet. */
12029 }
12031 /* Merge Tag_compatibility attributes and any common GNU ones. */
12035 /* Check for any attributes not known on ARM. */
12039 }
12042 /* Return TRUE if the two EABI versions are incompatible. */
12044 static bfd_boolean
12046 {
12047 /* v4 and v5 are the same spec before and after it was released,
12048 so allow mixing them. */
12054 }
12056 /* Merge backend specific data from an object file to the output
12057 object file when linking. */
12059 static bfd_boolean
12062 /* Display the flags field. */
12064 static bfd_boolean
12066 {
12072 /* Print normal ELF private data. */
12076 /* Ignore init flag - it may not be set, despite the flags field
12077 containing valid data. */
12079 /* xgettext:c-format */
12083 {
12085 /* The following flag bits are GNU extensions and not part of the
12086 official ARM ELF extended ABI. Hence they are only decoded if
12087 the EABI version is not set. */
12093 else
12100 else
12129 else
12140 else
12172 eabi:
12185 }
12203 }
12205 static int
12207 {
12209 {
12214 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
12215 This allows us to distinguish between data used by Thumb instructions
12216 and non-data (which is probably code) inside Thumb regions of an
12217 executable. */
12224 }
12227 }
12235 {
12238 {
12242 }
12245 }
12247 /* Update the got entry reference counts for the section being removed. */
12249 static bfd_boolean
12254 {
12278 {
12283 bfd_boolean call_reloc_p;
12284 bfd_boolean may_become_dynamic_p;
12285 bfd_boolean may_need_local_target_p;
12291 {
12296 }
12306 {
12312 {
12315 }
12317 {
12320 }
12341 {
12344 }
12345 /* Fall through. */
12358 /* Should the interworking branches be here also? */
12361 {
12364 {
12367 }
12368 else
12370 }
12371 else
12377 }
12381 {
12382 /* If PLT refcount book-keeping is wrong and too low, we'll
12383 see a zero value (going to -1) for the root PLT reference
12384 count. */
12386 {
12389 }
12390 else
12391 /* A value of -1 means the symbol has become local, forced
12392 or seeing a hidden definition. Any other negative value
12393 is an error. */
12405 }
12408 {
12414 else
12415 {
12425 }
12428 {
12429 /* Everything must go for SEC. */
12432 }
12433 }
12434 }
12437 }
12439 /* Look through the relocs for a section during the first phase. */
12441 static bfd_boolean
12444 {
12452 bfd_boolean call_reloc_p;
12453 bfd_boolean may_become_dynamic_p;
12454 bfd_boolean may_need_local_target_p;
12468 /* Create dynamic sections for relocatable executables so that we can
12469 copy relocations. */
12472 {
12475 }
12490 {
12502 /* PR 9934: It is possible to have relocations that do not
12503 refer to symbols, thus it is also possible to have an
12504 object file containing relocations but no symbol table. */
12506 {
12508 r_symndx);
12510 }
12515 {
12517 {
12518 /* A local symbol. */
12523 }
12524 else
12525 {
12531 /* PR15323, ref flags aren't set for references in the
12532 same object. */
12534 }
12535 }
12543 /* Could be done earlier, if h were already available. */
12546 {
12556 /* This symbol requires a global offset table entry. */
12557 {
12561 {
12572 }
12575 {
12578 }
12579 else
12580 {
12581 /* This is a global offset table entry for a local symbol. */
12586 }
12588 /* If a variable is accessed with both tls methods, two
12589 slots may be created. */
12594 /* We will already have issued an error message if there
12595 is a TLS/non-TLS mismatch, based on the symbol
12596 type. So just combine any TLS types needed. */
12601 /* If the symbol is accessed in both IE and GDESC
12602 method, we're able to relax. Turn off the GDESC flag,
12603 without messing up with any other kind of tls types
12604 that may be involved */
12609 {
12612 else
12614 }
12615 }
12616 /* Fall through. */
12621 /* Fall through. */
12643 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
12644 ldr __GOTT_INDEX__ offsets. */
12646 {
12649 }
12650 /* Fall through. */
12657 {
12659 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
12664 }
12666 /* Fall through. */
12676 /* Should the interworking branches be listed here? */
12679 {
12682 {
12683 /* In shared libraries and relocatable executables,
12684 we treat local relative references as calls;
12685 see the related SYMBOL_CALLS_LOCAL code in
12686 allocate_dynrelocs. */
12689 }
12690 else
12691 /* We are creating a shared library or relocatable
12692 executable, and this is a reloc against a global symbol,
12693 or a non-PC-relative reloc against a local symbol.
12694 We may need to copy the reloc into the output. */
12696 }
12697 else
12701 /* This relocation describes the C++ object vtable hierarchy.
12702 Reconstruct it for later use during GC. */
12708 /* This relocation describes which C++ vtable entries are actually
12709 used. Record for later use during GC. */
12716 }
12719 {
12721 /* We may need a .plt entry if the function this reloc
12722 refers to is in a different object, regardless of the
12723 symbol's type. We can't tell for sure yet, because
12724 something later might force the symbol local. */
12727 /* If this reloc is in a read-only section, we might
12728 need a copy reloc. We can't check reliably at this
12729 stage whether the section is read-only, as input
12730 sections have not yet been mapped to output sections.
12731 Tentatively set the flag for now, and correct in
12732 adjust_dynamic_symbol. */
12734 }
12738 {
12744 {
12747 }
12748 else
12749 {
12755 }
12757 /* If the symbol is a function that doesn't bind locally,
12758 this relocation will need a PLT entry. */
12765 /* It's too early to use htab->use_blx here, so we have to
12766 record possible blx references separately from
12767 relocs that definitely need a thumb stub. */
12775 }
12778 {
12781 /* Create a reloc section in dynobj. */
12783 {
12784 sreloc = _bfd_elf_make_dynamic_reloc_section
12790 /* BPABI objects never have dynamic relocations mapped. */
12792 {
12793 flagword flags;
12798 }
12799 }
12801 /* If this is a global symbol, count the number of
12802 relocations we need for this symbol. */
12805 else
12806 {
12810 }
12814 {
12825 }
12830 }
12831 }
12834 }
12836 /* Unwinding tables are not referenced directly. This pass marks them as
12837 required if the corresponding code section is marked. */
12839 static bfd_boolean
12841 elf_gc_mark_hook_fn gc_mark_hook)
12842 {
12845 bfd_boolean again;
12849 /* Marking EH data may cause additional code sections to be marked,
12850 requiring multiple passes. */
12853 {
12856 {
12864 {
12873 {
12877 }
12878 }
12879 }
12880 }
12883 }
12885 /* Treat mapping symbols as special target symbols. */
12887 static bfd_boolean
12889 {
12891 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
12892 }
12894 /* This is a copy of elf_find_function() from elf.c except that
12895 ARM mapping symbols are ignored when looking for function names
12896 and STT_ARM_TFUNC is considered to a function type. */
12898 static bfd_boolean
12902 bfd_vma offset,
12905 {
12912 {
12918 {
12927 /* Skip mapping symbols. */
12930 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
12932 /* Fall through. */
12936 {
12939 }
12941 }
12942 }
12953 }
12956 /* Find the nearest line to a particular section and offset, for error
12957 reporting. This code is a duplicate of the code in elf.c, except
12958 that it uses arm_elf_find_function. */
12960 static bfd_boolean
12964 bfd_vma offset,
12968 {
12971 /* We skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain uses it. */
12978 {
12982 functionname_ptr);
12985 }
13005 }
13007 static bfd_boolean
13012 {
13013 bfd_boolean found;
13018 }
13020 /* Adjust a symbol defined by a dynamic object and referenced by a
13021 regular object. The current definition is in some section of the
13022 dynamic object, but we're not including those sections. We have to
13023 change the definition to something the rest of the link can
13024 understand. */
13026 static bfd_boolean
13029 {
13041 /* Make sure we know what is going on here. */
13052 /* If this is a function, put it in the procedure linkage table. We
13053 will fill in the contents of the procedure linkage table later,
13054 when we know the address of the .got section. */
13056 {
13057 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
13058 symbol binds locally. */
13064 {
13065 /* This case can occur if we saw a PLT32 reloc in an input
13066 file, but the symbol was never referred to by a dynamic
13067 object, or if all references were garbage collected. In
13068 such a case, we don't actually need to build a procedure
13069 linkage table, and we can just do a PC24 reloc instead. */
13075 }
13078 }
13079 else
13080 {
13081 /* It's possible that we incorrectly decided a .plt reloc was
13082 needed for an R_ARM_PC24 or similar reloc to a non-function sym
13083 in check_relocs. We can't decide accurately between function
13084 and non-function syms in check-relocs; Objects loaded later in
13085 the link may change h->type. So fix it now. */
13090 }
13092 /* If this is a weak symbol, and there is a real definition, the
13093 processor independent code will have arranged for us to see the
13094 real definition first, and we can just use the same value. */
13096 {
13102 }
13104 /* If there are no non-GOT references, we do not need a copy
13105 relocation. */
13109 /* This is a reference to a symbol defined by a dynamic object which
13110 is not a function. */
13112 /* If we are creating a shared library, we must presume that the
13113 only references to the symbol are via the global offset table.
13114 For such cases we need not do anything here; the relocations will
13115 be handled correctly by relocate_section. Relocatable executables
13116 can reference data in shared objects directly, so we don't need to
13117 do anything here. */
13121 /* We must allocate the symbol in our .dynbss section, which will
13122 become part of the .bss section of the executable. There will be
13123 an entry for this symbol in the .dynsym section. The dynamic
13124 object will contain position independent code, so all references
13125 from the dynamic object to this symbol will go through the global
13126 offset table. The dynamic linker will use the .dynsym entry to
13127 determine the address it must put in the global offset table, so
13128 both the dynamic object and the regular object will refer to the
13129 same memory location for the variable. */
13133 /* We must generate a R_ARM_COPY reloc to tell the dynamic linker to
13134 copy the initial value out of the dynamic object and into the
13135 runtime process image. We need to remember the offset into the
13136 .rel(a).bss section we are going to use. */
13138 {
13144 }
13147 }
13149 /* Allocate space in .plt, .got and associated reloc sections for
13150 dynamic relocs. */
13152 static bfd_boolean
13154 {
13172 {
13173 /* Make sure this symbol is output as a dynamic symbol.
13174 Undefined weak syms won't yet be marked as dynamic. */
13177 {
13180 }
13182 /* If the call in the PLT entry binds locally, the associated
13183 GOT entry should use an R_ARM_IRELATIVE relocation instead of
13184 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
13185 than the .plt section. */
13187 {
13191 /* All non-call references can be resolved directly.
13192 This means that they can (and in some cases, must)
13193 resolve directly to the run-time target, rather than
13194 to the PLT. That in turns means that any .got entry
13195 would be equal to the .igot.plt entry, so there's
13196 no point having both. */
13198 }
13203 {
13206 /* If this symbol is not defined in a regular file, and we are
13207 not generating a shared library, then set the symbol to this
13208 location in the .plt. This is required to make function
13209 pointers compare as equal between the normal executable and
13210 the shared library. */
13213 {
13217 /* Make sure the function is not marked as Thumb, in case
13218 it is the target of an ABS32 relocation, which will
13219 point to the PLT entry. */
13221 }
13225 /* VxWorks executables have a second set of relocations for
13226 each PLT entry. They go in a separate relocation section,
13227 which is processed by the kernel loader. */
13229 {
13230 /* There is a relocation for the initial PLT entry:
13231 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
13235 /* There are two extra relocations for each subsequent
13236 PLT entry: an R_ARM_32 relocation for the GOT entry,
13237 and an R_ARM_32 relocation for the PLT entry. */
13239 }
13240 }
13241 else
13242 {
13245 }
13246 }
13247 else
13248 {
13251 }
13257 {
13259 bfd_boolean dyn;
13263 /* Make sure this symbol is output as a dynamic symbol.
13264 Undefined weak syms won't yet be marked as dynamic. */
13267 {
13270 }
13273 {
13281 /* Non-TLS symbols need one GOT slot. */
13283 else
13284 {
13286 {
13287 /* R_ARM_TLS_DESC needs 2 GOT slots. */
13288 eh->tlsdesc_got
13293 /* plt.got_offset needs to know there's a TLS_DESC
13294 reloc in the middle of .got.plt. */
13296 }
13299 {
13300 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
13301 the symbol is both GD and GDESC, got.offset may
13302 have been overwritten. */
13305 }
13308 /* R_ARM_TLS_IE32 needs one GOT slot. */
13310 }
13324 {
13332 {
13334 /* GDESC needs a trampoline to jump to. */
13336 }
13338 /* Only GD needs it. GDESC just emits one relocation per
13339 2 entries. */
13342 }
13344 {
13346 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
13348 }
13351 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
13352 they all resolve dynamically instead. Reserve room for the
13353 GOT entry's R_ARM_IRELATIVE relocation. */
13357 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
13359 }
13360 }
13361 else
13364 /* Allocate stubs for exported Thumb functions on v4t. */
13369 {
13376 /* Create a new symbol to regist the real location of the function. */
13390 /* Point the symbol at the stub. */
13395 }
13400 /* In the shared -Bsymbolic case, discard space allocated for
13401 dynamic pc-relative relocs against symbols which turn out to be
13402 defined in regular objects. For the normal shared case, discard
13403 space for pc-relative relocs that have become local due to symbol
13404 visibility changes. */
13407 {
13408 /* The only relocs that use pc_count are R_ARM_REL32 and
13409 R_ARM_REL32_NOI, which will appear on something like
13410 ".long foo - .". We want calls to protected symbols to resolve
13411 directly to the function rather than going via the plt. If people
13412 want function pointer comparisons to work as expected then they
13413 should avoid writing assembly like ".long foo - .". */
13415 {
13419 {
13424 else
13426 }
13427 }
13430 {
13434 {
13437 else
13439 }
13440 }
13442 /* Also discard relocs on undefined weak syms with non-default
13443 visibility. */
13446 {
13450 /* Make sure undefined weak symbols are output as a dynamic
13451 symbol in PIEs. */
13454 {
13457 }
13458 }
13462 {
13463 /* Output absolute symbols so that we can create relocations
13464 against them. For normal symbols we output a relocation
13465 against the section that contains them. */
13468 }
13470 }
13471 else
13472 {
13473 /* For the non-shared case, discard space for relocs against
13474 symbols which turn out to need copy relocs or are not
13475 dynamic. */
13483 {
13484 /* Make sure this symbol is output as a dynamic symbol.
13485 Undefined weak syms won't yet be marked as dynamic. */
13488 {
13491 }
13493 /* If that succeeded, we know we'll be keeping all the
13494 relocs. */
13497 }
13501 keep: ;
13502 }
13504 /* Finally, allocate space. */
13506 {
13512 else
13514 }
13517 }
13519 /* Find any dynamic relocs that apply to read-only sections. */
13521 static bfd_boolean
13523 {
13529 {
13533 {
13538 /* Not an error, just cut short the traversal. */
13540 }
13541 }
13543 }
13545 void
13548 {
13556 }
13558 /* Set the sizes of the dynamic sections. */
13560 static bfd_boolean
13563 {
13566 bfd_boolean plt;
13567 bfd_boolean relocs;
13580 {
13581 /* Set the contents of the .interp section to the interpreter. */
13583 {
13588 }
13589 }
13591 /* Set up .got offsets for local syms, and space for local dynamic
13592 relocs. */
13594 {
13600 bfd_size_type locsymcount;
13610 {
13615 {
13618 {
13619 /* Input section has been discarded, either because
13620 it is a copy of a linkonce section or due to
13621 linker script /DISCARD/, so we'll be discarding
13622 the relocs too. */
13623 }
13627 {
13628 /* Relocations in vxworks .tls_vars sections are
13629 handled specially by the loader. */
13630 }
13632 {
13637 }
13638 }
13639 }
13657 {
13661 {
13665 {
13670 /* All references to the PLT are calls, so all
13671 non-call references can resolve directly to the
13672 run-time target. This means that the .got entry
13673 would be the same as the .igot.plt entry, so there's
13674 no point creating both. */
13676 }
13677 else
13678 {
13681 }
13684 {
13690 else
13692 }
13693 }
13695 {
13700 /* TLS_GD relocs need an 8-byte structure in the GOT. */
13703 {
13708 /* plt.got_offset needs to know there's a TLS_DESC
13709 reloc in the middle of .got.plt. */
13711 }
13716 {
13717 /* If the symbol is both GD and GDESC, *local_got
13718 may have been overwritten. */
13721 }
13727 /* If all references to an STT_GNU_IFUNC PLT are calls,
13728 then all non-call references, including this GOT entry,
13729 resolve directly to the run-time target. */
13735 {
13741 {
13745 }
13746 }
13747 }
13748 else
13750 }
13751 }
13754 {
13755 /* Allocate two GOT entries and one dynamic relocation (if necessary)
13756 for R_ARM_TLS_LDM32 relocations. */
13761 }
13762 else
13765 /* Allocate global sym .plt and .got entries, and space for global
13766 sym dynamic relocs. */
13769 /* Here we rummage through the found bfds to collect glue information. */
13771 {
13775 /* Initialise mapping tables for code/data. */
13780 /* xgettext:c-format */
13783 }
13785 /* Allocate space for the glue sections now that we've sized them. */
13788 /* For every jump slot reserved in the sgotplt, reloc_count is
13789 incremented. However, when we reserve space for TLS descriptors,
13790 it's not incremented, so in order to compute the space reserved
13791 for them, it suffices to multiply the reloc count by the jump
13792 slot size. */
13797 {
13804 /* If we're not using lazy TLS relocations, don't generate the
13805 PLT and GOT entries they require. */
13807 {
13813 }
13814 }
13816 /* The check_relocs and adjust_dynamic_symbol entry points have
13817 determined the sizes of the various dynamic sections. Allocate
13818 memory for them. */
13822 {
13828 /* It's OK to base decisions on the section name, because none
13829 of the dynobj section names depend upon the input files. */
13833 {
13834 /* Remember whether there is a PLT. */
13836 }
13838 {
13840 {
13841 /* Remember whether there are any reloc sections other
13842 than .rel(a).plt and .rela.plt.unloaded. */
13846 /* We use the reloc_count field as a counter if we need
13847 to copy relocs into the output file. */
13849 }
13850 }
13856 {
13857 /* It's not one of our sections, so don't allocate space. */
13859 }
13862 {
13863 /* If we don't need this section, strip it from the
13864 output file. This is mostly to handle .rel(a).bss and
13865 .rel(a).plt. We must create both sections in
13866 create_dynamic_sections, because they must be created
13867 before the linker maps input sections to output
13868 sections. The linker does that before
13869 adjust_dynamic_symbol is called, and it is that
13870 function which decides whether anything needs to go
13871 into these sections. */
13874 }
13879 /* Allocate memory for the section contents. */
13883 }
13886 {
13887 /* Add some entries to the .dynamic section. We fill in the
13888 values later, in elf32_arm_finish_dynamic_sections, but we
13889 must add the entries now so that we get the correct size for
13890 the .dynamic section. The DT_DEBUG entry is filled in by the
13891 dynamic linker and used by the debugger. */
13892 #define add_dynamic_entry(TAG, VAL) \
13893 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
13896 {
13899 }
13902 {
13914 }
13917 {
13919 {
13924 }
13925 else
13926 {
13931 }
13932 }
13934 /* If any dynamic relocs apply to a read-only section,
13935 then we need a DT_TEXTREL entry. */
13938 info);
13941 {
13944 }
13948 }
13949 #undef add_dynamic_entry
13952 }
13954 /* Size sections even though they're not dynamic. We use it to setup
13955 _TLS_MODULE_BASE_, if needed. */
13957 static bfd_boolean
13960 {
13969 {
13972 tlsbase = elf_link_hash_lookup
13976 {
13992 }
13993 }
13995 }
13997 /* Finish up dynamic symbol handling. We set the contents of various
13998 dynamic sections here. */
14000 static bfd_boolean
14005 {
14016 {
14018 {
14022 }
14025 {
14026 /* Mark the symbol as undefined, rather than as defined in
14027 the .plt section. Leave the value alone. */
14029 /* If the symbol is weak, we do need to clear the value.
14030 Otherwise, the PLT entry would provide a definition for
14031 the symbol even if the symbol wasn't defined anywhere,
14032 and so the symbol would never be NULL. */
14035 }
14037 {
14038 /* At least one non-call relocation references this .iplt entry,
14039 so the .iplt entry is the function's canonical address. */
14047 }
14048 }
14051 {
14053 Elf_Internal_Rela rel;
14055 /* This symbol needs a copy reloc. Set it up. */
14069 }
14071 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
14072 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
14073 to the ".got" section. */
14079 }
14081 static void
14085 {
14089 {
14092 /* Emit mov pc,rx if bx is not permitted. */
14096 }
14097 }
14099 /* Install the special first PLT entry for elf32-arm-nacl. Unlike
14100 other variants, NaCl needs this entry in a static executable's
14101 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
14102 zero. For .iplt really only the last bundle is useful, and .iplt
14103 could have a shorter first entry, with each individual PLT entry's
14104 relative branch calculated differently so it targets the last
14105 bundle instead of the instruction before it (labelled .Lplt_tail
14106 above). But it's simpler to keep the size and layout of PLT0
14107 consistent with the dynamic case, at the cost of some dead code at
14108 the start of .iplt and the one dead store to the stack at the start
14109 of .Lplt_tail. */
14110 static void
14113 {
14129 }
14131 /* Finish up the dynamic sections. */
14133 static bfd_boolean
14135 {
14148 /* A broken linker script might have discarded the dynamic sections.
14149 Catch this here so that we do not seg-fault later on. */
14155 {
14167 {
14168 Elf_Internal_Dyn dyn;
14175 {
14208 get_vma:
14211 {
14212 /* PR ld/14397: Issue an error message if a required section is missing. */
14217 }
14220 else
14221 /* In the BPABI, tags in the PT_DYNAMIC section point
14222 at the file offset, not the memory address, for the
14223 convenience of the post linker. */
14228 get_vma_if_bpabi:
14243 {
14244 /* My reading of the SVR4 ABI indicates that the
14245 procedure linkage table relocs (DT_JMPREL) should be
14246 included in the overall relocs (DT_REL). This is
14247 what Solaris does. However, UnixWare can not handle
14248 that case. Therefore, we override the DT_RELSZ entry
14249 here to make it not include the JMPREL relocs. Since
14250 the linker script arranges for .rel(a).plt to follow all
14251 other relocation sections, we don't have to worry
14252 about changing the DT_REL entry. */
14258 }
14259 /* Fall through. */
14263 /* In the BPABI, the DT_REL tag must point at the file
14264 offset, not the VMA, of the first relocation
14265 section. So, we use code similar to that in
14266 elflink.c, but do not check for SHF_ALLOC on the
14267 relcoation section, since relocations sections are
14268 never allocated under the BPABI. The comments above
14269 about Unixware notwithstanding, we include all of the
14270 relocations here. */
14272 {
14278 {
14279 Elf_Internal_Shdr *hdr
14282 {
14289 }
14290 }
14292 }
14309 /* Set the bottom bit of DT_INIT/FINI if the
14310 corresponding function is Thumb. */
14316 get_sym:
14317 /* If it wasn't set by elf_bfd_final_link
14318 then there is nothing to adjust. */
14320 {
14326 {
14329 }
14330 }
14332 }
14333 }
14335 /* Fill in the first entry in the procedure linkage table. */
14337 {
14341 /* Calculate the addresses of the GOT and PLT. */
14346 {
14347 /* The VxWorks GOT is relocated by the dynamic linker.
14348 Therefore, we must emit relocations rather than simply
14349 computing the values now. */
14350 Elf_Internal_Rela rel;
14361 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
14367 }
14371 else
14372 {
14385 #ifdef FOUR_WORD_PLT
14386 /* The displacement value goes in the otherwise-unused
14387 last word of the second entry. */
14389 #else
14391 #endif
14392 }
14393 }
14395 /* UnixWare sets the entsize of .plt to 4, although that doesn't
14396 really seem like the right value. */
14401 {
14402 bfd_vma got_address
14406 bfd_vma plt_address
14422 }
14425 {
14429 #ifdef FOUR_WORD_PLT
14432 #endif
14433 }
14436 {
14437 /* Correct the .rel(a).plt.unloaded relocations. They will have
14438 incorrect symbol indexes. */
14447 {
14448 Elf_Internal_Rela rel;
14459 }
14460 }
14461 }
14464 /* NaCl uses a special first entry in .iplt too. */
14467 /* Fill in the first three entries in the global offset table. */
14469 {
14471 {
14474 else
14480 }
14483 }
14486 }
14488 static void
14489 elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
14490 {
14498 else
14503 {
14507 }
14511 {
14515 else
14517 }
14518 }
14520 static enum elf_reloc_type_class
14524 {
14526 {
14535 }
14536 }
14538 static void
14540 {
14542 }
14544 /* Return TRUE if this is an unwinding table entry. */
14546 static bfd_boolean
14548 {
14551 }
14554 /* Set the type and flags for an ARM section. We do this by
14555 the section name, which is a hack, but ought to work. */
14557 static bfd_boolean
14559 {
14565 {
14568 }
14570 }
14572 /* Handle an ARM specific section when reading an object file. This is
14573 called when bfd_section_from_shdr finds a section with an unknown
14574 type. */
14576 static bfd_boolean
14581 {
14582 /* There ought to be a place to keep ELF backend specific flags, but
14583 at the moment there isn't one. We just keep track of the
14584 sections by their name, instead. Fortunately, the ABI gives
14585 names for all the ARM specific sections, so we will probably get
14586 away with this. */
14588 {
14596 }
14602 }
14606 {
14609 else
14611 }
14614 {
14623 enum map_symbol_type
14624 {
14625 ARM_MAP_ARM,
14626 ARM_MAP_THUMB,
14627 ARM_MAP_DATA
14628 };
14631 /* Output a single mapping symbol. */
14633 static bfd_boolean
14636 bfd_vma offset)
14637 {
14639 Elf_Internal_Sym sym;
14651 }
14653 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
14654 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
14656 static bfd_boolean
14658 bfd_boolean is_iplt_entry_p,
14661 {
14673 {
14676 }
14677 else
14678 {
14681 }
14687 {
14692 }
14694 {
14703 }
14705 {
14708 }
14709 else
14710 {
14711 bfd_boolean thumb_stub_p;
14715 {
14718 }
14719 #ifdef FOUR_WORD_PLT
14724 #else
14725 /* A three-word PLT with no Thumb thunk contains only Arm code,
14726 so only need to output a mapping symbol for the first PLT entry and
14727 entries with thumb thunks. */
14729 {
14732 }
14733 #endif
14734 }
14737 }
14739 /* Output mapping symbols for PLT entries associated with H. */
14741 static bfd_boolean
14743 {
14751 /* When warning symbols are created, they **replace** the "real"
14752 entry in the hash table, thus we never get to see the real
14753 symbol in a hash traversal. So look at it now. */
14759 }
14761 /* Output a single local symbol for a generated stub. */
14763 static bfd_boolean
14766 {
14767 Elf_Internal_Sym sym;
14778 }
14780 static bfd_boolean
14783 {
14786 bfd_vma addr;
14795 /* Massage our args to the form they really have. */
14801 /* Ensure this stub is attached to the current section being
14802 processed. */
14811 {
14825 }
14830 {
14832 {
14849 }
14852 {
14856 }
14859 {
14876 }
14877 }
14880 }
14882 /* Output mapping symbols for linker generated sections,
14883 and for those data-only sections that do not have a
14884 $d. */
14886 static bfd_boolean
14891 Elf_Internal_Sym *,
14892 asection *,
14894 {
14895 output_arch_syminfo osi;
14897 bfd_vma offset;
14898 bfd_size_type size;
14911 /* Add a $d mapping symbol to data-only sections that
14912 don't have any mapping symbol. This may result in (harmless) redundant
14913 mapping symbols. */
14917 {
14922 {
14927 == SEC_HAS_CONTENTS
14932 {
14937 }
14938 }
14939 }
14941 /* ARM->Thumb glue. */
14943 {
14945 ARM2THUMB_GLUE_SECTION_NAME);
14954 else
14958 {
14961 }
14962 }
14964 /* Thumb->ARM glue. */
14966 {
14968 THUMB2ARM_GLUE_SECTION_NAME);
14975 {
14978 }
14979 }
14981 /* ARMv4 BX veneers. */
14983 {
14985 ARM_BX_GLUE_SECTION_NAME);
14991 }
14993 /* Long calls stubs. */
14995 {
15001 {
15002 /* Ignore non-stub sections. */
15012 }
15013 }
15015 /* Finally, output mapping symbols for the PLT. */
15017 {
15022 /* Output mapping symbols for the plt header. SymbianOS does not have a
15023 plt header. */
15025 {
15026 /* VxWorks shared libraries have no PLT header. */
15028 {
15033 }
15034 }
15036 {
15039 }
15041 {
15044 #ifndef FOUR_WORD_PLT
15047 #endif
15048 }
15049 }
15051 {
15052 /* NaCl uses a special first entry in .iplt too. */
15058 }
15061 {
15066 {
15072 {
15080 }
15081 }
15082 }
15084 {
15085 /* Mapping symbols for the lazy tls trampoline. */
15092 }
15094 {
15095 /* Mapping symbols for the tls trampoline. */
15098 #ifdef FOUR_WORD_PLT
15102 #endif
15103 }
15106 }
15108 /* Allocate target specific section data. */
15110 static bfd_boolean
15112 {
15114 {
15122 }
15125 }
15128 /* Used to order a list of mapping symbols by address. */
15130 static int
15132 {
15141 /* Ensure results do not depend on the host qsort for objects with
15142 multiple mapping symbols at the same address by sorting on type
15143 after vma. */
15147 else
15149 }
15151 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
15153 static unsigned long
15155 {
15157 }
15159 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
15160 relocations. */
15162 static void
15164 {
15168 /* High bit of first word is supposed to be zero. */
15172 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
15173 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
15179 }
15181 /* Data for make_branch_to_a8_stub(). */
15183 struct a8_branch_to_stub_data
15184 {
15187 };
15190 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
15191 places for a particular section. */
15193 static bfd_boolean
15196 {
15202 bfd_signed_vma branch_offset;
15231 /* We attempt to avoid this condition by setting stubs_always_after_branch
15232 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
15233 This check is just to be on the safe side... */
15235 {
15239 }
15242 {
15253 {
15258 jump24:
15260 {
15261 /* There's not much we can do apart from complain if this
15262 happens. */
15266 }
15268 /* i1 = not(j1 eor s), so:
15269 not i1 = j1 eor s
15270 j1 = (not i1) eor s. */
15282 }
15288 }
15294 }
15296 /* Do code byteswapping. Return FALSE afterwards so that the section is
15297 written out as normal. */
15299 static bfd_boolean
15304 {
15310 bfd_vma ptr;
15311 bfd_vma end;
15313 bfd_byte tmp;
15319 /* If this section has not been allocated an _arm_elf_section_data
15320 structure then we cannot record anything. */
15330 {
15335 {
15339 {
15341 {
15342 bfd_vma branch_to_veneer;
15343 /* Original condition code of instruction, plus bit mask for
15344 ARM B instruction. */
15348 /* The instruction is before the label. */
15351 /* Above offset included in -4 below. */
15365 }
15369 {
15370 bfd_vma branch_from_veneer;
15373 /* Take size of veneer into account. */
15382 /* Original instruction. */
15389 /* Branch back to insn after original insn. */
15395 }
15400 }
15401 }
15402 }
15405 {
15406 arm_unwind_table_edit *edit_node
15408 /* Now, sec->size is the size of the section we will write. The original
15409 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
15410 markers) was sec->rawsize. (This isn't the case if we perform no
15411 edits, then rawsize will be zero and we should use size). */
15418 {
15420 {
15424 {
15427 out_index++;
15428 in_index++;
15429 }
15433 {
15435 {
15437 in_index++;
15442 {
15450 /* Note: this is meant to be equivalent to an
15451 R_ARM_PREL31 relocation. These synthetic
15452 EXIDX_CANTUNWIND markers are not relocated by the
15453 usual BFD method. */
15457 /* First address we can't unwind. */
15461 /* Code for EXIDX_CANTUNWIND. */
15465 out_index++;
15467 }
15469 }
15472 }
15473 }
15474 else
15475 {
15476 /* No more edits, copy remaining entries verbatim. */
15479 out_index++;
15480 in_index++;
15481 }
15482 }
15486 edited_contents,
15490 }
15492 /* Fix code to point to Cortex-A8 erratum stubs. */
15494 {
15502 }
15508 {
15513 {
15516 else
15520 {
15522 /* Byte swap code words. */
15524 {
15532 }
15536 /* Byte swap code halfwords. */
15538 {
15543 }
15547 /* Leave data alone. */
15549 }
15551 }
15552 }
15560 }
15562 /* Mangle thumb function symbols as we read them in. */
15564 static bfd_boolean
15569 {
15573 /* New EABI objects mark thumb function symbols by setting the low bit of
15574 the address. */
15577 {
15579 {
15582 }
15583 else
15585 }
15587 {
15590 }
15593 else
15597 }
15600 /* Mangle thumb function symbols as we write them out. */
15602 static void
15607 {
15608 Elf_Internal_Sym newsym;
15610 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
15611 of the address set, as per the new EABI. We do this unconditionally
15612 because objcopy does not set the elf header flags until after
15613 it writes out the symbol table. */
15615 {
15620 {
15621 /* Do this only for defined symbols. At link type, the static
15622 linker will simulate the work of dynamic linker of resolving
15623 symbols and will carry over the thumbness of found symbols to
15624 the output symbol table. It's not clear how it happens, but
15625 the thumbness of undefined symbols can well be different at
15626 runtime, and writing '1' for them will be confusing for users
15627 and possibly for dynamic linker itself.
15628 */
15630 }
15633 }
15635 }
15637 /* Add the PT_ARM_EXIDX program header. */
15639 static bfd_boolean
15642 {
15648 {
15649 /* If there is already a PT_ARM_EXIDX header, then we do not
15650 want to add another one. This situation arises when running
15651 "strip"; the input binary already has the header. */
15656 {
15667 }
15668 }
15671 }
15673 /* We may add a PT_ARM_EXIDX program header. */
15675 static int
15678 {
15684 else
15686 }
15688 /* Hook called by the linker routine which adds symbols from an object
15689 file. */
15691 static bfd_boolean
15695 {
15707 }
15709 /* We use this to override swap_symbol_in and swap_symbol_out. */
15711 {
15724 bfd_elf32_write_out_phdrs,
15725 bfd_elf32_write_shdrs_and_ehdr,
15726 bfd_elf32_checksum_contents,
15727 bfd_elf32_write_relocs,
15728 elf32_arm_swap_symbol_in,
15729 elf32_arm_swap_symbol_out,
15730 bfd_elf32_slurp_reloc_table,
15731 bfd_elf32_slurp_symbol_table,
15732 bfd_elf32_swap_dyn_in,
15733 bfd_elf32_swap_dyn_out,
15734 bfd_elf32_swap_reloc_in,
15735 bfd_elf32_swap_reloc_out,
15736 bfd_elf32_swap_reloca_in,
15737 bfd_elf32_swap_reloca_out
15738 };
15740 #define ELF_ARCH bfd_arch_arm
15741 #define ELF_TARGET_ID ARM_ELF_DATA
15742 #define ELF_MACHINE_CODE EM_ARM
15743 #ifdef __QNXTARGET__
15744 #define ELF_MAXPAGESIZE 0x1000
15745 #else
15746 #define ELF_MAXPAGESIZE 0x8000
15747 #endif
15748 #define ELF_MINPAGESIZE 0x1000
15749 #define ELF_COMMONPAGESIZE 0x1000
15751 #define bfd_elf32_mkobject elf32_arm_mkobject
15753 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
15754 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
15755 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
15756 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
15757 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
15758 #define bfd_elf32_bfd_link_hash_table_free elf32_arm_hash_table_free
15759 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
15760 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
15761 #define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
15762 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
15763 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
15764 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
15765 #define bfd_elf32_bfd_final_link elf32_arm_final_link
15767 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
15768 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
15769 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
15770 #define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
15771 #define elf_backend_check_relocs elf32_arm_check_relocs
15772 #define elf_backend_relocate_section elf32_arm_relocate_section
15773 #define elf_backend_write_section elf32_arm_write_section
15774 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
15775 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
15776 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
15777 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
15778 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
15779 #define elf_backend_always_size_sections elf32_arm_always_size_sections
15780 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
15781 #define elf_backend_post_process_headers elf32_arm_post_process_headers
15782 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
15783 #define elf_backend_object_p elf32_arm_object_p
15784 #define elf_backend_fake_sections elf32_arm_fake_sections
15785 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
15786 #define elf_backend_final_write_processing elf32_arm_final_write_processing
15787 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
15788 #define elf_backend_size_info elf32_arm_size_info
15789 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
15790 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
15791 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
15792 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
15793 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
15795 #define elf_backend_can_refcount 1
15796 #define elf_backend_can_gc_sections 1
15797 #define elf_backend_plt_readonly 1
15798 #define elf_backend_want_got_plt 1
15799 #define elf_backend_want_plt_sym 0
15800 #define elf_backend_may_use_rel_p 1
15801 #define elf_backend_may_use_rela_p 0
15802 #define elf_backend_default_use_rela_p 0
15804 #define elf_backend_got_header_size 12
15806 #undef elf_backend_obj_attrs_vendor
15808 #undef elf_backend_obj_attrs_section
15810 #undef elf_backend_obj_attrs_arg_type
15811 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
15812 #undef elf_backend_obj_attrs_section_type
15813 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
15814 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
15815 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
15819 /* Native Client targets. */
15821 #undef TARGET_LITTLE_SYM
15822 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_nacl_vec
15823 #undef TARGET_LITTLE_NAME
15825 #undef TARGET_BIG_SYM
15826 #define TARGET_BIG_SYM bfd_elf32_bigarm_nacl_vec
15827 #undef TARGET_BIG_NAME
15830 /* Like elf32_arm_link_hash_table_create -- but overrides
15831 appropriately for NaCl. */
15835 {
15840 {
15848 }
15850 }
15852 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
15853 really need to use elf32_arm_modify_segment_map. But we do it
15854 anyway just to reduce gratuitous differences with the stock ARM backend. */
15856 static bfd_boolean
15858 {
15861 }
15863 static void
15865 {
15868 }
15871 #undef elf32_bed
15872 #define elf32_bed elf32_arm_nacl_bed
15873 #undef bfd_elf32_bfd_link_hash_table_create
15874 #define bfd_elf32_bfd_link_hash_table_create \
15875 elf32_arm_nacl_link_hash_table_create
15876 #undef elf_backend_plt_alignment
15877 #define elf_backend_plt_alignment 4
15878 #undef elf_backend_modify_segment_map
15879 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
15880 #undef elf_backend_modify_program_headers
15881 #define elf_backend_modify_program_headers nacl_modify_program_headers
15882 #undef elf_backend_final_write_processing
15883 #define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
15885 #undef ELF_MAXPAGESIZE
15886 #define ELF_MAXPAGESIZE 0x10000
15887 #undef ELF_MINPAGESIZE
15888 #undef ELF_COMMONPAGESIZE
15893 /* Reset to defaults. */
15894 #undef elf_backend_plt_alignment
15895 #undef elf_backend_modify_segment_map
15896 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
15897 #undef elf_backend_modify_program_headers
15898 #undef elf_backend_final_write_processing
15899 #define elf_backend_final_write_processing elf32_arm_final_write_processing
15900 #undef ELF_MINPAGESIZE
15901 #define ELF_MINPAGESIZE 0x1000
15902 #undef ELF_COMMONPAGESIZE
15903 #define ELF_COMMONPAGESIZE 0x1000
15906 /* VxWorks Targets. */
15908 #undef TARGET_LITTLE_SYM
15909 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vxworks_vec
15910 #undef TARGET_LITTLE_NAME
15912 #undef TARGET_BIG_SYM
15913 #define TARGET_BIG_SYM bfd_elf32_bigarm_vxworks_vec
15914 #undef TARGET_BIG_NAME
15917 /* Like elf32_arm_link_hash_table_create -- but overrides
15918 appropriately for VxWorks. */
15922 {
15927 {
15932 }
15934 }
15936 static void
15938 {
15941 }
15943 #undef elf32_bed
15944 #define elf32_bed elf32_arm_vxworks_bed
15946 #undef bfd_elf32_bfd_link_hash_table_create
15947 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
15948 #undef elf_backend_final_write_processing
15949 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
15950 #undef elf_backend_emit_relocs
15951 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
15953 #undef elf_backend_may_use_rel_p
15954 #define elf_backend_may_use_rel_p 0
15955 #undef elf_backend_may_use_rela_p
15956 #define elf_backend_may_use_rela_p 1
15957 #undef elf_backend_default_use_rela_p
15958 #define elf_backend_default_use_rela_p 1
15959 #undef elf_backend_want_plt_sym
15960 #define elf_backend_want_plt_sym 1
15961 #undef ELF_MAXPAGESIZE
15962 #define ELF_MAXPAGESIZE 0x1000
15967 /* Merge backend specific data from an object file to the output
15968 object file when linking. */
15970 static bfd_boolean
15972 {
15973 flagword out_flags;
15974 flagword in_flags;
15978 /* Check if we have the same endianness. */
15988 /* The input BFD must have had its flags initialised. */
15989 /* The following seems bogus to me -- The flags are initialized in
15990 the assembler but I don't think an elf_flags_init field is
15991 written into the object. */
15992 /* BFD_ASSERT (elf_flags_init (ibfd)); */
15997 /* In theory there is no reason why we couldn't handle this. However
15998 in practice it isn't even close to working and there is no real
15999 reason to want it. */
16003 {
16005 ibfd);
16007 }
16010 {
16011 /* If the input is the default architecture and had the default
16012 flags then do not bother setting the flags for the output
16013 architecture, instead allow future merges to do this. If no
16014 future merges ever set these flags then they will retain their
16015 uninitialised values, which surprise surprise, correspond
16016 to the default values. */
16029 }
16031 /* Determine what should happen if the input ARM architecture
16032 does not match the output ARM architecture. */
16036 /* Identical flags must be compatible. */
16040 /* Check to see if the input BFD actually contains any sections. If
16041 not, its flags may not have been initialised either, but it
16042 cannot actually cause any incompatiblity. Do not short-circuit
16043 dynamic objects; their section list may be emptied by
16044 elf_link_add_object_symbols.
16046 Also check to see if there are no code sections in the input.
16047 In this case there is no need to check for code specific flags.
16048 XXX - do we need to worry about floating-point format compatability
16049 in data sections ? */
16051 {
16056 {
16057 /* Ignore synthetic glue sections. */
16060 {
16068 }
16069 }
16073 }
16075 /* Complain about various flag mismatches. */
16078 {
16079 _bfd_error_handler
16085 }
16087 /* Not sure what needs to be checked for EABI versions >= 1. */
16088 /* VxWorks libraries do not use these flags. */
16092 {
16094 {
16095 _bfd_error_handler
16101 }
16104 {
16106 _bfd_error_handler
16107 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
16109 else
16110 _bfd_error_handler
16111 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
16115 }
16118 {
16120 _bfd_error_handler
16123 else
16124 _bfd_error_handler
16129 }
16132 {
16134 _bfd_error_handler
16137 else
16138 _bfd_error_handler
16143 }
16145 #ifdef EF_ARM_SOFT_FLOAT
16147 {
16148 /* We can allow interworking between code that is VFP format
16149 layout, and uses either soft float or integer regs for
16150 passing floating point arguments and results. We already
16151 know that the APCS_FLOAT flags match; similarly for VFP
16152 flags. */
16155 {
16157 _bfd_error_handler
16160 else
16161 _bfd_error_handler
16166 }
16167 }
16168 #endif
16170 /* Interworking mismatch is only a warning. */
16172 {
16174 {
16175 _bfd_error_handler
16178 }
16179 else
16180 {
16181 _bfd_error_handler
16184 }
16185 }
16186 }
16189 }
16192 /* Symbian OS Targets. */
16194 #undef TARGET_LITTLE_SYM
16195 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_symbian_vec
16196 #undef TARGET_LITTLE_NAME
16198 #undef TARGET_BIG_SYM
16199 #define TARGET_BIG_SYM bfd_elf32_bigarm_symbian_vec
16200 #undef TARGET_BIG_NAME
16203 /* Like elf32_arm_link_hash_table_create -- but overrides
16204 appropriately for Symbian OS. */
16208 {
16213 {
16216 /* There is no PLT header for Symbian OS. */
16218 /* The PLT entries are each one instruction and one word. */
16221 /* Symbian uses armv5t or above, so use_blx is always true. */
16224 }
16226 }
16228 static const struct bfd_elf_special_section
16229 elf32_arm_symbian_special_sections[] =
16230 {
16231 /* In a BPABI executable, the dynamic linking sections do not go in
16232 the loadable read-only segment. The post-linker may wish to
16233 refer to these sections, but they are not part of the final
16234 program image. */
16240 /* These sections do not need to be writable as the SymbianOS
16241 postlinker will arrange things so that no dynamic relocation is
16242 required. */
16247 };
16249 static void
16252 {
16253 /* BPABI objects are never loaded directly by an OS kernel; they are
16254 processed by a postlinker first, into an OS-specific format. If
16255 the D_PAGED bit is set on the file, BFD will align segments on
16256 page boundaries, so that an OS can directly map the file. With
16257 BPABI objects, that just results in wasted space. In addition,
16258 because we clear the D_PAGED bit, map_sections_to_segments will
16259 recognize that the program headers should not be mapped into any
16260 loadable segment. */
16263 }
16265 static bfd_boolean
16268 {
16272 /* BPABI shared libraries and executables should have a PT_DYNAMIC
16273 segment. However, because the .dynamic section is not marked
16274 with SEC_LOAD, the generic ELF code will not create such a
16275 segment. */
16278 {
16284 {
16288 }
16289 }
16291 /* Also call the generic arm routine. */
16293 }
16295 /* Return address for Ith PLT stub in section PLT, for relocation REL
16296 or (bfd_vma) -1 if it should not be included. */
16298 static bfd_vma
16301 {
16303 }
16306 #undef elf32_bed
16307 #define elf32_bed elf32_arm_symbian_bed
16309 /* The dynamic sections are not allocated on SymbianOS; the postlinker
16310 will process them and then discard them. */
16311 #undef ELF_DYNAMIC_SEC_FLAGS
16312 #define ELF_DYNAMIC_SEC_FLAGS \
16313 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
16315 #undef elf_backend_emit_relocs
16317 #undef bfd_elf32_bfd_link_hash_table_create
16318 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
16319 #undef elf_backend_special_sections
16320 #define elf_backend_special_sections elf32_arm_symbian_special_sections
16321 #undef elf_backend_begin_write_processing
16322 #define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
16323 #undef elf_backend_final_write_processing
16324 #define elf_backend_final_write_processing elf32_arm_final_write_processing
16326 #undef elf_backend_modify_segment_map
16327 #define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
16329 /* There is no .got section for BPABI objects, and hence no header. */
16330 #undef elf_backend_got_header_size
16331 #define elf_backend_got_header_size 0
16333 /* Similarly, there is no .got.plt section. */
16334 #undef elf_backend_want_got_plt
16335 #define elf_backend_want_got_plt 0
16337 #undef elf_backend_plt_sym_val
16338 #define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
16340 #undef elf_backend_may_use_rel_p
16341 #define elf_backend_may_use_rel_p 1
16342 #undef elf_backend_may_use_rela_p
16343 #define elf_backend_may_use_rela_p 0
16344 #undef elf_backend_default_use_rela_p
16345 #define elf_backend_default_use_rela_p 0
16346 #undef elf_backend_want_plt_sym
16347 #define elf_backend_want_plt_sym 0
16348 #undef ELF_MAXPAGESIZE
16349 #define ELF_MAXPAGESIZE 0x8000