| blob | 9d9451c786219882319dbf70ee44ca1c4c350826 |
1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2013 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
71 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
72 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
73 #define ST0_FR (1 << 26)
75 /* The sizes of floating point registers. */
77 enum
78 {
81 };
83 enum
84 {
87 };
99 NULL
100 };
102 /* For backwards compatibility we default to MIPS16. This flag is
103 overridden as soon as unambiguous ELF file flags tell us the
104 compressed ISA encoding used. */
108 {
109 mips_compression_mips16,
110 mips_compression_micromips,
111 NULL
112 };
116 /* The standard register names, and all the valid aliases for them. */
117 struct register_alias
118 {
121 };
123 /* Aliases for o32 and most other ABIs. */
129 };
131 /* Aliases for n32 and n64. */
137 };
139 /* Aliases for ABI-independent registers. */
141 /* The architecture manuals specify these ABI-independent names for
142 the GPRs. */
148 #undef R
150 /* k0 and k1 are sometimes called these instead (for "kernel
151 temp"). */
155 /* This is the traditional GDB name for the CP0 status register. */
158 /* This is the traditional GDB name for the CP0 BadVAddr register. */
161 /* This is the traditional GDB name for the FCSR. */
163 };
166 #define R(n) { #n, n }
171 #undef R
172 };
174 #ifndef MIPS_DEFAULT_FPU_TYPE
175 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
176 #endif
182 /* Properties (for struct target_desc) describing the g/G packet
183 layout. */
192 {
194 }
196 static int
198 {
200 }
202 /* Return 1 if REGNUM refers to a floating-point general register, raw
203 or cooked. Otherwise return 0. */
205 static int
207 {
212 }
214 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
215 == MIPS_ABI_EABI32 \
216 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
218 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
219 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
221 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
222 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
224 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
226 /* Return the MIPS ABI associated with GDBARCH. */
227 enum mips_abi
229 {
231 }
233 int
235 {
238 /* If we know how big the registers are, use that size. */
242 /* Fall back to the previous behavior. */
245 }
247 /* Return the currently configured (or set) saved register size. */
249 unsigned int
251 {
253 {
266 }
267 }
269 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
270 are some functions to handle addresses associated with compressed
271 code including but not limited to testing, setting, or clearing
272 bit 0 of such addresses. */
274 /* Return one iff compressed code is the MIPS16 instruction set. */
276 static int
278 {
280 }
282 /* Return one iff compressed code is the microMIPS instruction set. */
284 static int
286 {
288 }
290 /* Return one iff ADDR denotes compressed code. */
292 static int
294 {
296 }
298 /* Return one iff ADDR denotes standard ISA code. */
300 static int
302 {
304 }
306 /* Return one iff ADDR denotes MIPS16 code. */
308 static int
310 {
312 }
314 /* Return one iff ADDR denotes microMIPS code. */
316 static int
318 {
320 }
322 /* Strip the ISA (compression) bit off from ADDR. */
324 static CORE_ADDR
326 {
328 }
330 /* Add the ISA (compression) bit to ADDR. */
332 static CORE_ADDR
334 {
336 }
338 /* Functions for setting and testing a bit in a minimal symbol that
339 marks it as MIPS16 or microMIPS function. The MSB of the minimal
340 symbol's "info" field is used for this purpose.
342 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
343 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
344 one of the "special" bits in a minimal symbol to mark it accordingly.
345 The test checks an ELF-private flag that is valid for true function
346 symbols only; in particular synthetic symbols such as for PLT stubs
347 have no ELF-private part at all.
349 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
350 in a minimal symbol. */
352 static void
354 {
364 }
366 /* Return one iff MSYM refers to standard ISA code. */
368 static int
370 {
372 }
374 /* Return one iff MSYM refers to MIPS16 code. */
376 static int
378 {
380 }
382 /* Return one iff MSYM refers to microMIPS code. */
384 static int
386 {
388 }
390 /* XFER a value from the big/little/left end of the register.
391 Depending on the size of the value it might occupy the entire
392 register or just part of it. Make an allowance for this, aligning
393 things accordingly. */
395 static void
400 {
404 /* Need to transfer the left or right part of the register, based on
405 the targets byte order. */
407 {
419 }
425 {
430 }
438 {
443 }
446 }
448 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
449 compatiblity mode. A return value of 1 means that we have
450 physical 64-bit registers, but should treat them as 32-bit registers. */
452 static int
454 {
456 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
457 meaningful. */
461 #if 0
462 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
463 in all the places we deal with FP registers. PR gdb/413. */
464 /* Otherwise check the FR bit in the status register - it controls
465 the FP compatiblity mode. If it is clear we are in compatibility
466 mode. */
469 #endif
472 }
474 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
480 /* The list of available "set mips " and "show mips " commands. */
485 /* Integer registers 0 thru 31 are handled explicitly by
486 mips_register_name(). Processor specific registers 32 and above
487 are listed in the following tables. */
489 enum
492 /* Generic MIPS. */
501 };
503 /* Names of IDT R3041 registers. */
514 };
516 /* Names of tx39 registers. */
527 };
529 /* Names of IRIX registers. */
536 };
538 /* Names of registers with Linux kernels. */
546 };
549 /* Return the name of the register corresponding to REGNO. */
552 {
554 /* GPR names for all ABIs other than n32/n64. */
560 };
562 /* GPR names for n32 and n64 ABIs. */
568 };
572 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
573 but then don't make the raw register names visible. This (upper)
574 range of user visible register numbers are the pseudo-registers.
576 This approach was adopted accommodate the following scenario:
577 It is possible to debug a 64-bit device using a 32-bit
578 programming model. In such instances, the raw registers are
579 configured to be 64-bits wide, while the pseudo registers are
580 configured to be 32-bits wide. The registers that the user
581 sees - the pseudo registers - match the users expectations
582 given the programming model being used. */
587 /* The MIPS integer registers are always mapped from 0 to 31. The
588 names of the registers (which reflects the conventions regarding
589 register use) vary depending on the ABI. */
591 {
594 else
596 }
600 {
605 }
606 else
609 }
611 /* Return the groups that a MIPS register can be categorised into. */
613 static int
616 {
626 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
627 (gdbarch), as not all architectures are multi-arch. */
638 /* Save the pseudo registers. Need to make certain that any code
639 extracting register values from a saved register cache also uses
640 pseudo registers. */
643 /* Restore the same pseudo register. */
647 }
649 /* Return the groups that a MIPS register can be categorised into.
650 This version is only used if we have a target description which
651 describes real registers (and their groups). */
653 static int
656 {
661 /* Only save, restore, and display the pseudo registers. Need to
662 make certain that any code extracting register values from a
663 saved register cache also uses pseudo registers.
665 Note: saving and restoring the pseudo registers is slightly
666 strange; if we have 64 bits, we should save and restore all
667 64 bits. But this is hard and has little benefit. */
676 }
678 /* Map the symbol table registers which live in the range [1 *
679 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
680 registers. Take care of alignment and size problems. */
682 static enum register_status
685 {
693 {
696 else
697 {
699 LONGEST regval;
706 }
707 }
708 else
710 }
712 static void
716 {
724 {
727 else
728 {
729 /* Sign extend the shortened version of the register prior
730 to placing it in the raw register. This is required for
731 some mips64 parts in order to avoid unpredictable behavior. */
735 }
736 }
737 else
739 }
741 static int
744 {
752 }
754 static int
757 {
762 {
766 {
769 {
772 }
775 }
776 }
777 else
781 }
783 /* Table to translate 3-bit register field to actual register number. */
786 /* Heuristic_proc_start may hunt through the text section for a long
787 time across a 2400 baud serial line. Allows the user to limit this
788 search. */
792 /* Number of bytes of storage in the actual machine representation for
793 register N. NOTE: This defines the pseudo register type so need to
794 rebuild the architecture vector. */
798 static void
801 {
804 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
805 instead of relying on globals. Doing that would let generic code
806 handle the search for this specific architecture. */
808 {
811 }
812 }
814 /* Convert to/from a register and the corresponding memory value. */
816 /* This predicate tests for the case of an 8 byte floating point
817 value that is being transferred to or from a pair of floating point
818 registers each of which are (or are considered to be) only 4 bytes
819 wide. */
820 static int
823 {
828 }
830 /* This predicate tests for the case of a value of less than 8
831 bytes in width that is being transfered to or from an 8 byte
832 general purpose register. */
833 static int
836 {
842 }
844 static int
847 {
850 }
852 static int
856 {
860 {
873 }
875 {
877 CORE_ADDR offset;
886 }
887 else
888 {
891 }
892 }
894 static void
897 {
901 {
904 }
906 {
910 /* Sign extend values, irrespective of type, that are stored to
911 a 64-bit general purpose register. (32-bit unsigned values
912 are stored as signed quantities within a 64-bit register.
913 When performing an operation, in compiled code, that combines
914 a 32-bit unsigned value with a signed 64-bit value, a type
915 conversion is first performed that zeroes out the high 32 bits.) */
917 {
920 else
924 }
925 else
926 {
929 else
933 }
934 }
935 else
936 {
939 }
940 }
942 /* Return the GDB type object for the "standard" data type of data in
943 register REG. */
947 {
950 {
951 /* The floating-point registers raw, or cooked, always match
952 mips_isa_regsize(), and also map 1:1, byte for byte. */
955 else
957 }
959 {
960 /* The raw or ISA registers. These are all sized according to
961 the ISA regsize. */
964 else
966 }
967 else
968 {
971 /* The cooked or ABI registers. These are sized according to
972 the ABI (with a few complications). */
980 /* The pseudo/cooked view of the embedded registers is always
981 32-bit. The raw view is handled below. */
984 /* The target, while possibly using a 64-bit register buffer,
985 is only transfering 32-bits of each integer register.
986 Reflect this in the cooked/pseudo (ABI) register value. */
989 /* The ABI is restricted to 32-bit registers (the ISA could be
990 32- or 64-bit). */
992 else
993 /* 64-bit ABI. */
995 }
996 }
998 /* Return the GDB type for the pseudo register REGNUM, which is the
999 ABI-level view. This function is only called if there is a target
1000 description which includes registers, so we know precisely the
1001 types of hardware registers. */
1005 {
1012 /* Absent registers are still absent. */
1018 /* Present the floating point registers however the hardware did;
1019 do not try to convert between FPU layouts. */
1022 /* Use pointer types for registers if we can. For n32 we can not,
1023 since we do not have a 64-bit pointer type. */
1026 {
1032 }
1050 {
1051 /* The pseudo/cooked view of embedded registers is always
1052 32-bit, even if the target transfers 64-bit values for them.
1053 New targets relying on XML descriptions should only transfer
1054 the necessary 32 bits, but older versions of GDB expected 64,
1055 so allow the target to provide 64 bits without interfering
1056 with the displayed type. */
1058 }
1060 /* For all other registers, pass through the hardware type. */
1062 }
1064 /* Should the upper word of 64-bit addresses be zeroed? */
1067 static int
1069 {
1071 {
1083 }
1084 }
1086 static void
1089 {
1094 {
1102 printf_filtered
1109 }
1110 }
1112 /* Tell if the program counter value in MEMADDR is in a standard ISA
1113 function. */
1115 int
1117 {
1120 /* Flags indicating that this is a MIPS16 or microMIPS function is
1121 stored by elfread.c in the high bit of the info field. Use this
1122 to decide if the function is standard MIPS. Otherwise if bit 0
1123 of the address is clear, then this is a standard MIPS function. */
1127 else
1129 }
1131 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1133 int
1135 {
1138 /* A flag indicating that this is a MIPS16 function is stored by
1139 elfread.c in the high bit of the info field. Use this to decide
1140 if the function is MIPS16. Otherwise if bit 0 of the address is
1141 set, then ELF file flags will tell if this is a MIPS16 function. */
1145 else
1147 }
1149 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1151 int
1153 {
1156 /* A flag indicating that this is a microMIPS function is stored by
1157 elfread.c in the high bit of the info field. Use this to decide
1158 if the function is microMIPS. Otherwise if bit 0 of the address
1159 is set, then ELF file flags will tell if this is a microMIPS
1160 function. */
1164 else
1166 }
1168 /* Tell the ISA type of the function the program counter value in MEMADDR
1169 is in. */
1171 static enum mips_isa
1173 {
1176 /* A flag indicating that this is a MIPS16 or a microMIPS function
1177 is stored by elfread.c in the high bit of the info field. Use
1178 this to decide if the function is MIPS16 or microMIPS or normal
1179 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1180 flags will tell if this is a MIPS16 or a microMIPS function. */
1183 {
1188 else
1190 }
1191 else
1192 {
1197 else
1199 }
1200 }
1202 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1210 /* This is used as a PIC thunk prefix. */
1214 /* Return non-zero if the PC is inside a call thunk (aka stub or
1215 trampoline) that should be treated as a temporary frame. */
1217 static int
1219 {
1220 CORE_ADDR start_addr;
1223 /* Find the starting address of the function containing the PC. */
1227 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1231 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1234 /* If the PC is in __fn_stub_*, this is a call stub. */
1239 }
1241 /* MIPS believes that the PC has a sign extended value. Perhaps the
1242 all registers should be sign extended for simplicity? */
1244 static CORE_ADDR
1246 {
1248 ULONGEST pc;
1254 }
1256 static CORE_ADDR
1258 {
1259 CORE_ADDR pc;
1264 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1265 intermediate frames. In this case we can get the caller's address
1266 from $ra, or if $ra contains an address within a thunk as well, then
1267 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1268 and thus the caller's address is in $s2. */
1270 {
1271 pc = frame_unwind_register_signed
1276 {
1277 pc = frame_unwind_register_signed
1281 }
1282 }
1284 }
1286 static CORE_ADDR
1288 {
1289 return frame_unwind_register_signed
1291 }
1293 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1294 dummy frame. The frame ID's base needs to match the TOS value
1295 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1296 breakpoint. */
1298 static struct frame_id
1300 {
1301 return frame_id_build
1306 }
1308 /* Implement the "write_pc" gdbarch method. */
1310 void
1312 {
1317 else
1319 }
1321 /* Fetch and return instruction from the specified location. Handle
1322 MIPS16/microMIPS as appropriate. */
1324 static ULONGEST
1327 {
1334 {
1346 }
1351 {
1355 }
1357 }
1359 /* These are the fields of 32 bit mips instructions. */
1360 #define mips32_op(x) (x >> 26)
1361 #define itype_op(x) (x >> 26)
1362 #define itype_rs(x) ((x >> 21) & 0x1f)
1363 #define itype_rt(x) ((x >> 16) & 0x1f)
1364 #define itype_immediate(x) (x & 0xffff)
1366 #define jtype_op(x) (x >> 26)
1367 #define jtype_target(x) (x & 0x03ffffff)
1369 #define rtype_op(x) (x >> 26)
1370 #define rtype_rs(x) ((x >> 21) & 0x1f)
1371 #define rtype_rt(x) ((x >> 16) & 0x1f)
1372 #define rtype_rd(x) ((x >> 11) & 0x1f)
1373 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1374 #define rtype_funct(x) (x & 0x3f)
1376 /* MicroMIPS instruction fields. */
1377 #define micromips_op(x) ((x) >> 10)
1379 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1380 bit and the size respectively of the field extracted. */
1381 #define b0s4_imm(x) ((x) & 0xf)
1382 #define b0s5_imm(x) ((x) & 0x1f)
1383 #define b0s5_reg(x) ((x) & 0x1f)
1384 #define b0s7_imm(x) ((x) & 0x7f)
1385 #define b0s10_imm(x) ((x) & 0x3ff)
1386 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1387 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1388 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1389 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1390 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1391 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1392 #define b6s4_op(x) (((x) >> 6) & 0xf)
1393 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1395 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1396 respectively of the field extracted. */
1397 #define b0s6_op(x) ((x) & 0x3f)
1398 #define b0s11_op(x) ((x) & 0x7ff)
1399 #define b0s12_imm(x) ((x) & 0xfff)
1400 #define b0s16_imm(x) ((x) & 0xffff)
1401 #define b0s26_imm(x) ((x) & 0x3ffffff)
1402 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1403 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1404 #define b12s4_op(x) (((x) >> 12) & 0xf)
1406 /* Return the size in bytes of the instruction INSN encoded in the ISA
1407 instruction set. */
1409 static int
1411 {
1413 {
1420 else
1425 else
1429 }
1431 }
1433 static LONGEST
1435 {
1437 }
1439 /* Determine the address of the next instruction executed after the INST
1440 floating condition branch instruction at PC. COUNT specifies the
1441 number of the floating condition bits tested by the branch. */
1443 static CORE_ADDR
1446 {
1451 ULONGEST fcs;
1455 /* No way to handle; it'll most likely trap anyway. */
1463 else
1467 }
1469 /* Return nonzero if the gdbarch is an Octeon series. */
1471 static int
1473 {
1479 }
1481 /* Return true if the OP represents the Octeon's BBIT instruction. */
1483 static int
1485 {
1488 /* BBIT0 is encoded as LWC2: 110 010. */
1489 /* BBIT032 is encoded as LDC2: 110 110. */
1490 /* BBIT1 is encoded as SWC2: 111 010. */
1491 /* BBIT132 is encoded as SDC2: 111 110. */
1495 }
1498 /* Determine where to set a single step breakpoint while considering
1499 branch prediction. */
1501 static CORE_ADDR
1503 {
1510 instruction. */
1511 {
1513 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1514 {
1516 {
1527 }
1528 }
1530 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1534 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1538 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1541 /* JALX: 011101 */
1542 /* The new PC will be alternate mode. */
1543 {
1547 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1549 }
1551 {
1557 /* Take into account the *32 instructions. */
1565 else
1567 }
1569 else
1571 }
1572 else
1575 /* Further subdivide into SPECIAL, REGIMM and other. */
1577 {
1581 {
1584 /* Set PC to that address. */
1588 {
1594 else
1596 }
1600 }
1604 {
1607 {
1612 less_branch:
1615 else
1624 else
1631 {
1636 /* No way to handle; it'll most likely trap anyway. */
1642 else
1644 }
1646 /* All of the other instructions in the REGIMM category */
1649 }
1650 }
1654 {
1657 /* Upper four bits get never changed... */
1659 }
1662 equal_branch:
1666 else
1670 neq_branch:
1674 else
1680 else
1688 else
1696 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1697 INSN. */
1699 static LONGEST
1701 {
1703 }
1705 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1706 INSN. */
1708 static LONGEST
1710 {
1712 }
1714 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1715 INSN. */
1717 static LONGEST
1719 {
1721 }
1723 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1725 static int
1727 {
1728 ULONGEST insn;
1732 }
1734 /* Calculate the address of the next microMIPS instruction to execute
1735 after the INSN coprocessor 1 conditional branch instruction at the
1736 address PC. COUNT denotes the number of coprocessor condition bits
1737 examined by the branch. */
1739 static CORE_ADDR
1742 {
1747 ULONGEST fcs;
1751 /* No way to handle; it'll most likely trap anyway. */
1759 else
1763 }
1765 /* Calculate the address of the next microMIPS instruction to execute
1766 after the instruction at the address PC. */
1768 static CORE_ADDR
1770 {
1772 ULONGEST insn;
1777 {
1778 /* 48-bit instructions. */
1780 /* No branch or jump instructions in this category. */
1784 /* 32-bit instructions. */
1790 {
1793 /* POOL32Axf: bits 000000 ... 111100 */
1795 /* JALR, JALR.HB: 000000 000x111100 111100 */
1796 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1802 {
1809 else
1819 else
1827 else
1841 else
1854 /* BC2F, BC2T: don't know how to handle these. */
1860 {
1865 /* No way to handle; it'll most likely trap anyway. */
1871 else
1873 }
1877 /* BC1ANY2F: bits 010000 11100 xxx01 */
1879 /* BC1ANY2T: bits 010000 11101 xxx01 */
1890 }
1903 else
1911 else
1918 }
1921 /* 16-bit instructions. */
1924 {
1927 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
1930 /* JRADDIUSP: bits 010001 11000 */
1935 {
1940 else
1942 }
1946 {
1951 else
1953 }
1959 }
1961 }
1964 }
1966 /* Decoding the next place to set a breakpoint is irregular for the
1967 mips 16 variant, but fortunately, there fewer instructions. We have
1968 to cope ith extensions for 16 bit instructions and a pair of actual
1969 32 bit instructions. We dont want to set a single step instruction
1970 on the extend instruction either. */
1972 /* Lots of mips16 instruction formats */
1973 /* Predicting jumps requires itype,ritype,i8type
1974 and their extensions extItype,extritype,extI8type. */
1975 enum mips16_inst_fmts
1976 {
1998 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1999 };
2000 /* I am heaping all the fields of the formats into one structure and
2001 then, only the fields which are involved in instruction extension. */
2002 struct upk_mips16
2003 {
2004 CORE_ADDR offset;
2007 };
2010 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2011 for the bits which make up the immediate extension. */
2013 static CORE_ADDR
2015 {
2016 CORE_ADDR value;
2025 }
2027 /* Only call this function if you know that this is an extendable
2028 instruction. It won't malfunction, but why make excess remote memory
2029 references? If the immediate operands get sign extended or something,
2030 do it after the extension is performed. */
2031 /* FIXME: Every one of these cases needs to worry about sign extension
2032 when the offset is to be used in relative addressing. */
2034 static unsigned int
2036 {
2042 }
2044 static void
2049 {
2050 CORE_ADDR offset;
2054 {
2056 {
2057 CORE_ADDR value;
2059 {
2062 }
2063 else
2064 {
2067 }
2071 }
2076 /* Most of the fields are the same as I type but the
2077 immediate value is of a different length. */
2078 CORE_ADDR value;
2080 {
2083 }
2084 else
2085 {
2088 }
2093 }
2095 {
2101 /* Low bit still set. */
2107 }
2110 }
2114 }
2117 static CORE_ADDR
2119 {
2121 }
2123 static CORE_ADDR
2126 {
2130 {
2132 {
2137 }
2139 instructions. */
2140 {
2146 else
2149 }
2151 {
2158 else
2161 }
2163 {
2170 else
2173 }
2175 {
2179 /* upk.regx contains the opcode */
2183 /* pc = add_offset_16(pc,upk.offset) ; */
2185 else
2188 }
2190 {
2192 /* upk.fmt = rrtype; */
2195 {
2201 else
2204 }
2205 else
2208 }
2210 /* This is an instruction extension. Fetch the real instruction
2211 (which follows the extension) and decode things based on
2212 that. */
2213 {
2218 }
2220 {
2223 }
2224 }
2226 }
2228 static CORE_ADDR
2230 {
2234 }
2236 /* The mips_next_pc function supports single_step when the remote
2237 target monitor or stub is not developed enough to do a single_step.
2238 It works by decoding the current instruction and predicting where a
2239 branch will go. This isnt hard because all the data is available.
2240 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2241 static CORE_ADDR
2243 {
2250 else
2252 }
2254 struct mips_frame_cache
2255 {
2256 CORE_ADDR base;
2258 };
2260 /* Set a register's saved stack address in temp_saved_regs. If an
2261 address has already been set for this register, do nothing; this
2262 way we will only recognize the first save of a given register in a
2263 function prologue.
2265 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2266 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2267 Strictly speaking, only the second range is used as it is only second
2268 range (the ABI instead of ISA registers) that comes into play when finding
2269 saved registers in a frame. */
2271 static void
2274 {
2277 {
2282 }
2283 }
2286 /* Fetch the immediate value from a MIPS16 instruction.
2287 If the previous instruction was an EXTEND, use it to extend
2288 the upper bits of the immediate value. This is a helper function
2289 for mips16_scan_prologue. */
2291 static int
2297 {
2301 {
2306 }
2307 else
2308 {
2317 }
2318 }
2321 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2322 the associated FRAME_CACHE if not null.
2323 Return the address of the first instruction past the prologue. */
2325 static CORE_ADDR
2330 {
2331 CORE_ADDR cur_pc;
2333 CORE_ADDR sp;
2347 /* Can be called when there's no process, and hence when there's no
2348 THIS_FRAME. */
2353 else
2360 {
2361 /* Save the previous instruction. If it's an EXTEND, we'll extract
2362 the immediate offset extension from it in mips16_get_imm. */
2365 /* Fetch and decode the instruction. */
2369 /* Normally we ignore extend instructions. However, if it is
2370 not followed by a valid prologue instruction, then this
2371 instruction is not part of the prologue either. We must
2372 remember in this case to adjust the end_prologue_addr back
2373 over the extend. */
2375 {
2378 }
2385 {
2389 else
2390 /* Exit loop if a positive stack adjustment is found, which
2391 usually means that the stack cleanup code in the function
2392 epilogue is reached. */
2394 }
2396 {
2400 }
2402 {
2406 }
2408 {
2411 }
2413 {
2416 }
2418 {
2421 }
2423 {
2428 }
2430 {
2434 }
2436 {
2440 }
2445 {
2449 }
2453 {
2454 /* This instruction is part of the prologue, but we don't
2455 need to do anything special to handle it. */
2456 }
2457 else
2458 {
2459 /* This instruction is not an instruction typically found
2460 in a prologue, so we must have reached the end of the
2461 prologue. */
2464 }
2465 }
2467 /* The entry instruction is typically the first instruction in a function,
2468 and it stores registers at offsets relative to the value of the old SP
2469 (before the prologue). But the value of the sp parameter to this
2470 function is the new SP (after the prologue has been executed). So we
2471 can't calculate those offsets until we've seen the entire prologue,
2472 and can calculate what the old SP must have been. */
2474 {
2478 /* The entry instruction always subtracts 32 from the SP. */
2481 /* Now we can calculate what the SP must have been at the
2482 start of the function prologue. */
2485 /* Check if a0-a3 were saved in the caller's argument save area. */
2487 {
2490 }
2492 /* Check if the ra register was pushed on the stack. */
2495 {
2498 }
2500 /* Check if the s0 and s1 registers were pushed on the stack. */
2502 {
2505 }
2506 }
2508 /* The SAVE instruction is similar to ENTRY, except that defined by the
2509 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2510 size of the frame is specified as an immediate field of instruction
2511 and an extended variation exists which lets additional registers and
2512 frame space to be specified. The instruction always treats registers
2513 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2515 {
2519 };
2523 };
2531 {
2534 }
2536 {
2539 }
2541 /* For standard SAVE the frame size of 0 means 128. */
2548 /* Now we can calculate what the SP must have been at the
2549 start of the function prologue. */
2552 /* Check if A0-A3 were saved in the caller's argument save area. */
2554 {
2557 }
2561 /* Check if the RA register was pushed on the stack. */
2563 {
2566 }
2568 /* Check if the S8 register was pushed on the stack. */
2570 {
2573 xsregs--;
2574 }
2575 /* Check if S2-S7 were pushed on the stack. */
2577 {
2580 }
2582 /* Check if the S1 register was pushed on the stack. */
2584 {
2587 }
2588 /* Check if the S0 register was pushed on the stack. */
2590 {
2593 }
2595 /* Check if A0-A3 were pushed on the stack. */
2597 {
2600 }
2601 }
2604 {
2609 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2610 be able to get rid of the assignment below, evetually. But it's
2611 still needed for now. */
2615 }
2617 /* If we didn't reach the end of the prologue when scanning the function
2618 instructions, then set end_prologue_addr to the address of the
2619 instruction immediately after the last one we scanned. */
2624 }
2626 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2627 Procedures that use the 32-bit instruction set are handled by the
2628 mips_insn32 unwinder. */
2632 {
2642 /* Analyze the function prologue. */
2643 {
2645 CORE_ADDR start_addr;
2650 /* We can't analyze the prologue if we couldn't find the begining
2651 of the function. */
2656 }
2658 /* gdbarch_sp_regnum contains the value and not the address. */
2664 }
2666 static void
2669 {
2671 this_cache);
2672 /* This marks the outermost frame. */
2676 }
2681 {
2683 this_cache);
2685 }
2687 static int
2690 {
2696 }
2699 {
2700 NORMAL_FRAME,
2701 default_frame_unwind_stop_reason,
2702 mips_insn16_frame_this_id,
2703 mips_insn16_frame_prev_register,
2704 NULL,
2705 mips_insn16_frame_sniffer
2706 };
2708 static CORE_ADDR
2711 {
2713 this_cache);
2715 }
2718 {
2720 mips_insn16_frame_base_address,
2721 mips_insn16_frame_base_address,
2722 mips_insn16_frame_base_address
2723 };
2727 {
2732 else
2734 }
2736 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2737 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2738 interpreted directly, and then multiplied by 4. */
2740 static int
2742 {
2747 }
2749 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2750 the address of the first instruction past the prologue. */
2752 static CORE_ADDR
2757 {
2766 CORE_ADDR prev_pc;
2767 CORE_ADDR cur_pc;
2769 CORE_ADDR sp;
2783 /* Can be called when there's no process, and hence when there's no
2784 THIS_FRAME. */
2789 else
2796 /* Permit at most one non-prologue non-control-transfer instruction
2797 in the middle which may have been reordered by the compiler for
2798 optimisation. */
2800 {
2807 {
2808 /* 48-bit instructions. */
2810 /* No prologue instructions in this category. */
2815 /* 32-bit instructions. */
2822 {
2823 /* Record $sp/$fp adjustment. */
2824 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2832 /* SUBU: bits 000000 00111010000 */
2833 /* DSUBU: bits 010110 00111010000 */
2836 /* (D)SUBU $sp, $v1 */
2839 /* ADDU: bits 000000 00101010000 */
2840 /* DADDU: bits 010110 00101010000 */
2851 /* SWP: bits 001000 1001 */
2852 /* SDP: bits 001000 1100 */
2854 /* S[DW]P reg,offset($sp) */
2855 {
2861 }
2863 /* SWM: bits 001000 1101 */
2864 /* SDM: bits 001000 1111 */
2866 /* SWM reglist,offset($sp) */
2869 {
2880 }
2881 else
2885 /* Record $sp/$fp adjustment. */
2886 /* Discard (D)ADDIU $gp used for PIC code. */
2893 /* (D)ADDIU $sp, imm */
2896 /* (D)ADDIU $fp, $sp, imm */
2897 {
2901 }
2903 /* (D)ADDIU $gp, imm */
2907 /* LUI $v1 is used for larger $sp adjustments. */
2908 /* Discard LUI $gp is used for PIC code. */
2911 /* LUI: bits 010000 001101 */
2913 /* LUI $v1, imm */
2916 /* LUI: bits 010000 001101 */
2918 /* LUI $gp, imm */
2922 /* ORI $v1 is used for larger $sp adjustments. */
2927 /* ORI $v1, imm */
2929 else
2937 /* S[DW]C1 reg,offset($sp) */
2947 /* S[DW] reg,offset($sp) */
2949 else
2956 }
2959 /* 16-bit instructions. */
2962 {
2967 /* MOVE $fp, $sp */
2968 {
2971 }
2973 /* MOVE reg, $a0-$a3 */
2979 /* SWM: bits 010001 0101 */
2980 {
2987 }
2988 else
2994 /* ADDIUSP: bits 010011 1 */
2997 /* ADDIUS5: bits 010011 0 */
2998 /* ADDIUS5 $sp, imm */
3000 else
3013 }
3015 }
3020 /* Enough non-prologue insns seen or positive stack adjustment? */
3022 {
3025 }
3028 }
3031 {
3036 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3037 be able to get rid of the assignment below, evetually. But it's
3038 still needed for now. */
3042 }
3044 /* If we didn't reach the end of the prologue when scanning the function
3045 instructions, then set end_prologue_addr to the address of the
3046 instruction immediately after the last one we scanned. Unless the
3047 last one looked like a non-prologue instruction (and we looked ahead),
3048 in which case use its address instead. */
3053 }
3055 /* Heuristic unwinder for procedures using microMIPS instructions.
3056 Procedures that use the 32-bit instruction set are handled by the
3057 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3061 {
3072 /* Analyze the function prologue. */
3073 {
3075 CORE_ADDR start_addr;
3080 /* We can't analyze the prologue if we couldn't find the begining
3081 of the function. */
3086 }
3088 /* gdbarch_sp_regnum contains the value and not the address. */
3094 }
3096 static void
3099 {
3101 this_cache);
3102 /* This marks the outermost frame. */
3106 }
3111 {
3113 this_cache);
3115 }
3117 static int
3120 {
3127 }
3130 {
3131 NORMAL_FRAME,
3132 default_frame_unwind_stop_reason,
3133 mips_micro_frame_this_id,
3134 mips_micro_frame_prev_register,
3135 NULL,
3136 mips_micro_frame_sniffer
3137 };
3139 static CORE_ADDR
3142 {
3144 this_cache);
3146 }
3149 {
3151 mips_micro_frame_base_address,
3152 mips_micro_frame_base_address,
3153 mips_micro_frame_base_address
3154 };
3158 {
3164 else
3166 }
3168 /* Mark all the registers as unset in the saved_regs array
3169 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3171 static void
3173 {
3177 {
3182 {
3184 }
3185 }
3186 }
3188 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3189 the associated FRAME_CACHE if not null.
3190 Return the address of the first instruction past the prologue. */
3192 static CORE_ADDR
3197 {
3198 CORE_ADDR cur_pc;
3200 frame-pointer. */
3201 CORE_ADDR sp;
3211 /* Can be called when there's no process, and hence when there's no
3212 THIS_FRAME. */
3217 else
3223 restart:
3227 {
3231 /* Fetch the instruction. */
3235 /* Save some code by pre-extracting some useful fields. */
3243 {
3246 else
3247 /* Exit loop if a positive stack adjustment is found, which
3248 usually means that the stack cleanup code in the function
3249 epilogue is reached. */
3252 }
3255 {
3257 }
3260 {
3261 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3263 }
3265 {
3266 /* Old gcc frame, r30 is virtual frame pointer. */
3270 {
3274 frame_addr = get_frame_register_signed
3280 {
3281 /* FP > SP + frame_size. This may be because of
3282 an alloca or somethings similar. Fix sp to
3283 "pre-alloca" value, and try again. */
3285 /* Need to reset the status of all registers. Otherwise,
3286 we will hit a guard that prevents the new address
3287 for each register to be recomputed during the second
3288 pass. */
3291 }
3292 }
3293 }
3294 /* move $30,$sp. With different versions of gas this will be either
3295 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3296 Accept any one of these. */
3298 {
3299 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3301 {
3305 frame_addr = get_frame_register_signed
3310 {
3311 /* FP > SP + frame_size. This may be because of
3312 an alloca or somethings similar. Fix sp to
3313 "pre-alloca" value, and try again. */
3315 /* Need to reset the status of all registers. Otherwise,
3316 we will hit a guard that prevents the new address
3317 for each register to be recomputed during the second
3318 pass. */
3321 }
3322 }
3323 }
3326 {
3328 }
3336 )
3337 {
3338 /* These instructions are part of the prologue, but we don't
3339 need to do anything special to handle them. */
3340 }
3341 /* The instructions below load $at or $t0 with an immediate
3342 value in preparation for a stack adjustment via
3343 subu $sp,$sp,[$at,$t0]. These instructions could also
3344 initialize a local variable, so we accept them only before
3345 a stack adjustment instruction was seen. */
3353 ))
3354 {
3357 }
3358 else
3359 {
3360 /* This instruction is not an instruction typically found
3361 in a prologue, so we must have reached the end of the
3362 prologue. */
3363 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
3364 loop now? Why would we need to continue scanning the function
3365 instructions? */
3369 /* Check for branches and jumps. For now, only jump to
3370 register are caught (i.e. returns). */
3373 }
3375 /* If the previous instruction was a jump, we must have reached
3376 the end of the prologue by now. Stop scanning so that we do
3377 not go past the function return. */
3380 }
3383 {
3388 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3389 this assignment below, eventually. But it's still needed
3390 for now. */
3395 }
3397 /* If we didn't reach the end of the prologue when scanning the function
3398 instructions, then set end_prologue_addr to the address of the
3399 instruction immediately after the last one we scanned. */
3400 /* brobecker/2004-10-10: I don't think this would ever happen, but
3401 we may as well be careful and do our best if we have a null
3402 end_prologue_addr. */
3406 /* In a frameless function, we might have incorrectly
3407 skipped some load immediate instructions. Undo the skipping
3408 if the load immediate was not followed by a stack adjustment. */
3413 }
3415 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3416 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3417 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3418 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3422 {
3433 /* Analyze the function prologue. */
3434 {
3436 CORE_ADDR start_addr;
3441 /* We can't analyze the prologue if we couldn't find the begining
3442 of the function. */
3447 }
3449 /* gdbarch_sp_regnum contains the value and not the address. */
3455 }
3457 static void
3460 {
3462 this_cache);
3463 /* This marks the outermost frame. */
3467 }
3472 {
3474 this_cache);
3476 }
3478 static int
3481 {
3486 }
3489 {
3490 NORMAL_FRAME,
3491 default_frame_unwind_stop_reason,
3492 mips_insn32_frame_this_id,
3493 mips_insn32_frame_prev_register,
3494 NULL,
3495 mips_insn32_frame_sniffer
3496 };
3498 static CORE_ADDR
3501 {
3503 this_cache);
3505 }
3508 {
3510 mips_insn32_frame_base_address,
3511 mips_insn32_frame_base_address,
3512 mips_insn32_frame_base_address
3513 };
3517 {
3521 else
3523 }
3527 {
3528 CORE_ADDR pc;
3529 CORE_ADDR start_addr;
3530 CORE_ADDR stack_addr;
3540 /* The return address is in the link register. */
3545 /* Frame ID, since it's a frameless / stackless function, no stack
3546 space is allocated and SP on entry is the current SP. */
3553 /* Assume that the frame's base is the same as the
3554 stack-pointer. */
3558 }
3560 static void
3563 {
3567 }
3572 {
3576 }
3578 static int
3581 {
3587 /* Use the stub unwinder for unreadable code. */
3594 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
3602 /* Calling a PIC function from a non-PIC function passes through a
3603 stub. The stub for foo is named ".pic.foo". */
3611 }
3614 {
3615 NORMAL_FRAME,
3616 default_frame_unwind_stop_reason,
3617 mips_stub_frame_this_id,
3618 mips_stub_frame_prev_register,
3619 NULL,
3620 mips_stub_frame_sniffer
3621 };
3623 static CORE_ADDR
3626 {
3630 }
3633 {
3635 mips_stub_frame_base_address,
3636 mips_stub_frame_base_address,
3637 mips_stub_frame_base_address
3638 };
3642 {
3645 else
3647 }
3649 /* mips_addr_bits_remove - remove useless address bits */
3651 static CORE_ADDR
3653 {
3660 /* This hack is a work-around for existing boards using PMON, the
3661 simulator, and any other 64-bit targets that doesn't have true
3662 64-bit addressing. On these targets, the upper 32 bits of
3663 addresses are ignored by the hardware. Thus, the PC or SP are
3664 likely to have been sign extended to all 1s by instruction
3665 sequences that load 32-bit addresses. For example, a typical
3666 piece of code that loads an address is this:
3668 lui $r2, <upper 16 bits>
3669 ori $r2, <lower 16 bits>
3671 But the lui sign-extends the value such that the upper 32 bits
3672 may be all 1s. The workaround is simply to mask off these
3673 bits. In the future, gcc may be changed to support true 64-bit
3674 addressing, and this masking will have to be disabled. */
3676 else
3678 }
3681 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3682 instruction and ending with a SC/SCD instruction. If such a sequence
3683 is found, attempt to step through it. A breakpoint is placed at the end of
3684 the sequence. */
3686 /* Instructions used during single-stepping of atomic sequences, standard
3687 ISA version. */
3688 #define LL_OPCODE 0x30
3689 #define LLD_OPCODE 0x34
3690 #define SC_OPCODE 0x38
3691 #define SCD_OPCODE 0x3c
3693 static int
3696 {
3700 ULONGEST insn;
3707 /* Assume all atomic sequences start with a ll/lld instruction. */
3711 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3712 instructions. */
3714 {
3719 /* Assume that there is at most one branch in the atomic
3720 sequence. If a branch is found, put a breakpoint in its
3721 destination address. */
3723 {
3751 /* Fall through. */
3756 }
3758 {
3762 standard single-step code. */
3764 last_breakpoint++;
3765 }
3769 }
3771 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3777 /* Insert a breakpoint right after the end of the atomic sequence. */
3780 /* Check for duplicated breakpoints. Check also for a breakpoint
3781 placed (branch instruction's destination) in the atomic sequence. */
3785 /* Effectively inserts the breakpoints. */
3790 }
3792 static int
3795 CORE_ADDR pc)
3796 {
3801 destination. */
3804 ULONGEST insn;
3808 /* Assume all atomic sequences start with a ll/lld instruction. */
3819 /* Assume all atomic sequences end with an sc/scd instruction. Assume
3820 that no atomic sequence is longer than "atomic_sequence_length"
3821 instructions. */
3825 {
3831 /* Assume that there is at most one conditional branch in the
3832 atomic sequence. If a branch is found, put a breakpoint in
3833 its destination address. */
3835 {
3836 /* 48-bit instructions. */
3841 /* 32-bit instructions. */
3844 {
3847 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
3848 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
3850 /* BLTZALS, BGEZALS: bits 010000 100x1 */
3853 /* BC2F, BC2T: bits 010000 1010x xxx00 */
3855 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
3858 /* BC1F, BC1T: bits 010000 1110x xxx00 */
3861 /* BC1ANY*: bits 010000 111xx xxx01 */
3863 /* Fall through. */
3880 /* POOL32Axf: bits 000000 ... 111100 */
3882 /* JALR, JALR.HB: 000000 000x111100 111100 */
3883 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
3885 /* Fall through. */
3895 /* SC, SCD: bits 011000 1x11 */
3898 }
3902 /* 16-bit instructions. */
3905 {
3914 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
3916 /* JRADDIUSP: bits 010001 11000 */
3922 }
3924 }
3926 {
3929 standard single-step code. */
3931 last_breakpoint++;
3932 }
3933 }
3937 /* Insert a breakpoint right after the end of the atomic sequence. */
3940 /* Check for duplicated breakpoints. Check also for a breakpoint
3941 placed (branch instruction's destination) in the atomic sequence */
3945 /* Effectively inserts the breakpoints. */
3950 }
3952 static int
3955 {
3960 else
3962 }
3964 /* mips_software_single_step() is called just before we want to resume
3965 the inferior, if we want to single-step it but there is no hardware
3966 or kernel single-step support (MIPS on GNU/Linux for example). We find
3967 the target of the coming instruction and breakpoint it. */
3969 int
3971 {
3984 }
3986 /* Test whether the PC points to the return instruction at the
3987 end of a function. */
3989 static int
3991 {
3992 ULONGEST insn;
3993 ULONGEST hint;
3995 /* This used to check for MIPS16, but this piece of code is never
3996 called for MIPS16 functions. And likewise microMIPS ones. */
4002 }
4005 /* This fencepost looks highly suspicious to me. Removing it also
4006 seems suspicious as it could affect remote debugging across serial
4007 lines. */
4009 static CORE_ADDR
4011 {
4012 CORE_ADDR start_pc;
4013 CORE_ADDR fence;
4031 /* Search back for previous return. */
4034 {
4035 /* It's not clear to me why we reach this point when
4036 stop_soon, but with this test, at least we
4037 don't print out warnings for every child forked (eg, on
4038 decstation). 22apr93 rich@cygnus.com. */
4040 {
4047 {
4048 /* This actually happens frequently in embedded
4049 development, when you first connect to a board
4050 and your stack pointer and pc are nowhere in
4051 particular. This message needs to give people
4052 in that situation enough information to
4053 determine that it's no big deal. */
4067 }
4068 }
4071 }
4073 {
4076 /* On MIPS16, any one of the following is likely to be the
4077 start of a function:
4078 extend save
4079 save
4080 entry
4081 addiu sp,-n
4082 daddiu sp,-n
4083 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4086 {
4088 {
4093 }
4095 }
4105 else
4107 }
4109 {
4110 ULONGEST insn;
4116 /* On microMIPS, any one of the following is likely to be the
4117 start of a function:
4118 ADDIUSP -imm
4119 (D)ADDIU $sp, -imm
4120 LUI $gp, imm */
4123 {
4133 /* (D)ADDIU $sp, imm */
4140 /* LUI: bits 010000 001101 */
4142 /* LUI $gp, imm */
4148 /* ADDIUSP: bits 010011 1 */
4149 {
4152 /* ADDIUSP -imm */
4154 }
4155 else
4156 /* ADDIUS5: bits 010011 0 */
4157 {
4161 /* ADDIUS5 $sp, -imm */
4163 }
4165 }
4168 }
4170 {
4171 /* Skip return and its delay slot. */
4174 }
4177 }
4179 struct mips_objfile_private
4180 {
4181 bfd_size_type size;
4183 };
4185 /* According to the current ABI, should the type be passed in a
4186 floating-point register (assuming that there is space)? When there
4187 is no FPU, FP are not even considered as possible candidates for
4188 FP registers and, consequently this returns false - forces FP
4189 arguments into integer registers. */
4191 static int
4194 {
4203 }
4205 /* On o32, argument passing in GPRs depends on the alignment of the type being
4206 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4208 static int
4210 {
4216 {
4220 }
4222 {
4230 }
4232 }
4234 /* Adjust the address downward (direction of stack growth) so that it
4235 is correctly aligned for a new stack frame. */
4236 static CORE_ADDR
4238 {
4240 }
4242 /* Implement the "push_dummy_code" gdbarch method. */
4244 static CORE_ADDR
4250 {
4252 CORE_ADDR nop_addr;
4253 CORE_ADDR bp_slot;
4255 /* Reserve enough room on the stack for our breakpoint instruction. */
4258 /* Return to microMIPS mode if calling microMIPS code to avoid
4259 triggering an address error exception on processors that only
4260 support microMIPS execution. */
4264 /* The breakpoint layer automatically adjusts the address of
4265 breakpoints inserted in a branch delay slot. With enough
4266 bad luck, the 4 bytes located just before our breakpoint
4267 instruction could look like a branch instruction, and thus
4268 trigger the adjustement, and break the function call entirely.
4269 So, we reserve those 4 bytes and write a nop instruction
4270 to prevent that from happening. */
4275 /* Inferior resumes at the function entry point. */
4279 }
4281 static CORE_ADDR
4286 {
4296 /* For shared libraries, "t9" needs to point at the function
4297 address. */
4300 /* Set the return address register to point to the entry point of
4301 the program, where a breakpoint lies in wait. */
4304 /* First ensure that the stack and structure return address (if any)
4305 are properly aligned. The stack has to be at least 64-bit
4306 aligned even on 32-bit machines, because doubles must be 64-bit
4307 aligned. For n32 and n64, stack frames need to be 128-bit
4308 aligned, so we round to this widest known alignment. */
4313 /* Now make space on the stack for the args. We allocate more
4314 than necessary for EABI, because the first few arguments are
4315 passed in registers, but that's OK. */
4325 /* Initialize the integer and float register pointers. */
4329 /* The struct_return pointer occupies the first parameter-passing reg. */
4331 {
4334 "mips_eabi_push_dummy_call: "
4338 }
4340 /* Now load as many as possible of the first arguments into
4341 registers, and push the rest onto the stack. Loop thru args
4342 from first to last. */
4344 {
4357 /* Function pointer arguments to mips16 code need to be made into
4358 mips16 pointers. */
4361 {
4366 else
4367 {
4371 }
4372 }
4373 /* The EABI passes structures that do not fit in a register by
4374 reference. */
4377 {
4385 }
4386 else
4389 /* 32-bit ABIs always start floating point arguments in an
4390 even-numbered floating point register. Round the FP register
4391 up before the check to see if there are any FP registers
4392 left. Non MIPS_EABI targets also pass the FP in the integer
4393 registers so also round up normal registers. */
4395 {
4397 float_argreg++;
4398 }
4400 /* Floating point arguments passed in registers have to be
4401 treated specially. On 32-bit architectures, doubles
4402 are passed in register pairs; the even register gets
4403 the low word, and the odd register gets the high word.
4404 On non-EABI processors, the first two floating point arguments are
4405 also copied to general registers, because MIPS16 functions
4406 don't use float registers for arguments. This duplication of
4407 arguments in general registers can't hurt non-MIPS16 functions
4408 because those registers are normally skipped. */
4409 /* MIPS_EABI squeezes a struct that contains a single floating
4410 point value into an FP register instead of pushing it onto the
4411 stack. */
4414 {
4415 /* EABI32 will pass doubles in consecutive registers, even on
4416 64-bit cores. At one time, we used to check the size of
4417 `float_argreg' to determine whether or not to pass doubles
4418 in consecutive registers, but this is not sufficient for
4419 making the ABI determination. */
4421 {
4426 /* Write the low word of the double to the even register(s). */
4434 /* Write the high word of the double to the odd register(s). */
4441 }
4442 else
4443 {
4444 /* This is a floating point value that fits entirely
4445 in a single register. */
4446 /* On 32 bit ABI's the float_argreg is further adjusted
4447 above to ensure that it is even register aligned. */
4453 }
4454 }
4455 else
4456 {
4457 /* Copy the argument to general registers or the stack in
4458 register-sized pieces. Large arguments are split between
4459 registers and stack. */
4460 /* Note: structs whose size is not a multiple of regsize
4461 are treated specially: Irix cc passes
4462 them in registers where gcc sometimes puts them on the
4463 stack. For maximum compatibility, we will put them in
4464 both places. */
4467 /* Note: Floating-point values that didn't fit into an FP
4468 register are only written to memory. */
4470 {
4471 /* Remember if the argument was written to the stack. */
4477 partial_len);
4479 /* Write this portion of the argument to the stack. */
4481 || odd_sized_struct
4483 {
4484 /* Should shorter than int integer values be
4485 promoted to int before being stored? */
4487 CORE_ADDR addr;
4490 {
4500 }
4503 {
4508 }
4513 {
4518 {
4521 }
4522 }
4524 }
4526 /* Note!!! This is NOT an else clause. Odd sized
4527 structs may go thru BOTH paths. Floating point
4528 arguments will not. */
4529 /* Write this portion of the argument to a general
4530 purpose register. */
4533 {
4534 LONGEST regval =
4539 argreg,
4542 argreg++;
4543 }
4548 /* Compute the offset into the stack at which we will
4549 copy the next parameter.
4551 In the new EABI (and the NABI32), the stack_offset
4552 only needs to be adjusted when it has been used. */
4556 }
4557 }
4560 }
4564 /* Return adjusted stack pointer. */
4566 }
4568 /* Determine the return value convention being used. */
4570 static enum return_value_convention
4574 {
4582 /* Floating point type? */
4584 {
4587 /* Structs with a single field of float type
4588 are returned in a floating point register. */
4592 {
4597 }
4598 }
4601 {
4602 /* A floating-point value belongs in the least significant part
4603 of FP0/FP1. */
4607 }
4608 else
4609 {
4610 /* An integer value goes in V0/V1. */
4614 }
4618 {
4625 offset);
4626 }
4629 }
4632 /* N32/N64 ABI stuff. */
4634 /* Search for a naturally aligned double at OFFSET inside a struct
4635 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4636 registers. */
4638 static int
4641 {
4654 {
4658 /* We're only looking at normal fields. */
4663 /* If we have gone past the offset, there is no double to pass. */
4670 /* If this field is entirely before the requested offset, go
4671 on to the next one. */
4675 /* If this is our special aligned double, we can stop. */
4680 /* This field starts at or before the requested offset, and
4681 overlaps it. If it is a structure, recurse inwards. */
4683 }
4686 }
4688 static CORE_ADDR
4693 {
4702 /* For shared libraries, "t9" needs to point at the function
4703 address. */
4706 /* Set the return address register to point to the entry point of
4707 the program, where a breakpoint lies in wait. */
4710 /* First ensure that the stack and structure return address (if any)
4711 are properly aligned. The stack has to be at least 64-bit
4712 aligned even on 32-bit machines, because doubles must be 64-bit
4713 aligned. For n32 and n64, stack frames need to be 128-bit
4714 aligned, so we round to this widest known alignment. */
4719 /* Now make space on the stack for the args. */
4729 /* Initialize the integer and float register pointers. */
4733 /* The struct_return pointer occupies the first parameter-passing reg. */
4735 {
4738 "mips_n32n64_push_dummy_call: "
4742 }
4744 /* Now load as many as possible of the first arguments into
4745 registers, and push the rest onto the stack. Loop thru args
4746 from first to last. */
4748 {
4762 /* A 128-bit long double value requires an even-odd pair of
4763 floating-point registers. */
4767 {
4768 float_argreg++;
4769 argreg++;
4770 }
4774 {
4775 /* This is a floating point value that fits entirely
4776 in a single register or a pair of registers. */
4788 float_argreg++;
4789 argreg++;
4791 {
4803 float_argreg++;
4804 argreg++;
4805 }
4806 }
4807 else
4808 {
4809 /* Copy the argument to general registers or the stack in
4810 register-sized pieces. Large arguments are split between
4811 registers and stack. */
4812 /* For N32/N64, structs, unions, or other composite types are
4813 treated as a sequence of doublewords, and are passed in integer
4814 or floating point registers as though they were simple scalar
4815 parameters to the extent that they fit, with any excess on the
4816 stack packed according to the normal memory layout of the
4817 object.
4818 The caller does not reserve space for the register arguments;
4819 the callee is responsible for reserving it if required. */
4820 /* Note: Floating-point values that didn't fit into an FP
4821 register are only written to memory. */
4823 {
4824 /* Remember if the argument was written to the stack. */
4830 partial_len);
4835 /* Write this portion of the argument to the stack. */
4837 {
4838 /* Should shorter than int integer values be
4839 promoted to int before being stored? */
4841 CORE_ADDR addr;
4844 {
4849 }
4852 {
4857 }
4862 {
4867 {
4870 }
4871 }
4873 }
4875 /* Note!!! This is NOT an else clause. Odd sized
4876 structs may go thru BOTH paths. */
4877 /* Write this portion of the argument to a general
4878 purpose register. */
4880 {
4881 LONGEST regval;
4883 /* Sign extend pointers, 32-bit integers and signed
4884 16-bit and 8-bit integers; everything else is taken
4885 as is. */
4894 byte_order);
4895 else
4897 byte_order);
4899 /* A non-floating-point argument being passed in a
4900 general register. If a struct or union, and if
4901 the remaining length is smaller than the register
4902 size, we have to adjust the register value on
4903 big endian targets.
4905 It does not seem to be necessary to do the
4906 same for integral types. */
4917 argreg,
4923 {
4926 float_argreg,
4929 regval);
4930 }
4932 float_argreg++;
4933 argreg++;
4934 }
4939 /* Compute the offset into the stack at which we will
4940 copy the next parameter.
4942 In N32 (N64?), the stack_offset only needs to be
4943 adjusted when it has been used. */
4947 }
4948 }
4951 }
4955 /* Return adjusted stack pointer. */
4957 }
4959 static enum return_value_convention
4963 {
4966 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
4968 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
4969 if needed), as appropriate for the type. Composite results (struct,
4970 union, or array) are returned in $2/$f0 and $3/$f2 according to the
4971 following rules:
4973 * A struct with only one or two floating point fields is returned in $f0
4974 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
4975 case.
4977 * Any other composite results of at most 128 bits are returned in
4978 $2 (first 64 bits) and $3 (remainder, if necessary).
4980 * Larger composite results are handled by converting the function to a
4981 procedure with an implicit first parameter, which is a pointer to an area
4982 reserved by the caller to receive the result. [The o32-bit ABI requires
4983 that all composite results be handled by conversion to implicit first
4984 parameters. The MIPS/SGI Fortran implementation has always made a
4985 specific exception to return COMPLEX results in the floating point
4986 registers.] */
4993 {
4994 /* A 128-bit floating-point value fills both $f0 and $f2. The
4995 two registers are used in the same as memory order, so the
4996 eight bytes with the lower memory address are in $f0. */
5011 }
5014 {
5015 /* A single or double floating-point value that fits in FP0. */
5025 }
5037 {
5038 /* A struct that contains one or two floats. Each value is part
5039 in the least significant part of their floating point
5040 register (or GPR, for soft float). */
5047 {
5052 offset);
5054 {
5055 /* A 16-byte long double field goes in two consecutive
5056 registers. */
5067 }
5068 else
5074 }
5076 }
5080 {
5081 /* A composite type. Extract the left justified value,
5082 regardless of the byte order. I.e. DO NOT USE
5083 mips_xfer_lower. */
5089 {
5099 offset);
5100 }
5102 }
5103 else
5104 {
5105 /* A scalar extract each part but least-significant-byte
5106 justified. */
5112 {
5123 }
5125 }
5126 }
5128 /* Which registers to use for passing floating-point values between
5129 function calls, one of floating-point, general and both kinds of
5130 registers. O32 and O64 use different register kinds for standard
5131 MIPS and MIPS16 code; to make the handling of cases where we may
5132 not know what kind of code is being used (e.g. no debug information)
5133 easier we sometimes use both kinds. */
5135 enum mips_fval_reg
5136 {
5137 mips_fval_fpr,
5138 mips_fval_gpr,
5139 mips_fval_both
5140 };
5142 /* O32 ABI stuff. */
5144 static CORE_ADDR
5149 {
5158 /* For shared libraries, "t9" needs to point at the function
5159 address. */
5162 /* Set the return address register to point to the entry point of
5163 the program, where a breakpoint lies in wait. */
5166 /* First ensure that the stack and structure return address (if any)
5167 are properly aligned. The stack has to be at least 64-bit
5168 aligned even on 32-bit machines, because doubles must be 64-bit
5169 aligned. For n32 and n64, stack frames need to be 128-bit
5170 aligned, so we round to this widest known alignment. */
5175 /* Now make space on the stack for the args. */
5177 {
5180 /* Align to double-word if necessary. */
5183 /* Allocate space on the stack. */
5185 }
5193 /* Initialize the integer and float register pointers. */
5197 /* The struct_return pointer occupies the first parameter-passing reg. */
5199 {
5202 "mips_o32_push_dummy_call: "
5207 }
5209 /* Now load as many as possible of the first arguments into
5210 registers, and push the rest onto the stack. Loop thru args
5211 from first to last. */
5213 {
5227 /* 32-bit ABIs always start floating point arguments in an
5228 even-numbered floating point register. Round the FP register
5229 up before the check to see if there are any FP registers
5230 left. O32 targets also pass the FP in the integer registers
5231 so also round up normal registers. */
5233 {
5235 float_argreg++;
5236 }
5238 /* Floating point arguments passed in registers have to be
5239 treated specially. On 32-bit architectures, doubles are
5240 passed in register pairs; the even FP register gets the
5241 low word, and the odd FP register gets the high word.
5242 On O32, the first two floating point arguments are also
5243 copied to general registers, following their memory order,
5244 because MIPS16 functions don't use float registers for
5245 arguments. This duplication of arguments in general
5246 registers can't hurt non-MIPS16 functions, because those
5247 registers are normally skipped. */
5251 {
5253 {
5258 /* First word. */
5266 regval);
5272 /* Second word. */
5280 regval);
5285 }
5286 else
5287 {
5288 /* This is a floating point value that fits entirely
5289 in a single register. */
5290 /* On 32 bit ABI's the float_argreg is further adjusted
5291 above to ensure that it is even register aligned. */
5298 /* Although two FP registers are reserved for each
5299 argument, only one corresponding integer register is
5300 reserved. */
5305 }
5306 /* Reserve space for the FP register. */
5308 }
5309 else
5310 {
5311 /* Copy the argument to general registers or the stack in
5312 register-sized pieces. Large arguments are split between
5313 registers and stack. */
5314 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5315 are treated specially: Irix cc passes
5316 them in registers where gcc sometimes puts them on the
5317 stack. For maximum compatibility, we will put them in
5318 both places. */
5321 /* Structures should be aligned to eight bytes (even arg registers)
5322 on MIPS_ABI_O32, if their first member has double precision. */
5324 {
5326 {
5327 argreg++;
5329 }
5330 }
5332 {
5333 /* Remember if the argument was written to the stack. */
5339 partial_len);
5341 /* Write this portion of the argument to the stack. */
5344 {
5345 /* Should shorter than int integer values be
5346 promoted to int before being stored? */
5348 CORE_ADDR addr;
5352 {
5357 }
5362 {
5367 {
5370 }
5371 }
5373 }
5375 /* Note!!! This is NOT an else clause. Odd sized
5376 structs may go thru BOTH paths. */
5377 /* Write this portion of the argument to a general
5378 purpose register. */
5380 {
5382 byte_order);
5383 /* Value may need to be sign extended, because
5384 mips_isa_regsize() != mips_abi_regsize(). */
5386 /* A non-floating-point argument being passed in a
5387 general register. If a struct or union, and if
5388 the remaining length is smaller than the register
5389 size, we have to adjust the register value on
5390 big endian targets.
5392 It does not seem to be necessary to do the
5393 same for integral types.
5395 Also don't do this adjustment on O64 binaries.
5397 cagney/2001-07-23: gdb/179: Also, GCC, when
5398 outputting LE O32 with sizeof (struct) <
5399 mips_abi_regsize(), generates a left shift
5400 as part of storing the argument in a register
5401 (the left shift isn't generated when
5402 sizeof (struct) >= mips_abi_regsize()). Since
5403 it is quite possible that this is GCC
5404 contradicting the LE/O32 ABI, GDB has not been
5405 adjusted to accommodate this. Either someone
5406 needs to demonstrate that the LE/O32 ABI
5407 specifies such a left shift OR this new ABI gets
5408 identified as such and GDB gets tweaked
5409 accordingly. */
5420 argreg,
5423 argreg++;
5425 /* Prevent subsequent floating point arguments from
5426 being passed in floating point registers. */
5428 }
5433 /* Compute the offset into the stack at which we will
5434 copy the next parameter.
5436 In older ABIs, the caller reserved space for
5437 registers that contained arguments. This was loosely
5438 refered to as their "home". Consequently, space is
5439 always allocated. */
5442 }
5443 }
5446 }
5450 /* Return adjusted stack pointer. */
5452 }
5454 static enum return_value_convention
5458 {
5471 {
5472 /* A single-precision floating-point value. If reading in or copying,
5473 then we get it from/put it to FP0 for standard MIPS code or GPR2
5474 for MIPS16 code. If writing out only, then we put it to both FP0
5475 and GPR2. We do not support reading in with no function known, if
5476 this safety check ever triggers, then we'll have to try harder. */
5480 {
5490 }
5505 }
5508 {
5509 /* A double-precision floating-point value. If reading in or copying,
5510 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5511 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5512 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5513 no function known, if this safety check ever triggers, then we'll
5514 have to try harder. */
5518 {
5529 }
5531 {
5532 /* The most significant part goes in FP1, and the least significant
5533 in FP0. */
5535 {
5562 }
5563 }
5565 {
5566 /* The two 32-bit parts are always placed in GPR2 and GPR3
5567 following these registers' memory order. */
5576 }
5578 }
5579 #if 0
5592 {
5593 /* A struct that contains one or two floats. Each value is part
5594 in the least significant part of their floating point
5595 register.. */
5601 {
5606 offset);
5612 }
5614 }
5615 #endif
5616 #if 0
5619 {
5620 /* A structure or union. Extract the left justified value,
5621 regardless of the byte order. I.e. DO NOT USE
5622 mips_xfer_lower. */
5628 {
5638 }
5640 }
5641 #endif
5642 else
5643 {
5644 /* A scalar extract each part but least-significant-byte
5645 justified. o32 thinks registers are 4 byte, regardless of
5646 the ISA. */
5652 {
5663 }
5665 }
5666 }
5668 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5669 ABI. */
5671 static CORE_ADDR
5677 {
5686 /* For shared libraries, "t9" needs to point at the function
5687 address. */
5690 /* Set the return address register to point to the entry point of
5691 the program, where a breakpoint lies in wait. */
5694 /* First ensure that the stack and structure return address (if any)
5695 are properly aligned. The stack has to be at least 64-bit
5696 aligned even on 32-bit machines, because doubles must be 64-bit
5697 aligned. For n32 and n64, stack frames need to be 128-bit
5698 aligned, so we round to this widest known alignment. */
5703 /* Now make space on the stack for the args. */
5705 {
5708 /* Allocate space on the stack. */
5710 }
5718 /* Initialize the integer and float register pointers. */
5722 /* The struct_return pointer occupies the first parameter-passing reg. */
5724 {
5727 "mips_o64_push_dummy_call: "
5732 }
5734 /* Now load as many as possible of the first arguments into
5735 registers, and push the rest onto the stack. Loop thru args
5736 from first to last. */
5738 {
5753 /* Function pointer arguments to mips16 code need to be made into
5754 mips16 pointers. */
5757 {
5761 {
5765 }
5766 }
5768 /* Floating point arguments passed in registers have to be
5769 treated specially. On 32-bit architectures, doubles are
5770 passed in register pairs; the even FP register gets the
5771 low word, and the odd FP register gets the high word.
5772 On O64, the first two floating point arguments are also
5773 copied to general registers, because MIPS16 functions
5774 don't use float registers for arguments. This duplication
5775 of arguments in general registers can't hurt non-MIPS16
5776 functions because those registers are normally skipped. */
5780 {
5790 argreg++;
5791 /* Reserve space for the FP register. */
5793 }
5794 else
5795 {
5796 /* Copy the argument to general registers or the stack in
5797 register-sized pieces. Large arguments are split between
5798 registers and stack. */
5799 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5800 are treated specially: Irix cc passes them in registers
5801 where gcc sometimes puts them on the stack. For maximum
5802 compatibility, we will put them in both places. */
5806 {
5807 /* Remember if the argument was written to the stack. */
5813 partial_len);
5815 /* Write this portion of the argument to the stack. */
5818 {
5819 /* Should shorter than int integer values be
5820 promoted to int before being stored? */
5822 CORE_ADDR addr;
5825 {
5831 }
5834 {
5839 }
5844 {
5849 {
5852 }
5853 }
5855 }
5857 /* Note!!! This is NOT an else clause. Odd sized
5858 structs may go thru BOTH paths. */
5859 /* Write this portion of the argument to a general
5860 purpose register. */
5862 {
5864 byte_order);
5865 /* Value may need to be sign extended, because
5866 mips_isa_regsize() != mips_abi_regsize(). */
5868 /* A non-floating-point argument being passed in a
5869 general register. If a struct or union, and if
5870 the remaining length is smaller than the register
5871 size, we have to adjust the register value on
5872 big endian targets.
5874 It does not seem to be necessary to do the
5875 same for integral types. */
5886 argreg,
5889 argreg++;
5891 /* Prevent subsequent floating point arguments from
5892 being passed in floating point registers. */
5894 }
5899 /* Compute the offset into the stack at which we will
5900 copy the next parameter.
5902 In older ABIs, the caller reserved space for
5903 registers that contained arguments. This was loosely
5904 refered to as their "home". Consequently, space is
5905 always allocated. */
5908 }
5909 }
5912 }
5916 /* Return adjusted stack pointer. */
5918 }
5920 static enum return_value_convention
5924 {
5936 {
5937 /* A floating-point value. If reading in or copying, then we get it
5938 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
5939 If writing out only, then we put it to both FP0 and GPR2. We do
5940 not support reading in with no function known, if this safety
5941 check ever triggers, then we'll have to try harder. */
5945 {
5955 }
5970 }
5971 else
5972 {
5973 /* A scalar extract each part but least-significant-byte
5974 justified. */
5980 {
5991 }
5993 }
5994 }
5996 /* Floating point register management.
5998 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
5999 64bit operations, these early MIPS cpus treat fp register pairs
6000 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6001 registers and offer a compatibility mode that emulates the MIPS2 fp
6002 model. When operating in MIPS2 fp compat mode, later cpu's split
6003 double precision floats into two 32-bit chunks and store them in
6004 consecutive fp regs. To display 64-bit floats stored in this
6005 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6006 Throw in user-configurable endianness and you have a real mess.
6008 The way this works is:
6009 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6010 double-precision value will be split across two logical registers.
6011 The lower-numbered logical register will hold the low-order bits,
6012 regardless of the processor's endianness.
6013 - If we are on a 64-bit processor, and we are looking for a
6014 single-precision value, it will be in the low ordered bits
6015 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6016 save slot in memory.
6017 - If we are in 64-bit mode, everything is straightforward.
6019 Note that this code only deals with "live" registers at the top of the
6020 stack. We will attempt to deal with saved registers later, when
6021 the raw/cooked register interface is in place. (We need a general
6022 interface that can deal with dynamic saved register sizes -- fp
6023 regs could be 32 bits wide in one frame and 64 on the frame above
6024 and below). */
6026 /* Copy a 32-bit single-precision value from the current frame
6027 into rare_buffer. */
6029 static void
6032 {
6041 {
6042 /* We have a 64-bit value for this register. Find the low-order
6043 32 bits. */
6048 else
6052 }
6053 else
6054 {
6056 }
6057 }
6059 /* Copy a 64-bit double-precision value from the current frame into
6060 rare_buffer. This may include getting half of it from the next
6061 register. */
6063 static void
6066 {
6071 {
6072 /* We have a 64-bit value for this register, and we should use
6073 all 64 bits. */
6077 }
6078 else
6079 {
6087 /* mips_read_fp_register_single will find the correct 32 bits from
6088 each register. */
6090 {
6093 }
6094 else
6095 {
6098 }
6099 }
6100 }
6102 static void
6120 {
6123 /* 4-byte registers: Print hex and floating. Also print even
6124 numbered registers as doubles. */
6137 else
6141 {
6149 else
6151 }
6152 }
6153 else
6154 {
6157 /* Eight byte registers: print each one as hex, float and double. */
6174 else
6180 else
6182 }
6183 }
6185 static void
6188 {
6194 {
6197 }
6201 {
6205 }
6209 /* The problem with printing numeric register names (r26, etc.) is that
6210 the user can't use them on input. Probably the best solution is to
6211 fix it so that either the numeric or the funky (a2, etc.) names
6212 are accepted on input. */
6215 else
6222 val,
6224 }
6226 /* Replacement for generic do_registers_info.
6227 Print regs in pretty columns. */
6229 static int
6232 {
6237 }
6240 /* Print a row's worth of GP (int) registers, with name labels above. */
6242 static int
6245 {
6247 /* Do values for GP (int) regs. */
6250 per row. */
6254 /* For GP registers, we print a separate row of names above the vals. */
6258 regnum++)
6259 {
6264 /* Large registers are handled separately. */
6266 {
6270 /* Print this register on a row by itself. */
6274 }
6280 col++;
6281 }
6286 /* Print the R0 to R31 names. */
6290 else
6293 /* Now print the values in hex, 4 or 8 to the row. */
6297 regnum++)
6298 {
6306 /* OK: get the data in raw format. */
6310 /* pad small registers */
6315 /* Now print the register value in hex, endian order. */
6321 else
6326 col++;
6327 }
6332 }
6334 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6336 static void
6339 {
6341 {
6348 }
6349 else
6350 /* Do all (or most) registers. */
6351 {
6355 {
6357 {
6360 else
6362 }
6363 else
6365 }
6366 }
6367 }
6369 static int
6372 {
6377 ULONGEST insn;
6390 /* _has_delay_slot above will have validated the read. */
6395 }
6397 /* To skip prologues, I use this predicate. Returns either PC itself
6398 if the code at PC does not look like a function prologue; otherwise
6399 returns an address that (if we're lucky) follows the prologue. If
6400 LENIENT, then we must skip everything which is involved in setting
6401 up the frame (it's OK to skip more, just so long as we don't skip
6402 anything which might clobber the registers which are being saved.
6403 We must skip more in the case where part of the prologue is in the
6404 delay slot of a non-prologue instruction). */
6406 static CORE_ADDR
6408 {
6409 CORE_ADDR limit_pc;
6410 CORE_ADDR func_addr;
6412 /* See if we can determine the end of the prologue via the symbol table.
6413 If so, then return either PC, or the PC after the prologue, whichever
6414 is greater. */
6416 {
6417 CORE_ADDR post_prologue_pc
6421 }
6423 /* Can't determine prologue from the symbol table, need to examine
6424 instructions. */
6426 /* Find an upper limit on the function prologue using the debug
6427 information. If the debug information could not be used to provide
6428 that bound, then use an arbitrary large number as the upper bound. */
6437 else
6439 }
6441 /* Check whether the PC is in a function epilogue (32-bit version).
6442 This is a helper function for mips_in_function_epilogue_p. */
6443 static int
6445 {
6449 {
6450 /* The MIPS epilogue is max. 12 bytes long. */
6459 {
6471 }
6474 }
6477 }
6479 /* Check whether the PC is in a function epilogue (microMIPS version).
6480 This is a helper function for mips_in_function_epilogue_p. */
6482 static int
6484 {
6487 CORE_ADDR addr;
6488 ULONGEST insn;
6497 /* The microMIPS epilogue is max. 12 bytes long. */
6506 {
6511 {
6512 /* 48-bit instructions. */
6514 /* No epilogue instructions in this category. */
6517 /* 32-bit instructions. */
6524 {
6531 /* (D)ADDIU $sp, imm */
6538 }
6541 /* 16-bit instructions. */
6544 {
6549 /* MOVE $zero, $zero aka NOP */
6555 /* JRADDIUSP: bits 010011 11000 */
6557 /* JRC: bits 010011 01101 */
6559 /* JRC $ra */
6566 /* ADDIUSP: bits 010011 1 */
6573 }
6574 }
6575 }
6578 }
6580 /* Check whether the PC is in a function epilogue (16-bit version).
6581 This is a helper function for mips_in_function_epilogue_p. */
6582 static int
6584 {
6588 {
6589 /* The MIPS epilogue is max. 12 bytes long. */
6598 {
6612 }
6615 }
6618 }
6620 /* The epilogue is defined here as the area at the end of a function,
6621 after an instruction which destroys the function's stack frame. */
6622 static int
6624 {
6629 else
6631 }
6633 /* Root of all "set mips "/"show mips " commands. This will eventually be
6634 used for all MIPS-specific commands. */
6636 static void
6638 {
6640 }
6642 static void
6644 {
6645 printf_unfiltered
6648 }
6650 /* Commands to show/set the MIPS FPU type. */
6652 static void
6654 {
6658 {
6659 printf_unfiltered
6663 }
6666 {
6678 }
6682 fpu);
6683 else
6684 printf_unfiltered
6686 }
6689 static void
6691 {
6695 }
6697 static void
6699 {
6704 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6705 instead of relying on globals. Doing that would let generic code
6706 handle the search for this specific architecture. */
6709 }
6711 static void
6713 {
6718 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6719 instead of relying on globals. Doing that would let generic code
6720 handle the search for this specific architecture. */
6723 }
6725 static void
6727 {
6732 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6733 instead of relying on globals. Doing that would let generic code
6734 handle the search for this specific architecture. */
6737 }
6739 static void
6741 {
6743 }
6745 /* Attempt to identify the particular processor model by reading the
6746 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
6747 the relevant processor still exists (it dates back to '94) and
6748 secondly this is not the way to do this. The processor type should
6749 be set by forcing an architecture change. */
6751 void
6753 {
6757 ULONGEST prid;
6762 }
6764 /* Just like reinit_frame_cache, but with the right arguments to be
6765 callable as an sfunc. */
6767 static void
6770 {
6772 }
6774 static int
6776 {
6779 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6780 disassembler needs to be able to locally determine the ISA, and
6781 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6782 work. */
6788 /* Round down the instruction address to the appropriate boundary. */
6792 /* Set the disassembler options. */
6794 /* This string is not recognized explicitly by the disassembler,
6795 but it tells the disassembler to not try to guess the ABI from
6796 the bfd elf headers, such that, if the user overrides the ABI
6797 of a program linked as NewABI, the disassembly will follow the
6798 register naming conventions specified by the user. */
6801 /* Call the appropriate disassembler based on the target endian-ness. */
6804 else
6806 }
6808 static int
6810 {
6811 /* Set up the disassembler info, so that we get the right
6812 register names from libopcodes. */
6817 }
6819 static int
6821 {
6822 /* Set up the disassembler info, so that we get the right
6823 register names from libopcodes. */
6828 }
6830 /* This function implements gdbarch_breakpoint_from_pc. It uses the
6831 program counter value to determine whether a 16- or 32-bit breakpoint
6832 should be used. It returns a pointer to a string of bytes that encode a
6833 breakpoint instruction, stores the length of the string to *lenptr, and
6834 adjusts pc (if necessary) to point to the actual memory location where
6835 the breakpoint should be inserted. */
6840 {
6844 {
6846 {
6851 }
6853 {
6856 ULONGEST insn;
6867 }
6868 else
6869 {
6870 /* The IDT board uses an unusual breakpoint value, and
6871 sometimes gets confused when it sees the usual MIPS
6872 breakpoint instruction. */
6876 /* Likewise, IRIX appears to expect a different breakpoint,
6877 although this is not apparent until you try to use pthreads. */
6890 else
6892 }
6893 }
6894 else
6895 {
6897 {
6902 }
6904 {
6907 ULONGEST insn;
6918 }
6919 else
6920 {
6933 else
6935 }
6936 }
6937 }
6939 /* Determine the remote breakpoint kind suitable for the PC. The following
6940 kinds are used:
6942 * 2 -- 16-bit MIPS16 mode breakpoint,
6944 * 3 -- 16-bit microMIPS mode breakpoint,
6946 * 4 -- 32-bit standard MIPS mode breakpoint,
6948 * 5 -- 32-bit microMIPS mode breakpoint. */
6950 static void
6953 {
6957 {
6960 }
6962 {
6963 ULONGEST insn;
6971 }
6972 else
6974 }
6976 /* Return non-zero if the ADDR instruction has a branch delay slot
6977 (i.e. it is a jump or branch instruction). This function is based
6978 on mips32_next_pc. */
6980 static int
6982 {
6995 {
7003 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7005 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7007 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7008 }
7009 else
7011 {
7021 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7022 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7024 /* BPOSGE32, BPOSGE64: bits 1110x */
7029 }
7030 }
7032 /* Return non-zero if the ADDR instruction, which must be a 32-bit
7033 instruction if MUSTBE32 is set or can be any instruction otherwise,
7034 has a branch delay slot (i.e. it is a non-compact jump instruction). */
7036 static int
7039 {
7040 ULONGEST insn;
7049 /* POOL16C: bits 010001 */
7051 /* JR16: bits 010001 01100 */
7053 /* JALR16, JALRS16: bits 010001 0111x */
7055 /* BEQZ16, BNEZ16: bits 10x011 */
7057 /* B16: bits 110011 */
7059 /* 32-bit instructions. */
7061 /* POOL32A: bits 000000 */
7062 {
7068 /* POOL32Axf: bits 000000 ... 111100 */
7070 /* JALR, JALR.HB: 000000 000x111100 111100 */
7071 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7072 }
7075 /* POOL32I: bits 010000 */
7077 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7079 /* BLEZ, BGTZ: bits 010000 001x0 */
7081 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7084 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7086 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7089 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7092 /* BC1ANY*: bits 010000 111xx xxx01 */
7094 /* JALS, JAL: bits x11101 */
7096 /* BEQ, BNE: bits 10x101 */
7098 /* J: bits 110101 */
7100 /* JALX: bits 111100 */
7101 }
7103 static int
7106 {
7117 }
7119 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7120 This assumes KSSEG exists. */
7122 static CORE_ADDR
7124 {
7129 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7130 a compiler warning produced where CORE_ADDR is a 32-bit type even
7131 though in that case this is dead code). */
7133 {
7137 else
7146 }
7149 else
7153 }
7155 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7156 it backwards if necessary. Return the address of the new location. */
7158 static CORE_ADDR
7160 {
7161 CORE_ADDR prev_addr;
7162 CORE_ADDR boundary;
7163 CORE_ADDR func_addr;
7165 /* If a breakpoint is set on the instruction in a branch delay slot,
7166 GDB gets confused. When the breakpoint is hit, the PC isn't on
7167 the instruction in the branch delay slot, the PC will point to
7168 the branch instruction. Since the PC doesn't match any known
7169 breakpoints, GDB reports a trap exception.
7171 There are two possible fixes for this problem.
7173 1) When the breakpoint gets hit, see if the BD bit is set in the
7174 Cause register (which indicates the last exception occurred in a
7175 branch delay slot). If the BD bit is set, fix the PC to point to
7176 the instruction in the branch delay slot.
7178 2) When the user sets the breakpoint, don't allow him to set the
7179 breakpoint on the instruction in the branch delay slot. Instead
7180 move the breakpoint to the branch instruction (which will have
7181 the same result).
7183 The problem with the first solution is that if the user then
7184 single-steps the processor, the branch instruction will get
7185 skipped (since GDB thinks the PC is on the instruction in the
7186 branch delay slot).
7188 So, we'll use the second solution. To do this we need to know if
7189 the instruction we're trying to set the breakpoint on is in the
7190 branch delay slot. */
7194 /* Make sure we don't scan back before the beginning of the current
7195 function, since we may fetch constant data or insns that look like
7196 a jump. Of course we might do that anyway if the compiler has
7197 moved constants inline. :-( */
7203 {
7207 /* If the previous instruction has a branch delay slot, we have
7208 to move the breakpoint to the branch instruction. */
7212 }
7213 else
7214 {
7221 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7222 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7223 so try for that first, then try the 2 byte JALR/JR.
7224 The microMIPS ASE has a whole range of jumps and branches
7225 with delay slots, some of which take 4 bytes and some take
7226 2 bytes, so the idea is the same.
7227 FIXME: We have to assume that bpaddr is not the second half
7228 of an extended instruction. */
7230 ? micromips_instruction_has_delay_slot
7236 {
7241 /* Looks like a JR/JALR at [target-1], but it could be
7242 the second word of a previous JAL/JALX, so record it
7243 and check back one more. */
7246 {
7248 /* Looks like a JAL/JALX at [target-2], but it could also
7249 be the second word of a previous JAL/JALX, record it,
7250 and check back one more. */
7252 else
7253 /* Looks like a JAL/JALX at [target-3], so any previously
7254 recorded JAL/JALX or JR/JALR must be wrong, because:
7256 >-3: JAL
7257 -2: JAL-ext (can't be JAL/JALX)
7258 -1: bdslot (can't be JR/JALR)
7259 0: target insn
7261 Of course it could be another JAL-ext which looks
7262 like a JAL, but in that case we'd have broken out
7263 of this loop at [target-2]:
7265 -4: JAL
7266 >-3: JAL-ext
7267 -2: bdslot (can't be jmp)
7268 -1: JR/JALR
7269 0: target insn */
7271 }
7272 else
7273 {
7274 /* Not a jump instruction: if we're at [target-1] this
7275 could be the second word of a JAL/JALX, so continue;
7276 otherwise we're done. */
7279 }
7280 }
7284 }
7287 }
7289 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7290 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7292 static int
7294 {
7296 {
7308 }
7309 }
7311 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7312 call stubs, one of sf, df, sc, or dc. */
7314 static int
7316 {
7319 }
7321 /* Code at PC is a compiler-generated stub. Such a stub for a function
7322 bar might have a name like __fn_stub_bar, and might look like this:
7324 mfc1 $4, $f13
7325 mfc1 $5, $f12
7326 mfc1 $6, $f15
7327 mfc1 $7, $f14
7329 followed by (or interspersed with):
7331 j bar
7333 or:
7335 lui $25, %hi(bar)
7336 addiu $25, $25, %lo(bar)
7337 jr $25
7339 ($1 may be used in old code; for robustness we accept any register)
7340 or, in PIC code:
7342 lui $28, %hi(_gp_disp)
7343 addiu $28, $28, %lo(_gp_disp)
7344 addu $28, $28, $25
7345 lw $25, %got(bar)
7346 addiu $25, $25, %lo(bar)
7347 jr $25
7349 In the case of a __call_stub_bar stub, the sequence to set up
7350 arguments might look like this:
7352 mtc1 $4, $f13
7353 mtc1 $5, $f12
7354 mtc1 $6, $f15
7355 mtc1 $7, $f14
7357 followed by (or interspersed with) one of the jump sequences above.
7359 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7360 of J or JR, respectively, followed by:
7362 mfc1 $2, $f0
7363 mfc1 $3, $f1
7364 jr $18
7366 We are at the beginning of the stub here, and scan down and extract
7367 the target address from the jump immediate instruction or, if a jump
7368 register instruction is used, from the register referred. Return
7369 the value of PC calculated or 0 if inconclusive.
7371 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7373 static CORE_ADDR
7375 {
7389 {
7391 CORE_ADDR imm;
7397 {
7400 {
7419 }
7432 {
7438 }
7447 {
7450 }
7458 {
7465 }
7467 }
7468 }
7471 }
7473 /* If PC is in a MIPS16 call or return stub, return the address of the
7474 target PC, which is either the callee or the caller. There are several
7475 cases which must be handled:
7477 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7478 and the target PC is in $31 ($ra).
7479 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7480 and the target PC is in $2.
7481 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7482 i.e. before the JALR instruction, this is effectively a call stub
7483 and the target PC is in $2. Otherwise this is effectively
7484 a return stub and the target PC is in $18.
7485 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7486 JAL or JALR instruction, this is effectively a call stub and the
7487 target PC is buried in the instruction stream. Otherwise this
7488 is effectively a return stub and the target PC is in $18.
7489 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7490 stub and the target PC is buried in the instruction stream.
7492 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7493 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7494 gory details. */
7496 static CORE_ADDR
7498 {
7500 CORE_ADDR start_addr;
7504 /* Find the starting address and name of the function containing the PC. */
7508 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7509 and the target PC is in $31 ($ra). */
7514 return get_frame_register_signed
7517 /* If the PC is in __mips16_call_stub_*, this is one of the call
7518 call/return stubs. */
7521 {
7522 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7523 and the target PC is in $2. */
7525 return get_frame_register_signed
7528 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7529 i.e. before the JALR instruction, this is effectively a call stub
7530 and the target PC is in $2. Otherwise this is effectively
7531 a return stub and the target PC is in $18. */
7535 {
7537 /* This is the 'call' part of a call stub. The return
7538 address is in $2. */
7539 return get_frame_register_signed
7541 else
7542 /* This is the 'return' part of a call stub. The return
7543 address is in $18. */
7544 return get_frame_register_signed
7546 }
7547 else
7549 }
7551 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7552 compiler-generated call or call/return stubs. */
7555 {
7557 /* This is the 'call' part of a call stub. Call this helper
7558 to scan through this code for interesting instructions
7559 and determine the final PC. */
7561 else
7562 /* This is the 'return' part of a call stub. The return address
7563 is in $18. */
7564 return get_frame_register_signed
7566 }
7569 }
7571 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7572 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7574 static int
7576 {
7577 CORE_ADDR start_addr;
7580 /* Find the starting address of the function containing the PC. */
7584 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7585 the start, i.e. after the JALR instruction, this is effectively
7586 a return stub. */
7595 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7596 the JAL or JALR instruction, this is effectively a return stub. */
7602 /* Consume the .pic. prefix of any PIC stub, this function must return
7603 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7604 or the call stub path will trigger in handle_inferior_event causing
7605 it to go astray. */
7610 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7618 }
7620 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7621 PC of the stub target. The stub just loads $t9 and jumps to it,
7622 so that $t9 has the correct value at function entry. */
7624 static CORE_ADDR
7626 {
7634 /* The stub for foo is named ".pic.foo", and is either two
7635 instructions inserted before foo or a three instruction sequence
7636 which jumps to foo. */
7644 /* A two-instruction header. */
7648 /* A three-instruction (plus delay slot) trampoline. */
7650 {
7657 /* A stub contains these instructions:
7658 lui t9, %hi(target)
7659 j target
7660 addiu t9, t9, %lo(target)
7661 nop
7663 This works even for N64, since stubs are only generated with
7664 -msym32. */
7671 }
7673 /* Not a recognized stub. */
7675 }
7677 static CORE_ADDR
7679 {
7681 CORE_ADDR target_pc;
7682 CORE_ADDR new_pc;
7684 do
7685 {
7690 {
7694 }
7698 {
7702 }
7706 {
7710 }
7711 }
7715 }
7717 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7718 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7720 static int
7722 {
7734 else
7735 /* This will hopefully (eventually) provoke a warning. Should
7736 we be calling complaint() here? */
7739 }
7742 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7743 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7745 static int
7747 {
7759 else
7760 /* This will hopefully (eventually) provoke a warning. Should we
7761 be calling complaint() here? */
7764 }
7766 static int
7768 {
7769 /* Only makes sense to supply raw registers. */
7771 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7772 decide if it is valid. Should instead define a standard sim/gdb
7773 register numbering scheme. */
7780 else
7782 }
7785 /* Convert an integer into an address. Extracting the value signed
7786 guarantees a correctly sign extended address. */
7788 static CORE_ADDR
7791 {
7794 }
7796 /* Dummy virtual frame pointer method. This is no more or less accurate
7797 than most other architectures; we just need to be explicit about it,
7798 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7799 an assertion failure. */
7801 static void
7804 {
7807 }
7809 static void
7811 {
7833 else
7835 }
7837 static void
7839 {
7849 }
7851 static enum mips_abi
7853 {
7861 }
7863 /* Return the default compressed instruction set, either of MIPS16
7864 or microMIPS, selected when none could have been determined from
7865 the ELF header of the binary being executed (or no binary has been
7866 selected. */
7868 static enum mips_isa
7870 {
7878 }
7880 static void
7882 {
7883 /* If the size matches the set of 32-bit or 64-bit integer registers,
7884 assume that's what we've got. */
7888 /* If the size matches the full set of registers GDB traditionally
7889 knows about, including floating point, for either 32-bit or
7890 64-bit, assume that's what we've got. */
7894 /* Otherwise we don't have a useful guess. */
7895 }
7899 {
7902 }
7906 {
7921 /* Fill in the OS dependent register numbers and names. */
7923 {
7936 }
7938 {
7953 }
7954 else
7955 {
7970 else
7972 }
7974 /* Check any target description for validity. */
7976 {
7982 };
7988 };
8014 {
8017 }
8022 {
8025 }
8036 {
8039 }
8041 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8042 backend is not prepared for that, though. */
8046 {
8049 }
8059 valid_p
8065 {
8068 }
8071 {
8074 /* The DSP registers are optional; it's OK if they are absent. */
8076 {
8096 {
8099 }
8103 }
8104 }
8106 /* It would be nice to detect an attempt to use a 64-bit ABI
8107 when only 32-bit registers are provided. */
8109 }
8111 /* First of all, extract the elf_flags, if available. */
8116 else
8122 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8124 {
8140 else
8143 }
8145 /* GCC creates a pseudo-section whose name describes the ABI. */
8149 /* If we have no useful BFD information, use the ABI from the last
8150 MIPS architecture (if there is one). */
8154 /* Try the architecture for any hint of the correct ABI. */
8158 {
8160 {
8170 /* On Irix, ELF64 executables use the N64 ABI. The
8171 pseudo-sections which describe the ABI aren't present
8172 on IRIX. (Even for executables created by gcc.) */
8176 else
8179 }
8180 }
8182 /* Default 64-bit objects to N64 instead of O32. */
8191 found_abi);
8193 /* What has the user specified from the command line? */
8197 wanted_abi);
8199 /* Now that we have found what the ABI for this binary would be,
8200 check whether the user is overriding it. */
8205 else
8209 mips_abi);
8211 /* Determine the default compressed ISA. */
8218 else
8222 /* Also used when doing an architecture lookup. */
8225 "mips_gdbarch_init: "
8227 mips64_transfers_32bit_regs_p);
8229 /* Determine the MIPS FPU type. */
8230 #ifdef HAVE_ELF
8234 Tag_GNU_MIPS_ABI_FP);
8240 {
8242 {
8251 /* Soft float or unknown. */
8254 }
8255 }
8259 {
8272 }
8275 else
8281 /* Check for blatant incompatibilities. */
8283 /* If we have only 32-bit registers, then we can't debug a 64-bit
8284 ABI. */
8289 {
8293 }
8295 /* Try to find a pre-existing architecture. */
8299 {
8300 /* MIPS needs to be pedantic about which ABI the object is
8301 using. */
8306 /* Need to be pedantic about which register virtual size is
8307 used. */
8311 /* Be pedantic about which FPU is selected. */
8318 }
8320 /* Need a new architecture. Fill in a target specific vector. */
8337 {
8338 /* Some useful properties can be inferred from the target. */
8340 {
8343 }
8345 {
8348 }
8349 }
8351 /* Initially set everything according to the default ABI/ISA. */
8362 mips_ax_pseudo_register_collect);
8363 set_gdbarch_ax_pseudo_register_push_stack
8367 mips_elf_make_msymbol_special);
8380 {
8447 }
8449 /* GCC creates a pseudo-section whose name specifies the size of
8450 longs, since -mlong32 or -mlong64 may be used independent of
8451 other options. How those options affect pointer sizes is ABI and
8452 architecture dependent, so use them to override the default sizes
8453 set by the ABI. This table shows the relationship between ABI,
8454 -mlongXX, and size of pointers:
8456 ABI -mlongXX ptr bits
8457 --- -------- --------
8458 o32 32 32
8459 o32 64 32
8460 n32 32 32
8461 n32 64 64
8462 o64 32 32
8463 o64 64 64
8464 n64 32 32
8465 n64 64 64
8466 eabi32 32 32
8467 eabi32 64 32
8468 eabi64 32 32
8469 eabi64 64 64
8471 Note that for o32 and eabi32, pointers are always 32 bits
8472 regardless of any -mlongXX option. For all others, pointers and
8473 longs are the same, as set by -mlongXX or set by defaults. */
8476 {
8481 {
8484 {
8496 }
8497 }
8498 }
8500 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8501 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8502 comment:
8504 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8505 flag in object files because to do so would make it impossible to
8506 link with libraries compiled without "-gp32". This is
8507 unnecessarily restrictive.
8509 We could solve this problem by adding "-gp32" multilibs to gcc,
8510 but to set this flag before gcc is built with such multilibs will
8511 break too many systems.''
8513 But even more unhelpfully, the default linker output target for
8514 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8515 for 64-bit programs - you need to change the ABI to change this,
8516 and not all gcc targets support that currently. Therefore using
8517 this flag to detect 32-bit mode would do the wrong thing given
8518 the current gcc - it would make GDB treat these 64-bit programs
8519 as 32-bit programs by default. */
8524 /* Add/remove bits from an address. The MIPS needs be careful to
8525 ensure that all 32 bit addresses are sign extended to 64 bits. */
8528 /* Unwind the frame. */
8533 /* Map debug register numbers onto internal register numbers. */
8536 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8538 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8541 /* MIPS version of CALL_DUMMY. */
8554 mips_remote_breakpoint_from_pc);
8556 mips_adjust_breakpoint_address);
8574 else
8577 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8578 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8579 need to all be folded into the target vector. Since they are
8580 being used as guards for target_stopped_by_watchpoint, why not have
8581 target_stopped_by_watchpoint return the type of watchpoint that the code
8582 is sitting on? */
8587 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8588 to support MIPS16. This is a bad thing. Make sure not to do it
8589 if we have an OS ABI that actually supports shared libraries, since
8590 shared library support is more important. If we have an OS someday
8591 that supports both shared libraries and MIPS16, we'll have to find
8592 a better place for these.
8593 macro/2012-04-25: But that applies to return trampolines only and
8594 currently no MIPS OS ABI uses shared libraries that have them. */
8598 mips_single_step_through_delay);
8600 /* Virtual tables. */
8605 /* Hook in OS ABI-specific overrides, if they have been registered. */
8609 /* The hook may have adjusted num_regs, fetch the final value and
8610 set pc_regnum and sp_regnum now that it has been fixed. */
8615 /* Unwind the frame. */
8628 {
8632 /* Override the normal target description methods to handle our
8633 dual real and pseudo registers. */
8636 mips_tdesc_register_reggroup_p);
8642 }
8644 /* Add ABI-specific aliases for the registers. */
8649 else
8654 /* Add some other standard aliases. */
8661 value_of_mips_user_reg,
8665 }
8667 static void
8669 {
8672 /* Force the architecture to update, and (if it's a MIPS architecture)
8673 mips_gdbarch_init will take care of the rest. */
8676 }
8678 /* Print out which MIPS ABI is in use. */
8680 static void
8685 {
8687 fprintf_filtered
8689 "The MIPS ABI is unknown because the current architecture "
8691 else
8692 {
8698 fprintf_filtered
8701 actual_abi_str);
8703 fprintf_filtered
8706 actual_abi_str);
8707 else
8708 {
8709 /* Probably shouldn't happen... */
8714 }
8715 }
8716 }
8718 /* Print out which MIPS compressed ISA encoding is used. */
8720 static void
8723 {
8725 value);
8726 }
8728 static void
8730 {
8733 {
8736 /* Determine the ISA. */
8738 {
8754 }
8755 /* Determine the size of a pointer. */
8762 ef_mips_32bitmode);
8765 ef_mips_arch);
8770 "mips_dump_tdep: "
8774 }
8777 MIPS_DEFAULT_FPU_TYPE,
8791 }
8795 void
8797 {
8810 /* Create feature sets with the appropriate properties. The values
8811 are not important. */
8818 /* Add root prefix command for all "set mips"/"show mips" commands. */
8827 /* Allow the user to override the ABI. */
8840 mips_abi_update,
8841 show_mips_abi,
8844 /* Allow the user to set the ISA to assume for compressed code if ELF
8845 file flags don't tell or there is no program file selected. This
8846 setting is updated whenever unambiguous ELF file flags are interpreted,
8847 and carried over to subsequent sessions. */
8857 mips_abi_update,
8858 show_mips_compression,
8861 /* Let the user turn off floating point and set the fence post for
8862 heuristic_proc_start. */
8888 /* We really would like to have both "0" and "unlimited" work, but
8889 command.c doesn't deal with that. So make it a var_zinteger
8890 because the user can always use "999999" or some such for unlimited. */
8898 reinit_frame_cache_sfunc,
8900 the start of a function is %s. */
8903 /* Allow the user to control whether the upper bits of 64-bit
8904 addresses should be zeroed. */
8914 /* Allow the user to control the size of 32 bit registers within the
8915 raw remote packet. */
8925 set_mips64_transfers_32bit_regs,
8927 MIPS target that transfers 32-bit
8928 quantities is %s. */
8931 /* Debug this files internals. */
8937 NULL,
8939 currently %s. */
8941 }