gdb/dcache.c

   1 /* Caching code for GDB, the GNU debugger.
   2
   3    Copyright (C) 1992, 1993, 1995, 1996, 1998, 1999, 2000, 2001, 2003, 2007,
   4    2008, 2009 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "dcache.h"
  23 #include "gdbcmd.h"
  24 #include "gdb_string.h"
  25 #include "gdbcore.h"
  26 #include "target.h"
  27
  28 /* The data cache could lead to incorrect results because it doesn't
  29    know about volatile variables, thus making it impossible to debug
  30    functions which use memory mapped I/O devices.  Set the nocache
  31    memory region attribute in those cases.
  32
  33    In general the dcache speeds up performance, some speed improvement
  34    comes from the actual caching mechanism, but the major gain is in
  35    the reduction of the remote protocol overhead; instead of reading
  36    or writing a large area of memory in 4 byte requests, the cache
  37    bundles up the requests into 32 byte (actually LINE_SIZE) chunks.
  38    Reducing the overhead to an eighth of what it was.  This is very
  39    obvious when displaying a large amount of data,
  40
  41    eg, x/200x 0
  42
  43    caching     |   no    yes
  44    ----------------------------
  45    first time  |   4 sec  2 sec improvement due to chunking
  46    second time |   4 sec  0 sec improvement due to caching
  47
  48    The cache structure is unusual, we keep a number of cache blocks
  49    (DCACHE_SIZE) and each one caches a LINE_SIZEed area of memory.
  50    Within each line we remember the address of the line (always a
  51    multiple of the LINE_SIZE) and a vector of bytes over the range.
  52    There's another vector which contains the state of the bytes.
  53
  54    ENTRY_INVALID means that the byte is just plain wrong, and has no
  55    correspondence with anything else (as it would when the cache is
  56    turned on, but nothing has been done to it).
  57
  58    ENTRY_DIRTY means that the byte has some data in it which should be
  59    written out to the remote target one day, but contains correct
  60    data.
  61
  62    ENTRY_VALID means that the data is the same in the cache as it is in
  63    remote memory.
  64
  65
  66    The ENTRY_DIRTY state is necessary because GDB likes to write large
  67    lumps of memory in small bits.  If the caching mechanism didn't
  68    maintain the DIRTY information, then something like a two byte
  69    write would mean that the entire cache line would have to be read,
  70    the two bytes modified and then written out again.  The alternative
  71    would be to not read in the cache line in the first place, and just
  72    write the two bytes directly into target memory.  The trouble with
  73    that is that it really nails performance, because of the remote
  74    protocol overhead.  This way, all those little writes are bundled
  75    up into an entire cache line write in one go, without having to
  76    read the cache line in the first place.
  77  */
  78
  79 /* NOTE: Interaction of dcache and memory region attributes
  80
  81    As there is no requirement that memory region attributes be aligned
  82    to or be a multiple of the dcache page size, dcache_read_line() and
  83    dcache_write_line() must break up the page by memory region.  If a
  84    chunk does not have the cache attribute set, an invalid memory type
  85    is set, etc., then the chunk is skipped.  Those chunks are handled
  86    in target_xfer_memory() (or target_xfer_memory_partial()).
  87
  88    This doesn't occur very often.  The most common occurance is when
  89    the last bit of the .text segment and the first bit of the .data
  90    segment fall within the same dcache page with a ro/cacheable memory
  91    region defined for the .text segment and a rw/non-cacheable memory
  92    region defined for the .data segment. */
  93
  94 /* This value regulates the number of cache blocks stored.
  95    Smaller values reduce the time spent searching for a cache
  96    line, and reduce memory requirements, but increase the risk
  97    of a line not being in memory */
  98
  99 #define DCACHE_SIZE 64
 100
 101 /* This value regulates the size of a cache line.  Smaller values
 102    reduce the time taken to read a single byte, but reduce overall
 103    throughput.  */
 104
 105 #define LINE_SIZE_POWER (5)
 106 #define LINE_SIZE (1 << LINE_SIZE_POWER)
 107
 108 /* Each cache block holds LINE_SIZE bytes of data
 109    starting at a multiple-of-LINE_SIZE address.  */
 110
 111 #define LINE_SIZE_MASK  ((LINE_SIZE - 1))
 112 #define XFORM(x)        ((x) & LINE_SIZE_MASK)
 113 #define MASK(x)         ((x) & ~LINE_SIZE_MASK)
 114
 115
 116 #define ENTRY_INVALID 0 /* data at this byte is wrong */
 117 #define ENTRY_DIRTY   1 /* data at this byte needs to be written back */
 118 #define ENTRY_VALID   2 /* data at this byte is same as in memory */
 119
 120 /* For cache state display by "info dcache".
 121    The letters I,D,V map to
 122    I = ENTRY_INVALID
 123    D = ENTRY_DIRTY
 124    V = ENTRY_VALID  */
 125 static const char state_chars[3] = { 'I', 'D', 'V' };
 126
 127 struct dcache_block
 128   {
 129     struct dcache_block *p;     /* next in list */
 130     CORE_ADDR addr;             /* Address for which data is recorded.  */
 131     gdb_byte data[LINE_SIZE];   /* bytes at given address */
 132     unsigned char state[LINE_SIZE];     /* what state the data is in */
 133
 134     /* whether anything in state is dirty - used to speed up the
 135        dirty scan. */
 136     int anydirty;
 137
 138     int refs;
 139   };
 140
 141
 142 /* FIXME: dcache_struct used to have a cache_has_stuff field that was
 143    used to record whether the cache had been accessed.  This was used
 144    to invalidate the cache whenever caching was (re-)enabled (if the
 145    cache was disabled and later re-enabled, it could contain stale
 146    data).  This was not needed because the cache is write through and
 147    the code that enables, disables, and deletes memory region all
 148    invalidate the cache.
 149
 150    This is overkill, since it also invalidates cache lines from
 151    unrelated regions.  One way this could be addressed by adding a
 152    new function that takes an address and a length and invalidates
 153    only those cache lines that match. */
 154
 155 struct dcache_struct
 156   {
 157     /* free list */
 158     struct dcache_block *free_head;
 159     struct dcache_block *free_tail;
 160
 161     /* in use list */
 162     struct dcache_block *valid_head;
 163     struct dcache_block *valid_tail;
 164
 165     /* The cache itself. */
 166     struct dcache_block *the_cache;
 167   };
 168
 169 static struct dcache_block *dcache_hit (DCACHE *dcache, CORE_ADDR addr);
 170
 171 static int dcache_write_line (DCACHE *dcache, struct dcache_block *db);
 172
 173 static int dcache_read_line (DCACHE *dcache, struct dcache_block *db);
 174
 175 static struct dcache_block *dcache_alloc (DCACHE *dcache, CORE_ADDR addr);
 176
 177 static int dcache_writeback (DCACHE *dcache);
 178
 179 static void dcache_info (char *exp, int tty);
 180
 181 void _initialize_dcache (void);
 182
 183 static int dcache_enabled_p = 0;
 184
 185 static void
 186 show_dcache_enabled_p (struct ui_file *file, int from_tty,
 187                        struct cmd_list_element *c, const char *value)
 188 {
 189   fprintf_filtered (file, _("Cache use for remote targets is %s.\n"), value);
 190 }
 191
 192
 193 DCACHE *last_cache;             /* Used by info dcache */
 194
 195
 196 /* Free all the data cache blocks, thus discarding all cached data.  */
 197
 198 void
 199 dcache_invalidate (DCACHE *dcache)
 200 {
 201   int i;
 202   dcache->valid_head = 0;
 203   dcache->valid_tail = 0;
 204
 205   dcache->free_head = 0;
 206   dcache->free_tail = 0;
 207
 208   for (i = 0; i < DCACHE_SIZE; i++)
 209     {
 210       struct dcache_block *db = dcache->the_cache + i;
 211
 212       if (!dcache->free_head)
 213         dcache->free_head = db;
 214       else
 215         dcache->free_tail->p = db;
 216       dcache->free_tail = db;
 217       db->p = 0;
 218     }
 219
 220   return;
 221 }
 222
 223 /* If addr is present in the dcache, return the address of the block
 224    containing it. */
 225
 226 static struct dcache_block *
 227 dcache_hit (DCACHE *dcache, CORE_ADDR addr)
 228 {
 229   struct dcache_block *db;
 230
 231   /* Search all cache blocks for one that is at this address.  */
 232   db = dcache->valid_head;
 233
 234   while (db)
 235     {
 236       if (MASK (addr) == db->addr)
 237         {
 238           db->refs++;
 239           return db;
 240         }
 241       db = db->p;
 242     }
 243
 244   return NULL;
 245 }
 246
 247 /* Make sure that anything in this line which needs to
 248    be written is. */
 249
 250 static int
 251 dcache_write_line (DCACHE *dcache, struct dcache_block *db)
 252 {
 253   CORE_ADDR memaddr;
 254   gdb_byte *myaddr;
 255   int len;
 256   int res;
 257   int reg_len;
 258   struct mem_region *region;
 259
 260   if (!db->anydirty)
 261     return 1;
 262
 263   len = LINE_SIZE;
 264   memaddr = db->addr;
 265   myaddr  = db->data;
 266
 267   while (len > 0)
 268     {
 269       int s;
 270       int e;
 271       int dirty_len;
 272
 273       region = lookup_mem_region(memaddr);
 274       if (memaddr + len < region->hi)
 275         reg_len = len;
 276       else
 277         reg_len = region->hi - memaddr;
 278
 279       if (!region->attrib.cache || region->attrib.mode == MEM_RO)
 280         {
 281           memaddr += reg_len;
 282           myaddr  += reg_len;
 283           len     -= reg_len;
 284           continue;
 285         }
 286
 287       while (reg_len > 0)
 288         {
 289           s = XFORM(memaddr);
 290           while (reg_len > 0) {
 291             if (db->state[s] == ENTRY_DIRTY)
 292               break;
 293             s++;
 294             reg_len--;
 295
 296             memaddr++;
 297             myaddr++;
 298             len--;
 299           }
 300
 301           e = s;
 302           while (reg_len > 0) {
 303             if (db->state[e] != ENTRY_DIRTY)
 304               break;
 305             e++;
 306             reg_len--;
 307           }
 308
 309           dirty_len = e - s;
 310           res = target_write (&current_target, TARGET_OBJECT_RAW_MEMORY,
 311                               NULL, myaddr, memaddr, dirty_len);
 312           if (res < dirty_len)
 313             return 0;
 314
 315           memset (&db->state[XFORM(memaddr)], ENTRY_VALID, res);
 316           memaddr += res;
 317           myaddr += res;
 318           len -= res;
 319         }
 320     }
 321
 322   db->anydirty = 0;
 323   return 1;
 324 }
 325
 326 /* Read cache line */
 327 static int
 328 dcache_read_line (DCACHE *dcache, struct dcache_block *db)
 329 {
 330   CORE_ADDR memaddr;
 331   gdb_byte *myaddr;
 332   int len;
 333   int res;
 334   int reg_len;
 335   struct mem_region *region;
 336
 337   /* If there are any dirty bytes in the line, it must be written
 338      before a new line can be read */
 339   if (db->anydirty)
 340     {
 341       if (!dcache_write_line (dcache, db))
 342         return 0;
 343     }
 344
 345   len = LINE_SIZE;
 346   memaddr = db->addr;
 347   myaddr  = db->data;
 348
 349   while (len > 0)
 350     {
 351       region = lookup_mem_region(memaddr);
 352       if (memaddr + len < region->hi)
 353         reg_len = len;
 354       else
 355         reg_len = region->hi - memaddr;
 356
 357       if (!region->attrib.cache || region->attrib.mode == MEM_WO)
 358         {
 359           memaddr += reg_len;
 360           myaddr  += reg_len;
 361           len     -= reg_len;
 362           continue;
 363         }
 364
 365       res = target_read (&current_target, TARGET_OBJECT_RAW_MEMORY,
 366                          NULL, myaddr, memaddr, reg_len);
 367       if (res < reg_len)
 368         return 0;
 369
 370       memaddr += res;
 371       myaddr += res;
 372       len -= res;
 373     }
 374
 375   memset (db->state, ENTRY_VALID, sizeof (db->data));
 376   db->anydirty = 0;
 377
 378   return 1;
 379 }
 380
 381 /* Get a free cache block, put or keep it on the valid list,
 382    and return its address.  */
 383
 384 static struct dcache_block *
 385 dcache_alloc (DCACHE *dcache, CORE_ADDR addr)
 386 {
 387   struct dcache_block *db;
 388
 389   /* Take something from the free list */
 390   db = dcache->free_head;
 391   if (db)
 392     {
 393       dcache->free_head = db->p;
 394     }
 395   else
 396     {
 397       /* Nothing left on free list, so grab one from the valid list */
 398       db = dcache->valid_head;
 399
 400       if (!dcache_write_line (dcache, db))
 401         return NULL;
 402
 403       dcache->valid_head = db->p;
 404     }
 405
 406   db->addr = MASK(addr);
 407   db->refs = 0;
 408   db->anydirty = 0;
 409   memset (db->state, ENTRY_INVALID, sizeof (db->data));
 410
 411   /* append this line to end of valid list */
 412   if (!dcache->valid_head)
 413     dcache->valid_head = db;
 414   else
 415     dcache->valid_tail->p = db;
 416   dcache->valid_tail = db;
 417   db->p = 0;
 418
 419   return db;
 420 }
 421
 422 /* Writeback any dirty lines. */
 423 static int
 424 dcache_writeback (DCACHE *dcache)
 425 {
 426   struct dcache_block *db;
 427
 428   db = dcache->valid_head;
 429
 430   while (db)
 431     {
 432       if (!dcache_write_line (dcache, db))
 433         return 0;
 434       db = db->p;
 435     }
 436   return 1;
 437 }
 438
 439
 440 /* Using the data cache DCACHE return the contents of the byte at
 441    address ADDR in the remote machine.
 442
 443    Returns 0 on error. */
 444
 445 static int
 446 dcache_peek_byte (DCACHE *dcache, CORE_ADDR addr, gdb_byte *ptr)
 447 {
 448   struct dcache_block *db = dcache_hit (dcache, addr);
 449
 450   if (!db)
 451     {
 452       db = dcache_alloc (dcache, addr);
 453       if (!db)
 454         return 0;
 455     }
 456
 457   if (db->state[XFORM (addr)] == ENTRY_INVALID)
 458     {
 459       if (!dcache_read_line(dcache, db))
 460          return 0;
 461     }
 462
 463   *ptr = db->data[XFORM (addr)];
 464   return 1;
 465 }
 466
 467
 468 /* Write the byte at PTR into ADDR in the data cache.
 469    Return zero on write error.
 470  */
 471
 472 static int
 473 dcache_poke_byte (DCACHE *dcache, CORE_ADDR addr, gdb_byte *ptr)
 474 {
 475   struct dcache_block *db = dcache_hit (dcache, addr);
 476
 477   if (!db)
 478     {
 479       db = dcache_alloc (dcache, addr);
 480       if (!db)
 481         return 0;
 482     }
 483
 484   db->data[XFORM (addr)] = *ptr;
 485   db->state[XFORM (addr)] = ENTRY_DIRTY;
 486   db->anydirty = 1;
 487   return 1;
 488 }
 489
 490 /* Initialize the data cache.  */
 491 DCACHE *
 492 dcache_init (void)
 493 {
 494   int csize = sizeof (struct dcache_block) * DCACHE_SIZE;
 495   DCACHE *dcache;
 496
 497   dcache = (DCACHE *) xmalloc (sizeof (*dcache));
 498
 499   dcache->the_cache = (struct dcache_block *) xmalloc (csize);
 500   memset (dcache->the_cache, 0, csize);
 501
 502   dcache_invalidate (dcache);
 503
 504   last_cache = dcache;
 505   return dcache;
 506 }
 507
 508 /* Free a data cache */
 509 void
 510 dcache_free (DCACHE *dcache)
 511 {
 512   if (last_cache == dcache)
 513     last_cache = NULL;
 514
 515   xfree (dcache->the_cache);
 516   xfree (dcache);
 517 }
 518
 519 /* Read or write LEN bytes from inferior memory at MEMADDR, transferring
 520    to or from debugger address MYADDR.  Write to inferior if SHOULD_WRITE is
 521    nonzero.
 522
 523    Returns length of data written or read; 0 for error.
 524
 525    This routine is indended to be called by remote_xfer_ functions. */
 526
 527 int
 528 dcache_xfer_memory (DCACHE *dcache, CORE_ADDR memaddr, gdb_byte *myaddr,
 529                     int len, int should_write)
 530 {
 531   int i;
 532   int (*xfunc) (DCACHE *dcache, CORE_ADDR addr, gdb_byte *ptr);
 533   xfunc = should_write ? dcache_poke_byte : dcache_peek_byte;
 534
 535   for (i = 0; i < len; i++)
 536     {
 537       if (!xfunc (dcache, memaddr + i, myaddr + i))
 538         return 0;
 539     }
 540
 541   /* FIXME: There may be some benefit from moving the cache writeback
 542      to a higher layer, as it could occur after a sequence of smaller
 543      writes have been completed (as when a stack frame is constructed
 544      for an inferior function call).  Note that only moving it up one
 545      level to target_xfer_memory() (also target_xfer_memory_partial())
 546      is not sufficent, since we want to coalesce memory transfers that
 547      are "logically" connected but not actually a single call to one
 548      of the memory transfer functions. */
 549
 550   if (should_write)
 551     dcache_writeback (dcache);
 552
 553   return len;
 554 }
 555
 556 static void
 557 dcache_info (char *exp, int tty)
 558 {
 559   struct dcache_block *p;
 560
 561   printf_filtered (_("Dcache line width %d, depth %d\n"),
 562                    LINE_SIZE, DCACHE_SIZE);
 563
 564   if (last_cache)
 565     {
 566       printf_filtered (_("Cache state:\n"));
 567
 568       for (p = last_cache->valid_head; p; p = p->p)
 569         {
 570           int j;
 571           printf_filtered (_("Line at %s, referenced %d times\n"),
 572                            paddr (p->addr), p->refs);
 573
 574           for (j = 0; j < LINE_SIZE; j++)
 575             printf_filtered ("%02x", p->data[j] & 0xFF);
 576           printf_filtered (("\n"));
 577
 578           for (j = 0; j < LINE_SIZE; j++)
 579             printf_filtered (" %c", state_chars[p->state[j]]);
 580           printf_filtered ("\n");
 581         }
 582     }
 583 }
 584
 585 void
 586 _initialize_dcache (void)
 587 {
 588   add_setshow_boolean_cmd ("remotecache", class_support,
 589                            &dcache_enabled_p, _("\
 590 Set cache use for remote targets."), _("\
 591 Show cache use for remote targets."), _("\
 592 When on, use data caching for remote targets.  For many remote targets\n\
 593 this option can offer better throughput for reading target memory.\n\
 594 Unfortunately, gdb does not currently know anything about volatile\n\
 595 registers and thus data caching will produce incorrect results with\n\
 596 volatile registers are in use.  By default, this option is off."),
 597                            NULL,
 598                            show_dcache_enabled_p,
 599                            &setlist, &showlist);
 600
 601   add_info ("dcache", dcache_info,
 602             _("\
 603 Print information on the dcache performance.\n\
 604 The state of each cached byte is represented by a letter:\n\
 605   I = invalid\n\
 606   D = dirty\n\
 607   V = valid"));
 608 }