sim/cris/semcrisv10f-switch.c

   1 /* Simulator instruction semantics for crisv10f.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2007 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifdef DEFINE_LABELS
  26
  27   /* The labels have the case they have because the enum of insn types
  28      is all uppercase and in the non-stdc case the insn symbol is built
  29      into the enum name.  */
  30
  31   static struct {
  32     int index;
  33     void *label;
  34   } labels[] = {
  35     { CRISV10F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
  36     { CRISV10F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
  37     { CRISV10F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
  38     { CRISV10F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
  39     { CRISV10F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
  40     { CRISV10F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
  41     { CRISV10F_INSN_NOP, && case_sem_INSN_NOP },
  42     { CRISV10F_INSN_MOVE_B_R, && case_sem_INSN_MOVE_B_R },
  43     { CRISV10F_INSN_MOVE_W_R, && case_sem_INSN_MOVE_W_R },
  44     { CRISV10F_INSN_MOVE_D_R, && case_sem_INSN_MOVE_D_R },
  45     { CRISV10F_INSN_MOVEPCR, && case_sem_INSN_MOVEPCR },
  46     { CRISV10F_INSN_MOVEQ, && case_sem_INSN_MOVEQ },
  47     { CRISV10F_INSN_MOVS_B_R, && case_sem_INSN_MOVS_B_R },
  48     { CRISV10F_INSN_MOVS_W_R, && case_sem_INSN_MOVS_W_R },
  49     { CRISV10F_INSN_MOVU_B_R, && case_sem_INSN_MOVU_B_R },
  50     { CRISV10F_INSN_MOVU_W_R, && case_sem_INSN_MOVU_W_R },
  51     { CRISV10F_INSN_MOVECBR, && case_sem_INSN_MOVECBR },
  52     { CRISV10F_INSN_MOVECWR, && case_sem_INSN_MOVECWR },
  53     { CRISV10F_INSN_MOVECDR, && case_sem_INSN_MOVECDR },
  54     { CRISV10F_INSN_MOVSCBR, && case_sem_INSN_MOVSCBR },
  55     { CRISV10F_INSN_MOVSCWR, && case_sem_INSN_MOVSCWR },
  56     { CRISV10F_INSN_MOVUCBR, && case_sem_INSN_MOVUCBR },
  57     { CRISV10F_INSN_MOVUCWR, && case_sem_INSN_MOVUCWR },
  58     { CRISV10F_INSN_ADDQ, && case_sem_INSN_ADDQ },
  59     { CRISV10F_INSN_SUBQ, && case_sem_INSN_SUBQ },
  60     { CRISV10F_INSN_CMP_R_B_R, && case_sem_INSN_CMP_R_B_R },
  61     { CRISV10F_INSN_CMP_R_W_R, && case_sem_INSN_CMP_R_W_R },
  62     { CRISV10F_INSN_CMP_R_D_R, && case_sem_INSN_CMP_R_D_R },
  63     { CRISV10F_INSN_CMP_M_B_M, && case_sem_INSN_CMP_M_B_M },
  64     { CRISV10F_INSN_CMP_M_W_M, && case_sem_INSN_CMP_M_W_M },
  65     { CRISV10F_INSN_CMP_M_D_M, && case_sem_INSN_CMP_M_D_M },
  66     { CRISV10F_INSN_CMPCBR, && case_sem_INSN_CMPCBR },
  67     { CRISV10F_INSN_CMPCWR, && case_sem_INSN_CMPCWR },
  68     { CRISV10F_INSN_CMPCDR, && case_sem_INSN_CMPCDR },
  69     { CRISV10F_INSN_CMPQ, && case_sem_INSN_CMPQ },
  70     { CRISV10F_INSN_CMPS_M_B_M, && case_sem_INSN_CMPS_M_B_M },
  71     { CRISV10F_INSN_CMPS_M_W_M, && case_sem_INSN_CMPS_M_W_M },
  72     { CRISV10F_INSN_CMPSCBR, && case_sem_INSN_CMPSCBR },
  73     { CRISV10F_INSN_CMPSCWR, && case_sem_INSN_CMPSCWR },
  74     { CRISV10F_INSN_CMPU_M_B_M, && case_sem_INSN_CMPU_M_B_M },
  75     { CRISV10F_INSN_CMPU_M_W_M, && case_sem_INSN_CMPU_M_W_M },
  76     { CRISV10F_INSN_CMPUCBR, && case_sem_INSN_CMPUCBR },
  77     { CRISV10F_INSN_CMPUCWR, && case_sem_INSN_CMPUCWR },
  78     { CRISV10F_INSN_MOVE_M_B_M, && case_sem_INSN_MOVE_M_B_M },
  79     { CRISV10F_INSN_MOVE_M_W_M, && case_sem_INSN_MOVE_M_W_M },
  80     { CRISV10F_INSN_MOVE_M_D_M, && case_sem_INSN_MOVE_M_D_M },
  81     { CRISV10F_INSN_MOVS_M_B_M, && case_sem_INSN_MOVS_M_B_M },
  82     { CRISV10F_INSN_MOVS_M_W_M, && case_sem_INSN_MOVS_M_W_M },
  83     { CRISV10F_INSN_MOVU_M_B_M, && case_sem_INSN_MOVU_M_B_M },
  84     { CRISV10F_INSN_MOVU_M_W_M, && case_sem_INSN_MOVU_M_W_M },
  85     { CRISV10F_INSN_MOVE_R_SPRV10, && case_sem_INSN_MOVE_R_SPRV10 },
  86     { CRISV10F_INSN_MOVE_SPR_RV10, && case_sem_INSN_MOVE_SPR_RV10 },
  87     { CRISV10F_INSN_RET_TYPE, && case_sem_INSN_RET_TYPE },
  88     { CRISV10F_INSN_MOVE_M_SPRV10, && case_sem_INSN_MOVE_M_SPRV10 },
  89     { CRISV10F_INSN_MOVE_C_SPRV10_P5, && case_sem_INSN_MOVE_C_SPRV10_P5 },
  90     { CRISV10F_INSN_MOVE_C_SPRV10_P9, && case_sem_INSN_MOVE_C_SPRV10_P9 },
  91     { CRISV10F_INSN_MOVE_C_SPRV10_P10, && case_sem_INSN_MOVE_C_SPRV10_P10 },
  92     { CRISV10F_INSN_MOVE_C_SPRV10_P11, && case_sem_INSN_MOVE_C_SPRV10_P11 },
  93     { CRISV10F_INSN_MOVE_C_SPRV10_P12, && case_sem_INSN_MOVE_C_SPRV10_P12 },
  94     { CRISV10F_INSN_MOVE_C_SPRV10_P13, && case_sem_INSN_MOVE_C_SPRV10_P13 },
  95     { CRISV10F_INSN_MOVE_C_SPRV10_P7, && case_sem_INSN_MOVE_C_SPRV10_P7 },
  96     { CRISV10F_INSN_MOVE_C_SPRV10_P14, && case_sem_INSN_MOVE_C_SPRV10_P14 },
  97     { CRISV10F_INSN_MOVE_C_SPRV10_P15, && case_sem_INSN_MOVE_C_SPRV10_P15 },
  98     { CRISV10F_INSN_MOVE_SPR_MV10, && case_sem_INSN_MOVE_SPR_MV10 },
  99     { CRISV10F_INSN_SBFS, && case_sem_INSN_SBFS },
 100     { CRISV10F_INSN_MOVEM_R_M, && case_sem_INSN_MOVEM_R_M },
 101     { CRISV10F_INSN_MOVEM_M_R, && case_sem_INSN_MOVEM_M_R },
 102     { CRISV10F_INSN_MOVEM_M_PC, && case_sem_INSN_MOVEM_M_PC },
 103     { CRISV10F_INSN_ADD_B_R, && case_sem_INSN_ADD_B_R },
 104     { CRISV10F_INSN_ADD_W_R, && case_sem_INSN_ADD_W_R },
 105     { CRISV10F_INSN_ADD_D_R, && case_sem_INSN_ADD_D_R },
 106     { CRISV10F_INSN_ADD_M_B_M, && case_sem_INSN_ADD_M_B_M },
 107     { CRISV10F_INSN_ADD_M_W_M, && case_sem_INSN_ADD_M_W_M },
 108     { CRISV10F_INSN_ADD_M_D_M, && case_sem_INSN_ADD_M_D_M },
 109     { CRISV10F_INSN_ADDCBR, && case_sem_INSN_ADDCBR },
 110     { CRISV10F_INSN_ADDCWR, && case_sem_INSN_ADDCWR },
 111     { CRISV10F_INSN_ADDCDR, && case_sem_INSN_ADDCDR },
 112     { CRISV10F_INSN_ADDCPC, && case_sem_INSN_ADDCPC },
 113     { CRISV10F_INSN_ADDS_B_R, && case_sem_INSN_ADDS_B_R },
 114     { CRISV10F_INSN_ADDS_W_R, && case_sem_INSN_ADDS_W_R },
 115     { CRISV10F_INSN_ADDS_M_B_M, && case_sem_INSN_ADDS_M_B_M },
 116     { CRISV10F_INSN_ADDS_M_W_M, && case_sem_INSN_ADDS_M_W_M },
 117     { CRISV10F_INSN_ADDSCBR, && case_sem_INSN_ADDSCBR },
 118     { CRISV10F_INSN_ADDSCWR, && case_sem_INSN_ADDSCWR },
 119     { CRISV10F_INSN_ADDSPCPC, && case_sem_INSN_ADDSPCPC },
 120     { CRISV10F_INSN_ADDU_B_R, && case_sem_INSN_ADDU_B_R },
 121     { CRISV10F_INSN_ADDU_W_R, && case_sem_INSN_ADDU_W_R },
 122     { CRISV10F_INSN_ADDU_M_B_M, && case_sem_INSN_ADDU_M_B_M },
 123     { CRISV10F_INSN_ADDU_M_W_M, && case_sem_INSN_ADDU_M_W_M },
 124     { CRISV10F_INSN_ADDUCBR, && case_sem_INSN_ADDUCBR },
 125     { CRISV10F_INSN_ADDUCWR, && case_sem_INSN_ADDUCWR },
 126     { CRISV10F_INSN_SUB_B_R, && case_sem_INSN_SUB_B_R },
 127     { CRISV10F_INSN_SUB_W_R, && case_sem_INSN_SUB_W_R },
 128     { CRISV10F_INSN_SUB_D_R, && case_sem_INSN_SUB_D_R },
 129     { CRISV10F_INSN_SUB_M_B_M, && case_sem_INSN_SUB_M_B_M },
 130     { CRISV10F_INSN_SUB_M_W_M, && case_sem_INSN_SUB_M_W_M },
 131     { CRISV10F_INSN_SUB_M_D_M, && case_sem_INSN_SUB_M_D_M },
 132     { CRISV10F_INSN_SUBCBR, && case_sem_INSN_SUBCBR },
 133     { CRISV10F_INSN_SUBCWR, && case_sem_INSN_SUBCWR },
 134     { CRISV10F_INSN_SUBCDR, && case_sem_INSN_SUBCDR },
 135     { CRISV10F_INSN_SUBS_B_R, && case_sem_INSN_SUBS_B_R },
 136     { CRISV10F_INSN_SUBS_W_R, && case_sem_INSN_SUBS_W_R },
 137     { CRISV10F_INSN_SUBS_M_B_M, && case_sem_INSN_SUBS_M_B_M },
 138     { CRISV10F_INSN_SUBS_M_W_M, && case_sem_INSN_SUBS_M_W_M },
 139     { CRISV10F_INSN_SUBSCBR, && case_sem_INSN_SUBSCBR },
 140     { CRISV10F_INSN_SUBSCWR, && case_sem_INSN_SUBSCWR },
 141     { CRISV10F_INSN_SUBU_B_R, && case_sem_INSN_SUBU_B_R },
 142     { CRISV10F_INSN_SUBU_W_R, && case_sem_INSN_SUBU_W_R },
 143     { CRISV10F_INSN_SUBU_M_B_M, && case_sem_INSN_SUBU_M_B_M },
 144     { CRISV10F_INSN_SUBU_M_W_M, && case_sem_INSN_SUBU_M_W_M },
 145     { CRISV10F_INSN_SUBUCBR, && case_sem_INSN_SUBUCBR },
 146     { CRISV10F_INSN_SUBUCWR, && case_sem_INSN_SUBUCWR },
 147     { CRISV10F_INSN_ADDI_B_R, && case_sem_INSN_ADDI_B_R },
 148     { CRISV10F_INSN_ADDI_W_R, && case_sem_INSN_ADDI_W_R },
 149     { CRISV10F_INSN_ADDI_D_R, && case_sem_INSN_ADDI_D_R },
 150     { CRISV10F_INSN_NEG_B_R, && case_sem_INSN_NEG_B_R },
 151     { CRISV10F_INSN_NEG_W_R, && case_sem_INSN_NEG_W_R },
 152     { CRISV10F_INSN_NEG_D_R, && case_sem_INSN_NEG_D_R },
 153     { CRISV10F_INSN_TEST_M_B_M, && case_sem_INSN_TEST_M_B_M },
 154     { CRISV10F_INSN_TEST_M_W_M, && case_sem_INSN_TEST_M_W_M },
 155     { CRISV10F_INSN_TEST_M_D_M, && case_sem_INSN_TEST_M_D_M },
 156     { CRISV10F_INSN_MOVE_R_M_B_M, && case_sem_INSN_MOVE_R_M_B_M },
 157     { CRISV10F_INSN_MOVE_R_M_W_M, && case_sem_INSN_MOVE_R_M_W_M },
 158     { CRISV10F_INSN_MOVE_R_M_D_M, && case_sem_INSN_MOVE_R_M_D_M },
 159     { CRISV10F_INSN_MULS_B, && case_sem_INSN_MULS_B },
 160     { CRISV10F_INSN_MULS_W, && case_sem_INSN_MULS_W },
 161     { CRISV10F_INSN_MULS_D, && case_sem_INSN_MULS_D },
 162     { CRISV10F_INSN_MULU_B, && case_sem_INSN_MULU_B },
 163     { CRISV10F_INSN_MULU_W, && case_sem_INSN_MULU_W },
 164     { CRISV10F_INSN_MULU_D, && case_sem_INSN_MULU_D },
 165     { CRISV10F_INSN_MSTEP, && case_sem_INSN_MSTEP },
 166     { CRISV10F_INSN_DSTEP, && case_sem_INSN_DSTEP },
 167     { CRISV10F_INSN_ABS, && case_sem_INSN_ABS },
 168     { CRISV10F_INSN_AND_B_R, && case_sem_INSN_AND_B_R },
 169     { CRISV10F_INSN_AND_W_R, && case_sem_INSN_AND_W_R },
 170     { CRISV10F_INSN_AND_D_R, && case_sem_INSN_AND_D_R },
 171     { CRISV10F_INSN_AND_M_B_M, && case_sem_INSN_AND_M_B_M },
 172     { CRISV10F_INSN_AND_M_W_M, && case_sem_INSN_AND_M_W_M },
 173     { CRISV10F_INSN_AND_M_D_M, && case_sem_INSN_AND_M_D_M },
 174     { CRISV10F_INSN_ANDCBR, && case_sem_INSN_ANDCBR },
 175     { CRISV10F_INSN_ANDCWR, && case_sem_INSN_ANDCWR },
 176     { CRISV10F_INSN_ANDCDR, && case_sem_INSN_ANDCDR },
 177     { CRISV10F_INSN_ANDQ, && case_sem_INSN_ANDQ },
 178     { CRISV10F_INSN_ORR_B_R, && case_sem_INSN_ORR_B_R },
 179     { CRISV10F_INSN_ORR_W_R, && case_sem_INSN_ORR_W_R },
 180     { CRISV10F_INSN_ORR_D_R, && case_sem_INSN_ORR_D_R },
 181     { CRISV10F_INSN_OR_M_B_M, && case_sem_INSN_OR_M_B_M },
 182     { CRISV10F_INSN_OR_M_W_M, && case_sem_INSN_OR_M_W_M },
 183     { CRISV10F_INSN_OR_M_D_M, && case_sem_INSN_OR_M_D_M },
 184     { CRISV10F_INSN_ORCBR, && case_sem_INSN_ORCBR },
 185     { CRISV10F_INSN_ORCWR, && case_sem_INSN_ORCWR },
 186     { CRISV10F_INSN_ORCDR, && case_sem_INSN_ORCDR },
 187     { CRISV10F_INSN_ORQ, && case_sem_INSN_ORQ },
 188     { CRISV10F_INSN_XOR, && case_sem_INSN_XOR },
 189     { CRISV10F_INSN_SWAP, && case_sem_INSN_SWAP },
 190     { CRISV10F_INSN_ASRR_B_R, && case_sem_INSN_ASRR_B_R },
 191     { CRISV10F_INSN_ASRR_W_R, && case_sem_INSN_ASRR_W_R },
 192     { CRISV10F_INSN_ASRR_D_R, && case_sem_INSN_ASRR_D_R },
 193     { CRISV10F_INSN_ASRQ, && case_sem_INSN_ASRQ },
 194     { CRISV10F_INSN_LSRR_B_R, && case_sem_INSN_LSRR_B_R },
 195     { CRISV10F_INSN_LSRR_W_R, && case_sem_INSN_LSRR_W_R },
 196     { CRISV10F_INSN_LSRR_D_R, && case_sem_INSN_LSRR_D_R },
 197     { CRISV10F_INSN_LSRQ, && case_sem_INSN_LSRQ },
 198     { CRISV10F_INSN_LSLR_B_R, && case_sem_INSN_LSLR_B_R },
 199     { CRISV10F_INSN_LSLR_W_R, && case_sem_INSN_LSLR_W_R },
 200     { CRISV10F_INSN_LSLR_D_R, && case_sem_INSN_LSLR_D_R },
 201     { CRISV10F_INSN_LSLQ, && case_sem_INSN_LSLQ },
 202     { CRISV10F_INSN_BTST, && case_sem_INSN_BTST },
 203     { CRISV10F_INSN_BTSTQ, && case_sem_INSN_BTSTQ },
 204     { CRISV10F_INSN_SETF, && case_sem_INSN_SETF },
 205     { CRISV10F_INSN_CLEARF, && case_sem_INSN_CLEARF },
 206     { CRISV10F_INSN_BCC_B, && case_sem_INSN_BCC_B },
 207     { CRISV10F_INSN_BA_B, && case_sem_INSN_BA_B },
 208     { CRISV10F_INSN_BCC_W, && case_sem_INSN_BCC_W },
 209     { CRISV10F_INSN_BA_W, && case_sem_INSN_BA_W },
 210     { CRISV10F_INSN_JUMP_R, && case_sem_INSN_JUMP_R },
 211     { CRISV10F_INSN_JUMP_M, && case_sem_INSN_JUMP_M },
 212     { CRISV10F_INSN_JUMP_C, && case_sem_INSN_JUMP_C },
 213     { CRISV10F_INSN_BREAK, && case_sem_INSN_BREAK },
 214     { CRISV10F_INSN_BOUND_R_B_R, && case_sem_INSN_BOUND_R_B_R },
 215     { CRISV10F_INSN_BOUND_R_W_R, && case_sem_INSN_BOUND_R_W_R },
 216     { CRISV10F_INSN_BOUND_R_D_R, && case_sem_INSN_BOUND_R_D_R },
 217     { CRISV10F_INSN_BOUND_M_B_M, && case_sem_INSN_BOUND_M_B_M },
 218     { CRISV10F_INSN_BOUND_M_W_M, && case_sem_INSN_BOUND_M_W_M },
 219     { CRISV10F_INSN_BOUND_M_D_M, && case_sem_INSN_BOUND_M_D_M },
 220     { CRISV10F_INSN_BOUND_CB, && case_sem_INSN_BOUND_CB },
 221     { CRISV10F_INSN_BOUND_CW, && case_sem_INSN_BOUND_CW },
 222     { CRISV10F_INSN_BOUND_CD, && case_sem_INSN_BOUND_CD },
 223     { CRISV10F_INSN_SCC, && case_sem_INSN_SCC },
 224     { CRISV10F_INSN_LZ, && case_sem_INSN_LZ },
 225     { CRISV10F_INSN_ADDOQ, && case_sem_INSN_ADDOQ },
 226     { CRISV10F_INSN_BDAPQPC, && case_sem_INSN_BDAPQPC },
 227     { CRISV10F_INSN_BDAP_32_PC, && case_sem_INSN_BDAP_32_PC },
 228     { CRISV10F_INSN_MOVE_M_PCPLUS_P0, && case_sem_INSN_MOVE_M_PCPLUS_P0 },
 229     { CRISV10F_INSN_MOVE_M_SPPLUS_P8, && case_sem_INSN_MOVE_M_SPPLUS_P8 },
 230     { CRISV10F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M },
 231     { CRISV10F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M },
 232     { CRISV10F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M },
 233     { CRISV10F_INSN_ADDO_CB, && case_sem_INSN_ADDO_CB },
 234     { CRISV10F_INSN_ADDO_CW, && case_sem_INSN_ADDO_CW },
 235     { CRISV10F_INSN_ADDO_CD, && case_sem_INSN_ADDO_CD },
 236     { CRISV10F_INSN_DIP_M, && case_sem_INSN_DIP_M },
 237     { CRISV10F_INSN_DIP_C, && case_sem_INSN_DIP_C },
 238     { CRISV10F_INSN_ADDI_ACR_B_R, && case_sem_INSN_ADDI_ACR_B_R },
 239     { CRISV10F_INSN_ADDI_ACR_W_R, && case_sem_INSN_ADDI_ACR_W_R },
 240     { CRISV10F_INSN_ADDI_ACR_D_R, && case_sem_INSN_ADDI_ACR_D_R },
 241     { CRISV10F_INSN_BIAP_PC_B_R, && case_sem_INSN_BIAP_PC_B_R },
 242     { CRISV10F_INSN_BIAP_PC_W_R, && case_sem_INSN_BIAP_PC_W_R },
 243     { CRISV10F_INSN_BIAP_PC_D_R, && case_sem_INSN_BIAP_PC_D_R },
 244     { 0, 0 }
 245   };
 246   int i;
 247
 248   for (i = 0; labels[i].label != 0; ++i)
 249     {
 250 #if FAST_P
 251       CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 252 #else
 253       CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 254 #endif
 255     }
 256
 257 #undef DEFINE_LABELS
 258 #endif /* DEFINE_LABELS */
 259
 260 #ifdef DEFINE_SWITCH
 261
 262 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 263    off frills like tracing and profiling.  */
 264 /* FIXME: A better way would be to have TRACE_RESULT check for something
 265    that can cause it to be optimized out.  Another way would be to emit
 266    special handlers into the instruction "stream".  */
 267
 268 #if FAST_P
 269 #undef TRACE_RESULT
 270 #define TRACE_RESULT(cpu, abuf, name, type, val)
 271 #endif
 272
 273 #undef GET_ATTR
 274 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 275 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 276 #else
 277 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
 278 #endif
 279
 280 {
 281
 282 #if WITH_SCACHE_PBB
 283
 284 /* Branch to next handler without going around main loop.  */
 285 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
 286 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 287
 288 #else /* ! WITH_SCACHE_PBB */
 289
 290 #define NEXT(vpc) BREAK (sem)
 291 #ifdef __GNUC__
 292 #if FAST_P
 293   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
 294 #else
 295   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
 296 #endif
 297 #else
 298   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
 299 #endif
 300
 301 #endif /* ! WITH_SCACHE_PBB */
 302
 303     {
 304
 305   CASE (sem, INSN_X_INVALID) : /* --invalid-- */
 306 {
 307   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 308   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 309 #define FLD(f) abuf->fields.fmt_empty.f
 310   int UNUSED written = 0;
 311   IADDR UNUSED pc = abuf->addr;
 312   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 313
 314   {
 315     /* Update the recorded pc in the cpu state struct.
 316        Only necessary for WITH_SCACHE case, but to avoid the
 317        conditional compilation ....  */
 318     SET_H_PC (pc);
 319     /* Virtual insns have zero size.  Overwrite vpc with address of next insn
 320        using the default-insn-bitsize spec.  When executing insns in parallel
 321        we may want to queue the fault and continue execution.  */
 322     vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 323     vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
 324   }
 325
 326 #undef FLD
 327 }
 328   NEXT (vpc);
 329
 330   CASE (sem, INSN_X_AFTER) : /* --after-- */
 331 {
 332   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 333   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 334 #define FLD(f) abuf->fields.fmt_empty.f
 335   int UNUSED written = 0;
 336   IADDR UNUSED pc = abuf->addr;
 337   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 338
 339   {
 340 #if WITH_SCACHE_PBB_CRISV10F
 341     crisv10f_pbb_after (current_cpu, sem_arg);
 342 #endif
 343   }
 344
 345 #undef FLD
 346 }
 347   NEXT (vpc);
 348
 349   CASE (sem, INSN_X_BEFORE) : /* --before-- */
 350 {
 351   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 352   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 353 #define FLD(f) abuf->fields.fmt_empty.f
 354   int UNUSED written = 0;
 355   IADDR UNUSED pc = abuf->addr;
 356   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 357
 358   {
 359 #if WITH_SCACHE_PBB_CRISV10F
 360     crisv10f_pbb_before (current_cpu, sem_arg);
 361 #endif
 362   }
 363
 364 #undef FLD
 365 }
 366   NEXT (vpc);
 367
 368   CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
 369 {
 370   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 371   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 372 #define FLD(f) abuf->fields.fmt_empty.f
 373   int UNUSED written = 0;
 374   IADDR UNUSED pc = abuf->addr;
 375   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 376
 377   {
 378 #if WITH_SCACHE_PBB_CRISV10F
 379 #ifdef DEFINE_SWITCH
 380     vpc = crisv10f_pbb_cti_chain (current_cpu, sem_arg,
 381                                pbb_br_type, pbb_br_npc);
 382     BREAK (sem);
 383 #else
 384     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
 385     vpc = crisv10f_pbb_cti_chain (current_cpu, sem_arg,
 386                                CPU_PBB_BR_TYPE (current_cpu),
 387                                CPU_PBB_BR_NPC (current_cpu));
 388 #endif
 389 #endif
 390   }
 391
 392 #undef FLD
 393 }
 394   NEXT (vpc);
 395
 396   CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 397 {
 398   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 399   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 400 #define FLD(f) abuf->fields.fmt_empty.f
 401   int UNUSED written = 0;
 402   IADDR UNUSED pc = abuf->addr;
 403   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 404
 405   {
 406 #if WITH_SCACHE_PBB_CRISV10F
 407     vpc = crisv10f_pbb_chain (current_cpu, sem_arg);
 408 #ifdef DEFINE_SWITCH
 409     BREAK (sem);
 410 #endif
 411 #endif
 412   }
 413
 414 #undef FLD
 415 }
 416   NEXT (vpc);
 417
 418   CASE (sem, INSN_X_BEGIN) : /* --begin-- */
 419 {
 420   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 421   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 422 #define FLD(f) abuf->fields.fmt_empty.f
 423   int UNUSED written = 0;
 424   IADDR UNUSED pc = abuf->addr;
 425   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 426
 427   {
 428 #if WITH_SCACHE_PBB_CRISV10F
 429 #if defined DEFINE_SWITCH || defined FAST_P
 430     /* In the switch case FAST_P is a constant, allowing several optimizations
 431        in any called inline functions.  */
 432     vpc = crisv10f_pbb_begin (current_cpu, FAST_P);
 433 #else
 434 #if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
 435     vpc = crisv10f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
 436 #else
 437     vpc = crisv10f_pbb_begin (current_cpu, 0);
 438 #endif
 439 #endif
 440 #endif
 441   }
 442
 443 #undef FLD
 444 }
 445   NEXT (vpc);
 446
 447   CASE (sem, INSN_NOP) : /* nop */
 448 {
 449   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 450   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 451 #define FLD(f) abuf->fields.fmt_empty.f
 452   int UNUSED written = 0;
 453   IADDR UNUSED pc = abuf->addr;
 454   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 455
 456 {
 457   {
 458     BI opval = 0;
 459     CPU (h_xbit) = opval;
 460     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 461   }
 462   {
 463     BI opval = 0;
 464     SET_H_INSN_PREFIXED_P (opval);
 465     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 466   }
 467 }
 468
 469 #undef FLD
 470 }
 471   NEXT (vpc);
 472
 473   CASE (sem, INSN_MOVE_B_R) : /* move.b move.m ${Rs},${Rd} */
 474 {
 475   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 476   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 477 #define FLD(f) abuf->fields.sfmt_add_b_r.f
 478   int UNUSED written = 0;
 479   IADDR UNUSED pc = abuf->addr;
 480   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 481
 482 {
 483   QI tmp_newval;
 484   tmp_newval = GET_H_GR (FLD (f_operand1));
 485 {
 486   SI tmp_oldregval;
 487   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 488   {
 489     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 490     SET_H_GR (FLD (f_operand2), opval);
 491     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 492   }
 493 }
 494 {
 495   {
 496     BI opval = LTQI (tmp_newval, 0);
 497     CPU (h_nbit) = opval;
 498     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 499   }
 500   {
 501     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 502     CPU (h_zbit) = opval;
 503     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 504   }
 505 SET_H_CBIT_MOVE (0);
 506 SET_H_VBIT_MOVE (0);
 507 {
 508   {
 509     BI opval = 0;
 510     CPU (h_xbit) = opval;
 511     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 512   }
 513   {
 514     BI opval = 0;
 515     SET_H_INSN_PREFIXED_P (opval);
 516     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 517   }
 518 }
 519 }
 520 }
 521
 522 #undef FLD
 523 }
 524   NEXT (vpc);
 525
 526   CASE (sem, INSN_MOVE_W_R) : /* move.w move.m ${Rs},${Rd} */
 527 {
 528   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 529   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 530 #define FLD(f) abuf->fields.sfmt_add_b_r.f
 531   int UNUSED written = 0;
 532   IADDR UNUSED pc = abuf->addr;
 533   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 534
 535 {
 536   HI tmp_newval;
 537   tmp_newval = GET_H_GR (FLD (f_operand1));
 538 {
 539   SI tmp_oldregval;
 540   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 541   {
 542     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 543     SET_H_GR (FLD (f_operand2), opval);
 544     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 545   }
 546 }
 547 {
 548   {
 549     BI opval = LTHI (tmp_newval, 0);
 550     CPU (h_nbit) = opval;
 551     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 552   }
 553   {
 554     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 555     CPU (h_zbit) = opval;
 556     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 557   }
 558 SET_H_CBIT_MOVE (0);
 559 SET_H_VBIT_MOVE (0);
 560 {
 561   {
 562     BI opval = 0;
 563     CPU (h_xbit) = opval;
 564     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 565   }
 566   {
 567     BI opval = 0;
 568     SET_H_INSN_PREFIXED_P (opval);
 569     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 570   }
 571 }
 572 }
 573 }
 574
 575 #undef FLD
 576 }
 577   NEXT (vpc);
 578
 579   CASE (sem, INSN_MOVE_D_R) : /* move.d move.m ${Rs},${Rd} */
 580 {
 581   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 582   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 583 #define FLD(f) abuf->fields.sfmt_add_b_r.f
 584   int UNUSED written = 0;
 585   IADDR UNUSED pc = abuf->addr;
 586   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 587
 588 {
 589   SI tmp_newval;
 590   tmp_newval = GET_H_GR (FLD (f_operand1));
 591   {
 592     SI opval = tmp_newval;
 593     SET_H_GR (FLD (f_operand2), opval);
 594     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 595   }
 596 {
 597   {
 598     BI opval = LTSI (tmp_newval, 0);
 599     CPU (h_nbit) = opval;
 600     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 601   }
 602   {
 603     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 604     CPU (h_zbit) = opval;
 605     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 606   }
 607 SET_H_CBIT_MOVE (0);
 608 SET_H_VBIT_MOVE (0);
 609 {
 610   {
 611     BI opval = 0;
 612     CPU (h_xbit) = opval;
 613     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 614   }
 615   {
 616     BI opval = 0;
 617     SET_H_INSN_PREFIXED_P (opval);
 618     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 619   }
 620 }
 621 }
 622 }
 623
 624 #undef FLD
 625 }
 626   NEXT (vpc);
 627
 628   CASE (sem, INSN_MOVEPCR) : /* move.d PC,${Rd} */
 629 {
 630   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 631   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 632 #define FLD(f) abuf->fields.sfmt_moveq.f
 633   int UNUSED written = 0;
 634   IADDR UNUSED pc = abuf->addr;
 635   SEM_BRANCH_INIT
 636   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 637
 638 {
 639   SI tmp_pcval;
 640   tmp_pcval = ADDSI (pc, 2);
 641   {
 642     SI opval = tmp_pcval;
 643     SET_H_GR (FLD (f_operand2), opval);
 644     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 645   }
 646 {
 647   {
 648     BI opval = LTSI (tmp_pcval, 0);
 649     CPU (h_nbit) = opval;
 650     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 651   }
 652   {
 653     BI opval = ANDIF (EQSI (tmp_pcval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 654     CPU (h_zbit) = opval;
 655     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 656   }
 657 SET_H_CBIT_MOVE (0);
 658 SET_H_VBIT_MOVE (0);
 659 {
 660   {
 661     BI opval = 0;
 662     CPU (h_xbit) = opval;
 663     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 664   }
 665   {
 666     BI opval = 0;
 667     SET_H_INSN_PREFIXED_P (opval);
 668     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 669   }
 670 }
 671 }
 672 }
 673
 674   SEM_BRANCH_FINI (vpc);
 675 #undef FLD
 676 }
 677   NEXT (vpc);
 678
 679   CASE (sem, INSN_MOVEQ) : /* moveq $i,$Rd */
 680 {
 681   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 682   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 683 #define FLD(f) abuf->fields.sfmt_moveq.f
 684   int UNUSED written = 0;
 685   IADDR UNUSED pc = abuf->addr;
 686   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 687
 688 {
 689   SI tmp_newval;
 690   tmp_newval = FLD (f_s6);
 691   {
 692     SI opval = tmp_newval;
 693     SET_H_GR (FLD (f_operand2), opval);
 694     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 695   }
 696 {
 697 SET_H_NBIT_MOVE (LTSI (tmp_newval, 0));
 698 SET_H_ZBIT_MOVE (ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))));
 699 SET_H_CBIT_MOVE (0);
 700 SET_H_VBIT_MOVE (0);
 701 {
 702   {
 703     BI opval = 0;
 704     CPU (h_xbit) = opval;
 705     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 706   }
 707   {
 708     BI opval = 0;
 709     SET_H_INSN_PREFIXED_P (opval);
 710     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 711   }
 712 }
 713 }
 714 }
 715
 716 #undef FLD
 717 }
 718   NEXT (vpc);
 719
 720   CASE (sem, INSN_MOVS_B_R) : /* movs.b movs.m ${Rs},${Rd} */
 721 {
 722   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 723   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 724 #define FLD(f) abuf->fields.sfmt_muls_b.f
 725   int UNUSED written = 0;
 726   IADDR UNUSED pc = abuf->addr;
 727   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 728
 729 {
 730   QI tmp_tmpops;
 731   SI tmp_newval;
 732   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 733   tmp_newval = EXTQISI (tmp_tmpops);
 734   {
 735     SI opval = tmp_newval;
 736     SET_H_GR (FLD (f_operand2), opval);
 737     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 738   }
 739 {
 740   {
 741     BI opval = LTSI (tmp_newval, 0);
 742     CPU (h_nbit) = opval;
 743     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 744   }
 745   {
 746     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 747     CPU (h_zbit) = opval;
 748     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 749   }
 750 SET_H_CBIT_MOVE (0);
 751 SET_H_VBIT_MOVE (0);
 752 {
 753   {
 754     BI opval = 0;
 755     CPU (h_xbit) = opval;
 756     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 757   }
 758   {
 759     BI opval = 0;
 760     SET_H_INSN_PREFIXED_P (opval);
 761     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 762   }
 763 }
 764 }
 765 }
 766
 767 #undef FLD
 768 }
 769   NEXT (vpc);
 770
 771   CASE (sem, INSN_MOVS_W_R) : /* movs.w movs.m ${Rs},${Rd} */
 772 {
 773   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 774   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 775 #define FLD(f) abuf->fields.sfmt_muls_b.f
 776   int UNUSED written = 0;
 777   IADDR UNUSED pc = abuf->addr;
 778   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 779
 780 {
 781   HI tmp_tmpops;
 782   SI tmp_newval;
 783   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 784   tmp_newval = EXTHISI (tmp_tmpops);
 785   {
 786     SI opval = tmp_newval;
 787     SET_H_GR (FLD (f_operand2), opval);
 788     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 789   }
 790 {
 791   {
 792     BI opval = LTSI (tmp_newval, 0);
 793     CPU (h_nbit) = opval;
 794     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 795   }
 796   {
 797     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 798     CPU (h_zbit) = opval;
 799     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 800   }
 801 SET_H_CBIT_MOVE (0);
 802 SET_H_VBIT_MOVE (0);
 803 {
 804   {
 805     BI opval = 0;
 806     CPU (h_xbit) = opval;
 807     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 808   }
 809   {
 810     BI opval = 0;
 811     SET_H_INSN_PREFIXED_P (opval);
 812     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 813   }
 814 }
 815 }
 816 }
 817
 818 #undef FLD
 819 }
 820   NEXT (vpc);
 821
 822   CASE (sem, INSN_MOVU_B_R) : /* movu.b movu.m ${Rs},${Rd} */
 823 {
 824   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 825   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 826 #define FLD(f) abuf->fields.sfmt_muls_b.f
 827   int UNUSED written = 0;
 828   IADDR UNUSED pc = abuf->addr;
 829   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 830
 831 {
 832   QI tmp_tmpops;
 833   SI tmp_newval;
 834   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 835   tmp_newval = ZEXTQISI (tmp_tmpops);
 836   {
 837     SI opval = tmp_newval;
 838     SET_H_GR (FLD (f_operand2), opval);
 839     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 840   }
 841 {
 842   {
 843     BI opval = LTSI (tmp_newval, 0);
 844     CPU (h_nbit) = opval;
 845     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 846   }
 847   {
 848     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 849     CPU (h_zbit) = opval;
 850     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 851   }
 852 SET_H_CBIT_MOVE (0);
 853 SET_H_VBIT_MOVE (0);
 854 {
 855   {
 856     BI opval = 0;
 857     CPU (h_xbit) = opval;
 858     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 859   }
 860   {
 861     BI opval = 0;
 862     SET_H_INSN_PREFIXED_P (opval);
 863     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 864   }
 865 }
 866 }
 867 }
 868
 869 #undef FLD
 870 }
 871   NEXT (vpc);
 872
 873   CASE (sem, INSN_MOVU_W_R) : /* movu.w movu.m ${Rs},${Rd} */
 874 {
 875   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 876   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 877 #define FLD(f) abuf->fields.sfmt_muls_b.f
 878   int UNUSED written = 0;
 879   IADDR UNUSED pc = abuf->addr;
 880   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 881
 882 {
 883   HI tmp_tmpops;
 884   SI tmp_newval;
 885   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 886   tmp_newval = ZEXTHISI (tmp_tmpops);
 887   {
 888     SI opval = tmp_newval;
 889     SET_H_GR (FLD (f_operand2), opval);
 890     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 891   }
 892 {
 893   {
 894     BI opval = LTSI (tmp_newval, 0);
 895     CPU (h_nbit) = opval;
 896     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 897   }
 898   {
 899     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 900     CPU (h_zbit) = opval;
 901     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 902   }
 903 SET_H_CBIT_MOVE (0);
 904 SET_H_VBIT_MOVE (0);
 905 {
 906   {
 907     BI opval = 0;
 908     CPU (h_xbit) = opval;
 909     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 910   }
 911   {
 912     BI opval = 0;
 913     SET_H_INSN_PREFIXED_P (opval);
 914     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 915   }
 916 }
 917 }
 918 }
 919
 920 #undef FLD
 921 }
 922   NEXT (vpc);
 923
 924   CASE (sem, INSN_MOVECBR) : /* move.b ${sconst8},${Rd} */
 925 {
 926   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 927   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 928 #define FLD(f) abuf->fields.sfmt_addcbr.f
 929   int UNUSED written = 0;
 930   IADDR UNUSED pc = abuf->addr;
 931   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 932
 933 {
 934   QI tmp_newval;
 935   tmp_newval = FLD (f_indir_pc__byte);
 936 {
 937   SI tmp_oldregval;
 938   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 939   {
 940     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 941     SET_H_GR (FLD (f_operand2), opval);
 942     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 943   }
 944 }
 945 {
 946   {
 947     BI opval = LTQI (tmp_newval, 0);
 948     CPU (h_nbit) = opval;
 949     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 950   }
 951   {
 952     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 953     CPU (h_zbit) = opval;
 954     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 955   }
 956 SET_H_CBIT_MOVE (0);
 957 SET_H_VBIT_MOVE (0);
 958 {
 959   {
 960     BI opval = 0;
 961     CPU (h_xbit) = opval;
 962     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 963   }
 964   {
 965     BI opval = 0;
 966     SET_H_INSN_PREFIXED_P (opval);
 967     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 968   }
 969 }
 970 }
 971 }
 972
 973 #undef FLD
 974 }
 975   NEXT (vpc);
 976
 977   CASE (sem, INSN_MOVECWR) : /* move.w ${sconst16},${Rd} */
 978 {
 979   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 980   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 981 #define FLD(f) abuf->fields.sfmt_addcwr.f
 982   int UNUSED written = 0;
 983   IADDR UNUSED pc = abuf->addr;
 984   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 985
 986 {
 987   HI tmp_newval;
 988   tmp_newval = FLD (f_indir_pc__word);
 989 {
 990   SI tmp_oldregval;
 991   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 992   {
 993     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 994     SET_H_GR (FLD (f_operand2), opval);
 995     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 996   }
 997 }
 998 {
 999   {
1000     BI opval = LTHI (tmp_newval, 0);
1001     CPU (h_nbit) = opval;
1002     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1003   }
1004   {
1005     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1006     CPU (h_zbit) = opval;
1007     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1008   }
1009 SET_H_CBIT_MOVE (0);
1010 SET_H_VBIT_MOVE (0);
1011 {
1012   {
1013     BI opval = 0;
1014     CPU (h_xbit) = opval;
1015     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1016   }
1017   {
1018     BI opval = 0;
1019     SET_H_INSN_PREFIXED_P (opval);
1020     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1021   }
1022 }
1023 }
1024 }
1025
1026 #undef FLD
1027 }
1028   NEXT (vpc);
1029
1030   CASE (sem, INSN_MOVECDR) : /* move.d ${const32},${Rd} */
1031 {
1032   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1033   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1034 #define FLD(f) abuf->fields.sfmt_bound_cd.f
1035   int UNUSED written = 0;
1036   IADDR UNUSED pc = abuf->addr;
1037   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
1038
1039 {
1040   SI tmp_newval;
1041   tmp_newval = FLD (f_indir_pc__dword);
1042   {
1043     SI opval = tmp_newval;
1044     SET_H_GR (FLD (f_operand2), opval);
1045     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1046   }
1047 {
1048   {
1049     BI opval = LTSI (tmp_newval, 0);
1050     CPU (h_nbit) = opval;
1051     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1052   }
1053   {
1054     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1055     CPU (h_zbit) = opval;
1056     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1057   }
1058 SET_H_CBIT_MOVE (0);
1059 SET_H_VBIT_MOVE (0);
1060 {
1061   {
1062     BI opval = 0;
1063     CPU (h_xbit) = opval;
1064     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1065   }
1066   {
1067     BI opval = 0;
1068     SET_H_INSN_PREFIXED_P (opval);
1069     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1070   }
1071 }
1072 }
1073 }
1074
1075 #undef FLD
1076 }
1077   NEXT (vpc);
1078
1079   CASE (sem, INSN_MOVSCBR) : /* movs.b ${sconst8},${Rd} */
1080 {
1081   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1082   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1083 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1084   int UNUSED written = 0;
1085   IADDR UNUSED pc = abuf->addr;
1086   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1087
1088 {
1089   SI tmp_newval;
1090   tmp_newval = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1091   {
1092     SI opval = tmp_newval;
1093     SET_H_GR (FLD (f_operand2), opval);
1094     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1095   }
1096 {
1097   {
1098     BI opval = LTSI (tmp_newval, 0);
1099     CPU (h_nbit) = opval;
1100     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1101   }
1102   {
1103     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1104     CPU (h_zbit) = opval;
1105     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1106   }
1107 SET_H_CBIT_MOVE (0);
1108 SET_H_VBIT_MOVE (0);
1109 {
1110   {
1111     BI opval = 0;
1112     CPU (h_xbit) = opval;
1113     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1114   }
1115   {
1116     BI opval = 0;
1117     SET_H_INSN_PREFIXED_P (opval);
1118     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1119   }
1120 }
1121 }
1122 }
1123
1124 #undef FLD
1125 }
1126   NEXT (vpc);
1127
1128   CASE (sem, INSN_MOVSCWR) : /* movs.w ${sconst16},${Rd} */
1129 {
1130   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1131   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1132 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1133   int UNUSED written = 0;
1134   IADDR UNUSED pc = abuf->addr;
1135   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1136
1137 {
1138   SI tmp_newval;
1139   tmp_newval = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1140   {
1141     SI opval = tmp_newval;
1142     SET_H_GR (FLD (f_operand2), opval);
1143     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1144   }
1145 {
1146   {
1147     BI opval = LTSI (tmp_newval, 0);
1148     CPU (h_nbit) = opval;
1149     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1150   }
1151   {
1152     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1153     CPU (h_zbit) = opval;
1154     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1155   }
1156 SET_H_CBIT_MOVE (0);
1157 SET_H_VBIT_MOVE (0);
1158 {
1159   {
1160     BI opval = 0;
1161     CPU (h_xbit) = opval;
1162     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1163   }
1164   {
1165     BI opval = 0;
1166     SET_H_INSN_PREFIXED_P (opval);
1167     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1168   }
1169 }
1170 }
1171 }
1172
1173 #undef FLD
1174 }
1175   NEXT (vpc);
1176
1177   CASE (sem, INSN_MOVUCBR) : /* movu.b ${uconst8},${Rd} */
1178 {
1179   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1180   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1181 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1182   int UNUSED written = 0;
1183   IADDR UNUSED pc = abuf->addr;
1184   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1185
1186 {
1187   SI tmp_newval;
1188   tmp_newval = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1189   {
1190     SI opval = tmp_newval;
1191     SET_H_GR (FLD (f_operand2), opval);
1192     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1193   }
1194 {
1195   {
1196     BI opval = LTSI (tmp_newval, 0);
1197     CPU (h_nbit) = opval;
1198     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1199   }
1200   {
1201     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1202     CPU (h_zbit) = opval;
1203     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1204   }
1205 SET_H_CBIT_MOVE (0);
1206 SET_H_VBIT_MOVE (0);
1207 {
1208   {
1209     BI opval = 0;
1210     CPU (h_xbit) = opval;
1211     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1212   }
1213   {
1214     BI opval = 0;
1215     SET_H_INSN_PREFIXED_P (opval);
1216     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1217   }
1218 }
1219 }
1220 }
1221
1222 #undef FLD
1223 }
1224   NEXT (vpc);
1225
1226   CASE (sem, INSN_MOVUCWR) : /* movu.w ${uconst16},${Rd} */
1227 {
1228   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1229   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1230 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1231   int UNUSED written = 0;
1232   IADDR UNUSED pc = abuf->addr;
1233   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1234
1235 {
1236   SI tmp_newval;
1237   tmp_newval = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1238   {
1239     SI opval = tmp_newval;
1240     SET_H_GR (FLD (f_operand2), opval);
1241     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1242   }
1243 {
1244   {
1245     BI opval = LTSI (tmp_newval, 0);
1246     CPU (h_nbit) = opval;
1247     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1248   }
1249   {
1250     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1251     CPU (h_zbit) = opval;
1252     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1253   }
1254 SET_H_CBIT_MOVE (0);
1255 SET_H_VBIT_MOVE (0);
1256 {
1257   {
1258     BI opval = 0;
1259     CPU (h_xbit) = opval;
1260     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1261   }
1262   {
1263     BI opval = 0;
1264     SET_H_INSN_PREFIXED_P (opval);
1265     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1266   }
1267 }
1268 }
1269 }
1270
1271 #undef FLD
1272 }
1273   NEXT (vpc);
1274
1275   CASE (sem, INSN_ADDQ) : /* addq $j,$Rd */
1276 {
1277   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1278   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1279 #define FLD(f) abuf->fields.sfmt_addq.f
1280   int UNUSED written = 0;
1281   IADDR UNUSED pc = abuf->addr;
1282   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1283
1284 {
1285   SI tmp_tmpopd;
1286   SI tmp_tmpops;
1287   BI tmp_carry;
1288   SI tmp_newval;
1289   tmp_tmpops = FLD (f_u6);
1290   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1291   tmp_carry = CPU (h_cbit);
1292   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1293   {
1294     SI opval = tmp_newval;
1295     SET_H_GR (FLD (f_operand2), opval);
1296     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1297   }
1298 {
1299   {
1300     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
1301     CPU (h_cbit) = opval;
1302     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1303   }
1304   {
1305     BI opval = LTSI (tmp_newval, 0);
1306     CPU (h_nbit) = opval;
1307     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1308   }
1309   {
1310     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1311     CPU (h_zbit) = opval;
1312     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1313   }
1314   {
1315     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1316     CPU (h_vbit) = opval;
1317     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1318   }
1319 {
1320   {
1321     BI opval = 0;
1322     CPU (h_xbit) = opval;
1323     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1324   }
1325   {
1326     BI opval = 0;
1327     SET_H_INSN_PREFIXED_P (opval);
1328     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1329   }
1330 }
1331 }
1332 }
1333
1334 #undef FLD
1335 }
1336   NEXT (vpc);
1337
1338   CASE (sem, INSN_SUBQ) : /* subq $j,$Rd */
1339 {
1340   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1341   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1342 #define FLD(f) abuf->fields.sfmt_addq.f
1343   int UNUSED written = 0;
1344   IADDR UNUSED pc = abuf->addr;
1345   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1346
1347 {
1348   SI tmp_tmpopd;
1349   SI tmp_tmpops;
1350   BI tmp_carry;
1351   SI tmp_newval;
1352   tmp_tmpops = FLD (f_u6);
1353   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1354   tmp_carry = CPU (h_cbit);
1355   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1356   {
1357     SI opval = tmp_newval;
1358     SET_H_GR (FLD (f_operand2), opval);
1359     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1360   }
1361 {
1362   {
1363     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1364     CPU (h_cbit) = opval;
1365     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1366   }
1367   {
1368     BI opval = LTSI (tmp_newval, 0);
1369     CPU (h_nbit) = opval;
1370     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1371   }
1372   {
1373     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1374     CPU (h_zbit) = opval;
1375     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1376   }
1377   {
1378     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1379     CPU (h_vbit) = opval;
1380     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1381   }
1382 {
1383   {
1384     BI opval = 0;
1385     CPU (h_xbit) = opval;
1386     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1387   }
1388   {
1389     BI opval = 0;
1390     SET_H_INSN_PREFIXED_P (opval);
1391     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1392   }
1393 }
1394 }
1395 }
1396
1397 #undef FLD
1398 }
1399   NEXT (vpc);
1400
1401   CASE (sem, INSN_CMP_R_B_R) : /* cmp-r.b $Rs,$Rd */
1402 {
1403   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1404   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1405 #define FLD(f) abuf->fields.sfmt_add_b_r.f
1406   int UNUSED written = 0;
1407   IADDR UNUSED pc = abuf->addr;
1408   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1409
1410 {
1411   QI tmp_tmpopd;
1412   QI tmp_tmpops;
1413   BI tmp_carry;
1414   QI tmp_newval;
1415   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1416   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1417   tmp_carry = CPU (h_cbit);
1418   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1419 ((void) 0); /*nop*/
1420 {
1421   {
1422     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1423     CPU (h_cbit) = opval;
1424     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1425   }
1426   {
1427     BI opval = LTQI (tmp_newval, 0);
1428     CPU (h_nbit) = opval;
1429     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1430   }
1431   {
1432     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1433     CPU (h_zbit) = opval;
1434     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1435   }
1436   {
1437     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1438     CPU (h_vbit) = opval;
1439     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1440   }
1441 {
1442   {
1443     BI opval = 0;
1444     CPU (h_xbit) = opval;
1445     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1446   }
1447   {
1448     BI opval = 0;
1449     SET_H_INSN_PREFIXED_P (opval);
1450     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1451   }
1452 }
1453 }
1454 }
1455
1456 #undef FLD
1457 }
1458   NEXT (vpc);
1459
1460   CASE (sem, INSN_CMP_R_W_R) : /* cmp-r.w $Rs,$Rd */
1461 {
1462   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1463   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1464 #define FLD(f) abuf->fields.sfmt_add_b_r.f
1465   int UNUSED written = 0;
1466   IADDR UNUSED pc = abuf->addr;
1467   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1468
1469 {
1470   HI tmp_tmpopd;
1471   HI tmp_tmpops;
1472   BI tmp_carry;
1473   HI tmp_newval;
1474   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1475   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1476   tmp_carry = CPU (h_cbit);
1477   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1478 ((void) 0); /*nop*/
1479 {
1480   {
1481     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1482     CPU (h_cbit) = opval;
1483     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1484   }
1485   {
1486     BI opval = LTHI (tmp_newval, 0);
1487     CPU (h_nbit) = opval;
1488     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1489   }
1490   {
1491     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1492     CPU (h_zbit) = opval;
1493     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1494   }
1495   {
1496     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1497     CPU (h_vbit) = opval;
1498     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1499   }
1500 {
1501   {
1502     BI opval = 0;
1503     CPU (h_xbit) = opval;
1504     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1505   }
1506   {
1507     BI opval = 0;
1508     SET_H_INSN_PREFIXED_P (opval);
1509     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1510   }
1511 }
1512 }
1513 }
1514
1515 #undef FLD
1516 }
1517   NEXT (vpc);
1518
1519   CASE (sem, INSN_CMP_R_D_R) : /* cmp-r.d $Rs,$Rd */
1520 {
1521   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1522   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1523 #define FLD(f) abuf->fields.sfmt_add_b_r.f
1524   int UNUSED written = 0;
1525   IADDR UNUSED pc = abuf->addr;
1526   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1527
1528 {
1529   SI tmp_tmpopd;
1530   SI tmp_tmpops;
1531   BI tmp_carry;
1532   SI tmp_newval;
1533   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1534   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1535   tmp_carry = CPU (h_cbit);
1536   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1537 ((void) 0); /*nop*/
1538 {
1539   {
1540     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1541     CPU (h_cbit) = opval;
1542     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1543   }
1544   {
1545     BI opval = LTSI (tmp_newval, 0);
1546     CPU (h_nbit) = opval;
1547     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1548   }
1549   {
1550     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1551     CPU (h_zbit) = opval;
1552     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1553   }
1554   {
1555     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1556     CPU (h_vbit) = opval;
1557     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1558   }
1559 {
1560   {
1561     BI opval = 0;
1562     CPU (h_xbit) = opval;
1563     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1564   }
1565   {
1566     BI opval = 0;
1567     SET_H_INSN_PREFIXED_P (opval);
1568     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1569   }
1570 }
1571 }
1572 }
1573
1574 #undef FLD
1575 }
1576   NEXT (vpc);
1577
1578   CASE (sem, INSN_CMP_M_B_M) : /* cmp-m.b [${Rs}${inc}],${Rd} */
1579 {
1580   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1581   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1582 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
1583   int UNUSED written = 0;
1584   IADDR UNUSED pc = abuf->addr;
1585   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1586
1587 {
1588   QI tmp_tmpopd;
1589   QI tmp_tmpops;
1590   BI tmp_carry;
1591   QI tmp_newval;
1592   tmp_tmpops = ({   SI tmp_addr;
1593   QI tmp_tmp_mem;
1594   BI tmp_postinc;
1595   tmp_postinc = FLD (f_memmode);
1596 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
1597 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
1598 ; if (NEBI (tmp_postinc, 0)) {
1599 {
1600 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1601   tmp_addr = ADDSI (tmp_addr, 1);
1602 }
1603   {
1604     SI opval = tmp_addr;
1605     SET_H_GR (FLD (f_operand1), opval);
1606     written |= (1 << 9);
1607     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1608   }
1609 }
1610 }
1611 ; tmp_tmp_mem; });
1612   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1613   tmp_carry = CPU (h_cbit);
1614   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1615 ((void) 0); /*nop*/
1616 {
1617   {
1618     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1619     CPU (h_cbit) = opval;
1620     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1621   }
1622   {
1623     BI opval = LTQI (tmp_newval, 0);
1624     CPU (h_nbit) = opval;
1625     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1626   }
1627   {
1628     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1629     CPU (h_zbit) = opval;
1630     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1631   }
1632   {
1633     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1634     CPU (h_vbit) = opval;
1635     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1636   }
1637 {
1638   {
1639     BI opval = 0;
1640     CPU (h_xbit) = opval;
1641     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1642   }
1643   {
1644     BI opval = 0;
1645     SET_H_INSN_PREFIXED_P (opval);
1646     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1647   }
1648 }
1649 }
1650 }
1651
1652   abuf->written = written;
1653 #undef FLD
1654 }
1655   NEXT (vpc);
1656
1657   CASE (sem, INSN_CMP_M_W_M) : /* cmp-m.w [${Rs}${inc}],${Rd} */
1658 {
1659   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1660   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1661 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
1662   int UNUSED written = 0;
1663   IADDR UNUSED pc = abuf->addr;
1664   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1665
1666 {
1667   HI tmp_tmpopd;
1668   HI tmp_tmpops;
1669   BI tmp_carry;
1670   HI tmp_newval;
1671   tmp_tmpops = ({   SI tmp_addr;
1672   HI tmp_tmp_mem;
1673   BI tmp_postinc;
1674   tmp_postinc = FLD (f_memmode);
1675 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
1676 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
1677 ; if (NEBI (tmp_postinc, 0)) {
1678 {
1679 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1680   tmp_addr = ADDSI (tmp_addr, 2);
1681 }
1682   {
1683     SI opval = tmp_addr;
1684     SET_H_GR (FLD (f_operand1), opval);
1685     written |= (1 << 9);
1686     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1687   }
1688 }
1689 }
1690 ; tmp_tmp_mem; });
1691   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1692   tmp_carry = CPU (h_cbit);
1693   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1694 ((void) 0); /*nop*/
1695 {
1696   {
1697     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1698     CPU (h_cbit) = opval;
1699     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1700   }
1701   {
1702     BI opval = LTHI (tmp_newval, 0);
1703     CPU (h_nbit) = opval;
1704     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1705   }
1706   {
1707     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1708     CPU (h_zbit) = opval;
1709     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1710   }
1711   {
1712     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1713     CPU (h_vbit) = opval;
1714     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1715   }
1716 {
1717   {
1718     BI opval = 0;
1719     CPU (h_xbit) = opval;
1720     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1721   }
1722   {
1723     BI opval = 0;
1724     SET_H_INSN_PREFIXED_P (opval);
1725     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1726   }
1727 }
1728 }
1729 }
1730
1731   abuf->written = written;
1732 #undef FLD
1733 }
1734   NEXT (vpc);
1735
1736   CASE (sem, INSN_CMP_M_D_M) : /* cmp-m.d [${Rs}${inc}],${Rd} */
1737 {
1738   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1739   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1740 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
1741   int UNUSED written = 0;
1742   IADDR UNUSED pc = abuf->addr;
1743   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1744
1745 {
1746   SI tmp_tmpopd;
1747   SI tmp_tmpops;
1748   BI tmp_carry;
1749   SI tmp_newval;
1750   tmp_tmpops = ({   SI tmp_addr;
1751   SI tmp_tmp_mem;
1752   BI tmp_postinc;
1753   tmp_postinc = FLD (f_memmode);
1754 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
1755 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
1756 ; if (NEBI (tmp_postinc, 0)) {
1757 {
1758 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1759   tmp_addr = ADDSI (tmp_addr, 4);
1760 }
1761   {
1762     SI opval = tmp_addr;
1763     SET_H_GR (FLD (f_operand1), opval);
1764     written |= (1 << 9);
1765     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1766   }
1767 }
1768 }
1769 ; tmp_tmp_mem; });
1770   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1771   tmp_carry = CPU (h_cbit);
1772   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1773 ((void) 0); /*nop*/
1774 {
1775   {
1776     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1777     CPU (h_cbit) = opval;
1778     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1779   }
1780   {
1781     BI opval = LTSI (tmp_newval, 0);
1782     CPU (h_nbit) = opval;
1783     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1784   }
1785   {
1786     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1787     CPU (h_zbit) = opval;
1788     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1789   }
1790   {
1791     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1792     CPU (h_vbit) = opval;
1793     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1794   }
1795 {
1796   {
1797     BI opval = 0;
1798     CPU (h_xbit) = opval;
1799     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1800   }
1801   {
1802     BI opval = 0;
1803     SET_H_INSN_PREFIXED_P (opval);
1804     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1805   }
1806 }
1807 }
1808 }
1809
1810   abuf->written = written;
1811 #undef FLD
1812 }
1813   NEXT (vpc);
1814
1815   CASE (sem, INSN_CMPCBR) : /* cmp.b $sconst8,$Rd */
1816 {
1817   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1818   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1819 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1820   int UNUSED written = 0;
1821   IADDR UNUSED pc = abuf->addr;
1822   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1823
1824 {
1825   QI tmp_tmpopd;
1826   QI tmp_tmpops;
1827   BI tmp_carry;
1828   QI tmp_newval;
1829   tmp_tmpops = TRUNCSIQI (FLD (f_indir_pc__byte));
1830   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1831   tmp_carry = CPU (h_cbit);
1832   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1833 ((void) 0); /*nop*/
1834 {
1835   {
1836     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1837     CPU (h_cbit) = opval;
1838     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1839   }
1840   {
1841     BI opval = LTQI (tmp_newval, 0);
1842     CPU (h_nbit) = opval;
1843     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1844   }
1845   {
1846     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1847     CPU (h_zbit) = opval;
1848     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1849   }
1850   {
1851     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1852     CPU (h_vbit) = opval;
1853     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1854   }
1855 {
1856   {
1857     BI opval = 0;
1858     CPU (h_xbit) = opval;
1859     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1860   }
1861   {
1862     BI opval = 0;
1863     SET_H_INSN_PREFIXED_P (opval);
1864     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1865   }
1866 }
1867 }
1868 }
1869
1870 #undef FLD
1871 }
1872   NEXT (vpc);
1873
1874   CASE (sem, INSN_CMPCWR) : /* cmp.w $sconst16,$Rd */
1875 {
1876   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1877   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1878 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1879   int UNUSED written = 0;
1880   IADDR UNUSED pc = abuf->addr;
1881   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1882
1883 {
1884   HI tmp_tmpopd;
1885   HI tmp_tmpops;
1886   BI tmp_carry;
1887   HI tmp_newval;
1888   tmp_tmpops = TRUNCSIHI (FLD (f_indir_pc__word));
1889   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1890   tmp_carry = CPU (h_cbit);
1891   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1892 ((void) 0); /*nop*/
1893 {
1894   {
1895     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1896     CPU (h_cbit) = opval;
1897     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1898   }
1899   {
1900     BI opval = LTHI (tmp_newval, 0);
1901     CPU (h_nbit) = opval;
1902     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1903   }
1904   {
1905     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1906     CPU (h_zbit) = opval;
1907     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1908   }
1909   {
1910     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1911     CPU (h_vbit) = opval;
1912     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1913   }
1914 {
1915   {
1916     BI opval = 0;
1917     CPU (h_xbit) = opval;
1918     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1919   }
1920   {
1921     BI opval = 0;
1922     SET_H_INSN_PREFIXED_P (opval);
1923     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1924   }
1925 }
1926 }
1927 }
1928
1929 #undef FLD
1930 }
1931   NEXT (vpc);
1932
1933   CASE (sem, INSN_CMPCDR) : /* cmp.d $const32,$Rd */
1934 {
1935   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1936   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1937 #define FLD(f) abuf->fields.sfmt_bound_cd.f
1938   int UNUSED written = 0;
1939   IADDR UNUSED pc = abuf->addr;
1940   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
1941
1942 {
1943   SI tmp_tmpopd;
1944   SI tmp_tmpops;
1945   BI tmp_carry;
1946   SI tmp_newval;
1947   tmp_tmpops = FLD (f_indir_pc__dword);
1948   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1949   tmp_carry = CPU (h_cbit);
1950   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1951 ((void) 0); /*nop*/
1952 {
1953   {
1954     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1955     CPU (h_cbit) = opval;
1956     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1957   }
1958   {
1959     BI opval = LTSI (tmp_newval, 0);
1960     CPU (h_nbit) = opval;
1961     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1962   }
1963   {
1964     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1965     CPU (h_zbit) = opval;
1966     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1967   }
1968   {
1969     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1970     CPU (h_vbit) = opval;
1971     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1972   }
1973 {
1974   {
1975     BI opval = 0;
1976     CPU (h_xbit) = opval;
1977     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1978   }
1979   {
1980     BI opval = 0;
1981     SET_H_INSN_PREFIXED_P (opval);
1982     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1983   }
1984 }
1985 }
1986 }
1987
1988 #undef FLD
1989 }
1990   NEXT (vpc);
1991
1992   CASE (sem, INSN_CMPQ) : /* cmpq $i,$Rd */
1993 {
1994   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1995   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1996 #define FLD(f) abuf->fields.sfmt_andq.f
1997   int UNUSED written = 0;
1998   IADDR UNUSED pc = abuf->addr;
1999   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2000
2001 {
2002   SI tmp_tmpopd;
2003   SI tmp_tmpops;
2004   BI tmp_carry;
2005   SI tmp_newval;
2006   tmp_tmpops = FLD (f_s6);
2007   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2008   tmp_carry = CPU (h_cbit);
2009   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2010 ((void) 0); /*nop*/
2011 {
2012   {
2013     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2014     CPU (h_cbit) = opval;
2015     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2016   }
2017   {
2018     BI opval = LTSI (tmp_newval, 0);
2019     CPU (h_nbit) = opval;
2020     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2021   }
2022   {
2023     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2024     CPU (h_zbit) = opval;
2025     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2026   }
2027   {
2028     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2029     CPU (h_vbit) = opval;
2030     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2031   }
2032 {
2033   {
2034     BI opval = 0;
2035     CPU (h_xbit) = opval;
2036     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2037   }
2038   {
2039     BI opval = 0;
2040     SET_H_INSN_PREFIXED_P (opval);
2041     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2042   }
2043 }
2044 }
2045 }
2046
2047 #undef FLD
2048 }
2049   NEXT (vpc);
2050
2051   CASE (sem, INSN_CMPS_M_B_M) : /* cmps-m.b [${Rs}${inc}],$Rd */
2052 {
2053   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2054   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2055 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2056   int UNUSED written = 0;
2057   IADDR UNUSED pc = abuf->addr;
2058   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2059
2060 {
2061   SI tmp_tmpopd;
2062   SI tmp_tmpops;
2063   BI tmp_carry;
2064   SI tmp_newval;
2065   tmp_tmpops = EXTQISI (({   SI tmp_addr;
2066   QI tmp_tmp_mem;
2067   BI tmp_postinc;
2068   tmp_postinc = FLD (f_memmode);
2069 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2070 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2071 ; if (NEBI (tmp_postinc, 0)) {
2072 {
2073 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2074   tmp_addr = ADDSI (tmp_addr, 1);
2075 }
2076   {
2077     SI opval = tmp_addr;
2078     SET_H_GR (FLD (f_operand1), opval);
2079     written |= (1 << 9);
2080     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2081   }
2082 }
2083 }
2084 ; tmp_tmp_mem; }));
2085   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2086   tmp_carry = CPU (h_cbit);
2087   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2088 ((void) 0); /*nop*/
2089 {
2090   {
2091     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2092     CPU (h_cbit) = opval;
2093     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2094   }
2095   {
2096     BI opval = LTSI (tmp_newval, 0);
2097     CPU (h_nbit) = opval;
2098     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2099   }
2100   {
2101     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2102     CPU (h_zbit) = opval;
2103     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2104   }
2105   {
2106     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2107     CPU (h_vbit) = opval;
2108     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2109   }
2110 {
2111   {
2112     BI opval = 0;
2113     CPU (h_xbit) = opval;
2114     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2115   }
2116   {
2117     BI opval = 0;
2118     SET_H_INSN_PREFIXED_P (opval);
2119     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2120   }
2121 }
2122 }
2123 }
2124
2125   abuf->written = written;
2126 #undef FLD
2127 }
2128   NEXT (vpc);
2129
2130   CASE (sem, INSN_CMPS_M_W_M) : /* cmps-m.w [${Rs}${inc}],$Rd */
2131 {
2132   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2133   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2134 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2135   int UNUSED written = 0;
2136   IADDR UNUSED pc = abuf->addr;
2137   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2138
2139 {
2140   SI tmp_tmpopd;
2141   SI tmp_tmpops;
2142   BI tmp_carry;
2143   SI tmp_newval;
2144   tmp_tmpops = EXTHISI (({   SI tmp_addr;
2145   HI tmp_tmp_mem;
2146   BI tmp_postinc;
2147   tmp_postinc = FLD (f_memmode);
2148 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2149 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2150 ; if (NEBI (tmp_postinc, 0)) {
2151 {
2152 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2153   tmp_addr = ADDSI (tmp_addr, 2);
2154 }
2155   {
2156     SI opval = tmp_addr;
2157     SET_H_GR (FLD (f_operand1), opval);
2158     written |= (1 << 9);
2159     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2160   }
2161 }
2162 }
2163 ; tmp_tmp_mem; }));
2164   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2165   tmp_carry = CPU (h_cbit);
2166   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2167 ((void) 0); /*nop*/
2168 {
2169   {
2170     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2171     CPU (h_cbit) = opval;
2172     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2173   }
2174   {
2175     BI opval = LTSI (tmp_newval, 0);
2176     CPU (h_nbit) = opval;
2177     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2178   }
2179   {
2180     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2181     CPU (h_zbit) = opval;
2182     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2183   }
2184   {
2185     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2186     CPU (h_vbit) = opval;
2187     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2188   }
2189 {
2190   {
2191     BI opval = 0;
2192     CPU (h_xbit) = opval;
2193     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2194   }
2195   {
2196     BI opval = 0;
2197     SET_H_INSN_PREFIXED_P (opval);
2198     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2199   }
2200 }
2201 }
2202 }
2203
2204   abuf->written = written;
2205 #undef FLD
2206 }
2207   NEXT (vpc);
2208
2209   CASE (sem, INSN_CMPSCBR) : /* [${Rs}${inc}],$Rd */
2210 {
2211   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2212   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2213 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2214   int UNUSED written = 0;
2215   IADDR UNUSED pc = abuf->addr;
2216   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2217
2218 {
2219   SI tmp_tmpopd;
2220   SI tmp_tmpops;
2221   BI tmp_carry;
2222   SI tmp_newval;
2223   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2224   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2225   tmp_carry = CPU (h_cbit);
2226   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2227 ((void) 0); /*nop*/
2228 {
2229   {
2230     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2231     CPU (h_cbit) = opval;
2232     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2233   }
2234   {
2235     BI opval = LTSI (tmp_newval, 0);
2236     CPU (h_nbit) = opval;
2237     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2238   }
2239   {
2240     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2241     CPU (h_zbit) = opval;
2242     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2243   }
2244   {
2245     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2246     CPU (h_vbit) = opval;
2247     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2248   }
2249 {
2250   {
2251     BI opval = 0;
2252     CPU (h_xbit) = opval;
2253     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2254   }
2255   {
2256     BI opval = 0;
2257     SET_H_INSN_PREFIXED_P (opval);
2258     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2259   }
2260 }
2261 }
2262 }
2263
2264 #undef FLD
2265 }
2266   NEXT (vpc);
2267
2268   CASE (sem, INSN_CMPSCWR) : /* [${Rs}${inc}],$Rd */
2269 {
2270   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2271   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2272 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2273   int UNUSED written = 0;
2274   IADDR UNUSED pc = abuf->addr;
2275   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2276
2277 {
2278   SI tmp_tmpopd;
2279   SI tmp_tmpops;
2280   BI tmp_carry;
2281   SI tmp_newval;
2282   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2283   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2284   tmp_carry = CPU (h_cbit);
2285   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2286 ((void) 0); /*nop*/
2287 {
2288   {
2289     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2290     CPU (h_cbit) = opval;
2291     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2292   }
2293   {
2294     BI opval = LTSI (tmp_newval, 0);
2295     CPU (h_nbit) = opval;
2296     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2297   }
2298   {
2299     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2300     CPU (h_zbit) = opval;
2301     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2302   }
2303   {
2304     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2305     CPU (h_vbit) = opval;
2306     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2307   }
2308 {
2309   {
2310     BI opval = 0;
2311     CPU (h_xbit) = opval;
2312     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2313   }
2314   {
2315     BI opval = 0;
2316     SET_H_INSN_PREFIXED_P (opval);
2317     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2318   }
2319 }
2320 }
2321 }
2322
2323 #undef FLD
2324 }
2325   NEXT (vpc);
2326
2327   CASE (sem, INSN_CMPU_M_B_M) : /* cmpu-m.b [${Rs}${inc}],$Rd */
2328 {
2329   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2330   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2331 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2332   int UNUSED written = 0;
2333   IADDR UNUSED pc = abuf->addr;
2334   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2335
2336 {
2337   SI tmp_tmpopd;
2338   SI tmp_tmpops;
2339   BI tmp_carry;
2340   SI tmp_newval;
2341   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
2342   QI tmp_tmp_mem;
2343   BI tmp_postinc;
2344   tmp_postinc = FLD (f_memmode);
2345 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2346 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2347 ; if (NEBI (tmp_postinc, 0)) {
2348 {
2349 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2350   tmp_addr = ADDSI (tmp_addr, 1);
2351 }
2352   {
2353     SI opval = tmp_addr;
2354     SET_H_GR (FLD (f_operand1), opval);
2355     written |= (1 << 9);
2356     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2357   }
2358 }
2359 }
2360 ; tmp_tmp_mem; }));
2361   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2362   tmp_carry = CPU (h_cbit);
2363   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2364 ((void) 0); /*nop*/
2365 {
2366   {
2367     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2368     CPU (h_cbit) = opval;
2369     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2370   }
2371   {
2372     BI opval = LTSI (tmp_newval, 0);
2373     CPU (h_nbit) = opval;
2374     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2375   }
2376   {
2377     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2378     CPU (h_zbit) = opval;
2379     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2380   }
2381   {
2382     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2383     CPU (h_vbit) = opval;
2384     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2385   }
2386 {
2387   {
2388     BI opval = 0;
2389     CPU (h_xbit) = opval;
2390     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2391   }
2392   {
2393     BI opval = 0;
2394     SET_H_INSN_PREFIXED_P (opval);
2395     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2396   }
2397 }
2398 }
2399 }
2400
2401   abuf->written = written;
2402 #undef FLD
2403 }
2404   NEXT (vpc);
2405
2406   CASE (sem, INSN_CMPU_M_W_M) : /* cmpu-m.w [${Rs}${inc}],$Rd */
2407 {
2408   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2409   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2410 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2411   int UNUSED written = 0;
2412   IADDR UNUSED pc = abuf->addr;
2413   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2414
2415 {
2416   SI tmp_tmpopd;
2417   SI tmp_tmpops;
2418   BI tmp_carry;
2419   SI tmp_newval;
2420   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
2421   HI tmp_tmp_mem;
2422   BI tmp_postinc;
2423   tmp_postinc = FLD (f_memmode);
2424 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2425 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2426 ; if (NEBI (tmp_postinc, 0)) {
2427 {
2428 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2429   tmp_addr = ADDSI (tmp_addr, 2);
2430 }
2431   {
2432     SI opval = tmp_addr;
2433     SET_H_GR (FLD (f_operand1), opval);
2434     written |= (1 << 9);
2435     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2436   }
2437 }
2438 }
2439 ; tmp_tmp_mem; }));
2440   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2441   tmp_carry = CPU (h_cbit);
2442   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2443 ((void) 0); /*nop*/
2444 {
2445   {
2446     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2447     CPU (h_cbit) = opval;
2448     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2449   }
2450   {
2451     BI opval = LTSI (tmp_newval, 0);
2452     CPU (h_nbit) = opval;
2453     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2454   }
2455   {
2456     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2457     CPU (h_zbit) = opval;
2458     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2459   }
2460   {
2461     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2462     CPU (h_vbit) = opval;
2463     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2464   }
2465 {
2466   {
2467     BI opval = 0;
2468     CPU (h_xbit) = opval;
2469     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2470   }
2471   {
2472     BI opval = 0;
2473     SET_H_INSN_PREFIXED_P (opval);
2474     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2475   }
2476 }
2477 }
2478 }
2479
2480   abuf->written = written;
2481 #undef FLD
2482 }
2483   NEXT (vpc);
2484
2485   CASE (sem, INSN_CMPUCBR) : /* [${Rs}${inc}],$Rd */
2486 {
2487   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2488   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2489 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2490   int UNUSED written = 0;
2491   IADDR UNUSED pc = abuf->addr;
2492   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2493
2494 {
2495   SI tmp_tmpopd;
2496   SI tmp_tmpops;
2497   BI tmp_carry;
2498   SI tmp_newval;
2499   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2500   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2501   tmp_carry = CPU (h_cbit);
2502   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2503 ((void) 0); /*nop*/
2504 {
2505   {
2506     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2507     CPU (h_cbit) = opval;
2508     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2509   }
2510   {
2511     BI opval = LTSI (tmp_newval, 0);
2512     CPU (h_nbit) = opval;
2513     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2514   }
2515   {
2516     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2517     CPU (h_zbit) = opval;
2518     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2519   }
2520   {
2521     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2522     CPU (h_vbit) = opval;
2523     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2524   }
2525 {
2526   {
2527     BI opval = 0;
2528     CPU (h_xbit) = opval;
2529     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2530   }
2531   {
2532     BI opval = 0;
2533     SET_H_INSN_PREFIXED_P (opval);
2534     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2535   }
2536 }
2537 }
2538 }
2539
2540 #undef FLD
2541 }
2542   NEXT (vpc);
2543
2544   CASE (sem, INSN_CMPUCWR) : /* [${Rs}${inc}],$Rd */
2545 {
2546   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2547   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2548 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2549   int UNUSED written = 0;
2550   IADDR UNUSED pc = abuf->addr;
2551   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2552
2553 {
2554   SI tmp_tmpopd;
2555   SI tmp_tmpops;
2556   BI tmp_carry;
2557   SI tmp_newval;
2558   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2559   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2560   tmp_carry = CPU (h_cbit);
2561   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2562 ((void) 0); /*nop*/
2563 {
2564   {
2565     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2566     CPU (h_cbit) = opval;
2567     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2568   }
2569   {
2570     BI opval = LTSI (tmp_newval, 0);
2571     CPU (h_nbit) = opval;
2572     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2573   }
2574   {
2575     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2576     CPU (h_zbit) = opval;
2577     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2578   }
2579   {
2580     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2581     CPU (h_vbit) = opval;
2582     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2583   }
2584 {
2585   {
2586     BI opval = 0;
2587     CPU (h_xbit) = opval;
2588     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2589   }
2590   {
2591     BI opval = 0;
2592     SET_H_INSN_PREFIXED_P (opval);
2593     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2594   }
2595 }
2596 }
2597 }
2598
2599 #undef FLD
2600 }
2601   NEXT (vpc);
2602
2603   CASE (sem, INSN_MOVE_M_B_M) : /* move-m.b [${Rs}${inc}],${Rd} */
2604 {
2605   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2606   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2607 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2608   int UNUSED written = 0;
2609   IADDR UNUSED pc = abuf->addr;
2610   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2611
2612 {
2613   SI tmp_tmp;
2614   tmp_tmp = ({   SI tmp_addr;
2615   QI tmp_tmp_mem;
2616   BI tmp_postinc;
2617   tmp_postinc = FLD (f_memmode);
2618 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2619 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2620 ; if (NEBI (tmp_postinc, 0)) {
2621 {
2622 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2623   tmp_addr = ADDSI (tmp_addr, 1);
2624 }
2625   {
2626     SI opval = tmp_addr;
2627     SET_H_GR (FLD (f_operand1), opval);
2628     written |= (1 << 10);
2629     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2630   }
2631 }
2632 }
2633 ; tmp_tmp_mem; });
2634 {
2635   SI tmp_oldregval;
2636   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2637   {
2638     SI opval = ORSI (ANDSI (tmp_tmp, 255), ANDSI (tmp_oldregval, 0xffffff00));
2639     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2640     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2641   }
2642 }
2643 {
2644   {
2645     BI opval = LTQI (tmp_tmp, 0);
2646     CPU (h_nbit) = opval;
2647     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2648   }
2649   {
2650     BI opval = ANDIF (EQQI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2651     CPU (h_zbit) = opval;
2652     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2653   }
2654 SET_H_CBIT_MOVE (0);
2655 SET_H_VBIT_MOVE (0);
2656 {
2657   {
2658     BI opval = 0;
2659     CPU (h_xbit) = opval;
2660     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2661   }
2662   {
2663     BI opval = 0;
2664     SET_H_INSN_PREFIXED_P (opval);
2665     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2666   }
2667 }
2668 }
2669 }
2670
2671   abuf->written = written;
2672 #undef FLD
2673 }
2674   NEXT (vpc);
2675
2676   CASE (sem, INSN_MOVE_M_W_M) : /* move-m.w [${Rs}${inc}],${Rd} */
2677 {
2678   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2679   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2680 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2681   int UNUSED written = 0;
2682   IADDR UNUSED pc = abuf->addr;
2683   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2684
2685 {
2686   SI tmp_tmp;
2687   tmp_tmp = ({   SI tmp_addr;
2688   HI tmp_tmp_mem;
2689   BI tmp_postinc;
2690   tmp_postinc = FLD (f_memmode);
2691 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2692 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2693 ; if (NEBI (tmp_postinc, 0)) {
2694 {
2695 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2696   tmp_addr = ADDSI (tmp_addr, 2);
2697 }
2698   {
2699     SI opval = tmp_addr;
2700     SET_H_GR (FLD (f_operand1), opval);
2701     written |= (1 << 10);
2702     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2703   }
2704 }
2705 }
2706 ; tmp_tmp_mem; });
2707 {
2708   SI tmp_oldregval;
2709   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2710   {
2711     SI opval = ORSI (ANDSI (tmp_tmp, 65535), ANDSI (tmp_oldregval, 0xffff0000));
2712     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2713     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2714   }
2715 }
2716 {
2717   {
2718     BI opval = LTHI (tmp_tmp, 0);
2719     CPU (h_nbit) = opval;
2720     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2721   }
2722   {
2723     BI opval = ANDIF (EQHI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2724     CPU (h_zbit) = opval;
2725     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2726   }
2727 SET_H_CBIT_MOVE (0);
2728 SET_H_VBIT_MOVE (0);
2729 {
2730   {
2731     BI opval = 0;
2732     CPU (h_xbit) = opval;
2733     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2734   }
2735   {
2736     BI opval = 0;
2737     SET_H_INSN_PREFIXED_P (opval);
2738     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2739   }
2740 }
2741 }
2742 }
2743
2744   abuf->written = written;
2745 #undef FLD
2746 }
2747   NEXT (vpc);
2748
2749   CASE (sem, INSN_MOVE_M_D_M) : /* move-m.d [${Rs}${inc}],${Rd} */
2750 {
2751   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2752   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2753 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2754   int UNUSED written = 0;
2755   IADDR UNUSED pc = abuf->addr;
2756   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2757
2758 {
2759   SI tmp_tmp;
2760   tmp_tmp = ({   SI tmp_addr;
2761   SI tmp_tmp_mem;
2762   BI tmp_postinc;
2763   tmp_postinc = FLD (f_memmode);
2764 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2765 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
2766 ; if (NEBI (tmp_postinc, 0)) {
2767 {
2768 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2769   tmp_addr = ADDSI (tmp_addr, 4);
2770 }
2771   {
2772     SI opval = tmp_addr;
2773     SET_H_GR (FLD (f_operand1), opval);
2774     written |= (1 << 9);
2775     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2776   }
2777 }
2778 }
2779 ; tmp_tmp_mem; });
2780   {
2781     SI opval = tmp_tmp;
2782     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2783     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2784   }
2785 {
2786   {
2787     BI opval = LTSI (tmp_tmp, 0);
2788     CPU (h_nbit) = opval;
2789     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2790   }
2791   {
2792     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2793     CPU (h_zbit) = opval;
2794     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2795   }
2796 SET_H_CBIT_MOVE (0);
2797 SET_H_VBIT_MOVE (0);
2798 {
2799   {
2800     BI opval = 0;
2801     CPU (h_xbit) = opval;
2802     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2803   }
2804   {
2805     BI opval = 0;
2806     SET_H_INSN_PREFIXED_P (opval);
2807     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2808   }
2809 }
2810 }
2811 }
2812
2813   abuf->written = written;
2814 #undef FLD
2815 }
2816   NEXT (vpc);
2817
2818   CASE (sem, INSN_MOVS_M_B_M) : /* movs-m.b [${Rs}${inc}],${Rd} */
2819 {
2820   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2821   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2822 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2823   int UNUSED written = 0;
2824   IADDR UNUSED pc = abuf->addr;
2825   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2826
2827 {
2828   SI tmp_tmp;
2829   tmp_tmp = EXTQISI (({   SI tmp_addr;
2830   QI tmp_tmp_mem;
2831   BI tmp_postinc;
2832   tmp_postinc = FLD (f_memmode);
2833 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2834 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2835 ; if (NEBI (tmp_postinc, 0)) {
2836 {
2837 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2838   tmp_addr = ADDSI (tmp_addr, 1);
2839 }
2840   {
2841     SI opval = tmp_addr;
2842     SET_H_GR (FLD (f_operand1), opval);
2843     written |= (1 << 8);
2844     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2845   }
2846 }
2847 }
2848 ; tmp_tmp_mem; }));
2849 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2850   {
2851     SI opval = tmp_tmp;
2852     SET_H_GR (FLD (f_operand1), opval);
2853     written |= (1 << 8);
2854     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2855   }
2856 } else {
2857   {
2858     SI opval = tmp_tmp;
2859     SET_H_GR (FLD (f_operand2), opval);
2860     written |= (1 << 7);
2861     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2862   }
2863 }
2864 {
2865   {
2866     BI opval = LTSI (tmp_tmp, 0);
2867     CPU (h_nbit) = opval;
2868     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2869   }
2870   {
2871     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2872     CPU (h_zbit) = opval;
2873     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2874   }
2875 SET_H_CBIT_MOVE (0);
2876 SET_H_VBIT_MOVE (0);
2877 {
2878   {
2879     BI opval = 0;
2880     CPU (h_xbit) = opval;
2881     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2882   }
2883   {
2884     BI opval = 0;
2885     SET_H_INSN_PREFIXED_P (opval);
2886     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2887   }
2888 }
2889 }
2890 }
2891
2892   abuf->written = written;
2893 #undef FLD
2894 }
2895   NEXT (vpc);
2896
2897   CASE (sem, INSN_MOVS_M_W_M) : /* movs-m.w [${Rs}${inc}],${Rd} */
2898 {
2899   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2900   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2901 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2902   int UNUSED written = 0;
2903   IADDR UNUSED pc = abuf->addr;
2904   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2905
2906 {
2907   SI tmp_tmp;
2908   tmp_tmp = EXTHISI (({   SI tmp_addr;
2909   HI tmp_tmp_mem;
2910   BI tmp_postinc;
2911   tmp_postinc = FLD (f_memmode);
2912 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2913 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2914 ; if (NEBI (tmp_postinc, 0)) {
2915 {
2916 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2917   tmp_addr = ADDSI (tmp_addr, 2);
2918 }
2919   {
2920     SI opval = tmp_addr;
2921     SET_H_GR (FLD (f_operand1), opval);
2922     written |= (1 << 8);
2923     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2924   }
2925 }
2926 }
2927 ; tmp_tmp_mem; }));
2928 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2929   {
2930     SI opval = tmp_tmp;
2931     SET_H_GR (FLD (f_operand1), opval);
2932     written |= (1 << 8);
2933     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2934   }
2935 } else {
2936   {
2937     SI opval = tmp_tmp;
2938     SET_H_GR (FLD (f_operand2), opval);
2939     written |= (1 << 7);
2940     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2941   }
2942 }
2943 {
2944   {
2945     BI opval = LTSI (tmp_tmp, 0);
2946     CPU (h_nbit) = opval;
2947     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2948   }
2949   {
2950     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2951     CPU (h_zbit) = opval;
2952     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2953   }
2954 SET_H_CBIT_MOVE (0);
2955 SET_H_VBIT_MOVE (0);
2956 {
2957   {
2958     BI opval = 0;
2959     CPU (h_xbit) = opval;
2960     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2961   }
2962   {
2963     BI opval = 0;
2964     SET_H_INSN_PREFIXED_P (opval);
2965     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2966   }
2967 }
2968 }
2969 }
2970
2971   abuf->written = written;
2972 #undef FLD
2973 }
2974   NEXT (vpc);
2975
2976   CASE (sem, INSN_MOVU_M_B_M) : /* movu-m.b [${Rs}${inc}],${Rd} */
2977 {
2978   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2979   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2980 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2981   int UNUSED written = 0;
2982   IADDR UNUSED pc = abuf->addr;
2983   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2984
2985 {
2986   SI tmp_tmp;
2987   tmp_tmp = ZEXTQISI (({   SI tmp_addr;
2988   QI tmp_tmp_mem;
2989   BI tmp_postinc;
2990   tmp_postinc = FLD (f_memmode);
2991 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2992 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2993 ; if (NEBI (tmp_postinc, 0)) {
2994 {
2995 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2996   tmp_addr = ADDSI (tmp_addr, 1);
2997 }
2998   {
2999     SI opval = tmp_addr;
3000     SET_H_GR (FLD (f_operand1), opval);
3001     written |= (1 << 8);
3002     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3003   }
3004 }
3005 }
3006 ; tmp_tmp_mem; }));
3007 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
3008   {
3009     SI opval = tmp_tmp;
3010     SET_H_GR (FLD (f_operand1), opval);
3011     written |= (1 << 8);
3012     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3013   }
3014 } else {
3015   {
3016     SI opval = tmp_tmp;
3017     SET_H_GR (FLD (f_operand2), opval);
3018     written |= (1 << 7);
3019     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3020   }
3021 }
3022 {
3023   {
3024     BI opval = LTSI (tmp_tmp, 0);
3025     CPU (h_nbit) = opval;
3026     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
3027   }
3028   {
3029     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
3030     CPU (h_zbit) = opval;
3031     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
3032   }
3033 SET_H_CBIT_MOVE (0);
3034 SET_H_VBIT_MOVE (0);
3035 {
3036   {
3037     BI opval = 0;
3038     CPU (h_xbit) = opval;
3039     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3040   }
3041   {
3042     BI opval = 0;
3043     SET_H_INSN_PREFIXED_P (opval);
3044     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3045   }
3046 }
3047 }
3048 }
3049
3050   abuf->written = written;
3051 #undef FLD
3052 }
3053   NEXT (vpc);
3054
3055   CASE (sem, INSN_MOVU_M_W_M) : /* movu-m.w [${Rs}${inc}],${Rd} */
3056 {
3057   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3058   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3059 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
3060   int UNUSED written = 0;
3061   IADDR UNUSED pc = abuf->addr;
3062   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3063
3064 {
3065   SI tmp_tmp;
3066   tmp_tmp = ZEXTHISI (({   SI tmp_addr;
3067   HI tmp_tmp_mem;
3068   BI tmp_postinc;
3069   tmp_postinc = FLD (f_memmode);
3070 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3071 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
3072 ; if (NEBI (tmp_postinc, 0)) {
3073 {
3074 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3075   tmp_addr = ADDSI (tmp_addr, 2);
3076 }
3077   {
3078     SI opval = tmp_addr;
3079     SET_H_GR (FLD (f_operand1), opval);
3080     written |= (1 << 8);
3081     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3082   }
3083 }
3084 }
3085 ; tmp_tmp_mem; }));
3086 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
3087   {
3088     SI opval = tmp_tmp;
3089     SET_H_GR (FLD (f_operand1), opval);
3090     written |= (1 << 8);
3091     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3092   }
3093 } else {
3094   {
3095     SI opval = tmp_tmp;
3096     SET_H_GR (FLD (f_operand2), opval);
3097     written |= (1 << 7);
3098     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3099   }
3100 }
3101 {
3102   {
3103     BI opval = LTSI (tmp_tmp, 0);
3104     CPU (h_nbit) = opval;
3105     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
3106   }
3107   {
3108     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
3109     CPU (h_zbit) = opval;
3110     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
3111   }
3112 SET_H_CBIT_MOVE (0);
3113 SET_H_VBIT_MOVE (0);
3114 {
3115   {
3116     BI opval = 0;
3117     CPU (h_xbit) = opval;
3118     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3119   }
3120   {
3121     BI opval = 0;
3122     SET_H_INSN_PREFIXED_P (opval);
3123     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3124   }
3125 }
3126 }
3127 }
3128
3129   abuf->written = written;
3130 #undef FLD
3131 }
3132   NEXT (vpc);
3133
3134   CASE (sem, INSN_MOVE_R_SPRV10) : /* move ${Rs},${Pd} */
3135 {
3136   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3137   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3138 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
3139   int UNUSED written = 0;
3140   IADDR UNUSED pc = abuf->addr;
3141   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3142
3143 {
3144   SI tmp_tmp;
3145   SI tmp_rno;
3146   tmp_tmp = GET_H_GR (FLD (f_operand1));
3147   tmp_rno = FLD (f_operand2);
3148 if (ORIF (ORIF (EQSI (tmp_rno, 0), EQSI (tmp_rno, 1)), ORIF (EQSI (tmp_rno, 4), EQSI (tmp_rno, 8)))) {
3149 cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special register");
3150 }
3151  else {
3152   {
3153     SI opval = tmp_tmp;
3154     SET_H_SR (FLD (f_operand2), opval);
3155     written |= (1 << 2);
3156     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3157   }
3158 }
3159 {
3160   {
3161     BI opval = 0;
3162     CPU (h_xbit) = opval;
3163     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3164   }
3165   {
3166     BI opval = 0;
3167     SET_H_INSN_PREFIXED_P (opval);
3168     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3169   }
3170 }
3171 }
3172
3173   abuf->written = written;
3174 #undef FLD
3175 }
3176   NEXT (vpc);
3177
3178   CASE (sem, INSN_MOVE_SPR_RV10) : /* move ${Ps},${Rd-sfield} */
3179 {
3180   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3181   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3182 #define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
3183   int UNUSED written = 0;
3184   IADDR UNUSED pc = abuf->addr;
3185   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3186
3187 {
3188   SI tmp_grno;
3189   SI tmp_prno;
3190   SI tmp_newval;
3191   tmp_prno = FLD (f_operand2);
3192   tmp_newval = GET_H_SR (FLD (f_operand2));
3193 if (EQSI (tmp_prno, 5)) {
3194 {
3195   SI tmp_oldregval;
3196   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3197   {
3198     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
3199     SET_H_GR (FLD (f_operand1), opval);
3200     written |= (1 << 4);
3201     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3202   }
3203 }
3204 }
3205  else if (EQSI (tmp_prno, 9)) {
3206   {
3207     SI opval = tmp_newval;
3208     SET_H_GR (FLD (f_operand1), opval);
3209     written |= (1 << 4);
3210     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3211   }
3212 }
3213  else if (EQSI (tmp_prno, 10)) {
3214   {
3215     SI opval = tmp_newval;
3216     SET_H_GR (FLD (f_operand1), opval);
3217     written |= (1 << 4);
3218     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3219   }
3220 }
3221  else if (EQSI (tmp_prno, 11)) {
3222   {
3223     SI opval = tmp_newval;
3224     SET_H_GR (FLD (f_operand1), opval);
3225     written |= (1 << 4);
3226     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3227   }
3228 }
3229  else if (EQSI (tmp_prno, 12)) {
3230   {
3231     SI opval = tmp_newval;
3232     SET_H_GR (FLD (f_operand1), opval);
3233     written |= (1 << 4);
3234     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3235   }
3236 }
3237  else if (EQSI (tmp_prno, 13)) {
3238   {
3239     SI opval = tmp_newval;
3240     SET_H_GR (FLD (f_operand1), opval);
3241     written |= (1 << 4);
3242     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3243   }
3244 }
3245  else if (EQSI (tmp_prno, 0)) {
3246 {
3247   SI tmp_oldregval;
3248   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3249   {
3250     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3251     SET_H_GR (FLD (f_operand1), opval);
3252     written |= (1 << 4);
3253     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3254   }
3255 }
3256 }
3257  else if (EQSI (tmp_prno, 1)) {
3258 {
3259   SI tmp_oldregval;
3260   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3261   {
3262     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3263     SET_H_GR (FLD (f_operand1), opval);
3264     written |= (1 << 4);
3265     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3266   }
3267 }
3268 }
3269  else if (EQSI (tmp_prno, 4)) {
3270 {
3271   SI tmp_oldregval;
3272   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3273   {
3274     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
3275     SET_H_GR (FLD (f_operand1), opval);
3276     written |= (1 << 4);
3277     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3278   }
3279 }
3280 }
3281  else if (EQSI (tmp_prno, 8)) {
3282   {
3283     SI opval = tmp_newval;
3284     SET_H_GR (FLD (f_operand1), opval);
3285     written |= (1 << 4);
3286     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3287   }
3288 }
3289  else if (EQSI (tmp_prno, 7)) {
3290   {
3291     SI opval = tmp_newval;
3292     SET_H_GR (FLD (f_operand1), opval);
3293     written |= (1 << 4);
3294     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3295   }
3296 }
3297  else if (EQSI (tmp_prno, 14)) {
3298   {
3299     SI opval = tmp_newval;
3300     SET_H_GR (FLD (f_operand1), opval);
3301     written |= (1 << 4);
3302     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3303   }
3304 }
3305  else if (EQSI (tmp_prno, 15)) {
3306   {
3307     SI opval = tmp_newval;
3308     SET_H_GR (FLD (f_operand1), opval);
3309     written |= (1 << 4);
3310     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3311   }
3312 }
3313  else {
3314 cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
3315 }
3316 {
3317   {
3318     BI opval = 0;
3319     CPU (h_xbit) = opval;
3320     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3321   }
3322   {
3323     BI opval = 0;
3324     SET_H_INSN_PREFIXED_P (opval);
3325     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3326   }
3327 }
3328 }
3329
3330   abuf->written = written;
3331 #undef FLD
3332 }
3333   NEXT (vpc);
3334
3335   CASE (sem, INSN_RET_TYPE) : /* ret/reti/retb */
3336 {
3337   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3338   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3339 #define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
3340   int UNUSED written = 0;
3341   IADDR UNUSED pc = abuf->addr;
3342   SEM_BRANCH_INIT
3343   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3344
3345 {
3346   SI tmp_retaddr;
3347   tmp_retaddr = GET_H_SR (FLD (f_operand2));
3348 {
3349   {
3350     BI opval = 0;
3351     CPU (h_xbit) = opval;
3352     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3353   }
3354   {
3355     BI opval = 0;
3356     SET_H_INSN_PREFIXED_P (opval);
3357     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3358   }
3359 }
3360 {
3361   {
3362     USI opval = tmp_retaddr;
3363     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3364     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3365   }
3366 }
3367 }
3368
3369   SEM_BRANCH_FINI (vpc);
3370 #undef FLD
3371 }
3372   NEXT (vpc);
3373
3374   CASE (sem, INSN_MOVE_M_SPRV10) : /* move [${Rs}${inc}],${Pd} */
3375 {
3376   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3377   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3378 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
3379   int UNUSED written = 0;
3380   IADDR UNUSED pc = abuf->addr;
3381   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3382
3383 {
3384   SI tmp_rno;
3385   SI tmp_newval;
3386   tmp_rno = FLD (f_operand2);
3387 if (EQSI (tmp_rno, 5)) {
3388   tmp_newval = EXTHISI (({   SI tmp_addr;
3389   HI tmp_tmp_mem;
3390   BI tmp_postinc;
3391   tmp_postinc = FLD (f_memmode);
3392 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3393 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
3394 ; if (NEBI (tmp_postinc, 0)) {
3395 {
3396 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3397   tmp_addr = ADDSI (tmp_addr, 2);
3398 }
3399   {
3400     SI opval = tmp_addr;
3401     SET_H_GR (FLD (f_operand1), opval);
3402     written |= (1 << 8);
3403     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3404   }
3405 }
3406 }
3407 ; tmp_tmp_mem; }));
3408 }
3409  else if (EQSI (tmp_rno, 9)) {
3410   tmp_newval = ({   SI tmp_addr;
3411   SI tmp_tmp_mem;
3412   BI tmp_postinc;
3413   tmp_postinc = FLD (f_memmode);
3414 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3415 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3416 ; if (NEBI (tmp_postinc, 0)) {
3417 {
3418 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3419   tmp_addr = ADDSI (tmp_addr, 4);
3420 }
3421   {
3422     SI opval = tmp_addr;
3423     SET_H_GR (FLD (f_operand1), opval);
3424     written |= (1 << 8);
3425     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3426   }
3427 }
3428 }
3429 ; tmp_tmp_mem; });
3430 }
3431  else if (EQSI (tmp_rno, 10)) {
3432   tmp_newval = ({   SI tmp_addr;
3433   SI tmp_tmp_mem;
3434   BI tmp_postinc;
3435   tmp_postinc = FLD (f_memmode);
3436 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3437 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3438 ; if (NEBI (tmp_postinc, 0)) {
3439 {
3440 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3441   tmp_addr = ADDSI (tmp_addr, 4);
3442 }
3443   {
3444     SI opval = tmp_addr;
3445     SET_H_GR (FLD (f_operand1), opval);
3446     written |= (1 << 8);
3447     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3448   }
3449 }
3450 }
3451 ; tmp_tmp_mem; });
3452 }
3453  else if (EQSI (tmp_rno, 11)) {
3454   tmp_newval = ({   SI tmp_addr;
3455   SI tmp_tmp_mem;
3456   BI tmp_postinc;
3457   tmp_postinc = FLD (f_memmode);
3458 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3459 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3460 ; if (NEBI (tmp_postinc, 0)) {
3461 {
3462 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3463   tmp_addr = ADDSI (tmp_addr, 4);
3464 }
3465   {
3466     SI opval = tmp_addr;
3467     SET_H_GR (FLD (f_operand1), opval);
3468     written |= (1 << 8);
3469     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3470   }
3471 }
3472 }
3473 ; tmp_tmp_mem; });
3474 }
3475  else if (EQSI (tmp_rno, 12)) {
3476   tmp_newval = ({   SI tmp_addr;
3477   SI tmp_tmp_mem;
3478   BI tmp_postinc;
3479   tmp_postinc = FLD (f_memmode);
3480 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3481 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3482 ; if (NEBI (tmp_postinc, 0)) {
3483 {
3484 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3485   tmp_addr = ADDSI (tmp_addr, 4);
3486 }
3487   {
3488     SI opval = tmp_addr;
3489     SET_H_GR (FLD (f_operand1), opval);
3490     written |= (1 << 8);
3491     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3492   }
3493 }
3494 }
3495 ; tmp_tmp_mem; });
3496 }
3497  else if (EQSI (tmp_rno, 13)) {
3498   tmp_newval = ({   SI tmp_addr;
3499   SI tmp_tmp_mem;
3500   BI tmp_postinc;
3501   tmp_postinc = FLD (f_memmode);
3502 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3503 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3504 ; if (NEBI (tmp_postinc, 0)) {
3505 {
3506 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3507   tmp_addr = ADDSI (tmp_addr, 4);
3508 }
3509   {
3510     SI opval = tmp_addr;
3511     SET_H_GR (FLD (f_operand1), opval);
3512     written |= (1 << 8);
3513     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3514   }
3515 }
3516 }
3517 ; tmp_tmp_mem; });
3518 }
3519  else if (EQSI (tmp_rno, 7)) {
3520   tmp_newval = ({   SI tmp_addr;
3521   SI tmp_tmp_mem;
3522   BI tmp_postinc;
3523   tmp_postinc = FLD (f_memmode);
3524 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3525 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3526 ; if (NEBI (tmp_postinc, 0)) {
3527 {
3528 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3529   tmp_addr = ADDSI (tmp_addr, 4);
3530 }
3531   {
3532     SI opval = tmp_addr;
3533     SET_H_GR (FLD (f_operand1), opval);
3534     written |= (1 << 8);
3535     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3536   }
3537 }
3538 }
3539 ; tmp_tmp_mem; });
3540 }
3541  else if (EQSI (tmp_rno, 14)) {
3542   tmp_newval = ({   SI tmp_addr;
3543   SI tmp_tmp_mem;
3544   BI tmp_postinc;
3545   tmp_postinc = FLD (f_memmode);
3546 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3547 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3548 ; if (NEBI (tmp_postinc, 0)) {
3549 {
3550 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3551   tmp_addr = ADDSI (tmp_addr, 4);
3552 }
3553   {
3554     SI opval = tmp_addr;
3555     SET_H_GR (FLD (f_operand1), opval);
3556     written |= (1 << 8);
3557     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3558   }
3559 }
3560 }
3561 ; tmp_tmp_mem; });
3562 }
3563  else if (EQSI (tmp_rno, 15)) {
3564   tmp_newval = ({   SI tmp_addr;
3565   SI tmp_tmp_mem;
3566   BI tmp_postinc;
3567   tmp_postinc = FLD (f_memmode);
3568 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3569 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3570 ; if (NEBI (tmp_postinc, 0)) {
3571 {
3572 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3573   tmp_addr = ADDSI (tmp_addr, 4);
3574 }
3575   {
3576     SI opval = tmp_addr;
3577     SET_H_GR (FLD (f_operand1), opval);
3578     written |= (1 << 8);
3579     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3580   }
3581 }
3582 }
3583 ; tmp_tmp_mem; });
3584 }
3585  else {
3586 cgen_rtx_error (current_cpu, "Trying to set unimplemented special register");
3587 }
3588   {
3589     SI opval = tmp_newval;
3590     SET_H_SR (FLD (f_operand2), opval);
3591     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3592   }
3593 {
3594   {
3595     BI opval = 0;
3596     CPU (h_xbit) = opval;
3597     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3598   }
3599   {
3600     BI opval = 0;
3601     SET_H_INSN_PREFIXED_P (opval);
3602     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3603   }
3604 }
3605 }
3606
3607   abuf->written = written;
3608 #undef FLD
3609 }
3610   NEXT (vpc);
3611
3612   CASE (sem, INSN_MOVE_C_SPRV10_P5) : /* move ${sconst16},${Pd} */
3613 {
3614   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3615   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3616 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p5.f
3617   int UNUSED written = 0;
3618   IADDR UNUSED pc = abuf->addr;
3619   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3620
3621 {
3622   {
3623     SI opval = FLD (f_indir_pc__word);
3624     SET_H_SR (FLD (f_operand2), opval);
3625     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3626   }
3627 {
3628   {
3629     BI opval = 0;
3630     CPU (h_xbit) = opval;
3631     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3632   }
3633   {
3634     BI opval = 0;
3635     SET_H_INSN_PREFIXED_P (opval);
3636     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3637   }
3638 }
3639 }
3640
3641 #undef FLD
3642 }
3643   NEXT (vpc);
3644
3645   CASE (sem, INSN_MOVE_C_SPRV10_P9) : /* move ${const32},${Pd} */
3646 {
3647   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3648   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3649 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3650   int UNUSED written = 0;
3651   IADDR UNUSED pc = abuf->addr;
3652   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3653
3654 {
3655   {
3656     SI opval = FLD (f_indir_pc__dword);
3657     SET_H_SR (FLD (f_operand2), opval);
3658     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3659   }
3660 {
3661   {
3662     BI opval = 0;
3663     CPU (h_xbit) = opval;
3664     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3665   }
3666   {
3667     BI opval = 0;
3668     SET_H_INSN_PREFIXED_P (opval);
3669     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3670   }
3671 }
3672 }
3673
3674 #undef FLD
3675 }
3676   NEXT (vpc);
3677
3678   CASE (sem, INSN_MOVE_C_SPRV10_P10) : /* move ${const32},${Pd} */
3679 {
3680   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3681   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3682 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3683   int UNUSED written = 0;
3684   IADDR UNUSED pc = abuf->addr;
3685   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3686
3687 {
3688   {
3689     SI opval = FLD (f_indir_pc__dword);
3690     SET_H_SR (FLD (f_operand2), opval);
3691     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3692   }
3693 {
3694   {
3695     BI opval = 0;
3696     CPU (h_xbit) = opval;
3697     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3698   }
3699   {
3700     BI opval = 0;
3701     SET_H_INSN_PREFIXED_P (opval);
3702     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3703   }
3704 }
3705 }
3706
3707 #undef FLD
3708 }
3709   NEXT (vpc);
3710
3711   CASE (sem, INSN_MOVE_C_SPRV10_P11) : /* move ${const32},${Pd} */
3712 {
3713   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3714   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3715 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3716   int UNUSED written = 0;
3717   IADDR UNUSED pc = abuf->addr;
3718   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3719
3720 {
3721   {
3722     SI opval = FLD (f_indir_pc__dword);
3723     SET_H_SR (FLD (f_operand2), opval);
3724     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3725   }
3726 {
3727   {
3728     BI opval = 0;
3729     CPU (h_xbit) = opval;
3730     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3731   }
3732   {
3733     BI opval = 0;
3734     SET_H_INSN_PREFIXED_P (opval);
3735     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3736   }
3737 }
3738 }
3739
3740 #undef FLD
3741 }
3742   NEXT (vpc);
3743
3744   CASE (sem, INSN_MOVE_C_SPRV10_P12) : /* move ${const32},${Pd} */
3745 {
3746   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3747   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3748 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3749   int UNUSED written = 0;
3750   IADDR UNUSED pc = abuf->addr;
3751   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3752
3753 {
3754   {
3755     SI opval = FLD (f_indir_pc__dword);
3756     SET_H_SR (FLD (f_operand2), opval);
3757     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3758   }
3759 {
3760   {
3761     BI opval = 0;
3762     CPU (h_xbit) = opval;
3763     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3764   }
3765   {
3766     BI opval = 0;
3767     SET_H_INSN_PREFIXED_P (opval);
3768     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3769   }
3770 }
3771 }
3772
3773 #undef FLD
3774 }
3775   NEXT (vpc);
3776
3777   CASE (sem, INSN_MOVE_C_SPRV10_P13) : /* move ${const32},${Pd} */
3778 {
3779   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3780   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3781 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3782   int UNUSED written = 0;
3783   IADDR UNUSED pc = abuf->addr;
3784   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3785
3786 {
3787   {
3788     SI opval = FLD (f_indir_pc__dword);
3789     SET_H_SR (FLD (f_operand2), opval);
3790     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3791   }
3792 {
3793   {
3794     BI opval = 0;
3795     CPU (h_xbit) = opval;
3796     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3797   }
3798   {
3799     BI opval = 0;
3800     SET_H_INSN_PREFIXED_P (opval);
3801     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3802   }
3803 }
3804 }
3805
3806 #undef FLD
3807 }
3808   NEXT (vpc);
3809
3810   CASE (sem, INSN_MOVE_C_SPRV10_P7) : /* move ${const32},${Pd} */
3811 {
3812   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3813   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3814 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3815   int UNUSED written = 0;
3816   IADDR UNUSED pc = abuf->addr;
3817   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3818
3819 {
3820   {
3821     SI opval = FLD (f_indir_pc__dword);
3822     SET_H_SR (FLD (f_operand2), opval);
3823     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3824   }
3825 {
3826   {
3827     BI opval = 0;
3828     CPU (h_xbit) = opval;
3829     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3830   }
3831   {
3832     BI opval = 0;
3833     SET_H_INSN_PREFIXED_P (opval);
3834     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3835   }
3836 }
3837 }
3838
3839 #undef FLD
3840 }
3841   NEXT (vpc);
3842
3843   CASE (sem, INSN_MOVE_C_SPRV10_P14) : /* move ${const32},${Pd} */
3844 {
3845   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3846   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3847 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3848   int UNUSED written = 0;
3849   IADDR UNUSED pc = abuf->addr;
3850   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3851
3852 {
3853   {
3854     SI opval = FLD (f_indir_pc__dword);
3855     SET_H_SR (FLD (f_operand2), opval);
3856     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3857   }
3858 {
3859   {
3860     BI opval = 0;
3861     CPU (h_xbit) = opval;
3862     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3863   }
3864   {
3865     BI opval = 0;
3866     SET_H_INSN_PREFIXED_P (opval);
3867     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3868   }
3869 }
3870 }
3871
3872 #undef FLD
3873 }
3874   NEXT (vpc);
3875
3876   CASE (sem, INSN_MOVE_C_SPRV10_P15) : /* move ${const32},${Pd} */
3877 {
3878   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3879   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3880 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3881   int UNUSED written = 0;
3882   IADDR UNUSED pc = abuf->addr;
3883   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3884
3885 {
3886   {
3887     SI opval = FLD (f_indir_pc__dword);
3888     SET_H_SR (FLD (f_operand2), opval);
3889     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3890   }
3891 {
3892   {
3893     BI opval = 0;
3894     CPU (h_xbit) = opval;
3895     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3896   }
3897   {
3898     BI opval = 0;
3899     SET_H_INSN_PREFIXED_P (opval);
3900     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3901   }
3902 }
3903 }
3904
3905 #undef FLD
3906 }
3907   NEXT (vpc);
3908
3909   CASE (sem, INSN_MOVE_SPR_MV10) : /* move ${Ps},[${Rd-sfield}${inc}] */
3910 {
3911   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3912   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3913 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
3914   int UNUSED written = 0;
3915   IADDR UNUSED pc = abuf->addr;
3916   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3917
3918 {
3919   SI tmp_rno;
3920   tmp_rno = FLD (f_operand2);
3921 if (EQSI (tmp_rno, 5)) {
3922 {
3923   SI tmp_addr;
3924   BI tmp_postinc;
3925   tmp_postinc = FLD (f_memmode);
3926   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3927 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
3928 if (EQBI (CPU (h_pbit), 0)) {
3929 {
3930   {
3931     HI opval = GET_H_SR (FLD (f_operand2));
3932     SETMEMHI (current_cpu, pc, tmp_addr, opval);
3933     written |= (1 << 11);
3934     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
3935   }
3936   {
3937     BI opval = CPU (h_pbit);
3938     CPU (h_cbit) = opval;
3939     written |= (1 << 10);
3940     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
3941   }
3942 }
3943 } else {
3944   {
3945     BI opval = 1;
3946     CPU (h_cbit) = opval;
3947     written |= (1 << 10);
3948     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
3949   }
3950 }
3951 } else {
3952   {
3953     HI opval = GET_H_SR (FLD (f_operand2));
3954     SETMEMHI (current_cpu, pc, tmp_addr, opval);
3955     written |= (1 << 11);
3956     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
3957   }
3958 }
3959 if (NEBI (tmp_postinc, 0)) {
3960 {
3961 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3962   tmp_addr = ADDSI (tmp_addr, 2);
3963 }
3964   {
3965     SI opval = tmp_addr;
3966     SET_H_GR (FLD (f_operand1), opval);
3967     written |= (1 << 9);
3968     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3969   }
3970 }
3971 }
3972 }
3973 }
3974  else if (EQSI (tmp_rno, 9)) {
3975 {
3976   SI tmp_addr;
3977   BI tmp_postinc;
3978   tmp_postinc = FLD (f_memmode);
3979   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3980 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
3981 if (EQBI (CPU (h_pbit), 0)) {
3982 {
3983   {
3984     SI opval = GET_H_SR (FLD (f_operand2));
3985     SETMEMSI (current_cpu, pc, tmp_addr, opval);
3986     written |= (1 << 13);
3987     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
3988   }
3989   {
3990     BI opval = CPU (h_pbit);
3991     CPU (h_cbit) = opval;
3992     written |= (1 << 10);
3993     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
3994   }
3995 }
3996 } else {
3997   {
3998     BI opval = 1;
3999     CPU (h_cbit) = opval;
4000     written |= (1 << 10);
4001     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4002   }
4003 }
4004 } else {
4005   {
4006     SI opval = GET_H_SR (FLD (f_operand2));
4007     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4008     written |= (1 << 13);
4009     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4010   }
4011 }
4012 if (NEBI (tmp_postinc, 0)) {
4013 {
4014 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4015   tmp_addr = ADDSI (tmp_addr, 4);
4016 }
4017   {
4018     SI opval = tmp_addr;
4019     SET_H_GR (FLD (f_operand1), opval);
4020     written |= (1 << 9);
4021     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4022   }
4023 }
4024 }
4025 }
4026 }
4027  else if (EQSI (tmp_rno, 10)) {
4028 {
4029   SI tmp_addr;
4030   BI tmp_postinc;
4031   tmp_postinc = FLD (f_memmode);
4032   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4033 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4034 if (EQBI (CPU (h_pbit), 0)) {
4035 {
4036   {
4037     SI opval = GET_H_SR (FLD (f_operand2));
4038     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4039     written |= (1 << 13);
4040     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4041   }
4042   {
4043     BI opval = CPU (h_pbit);
4044     CPU (h_cbit) = opval;
4045     written |= (1 << 10);
4046     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4047   }
4048 }
4049 } else {
4050   {
4051     BI opval = 1;
4052     CPU (h_cbit) = opval;
4053     written |= (1 << 10);
4054     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4055   }
4056 }
4057 } else {
4058   {
4059     SI opval = GET_H_SR (FLD (f_operand2));
4060     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4061     written |= (1 << 13);
4062     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4063   }
4064 }
4065 if (NEBI (tmp_postinc, 0)) {
4066 {
4067 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4068   tmp_addr = ADDSI (tmp_addr, 4);
4069 }
4070   {
4071     SI opval = tmp_addr;
4072     SET_H_GR (FLD (f_operand1), opval);
4073     written |= (1 << 9);
4074     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4075   }
4076 }
4077 }
4078 }
4079 }
4080  else if (EQSI (tmp_rno, 11)) {
4081 {
4082   SI tmp_addr;
4083   BI tmp_postinc;
4084   tmp_postinc = FLD (f_memmode);
4085   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4086 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4087 if (EQBI (CPU (h_pbit), 0)) {
4088 {
4089   {
4090     SI opval = GET_H_SR (FLD (f_operand2));
4091     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4092     written |= (1 << 13);
4093     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4094   }
4095   {
4096     BI opval = CPU (h_pbit);
4097     CPU (h_cbit) = opval;
4098     written |= (1 << 10);
4099     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4100   }
4101 }
4102 } else {
4103   {
4104     BI opval = 1;
4105     CPU (h_cbit) = opval;
4106     written |= (1 << 10);
4107     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4108   }
4109 }
4110 } else {
4111   {
4112     SI opval = GET_H_SR (FLD (f_operand2));
4113     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4114     written |= (1 << 13);
4115     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4116   }
4117 }
4118 if (NEBI (tmp_postinc, 0)) {
4119 {
4120 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4121   tmp_addr = ADDSI (tmp_addr, 4);
4122 }
4123   {
4124     SI opval = tmp_addr;
4125     SET_H_GR (FLD (f_operand1), opval);
4126     written |= (1 << 9);
4127     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4128   }
4129 }
4130 }
4131 }
4132 }
4133  else if (EQSI (tmp_rno, 12)) {
4134 {
4135   SI tmp_addr;
4136   BI tmp_postinc;
4137   tmp_postinc = FLD (f_memmode);
4138   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4139 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4140 if (EQBI (CPU (h_pbit), 0)) {
4141 {
4142   {
4143     SI opval = GET_H_SR (FLD (f_operand2));
4144     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4145     written |= (1 << 13);
4146     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4147   }
4148   {
4149     BI opval = CPU (h_pbit);
4150     CPU (h_cbit) = opval;
4151     written |= (1 << 10);
4152     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4153   }
4154 }
4155 } else {
4156   {
4157     BI opval = 1;
4158     CPU (h_cbit) = opval;
4159     written |= (1 << 10);
4160     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4161   }
4162 }
4163 } else {
4164   {
4165     SI opval = GET_H_SR (FLD (f_operand2));
4166     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4167     written |= (1 << 13);
4168     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4169   }
4170 }
4171 if (NEBI (tmp_postinc, 0)) {
4172 {
4173 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4174   tmp_addr = ADDSI (tmp_addr, 4);
4175 }
4176   {
4177     SI opval = tmp_addr;
4178     SET_H_GR (FLD (f_operand1), opval);
4179     written |= (1 << 9);
4180     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4181   }
4182 }
4183 }
4184 }
4185 }
4186  else if (EQSI (tmp_rno, 13)) {
4187 {
4188   SI tmp_addr;
4189   BI tmp_postinc;
4190   tmp_postinc = FLD (f_memmode);
4191   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4192 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4193 if (EQBI (CPU (h_pbit), 0)) {
4194 {
4195   {
4196     SI opval = GET_H_SR (FLD (f_operand2));
4197     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4198     written |= (1 << 13);
4199     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4200   }
4201   {
4202     BI opval = CPU (h_pbit);
4203     CPU (h_cbit) = opval;
4204     written |= (1 << 10);
4205     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4206   }
4207 }
4208 } else {
4209   {
4210     BI opval = 1;
4211     CPU (h_cbit) = opval;
4212     written |= (1 << 10);
4213     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4214   }
4215 }
4216 } else {
4217   {
4218     SI opval = GET_H_SR (FLD (f_operand2));
4219     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4220     written |= (1 << 13);
4221     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4222   }
4223 }
4224 if (NEBI (tmp_postinc, 0)) {
4225 {
4226 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4227   tmp_addr = ADDSI (tmp_addr, 4);
4228 }
4229   {
4230     SI opval = tmp_addr;
4231     SET_H_GR (FLD (f_operand1), opval);
4232     written |= (1 << 9);
4233     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4234   }
4235 }
4236 }
4237 }
4238 }
4239  else if (EQSI (tmp_rno, 0)) {
4240 {
4241   SI tmp_addr;
4242   BI tmp_postinc;
4243   tmp_postinc = FLD (f_memmode);
4244   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4245 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4246 if (EQBI (CPU (h_pbit), 0)) {
4247 {
4248   {
4249     QI opval = GET_H_SR (FLD (f_operand2));
4250     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4251     written |= (1 << 12);
4252     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4253   }
4254   {
4255     BI opval = CPU (h_pbit);
4256     CPU (h_cbit) = opval;
4257     written |= (1 << 10);
4258     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4259   }
4260 }
4261 } else {
4262   {
4263     BI opval = 1;
4264     CPU (h_cbit) = opval;
4265     written |= (1 << 10);
4266     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4267   }
4268 }
4269 } else {
4270   {
4271     QI opval = GET_H_SR (FLD (f_operand2));
4272     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4273     written |= (1 << 12);
4274     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4275   }
4276 }
4277 if (NEBI (tmp_postinc, 0)) {
4278 {
4279 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4280   tmp_addr = ADDSI (tmp_addr, 1);
4281 }
4282   {
4283     SI opval = tmp_addr;
4284     SET_H_GR (FLD (f_operand1), opval);
4285     written |= (1 << 9);
4286     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4287   }
4288 }
4289 }
4290 }
4291 }
4292  else if (EQSI (tmp_rno, 1)) {
4293 {
4294   SI tmp_addr;
4295   BI tmp_postinc;
4296   tmp_postinc = FLD (f_memmode);
4297   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4298 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4299 if (EQBI (CPU (h_pbit), 0)) {
4300 {
4301   {
4302     QI opval = GET_H_SR (FLD (f_operand2));
4303     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4304     written |= (1 << 12);
4305     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4306   }
4307   {
4308     BI opval = CPU (h_pbit);
4309     CPU (h_cbit) = opval;
4310     written |= (1 << 10);
4311     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4312   }
4313 }
4314 } else {
4315   {
4316     BI opval = 1;
4317     CPU (h_cbit) = opval;
4318     written |= (1 << 10);
4319     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4320   }
4321 }
4322 } else {
4323   {
4324     QI opval = GET_H_SR (FLD (f_operand2));
4325     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4326     written |= (1 << 12);
4327     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4328   }
4329 }
4330 if (NEBI (tmp_postinc, 0)) {
4331 {
4332 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4333   tmp_addr = ADDSI (tmp_addr, 1);
4334 }
4335   {
4336     SI opval = tmp_addr;
4337     SET_H_GR (FLD (f_operand1), opval);
4338     written |= (1 << 9);
4339     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4340   }
4341 }
4342 }
4343 }
4344 }
4345  else if (EQSI (tmp_rno, 4)) {
4346 {
4347   SI tmp_addr;
4348   BI tmp_postinc;
4349   tmp_postinc = FLD (f_memmode);
4350   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4351 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4352 if (EQBI (CPU (h_pbit), 0)) {
4353 {
4354   {
4355     HI opval = GET_H_SR (FLD (f_operand2));
4356     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4357     written |= (1 << 11);
4358     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4359   }
4360   {
4361     BI opval = CPU (h_pbit);
4362     CPU (h_cbit) = opval;
4363     written |= (1 << 10);
4364     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4365   }
4366 }
4367 } else {
4368   {
4369     BI opval = 1;
4370     CPU (h_cbit) = opval;
4371     written |= (1 << 10);
4372     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4373   }
4374 }
4375 } else {
4376   {
4377     HI opval = GET_H_SR (FLD (f_operand2));
4378     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4379     written |= (1 << 11);
4380     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4381   }
4382 }
4383 if (NEBI (tmp_postinc, 0)) {
4384 {
4385 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4386   tmp_addr = ADDSI (tmp_addr, 2);
4387 }
4388   {
4389     SI opval = tmp_addr;
4390     SET_H_GR (FLD (f_operand1), opval);
4391     written |= (1 << 9);
4392     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4393   }
4394 }
4395 }
4396 }
4397 }
4398  else if (EQSI (tmp_rno, 8)) {
4399 {
4400   SI tmp_addr;
4401   BI tmp_postinc;
4402   tmp_postinc = FLD (f_memmode);
4403   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4404 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4405 if (EQBI (CPU (h_pbit), 0)) {
4406 {
4407   {
4408     SI opval = GET_H_SR (FLD (f_operand2));
4409     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4410     written |= (1 << 13);
4411     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4412   }
4413   {
4414     BI opval = CPU (h_pbit);
4415     CPU (h_cbit) = opval;
4416     written |= (1 << 10);
4417     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4418   }
4419 }
4420 } else {
4421   {
4422     BI opval = 1;
4423     CPU (h_cbit) = opval;
4424     written |= (1 << 10);
4425     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4426   }
4427 }
4428 } else {
4429   {
4430     SI opval = GET_H_SR (FLD (f_operand2));
4431     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4432     written |= (1 << 13);
4433     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4434   }
4435 }
4436 if (NEBI (tmp_postinc, 0)) {
4437 {
4438 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4439   tmp_addr = ADDSI (tmp_addr, 4);
4440 }
4441   {
4442     SI opval = tmp_addr;
4443     SET_H_GR (FLD (f_operand1), opval);
4444     written |= (1 << 9);
4445     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4446   }
4447 }
4448 }
4449 }
4450 }
4451  else if (EQSI (tmp_rno, 7)) {
4452 {
4453   SI tmp_addr;
4454   BI tmp_postinc;
4455   tmp_postinc = FLD (f_memmode);
4456   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4457 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4458 if (EQBI (CPU (h_pbit), 0)) {
4459 {
4460   {
4461     SI opval = GET_H_SR (FLD (f_operand2));
4462     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4463     written |= (1 << 13);
4464     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4465   }
4466   {
4467     BI opval = CPU (h_pbit);
4468     CPU (h_cbit) = opval;
4469     written |= (1 << 10);
4470     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4471   }
4472 }
4473 } else {
4474   {
4475     BI opval = 1;
4476     CPU (h_cbit) = opval;
4477     written |= (1 << 10);
4478     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4479   }
4480 }
4481 } else {
4482   {
4483     SI opval = GET_H_SR (FLD (f_operand2));
4484     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4485     written |= (1 << 13);
4486     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4487   }
4488 }
4489 if (NEBI (tmp_postinc, 0)) {
4490 {
4491 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4492   tmp_addr = ADDSI (tmp_addr, 4);
4493 }
4494   {
4495     SI opval = tmp_addr;
4496     SET_H_GR (FLD (f_operand1), opval);
4497     written |= (1 << 9);
4498     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4499   }
4500 }
4501 }
4502 }
4503 }
4504  else if (EQSI (tmp_rno, 14)) {
4505 {
4506   SI tmp_addr;
4507   BI tmp_postinc;
4508   tmp_postinc = FLD (f_memmode);
4509   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4510 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4511 if (EQBI (CPU (h_pbit), 0)) {
4512 {
4513   {
4514     SI opval = GET_H_SR (FLD (f_operand2));
4515     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4516     written |= (1 << 13);
4517     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4518   }
4519   {
4520     BI opval = CPU (h_pbit);
4521     CPU (h_cbit) = opval;
4522     written |= (1 << 10);
4523     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4524   }
4525 }
4526 } else {
4527   {
4528     BI opval = 1;
4529     CPU (h_cbit) = opval;
4530     written |= (1 << 10);
4531     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4532   }
4533 }
4534 } else {
4535   {
4536     SI opval = GET_H_SR (FLD (f_operand2));
4537     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4538     written |= (1 << 13);
4539     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4540   }
4541 }
4542 if (NEBI (tmp_postinc, 0)) {
4543 {
4544 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4545   tmp_addr = ADDSI (tmp_addr, 4);
4546 }
4547   {
4548     SI opval = tmp_addr;
4549     SET_H_GR (FLD (f_operand1), opval);
4550     written |= (1 << 9);
4551     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4552   }
4553 }
4554 }
4555 }
4556 }
4557  else if (EQSI (tmp_rno, 15)) {
4558 {
4559   SI tmp_addr;
4560   BI tmp_postinc;
4561   tmp_postinc = FLD (f_memmode);
4562   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4563 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4564 if (EQBI (CPU (h_pbit), 0)) {
4565 {
4566   {
4567     SI opval = GET_H_SR (FLD (f_operand2));
4568     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4569     written |= (1 << 13);
4570     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4571   }
4572   {
4573     BI opval = CPU (h_pbit);
4574     CPU (h_cbit) = opval;
4575     written |= (1 << 10);
4576     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4577   }
4578 }
4579 } else {
4580   {
4581     BI opval = 1;
4582     CPU (h_cbit) = opval;
4583     written |= (1 << 10);
4584     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4585   }
4586 }
4587 } else {
4588   {
4589     SI opval = GET_H_SR (FLD (f_operand2));
4590     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4591     written |= (1 << 13);
4592     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4593   }
4594 }
4595 if (NEBI (tmp_postinc, 0)) {
4596 {
4597 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4598   tmp_addr = ADDSI (tmp_addr, 4);
4599 }
4600   {
4601     SI opval = tmp_addr;
4602     SET_H_GR (FLD (f_operand1), opval);
4603     written |= (1 << 9);
4604     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4605   }
4606 }
4607 }
4608 }
4609 }
4610  else {
4611 cgen_rtx_error (current_cpu, "write from unimplemented special register");
4612 }
4613 {
4614   {
4615     BI opval = 0;
4616     CPU (h_xbit) = opval;
4617     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4618   }
4619   {
4620     BI opval = 0;
4621     SET_H_INSN_PREFIXED_P (opval);
4622     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4623   }
4624 }
4625 }
4626
4627   abuf->written = written;
4628 #undef FLD
4629 }
4630   NEXT (vpc);
4631
4632   CASE (sem, INSN_SBFS) : /* sbfs [${Rd-sfield}${inc}] */
4633 {
4634   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4635   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4636 #define FLD(f) abuf->fields.fmt_empty.f
4637   int UNUSED written = 0;
4638   IADDR UNUSED pc = abuf->addr;
4639   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4640
4641 cgen_rtx_error (current_cpu, "SBFS isn't implemented");
4642
4643 #undef FLD
4644 }
4645   NEXT (vpc);
4646
4647   CASE (sem, INSN_MOVEM_R_M) : /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
4648 {
4649   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4650   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4651 #define FLD(f) abuf->fields.sfmt_movem_r_m.f
4652   int UNUSED written = 0;
4653   IADDR UNUSED pc = abuf->addr;
4654   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4655
4656 {
4657   SI tmp_addr;
4658   BI tmp_postinc;
4659   tmp_postinc = FLD (f_memmode);
4660 {
4661   SI tmp_dummy;
4662   tmp_dummy = GET_H_GR (FLD (f_operand2));
4663 }
4664   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4665 {
4666 if (GESI (FLD (f_operand2), 15)) {
4667 {
4668   SI tmp_tmp;
4669   tmp_tmp = GET_H_GR (((UINT) 15));
4670   {
4671     SI opval = tmp_tmp;
4672     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4673     written |= (1 << 23);
4674     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4675   }
4676   tmp_addr = ADDSI (tmp_addr, 4);
4677 }
4678 }
4679 if (GESI (FLD (f_operand2), 14)) {
4680 {
4681   SI tmp_tmp;
4682   tmp_tmp = GET_H_GR (((UINT) 14));
4683   {
4684     SI opval = tmp_tmp;
4685     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4686     written |= (1 << 23);
4687     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4688   }
4689   tmp_addr = ADDSI (tmp_addr, 4);
4690 }
4691 }
4692 if (GESI (FLD (f_operand2), 13)) {
4693 {
4694   SI tmp_tmp;
4695   tmp_tmp = GET_H_GR (((UINT) 13));
4696   {
4697     SI opval = tmp_tmp;
4698     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4699     written |= (1 << 23);
4700     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4701   }
4702   tmp_addr = ADDSI (tmp_addr, 4);
4703 }
4704 }
4705 if (GESI (FLD (f_operand2), 12)) {
4706 {
4707   SI tmp_tmp;
4708   tmp_tmp = GET_H_GR (((UINT) 12));
4709   {
4710     SI opval = tmp_tmp;
4711     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4712     written |= (1 << 23);
4713     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4714   }
4715   tmp_addr = ADDSI (tmp_addr, 4);
4716 }
4717 }
4718 if (GESI (FLD (f_operand2), 11)) {
4719 {
4720   SI tmp_tmp;
4721   tmp_tmp = GET_H_GR (((UINT) 11));
4722   {
4723     SI opval = tmp_tmp;
4724     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4725     written |= (1 << 23);
4726     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4727   }
4728   tmp_addr = ADDSI (tmp_addr, 4);
4729 }
4730 }
4731 if (GESI (FLD (f_operand2), 10)) {
4732 {
4733   SI tmp_tmp;
4734   tmp_tmp = GET_H_GR (((UINT) 10));
4735   {
4736     SI opval = tmp_tmp;
4737     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4738     written |= (1 << 23);
4739     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4740   }
4741   tmp_addr = ADDSI (tmp_addr, 4);
4742 }
4743 }
4744 if (GESI (FLD (f_operand2), 9)) {
4745 {
4746   SI tmp_tmp;
4747   tmp_tmp = GET_H_GR (((UINT) 9));
4748   {
4749     SI opval = tmp_tmp;
4750     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4751     written |= (1 << 23);
4752     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4753   }
4754   tmp_addr = ADDSI (tmp_addr, 4);
4755 }
4756 }
4757 if (GESI (FLD (f_operand2), 8)) {
4758 {
4759   SI tmp_tmp;
4760   tmp_tmp = GET_H_GR (((UINT) 8));
4761   {
4762     SI opval = tmp_tmp;
4763     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4764     written |= (1 << 23);
4765     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4766   }
4767   tmp_addr = ADDSI (tmp_addr, 4);
4768 }
4769 }
4770 if (GESI (FLD (f_operand2), 7)) {
4771 {
4772   SI tmp_tmp;
4773   tmp_tmp = GET_H_GR (((UINT) 7));
4774   {
4775     SI opval = tmp_tmp;
4776     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4777     written |= (1 << 23);
4778     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4779   }
4780   tmp_addr = ADDSI (tmp_addr, 4);
4781 }
4782 }
4783 if (GESI (FLD (f_operand2), 6)) {
4784 {
4785   SI tmp_tmp;
4786   tmp_tmp = GET_H_GR (((UINT) 6));
4787   {
4788     SI opval = tmp_tmp;
4789     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4790     written |= (1 << 23);
4791     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4792   }
4793   tmp_addr = ADDSI (tmp_addr, 4);
4794 }
4795 }
4796 if (GESI (FLD (f_operand2), 5)) {
4797 {
4798   SI tmp_tmp;
4799   tmp_tmp = GET_H_GR (((UINT) 5));
4800   {
4801     SI opval = tmp_tmp;
4802     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4803     written |= (1 << 23);
4804     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4805   }
4806   tmp_addr = ADDSI (tmp_addr, 4);
4807 }
4808 }
4809 if (GESI (FLD (f_operand2), 4)) {
4810 {
4811   SI tmp_tmp;
4812   tmp_tmp = GET_H_GR (((UINT) 4));
4813   {
4814     SI opval = tmp_tmp;
4815     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4816     written |= (1 << 23);
4817     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4818   }
4819   tmp_addr = ADDSI (tmp_addr, 4);
4820 }
4821 }
4822 if (GESI (FLD (f_operand2), 3)) {
4823 {
4824   SI tmp_tmp;
4825   tmp_tmp = GET_H_GR (((UINT) 3));
4826   {
4827     SI opval = tmp_tmp;
4828     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4829     written |= (1 << 23);
4830     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4831   }
4832   tmp_addr = ADDSI (tmp_addr, 4);
4833 }
4834 }
4835 if (GESI (FLD (f_operand2), 2)) {
4836 {
4837   SI tmp_tmp;
4838   tmp_tmp = GET_H_GR (((UINT) 2));
4839   {
4840     SI opval = tmp_tmp;
4841     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4842     written |= (1 << 23);
4843     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4844   }
4845   tmp_addr = ADDSI (tmp_addr, 4);
4846 }
4847 }
4848 if (GESI (FLD (f_operand2), 1)) {
4849 {
4850   SI tmp_tmp;
4851   tmp_tmp = GET_H_GR (((UINT) 1));
4852   {
4853     SI opval = tmp_tmp;
4854     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4855     written |= (1 << 23);
4856     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4857   }
4858   tmp_addr = ADDSI (tmp_addr, 4);
4859 }
4860 }
4861 if (GESI (FLD (f_operand2), 0)) {
4862 {
4863   SI tmp_tmp;
4864   tmp_tmp = GET_H_GR (((UINT) 0));
4865   {
4866     SI opval = tmp_tmp;
4867     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4868     written |= (1 << 23);
4869     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4870   }
4871   tmp_addr = ADDSI (tmp_addr, 4);
4872 }
4873 }
4874 }
4875 if (NEBI (tmp_postinc, 0)) {
4876   {
4877     SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
4878     SET_H_GR (FLD (f_operand1), opval);
4879     written |= (1 << 22);
4880     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4881   }
4882 }
4883 {
4884   {
4885     BI opval = 0;
4886     CPU (h_xbit) = opval;
4887     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4888   }
4889   {
4890     BI opval = 0;
4891     SET_H_INSN_PREFIXED_P (opval);
4892     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4893   }
4894 }
4895 }
4896
4897   abuf->written = written;
4898 #undef FLD
4899 }
4900   NEXT (vpc);
4901
4902   CASE (sem, INSN_MOVEM_M_R) : /* movem [${Rs}${inc}],${Rd} */
4903 {
4904   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4905   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4906 #define FLD(f) abuf->fields.sfmt_movem_m_r.f
4907   int UNUSED written = 0;
4908   IADDR UNUSED pc = abuf->addr;
4909   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4910
4911 {
4912   SI tmp_addr;
4913   BI tmp_postinc;
4914   tmp_postinc = FLD (f_memmode);
4915   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4916 {
4917   SI tmp_dummy;
4918   tmp_dummy = GET_H_GR (FLD (f_operand2));
4919 }
4920 {
4921 if (GESI (FLD (f_operand2), 14)) {
4922 {
4923   SI tmp_tmp;
4924   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4925   {
4926     SI opval = tmp_tmp;
4927     SET_H_GR (((UINT) 14), opval);
4928     written |= (1 << 14);
4929     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4930   }
4931   tmp_addr = ADDSI (tmp_addr, 4);
4932 }
4933 }
4934 if (GESI (FLD (f_operand2), 13)) {
4935 {
4936   SI tmp_tmp;
4937   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4938   {
4939     SI opval = tmp_tmp;
4940     SET_H_GR (((UINT) 13), opval);
4941     written |= (1 << 13);
4942     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4943   }
4944   tmp_addr = ADDSI (tmp_addr, 4);
4945 }
4946 }
4947 if (GESI (FLD (f_operand2), 12)) {
4948 {
4949   SI tmp_tmp;
4950   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4951   {
4952     SI opval = tmp_tmp;
4953     SET_H_GR (((UINT) 12), opval);
4954     written |= (1 << 12);
4955     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4956   }
4957   tmp_addr = ADDSI (tmp_addr, 4);
4958 }
4959 }
4960 if (GESI (FLD (f_operand2), 11)) {
4961 {
4962   SI tmp_tmp;
4963   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4964   {
4965     SI opval = tmp_tmp;
4966     SET_H_GR (((UINT) 11), opval);
4967     written |= (1 << 11);
4968     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4969   }
4970   tmp_addr = ADDSI (tmp_addr, 4);
4971 }
4972 }
4973 if (GESI (FLD (f_operand2), 10)) {
4974 {
4975   SI tmp_tmp;
4976   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4977   {
4978     SI opval = tmp_tmp;
4979     SET_H_GR (((UINT) 10), opval);
4980     written |= (1 << 10);
4981     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4982   }
4983   tmp_addr = ADDSI (tmp_addr, 4);
4984 }
4985 }
4986 if (GESI (FLD (f_operand2), 9)) {
4987 {
4988   SI tmp_tmp;
4989   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4990   {
4991     SI opval = tmp_tmp;
4992     SET_H_GR (((UINT) 9), opval);
4993     written |= (1 << 22);
4994     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4995   }
4996   tmp_addr = ADDSI (tmp_addr, 4);
4997 }
4998 }
4999 if (GESI (FLD (f_operand2), 8)) {
5000 {
5001   SI tmp_tmp;
5002   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5003   {
5004     SI opval = tmp_tmp;
5005     SET_H_GR (((UINT) 8), opval);
5006     written |= (1 << 21);
5007     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5008   }
5009   tmp_addr = ADDSI (tmp_addr, 4);
5010 }
5011 }
5012 if (GESI (FLD (f_operand2), 7)) {
5013 {
5014   SI tmp_tmp;
5015   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5016   {
5017     SI opval = tmp_tmp;
5018     SET_H_GR (((UINT) 7), opval);
5019     written |= (1 << 20);
5020     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5021   }
5022   tmp_addr = ADDSI (tmp_addr, 4);
5023 }
5024 }
5025 if (GESI (FLD (f_operand2), 6)) {
5026 {
5027   SI tmp_tmp;
5028   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5029   {
5030     SI opval = tmp_tmp;
5031     SET_H_GR (((UINT) 6), opval);
5032     written |= (1 << 19);
5033     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5034   }
5035   tmp_addr = ADDSI (tmp_addr, 4);
5036 }
5037 }
5038 if (GESI (FLD (f_operand2), 5)) {
5039 {
5040   SI tmp_tmp;
5041   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5042   {
5043     SI opval = tmp_tmp;
5044     SET_H_GR (((UINT) 5), opval);
5045     written |= (1 << 18);
5046     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5047   }
5048   tmp_addr = ADDSI (tmp_addr, 4);
5049 }
5050 }
5051 if (GESI (FLD (f_operand2), 4)) {
5052 {
5053   SI tmp_tmp;
5054   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5055   {
5056     SI opval = tmp_tmp;
5057     SET_H_GR (((UINT) 4), opval);
5058     written |= (1 << 17);
5059     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5060   }
5061   tmp_addr = ADDSI (tmp_addr, 4);
5062 }
5063 }
5064 if (GESI (FLD (f_operand2), 3)) {
5065 {
5066   SI tmp_tmp;
5067   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5068   {
5069     SI opval = tmp_tmp;
5070     SET_H_GR (((UINT) 3), opval);
5071     written |= (1 << 16);
5072     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5073   }
5074   tmp_addr = ADDSI (tmp_addr, 4);
5075 }
5076 }
5077 if (GESI (FLD (f_operand2), 2)) {
5078 {
5079   SI tmp_tmp;
5080   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5081   {
5082     SI opval = tmp_tmp;
5083     SET_H_GR (((UINT) 2), opval);
5084     written |= (1 << 15);
5085     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5086   }
5087   tmp_addr = ADDSI (tmp_addr, 4);
5088 }
5089 }
5090 if (GESI (FLD (f_operand2), 1)) {
5091 {
5092   SI tmp_tmp;
5093   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5094   {
5095     SI opval = tmp_tmp;
5096     SET_H_GR (((UINT) 1), opval);
5097     written |= (1 << 9);
5098     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5099   }
5100   tmp_addr = ADDSI (tmp_addr, 4);
5101 }
5102 }
5103 if (GESI (FLD (f_operand2), 0)) {
5104 {
5105   SI tmp_tmp;
5106   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5107   {
5108     SI opval = tmp_tmp;
5109     SET_H_GR (((UINT) 0), opval);
5110     written |= (1 << 8);
5111     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5112   }
5113   tmp_addr = ADDSI (tmp_addr, 4);
5114 }
5115 }
5116 }
5117 if (NEBI (tmp_postinc, 0)) {
5118   {
5119     SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
5120     SET_H_GR (FLD (f_operand1), opval);
5121     written |= (1 << 7);
5122     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5123   }
5124 }
5125 {
5126   {
5127     BI opval = 0;
5128     CPU (h_xbit) = opval;
5129     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5130   }
5131   {
5132     BI opval = 0;
5133     SET_H_INSN_PREFIXED_P (opval);
5134     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5135   }
5136 }
5137 }
5138
5139   abuf->written = written;
5140 #undef FLD
5141 }
5142   NEXT (vpc);
5143
5144   CASE (sem, INSN_MOVEM_M_PC) : /* movem [${Rs}${inc}],${Rd} */
5145 {
5146   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5147   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5148 #define FLD(f) abuf->fields.sfmt_movem_m_r.f
5149   int UNUSED written = 0;
5150   IADDR UNUSED pc = abuf->addr;
5151   SEM_BRANCH_INIT
5152   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5153
5154 {
5155   SI tmp_addr;
5156   BI tmp_postinc;
5157   tmp_postinc = FLD (f_memmode);
5158   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5159 {
5160   {
5161     USI opval = GETMEMSI (current_cpu, pc, tmp_addr);
5162     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
5163     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
5164   }
5165   tmp_addr = ADDSI (tmp_addr, 4);
5166 {
5167   SI tmp_tmp;
5168   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5169   {
5170     SI opval = tmp_tmp;
5171     SET_H_GR (((UINT) 14), opval);
5172     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5173   }
5174   tmp_addr = ADDSI (tmp_addr, 4);
5175 }
5176 {
5177   SI tmp_tmp;
5178   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5179   {
5180     SI opval = tmp_tmp;
5181     SET_H_GR (((UINT) 13), opval);
5182     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5183   }
5184   tmp_addr = ADDSI (tmp_addr, 4);
5185 }
5186 {
5187   SI tmp_tmp;
5188   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5189   {
5190     SI opval = tmp_tmp;
5191     SET_H_GR (((UINT) 12), opval);
5192     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5193   }
5194   tmp_addr = ADDSI (tmp_addr, 4);
5195 }
5196 {
5197   SI tmp_tmp;
5198   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5199   {
5200     SI opval = tmp_tmp;
5201     SET_H_GR (((UINT) 11), opval);
5202     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5203   }
5204   tmp_addr = ADDSI (tmp_addr, 4);
5205 }
5206 {
5207   SI tmp_tmp;
5208   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5209   {
5210     SI opval = tmp_tmp;
5211     SET_H_GR (((UINT) 10), opval);
5212     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5213   }
5214   tmp_addr = ADDSI (tmp_addr, 4);
5215 }
5216 {
5217   SI tmp_tmp;
5218   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5219   {
5220     SI opval = tmp_tmp;
5221     SET_H_GR (((UINT) 9), opval);
5222     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5223   }
5224   tmp_addr = ADDSI (tmp_addr, 4);
5225 }
5226 {
5227   SI tmp_tmp;
5228   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5229   {
5230     SI opval = tmp_tmp;
5231     SET_H_GR (((UINT) 8), opval);
5232     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5233   }
5234   tmp_addr = ADDSI (tmp_addr, 4);
5235 }
5236 {
5237   SI tmp_tmp;
5238   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5239   {
5240     SI opval = tmp_tmp;
5241     SET_H_GR (((UINT) 7), opval);
5242     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5243   }
5244   tmp_addr = ADDSI (tmp_addr, 4);
5245 }
5246 {
5247   SI tmp_tmp;
5248   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5249   {
5250     SI opval = tmp_tmp;
5251     SET_H_GR (((UINT) 6), opval);
5252     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5253   }
5254   tmp_addr = ADDSI (tmp_addr, 4);
5255 }
5256 {
5257   SI tmp_tmp;
5258   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5259   {
5260     SI opval = tmp_tmp;
5261     SET_H_GR (((UINT) 5), opval);
5262     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5263   }
5264   tmp_addr = ADDSI (tmp_addr, 4);
5265 }
5266 {
5267   SI tmp_tmp;
5268   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5269   {
5270     SI opval = tmp_tmp;
5271     SET_H_GR (((UINT) 4), opval);
5272     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5273   }
5274   tmp_addr = ADDSI (tmp_addr, 4);
5275 }
5276 {
5277   SI tmp_tmp;
5278   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5279   {
5280     SI opval = tmp_tmp;
5281     SET_H_GR (((UINT) 3), opval);
5282     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5283   }
5284   tmp_addr = ADDSI (tmp_addr, 4);
5285 }
5286 {
5287   SI tmp_tmp;
5288   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5289   {
5290     SI opval = tmp_tmp;
5291     SET_H_GR (((UINT) 2), opval);
5292     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5293   }
5294   tmp_addr = ADDSI (tmp_addr, 4);
5295 }
5296 {
5297   SI tmp_tmp;
5298   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5299   {
5300     SI opval = tmp_tmp;
5301     SET_H_GR (((UINT) 1), opval);
5302     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5303   }
5304   tmp_addr = ADDSI (tmp_addr, 4);
5305 }
5306 {
5307   SI tmp_tmp;
5308   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5309   {
5310     SI opval = tmp_tmp;
5311     SET_H_GR (((UINT) 0), opval);
5312     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5313   }
5314   tmp_addr = ADDSI (tmp_addr, 4);
5315 }
5316 }
5317 if (NEBI (tmp_postinc, 0)) {
5318   {
5319     SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
5320     SET_H_GR (FLD (f_operand1), opval);
5321     written |= (1 << 5);
5322     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5323   }
5324 }
5325 {
5326   {
5327     BI opval = 0;
5328     CPU (h_xbit) = opval;
5329     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5330   }
5331   {
5332     BI opval = 0;
5333     SET_H_INSN_PREFIXED_P (opval);
5334     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5335   }
5336 }
5337 }
5338
5339   abuf->written = written;
5340   SEM_BRANCH_FINI (vpc);
5341 #undef FLD
5342 }
5343   NEXT (vpc);
5344
5345   CASE (sem, INSN_ADD_B_R) : /* add.b $Rs,$Rd */
5346 {
5347   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5348   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5349 #define FLD(f) abuf->fields.sfmt_add_b_r.f
5350   int UNUSED written = 0;
5351   IADDR UNUSED pc = abuf->addr;
5352   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5353
5354 {
5355   QI tmp_tmpopd;
5356   QI tmp_tmpops;
5357   BI tmp_carry;
5358   QI tmp_newval;
5359   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5360   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5361   tmp_carry = CPU (h_cbit);
5362   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5363 {
5364   SI tmp_oldregval;
5365   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5366   {
5367     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5368     SET_H_GR (FLD (f_operand2), opval);
5369     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5370   }
5371 }
5372 {
5373   {
5374     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5375     CPU (h_cbit) = opval;
5376     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5377   }
5378   {
5379     BI opval = LTQI (tmp_newval, 0);
5380     CPU (h_nbit) = opval;
5381     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5382   }
5383   {
5384     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5385     CPU (h_zbit) = opval;
5386     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5387   }
5388   {
5389     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5390     CPU (h_vbit) = opval;
5391     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5392   }
5393 {
5394   {
5395     BI opval = 0;
5396     CPU (h_xbit) = opval;
5397     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5398   }
5399   {
5400     BI opval = 0;
5401     SET_H_INSN_PREFIXED_P (opval);
5402     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5403   }
5404 }
5405 }
5406 }
5407
5408 #undef FLD
5409 }
5410   NEXT (vpc);
5411
5412   CASE (sem, INSN_ADD_W_R) : /* add.w $Rs,$Rd */
5413 {
5414   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5415   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5416 #define FLD(f) abuf->fields.sfmt_add_b_r.f
5417   int UNUSED written = 0;
5418   IADDR UNUSED pc = abuf->addr;
5419   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5420
5421 {
5422   HI tmp_tmpopd;
5423   HI tmp_tmpops;
5424   BI tmp_carry;
5425   HI tmp_newval;
5426   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5427   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5428   tmp_carry = CPU (h_cbit);
5429   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5430 {
5431   SI tmp_oldregval;
5432   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5433   {
5434     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5435     SET_H_GR (FLD (f_operand2), opval);
5436     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5437   }
5438 }
5439 {
5440   {
5441     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5442     CPU (h_cbit) = opval;
5443     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5444   }
5445   {
5446     BI opval = LTHI (tmp_newval, 0);
5447     CPU (h_nbit) = opval;
5448     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5449   }
5450   {
5451     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5452     CPU (h_zbit) = opval;
5453     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5454   }
5455   {
5456     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5457     CPU (h_vbit) = opval;
5458     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5459   }
5460 {
5461   {
5462     BI opval = 0;
5463     CPU (h_xbit) = opval;
5464     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5465   }
5466   {
5467     BI opval = 0;
5468     SET_H_INSN_PREFIXED_P (opval);
5469     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5470   }
5471 }
5472 }
5473 }
5474
5475 #undef FLD
5476 }
5477   NEXT (vpc);
5478
5479   CASE (sem, INSN_ADD_D_R) : /* add.d $Rs,$Rd */
5480 {
5481   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5482   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5483 #define FLD(f) abuf->fields.sfmt_add_b_r.f
5484   int UNUSED written = 0;
5485   IADDR UNUSED pc = abuf->addr;
5486   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5487
5488 {
5489   SI tmp_tmpopd;
5490   SI tmp_tmpops;
5491   BI tmp_carry;
5492   SI tmp_newval;
5493   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5494   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5495   tmp_carry = CPU (h_cbit);
5496   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5497   {
5498     SI opval = tmp_newval;
5499     SET_H_GR (FLD (f_operand2), opval);
5500     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5501   }
5502 {
5503   {
5504     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5505     CPU (h_cbit) = opval;
5506     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5507   }
5508   {
5509     BI opval = LTSI (tmp_newval, 0);
5510     CPU (h_nbit) = opval;
5511     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5512   }
5513   {
5514     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5515     CPU (h_zbit) = opval;
5516     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5517   }
5518   {
5519     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5520     CPU (h_vbit) = opval;
5521     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5522   }
5523 {
5524   {
5525     BI opval = 0;
5526     CPU (h_xbit) = opval;
5527     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5528   }
5529   {
5530     BI opval = 0;
5531     SET_H_INSN_PREFIXED_P (opval);
5532     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5533   }
5534 }
5535 }
5536 }
5537
5538 #undef FLD
5539 }
5540   NEXT (vpc);
5541
5542   CASE (sem, INSN_ADD_M_B_M) : /* add-m.b [${Rs}${inc}],${Rd} */
5543 {
5544   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5545   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5546 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5547   int UNUSED written = 0;
5548   IADDR UNUSED pc = abuf->addr;
5549   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5550
5551 {
5552   QI tmp_tmpopd;
5553   QI tmp_tmpops;
5554   BI tmp_carry;
5555   QI tmp_newval;
5556   tmp_tmpops = ({   SI tmp_addr;
5557   QI tmp_tmp_mem;
5558   BI tmp_postinc;
5559   tmp_postinc = FLD (f_memmode);
5560 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5561 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
5562 ; if (NEBI (tmp_postinc, 0)) {
5563 {
5564 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5565   tmp_addr = ADDSI (tmp_addr, 1);
5566 }
5567   {
5568     SI opval = tmp_addr;
5569     SET_H_GR (FLD (f_operand1), opval);
5570     written |= (1 << 12);
5571     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5572   }
5573 }
5574 }
5575 ; tmp_tmp_mem; });
5576   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5577   tmp_carry = CPU (h_cbit);
5578   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5579 {
5580   SI tmp_oldregval;
5581   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5582   {
5583     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5584     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5585     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5586   }
5587 }
5588 {
5589   {
5590     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5591     CPU (h_cbit) = opval;
5592     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5593   }
5594   {
5595     BI opval = LTQI (tmp_newval, 0);
5596     CPU (h_nbit) = opval;
5597     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5598   }
5599   {
5600     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5601     CPU (h_zbit) = opval;
5602     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5603   }
5604   {
5605     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5606     CPU (h_vbit) = opval;
5607     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5608   }
5609 {
5610   {
5611     BI opval = 0;
5612     CPU (h_xbit) = opval;
5613     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5614   }
5615   {
5616     BI opval = 0;
5617     SET_H_INSN_PREFIXED_P (opval);
5618     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5619   }
5620 }
5621 }
5622 }
5623
5624   abuf->written = written;
5625 #undef FLD
5626 }
5627   NEXT (vpc);
5628
5629   CASE (sem, INSN_ADD_M_W_M) : /* add-m.w [${Rs}${inc}],${Rd} */
5630 {
5631   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5632   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5633 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5634   int UNUSED written = 0;
5635   IADDR UNUSED pc = abuf->addr;
5636   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5637
5638 {
5639   HI tmp_tmpopd;
5640   HI tmp_tmpops;
5641   BI tmp_carry;
5642   HI tmp_newval;
5643   tmp_tmpops = ({   SI tmp_addr;
5644   HI tmp_tmp_mem;
5645   BI tmp_postinc;
5646   tmp_postinc = FLD (f_memmode);
5647 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5648 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
5649 ; if (NEBI (tmp_postinc, 0)) {
5650 {
5651 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5652   tmp_addr = ADDSI (tmp_addr, 2);
5653 }
5654   {
5655     SI opval = tmp_addr;
5656     SET_H_GR (FLD (f_operand1), opval);
5657     written |= (1 << 12);
5658     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5659   }
5660 }
5661 }
5662 ; tmp_tmp_mem; });
5663   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5664   tmp_carry = CPU (h_cbit);
5665   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5666 {
5667   SI tmp_oldregval;
5668   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5669   {
5670     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5671     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5672     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5673   }
5674 }
5675 {
5676   {
5677     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5678     CPU (h_cbit) = opval;
5679     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5680   }
5681   {
5682     BI opval = LTHI (tmp_newval, 0);
5683     CPU (h_nbit) = opval;
5684     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5685   }
5686   {
5687     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5688     CPU (h_zbit) = opval;
5689     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5690   }
5691   {
5692     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5693     CPU (h_vbit) = opval;
5694     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5695   }
5696 {
5697   {
5698     BI opval = 0;
5699     CPU (h_xbit) = opval;
5700     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5701   }
5702   {
5703     BI opval = 0;
5704     SET_H_INSN_PREFIXED_P (opval);
5705     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5706   }
5707 }
5708 }
5709 }
5710
5711   abuf->written = written;
5712 #undef FLD
5713 }
5714   NEXT (vpc);
5715
5716   CASE (sem, INSN_ADD_M_D_M) : /* add-m.d [${Rs}${inc}],${Rd} */
5717 {
5718   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5719   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5720 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5721   int UNUSED written = 0;
5722   IADDR UNUSED pc = abuf->addr;
5723   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5724
5725 {
5726   SI tmp_tmpopd;
5727   SI tmp_tmpops;
5728   BI tmp_carry;
5729   SI tmp_newval;
5730   tmp_tmpops = ({   SI tmp_addr;
5731   SI tmp_tmp_mem;
5732   BI tmp_postinc;
5733   tmp_postinc = FLD (f_memmode);
5734 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5735 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
5736 ; if (NEBI (tmp_postinc, 0)) {
5737 {
5738 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5739   tmp_addr = ADDSI (tmp_addr, 4);
5740 }
5741   {
5742     SI opval = tmp_addr;
5743     SET_H_GR (FLD (f_operand1), opval);
5744     written |= (1 << 11);
5745     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5746   }
5747 }
5748 }
5749 ; tmp_tmp_mem; });
5750   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5751   tmp_carry = CPU (h_cbit);
5752   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5753   {
5754     SI opval = tmp_newval;
5755     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5756     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5757   }
5758 {
5759   {
5760     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5761     CPU (h_cbit) = opval;
5762     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5763   }
5764   {
5765     BI opval = LTSI (tmp_newval, 0);
5766     CPU (h_nbit) = opval;
5767     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5768   }
5769   {
5770     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5771     CPU (h_zbit) = opval;
5772     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5773   }
5774   {
5775     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5776     CPU (h_vbit) = opval;
5777     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5778   }
5779 {
5780   {
5781     BI opval = 0;
5782     CPU (h_xbit) = opval;
5783     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5784   }
5785   {
5786     BI opval = 0;
5787     SET_H_INSN_PREFIXED_P (opval);
5788     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5789   }
5790 }
5791 }
5792 }
5793
5794   abuf->written = written;
5795 #undef FLD
5796 }
5797   NEXT (vpc);
5798
5799   CASE (sem, INSN_ADDCBR) : /* add.b ${sconst8}],${Rd} */
5800 {
5801   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5802   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5803 #define FLD(f) abuf->fields.sfmt_addcbr.f
5804   int UNUSED written = 0;
5805   IADDR UNUSED pc = abuf->addr;
5806   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
5807
5808 {
5809   QI tmp_tmpopd;
5810   QI tmp_tmpops;
5811   BI tmp_carry;
5812   QI tmp_newval;
5813   tmp_tmpops = FLD (f_indir_pc__byte);
5814   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5815   tmp_carry = CPU (h_cbit);
5816   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5817 {
5818   SI tmp_oldregval;
5819   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5820   {
5821     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5822     SET_H_GR (FLD (f_operand2), opval);
5823     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5824   }
5825 }
5826 {
5827   {
5828     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5829     CPU (h_cbit) = opval;
5830     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5831   }
5832   {
5833     BI opval = LTQI (tmp_newval, 0);
5834     CPU (h_nbit) = opval;
5835     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5836   }
5837   {
5838     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5839     CPU (h_zbit) = opval;
5840     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5841   }
5842   {
5843     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5844     CPU (h_vbit) = opval;
5845     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5846   }
5847 {
5848   {
5849     BI opval = 0;
5850     CPU (h_xbit) = opval;
5851     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5852   }
5853   {
5854     BI opval = 0;
5855     SET_H_INSN_PREFIXED_P (opval);
5856     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5857   }
5858 }
5859 }
5860 }
5861
5862 #undef FLD
5863 }
5864   NEXT (vpc);
5865
5866   CASE (sem, INSN_ADDCWR) : /* add.w ${sconst16}],${Rd} */
5867 {
5868   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5869   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5870 #define FLD(f) abuf->fields.sfmt_addcwr.f
5871   int UNUSED written = 0;
5872   IADDR UNUSED pc = abuf->addr;
5873   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
5874
5875 {
5876   HI tmp_tmpopd;
5877   HI tmp_tmpops;
5878   BI tmp_carry;
5879   HI tmp_newval;
5880   tmp_tmpops = FLD (f_indir_pc__word);
5881   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5882   tmp_carry = CPU (h_cbit);
5883   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5884 {
5885   SI tmp_oldregval;
5886   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5887   {
5888     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5889     SET_H_GR (FLD (f_operand2), opval);
5890     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5891   }
5892 }
5893 {
5894   {
5895     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5896     CPU (h_cbit) = opval;
5897     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5898   }
5899   {
5900     BI opval = LTHI (tmp_newval, 0);
5901     CPU (h_nbit) = opval;
5902     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5903   }
5904   {
5905     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5906     CPU (h_zbit) = opval;
5907     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5908   }
5909   {
5910     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5911     CPU (h_vbit) = opval;
5912     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5913   }
5914 {
5915   {
5916     BI opval = 0;
5917     CPU (h_xbit) = opval;
5918     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5919   }
5920   {
5921     BI opval = 0;
5922     SET_H_INSN_PREFIXED_P (opval);
5923     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5924   }
5925 }
5926 }
5927 }
5928
5929 #undef FLD
5930 }
5931   NEXT (vpc);
5932
5933   CASE (sem, INSN_ADDCDR) : /* add.d ${const32}],${Rd} */
5934 {
5935   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5936   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5937 #define FLD(f) abuf->fields.sfmt_addcdr.f
5938   int UNUSED written = 0;
5939   IADDR UNUSED pc = abuf->addr;
5940   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
5941
5942 {
5943   SI tmp_tmpopd;
5944   SI tmp_tmpops;
5945   BI tmp_carry;
5946   SI tmp_newval;
5947   tmp_tmpops = FLD (f_indir_pc__dword);
5948   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5949   tmp_carry = CPU (h_cbit);
5950   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5951   {
5952     SI opval = tmp_newval;
5953     SET_H_GR (FLD (f_operand2), opval);
5954     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5955   }
5956 {
5957   {
5958     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5959     CPU (h_cbit) = opval;
5960     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5961   }
5962   {
5963     BI opval = LTSI (tmp_newval, 0);
5964     CPU (h_nbit) = opval;
5965     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5966   }
5967   {
5968     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5969     CPU (h_zbit) = opval;
5970     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5971   }
5972   {
5973     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5974     CPU (h_vbit) = opval;
5975     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5976   }
5977 {
5978   {
5979     BI opval = 0;
5980     CPU (h_xbit) = opval;
5981     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5982   }
5983   {
5984     BI opval = 0;
5985     SET_H_INSN_PREFIXED_P (opval);
5986     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5987   }
5988 }
5989 }
5990 }
5991
5992 #undef FLD
5993 }
5994   NEXT (vpc);
5995
5996   CASE (sem, INSN_ADDCPC) : /* add.d ${sconst32},PC */
5997 {
5998   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5999   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6000 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
6001   int UNUSED written = 0;
6002   IADDR UNUSED pc = abuf->addr;
6003   SEM_BRANCH_INIT
6004   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
6005
6006 {
6007   SI tmp_newpc;
6008   SI tmp_oldpc;
6009   SI tmp_offs;
6010   tmp_offs = FLD (f_indir_pc__dword);
6011   tmp_oldpc = ADDSI (pc, 6);
6012   tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
6013   {
6014     USI opval = tmp_newpc;
6015     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
6016     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
6017   }
6018 {
6019   {
6020     BI opval = ORIF (ANDIF (LTSI (tmp_offs, 0), LTSI (tmp_oldpc, 0)), ORIF (ANDIF (LTSI (tmp_oldpc, 0), GESI (tmp_newpc, 0)), ANDIF (LTSI (tmp_offs, 0), GESI (tmp_newpc, 0))));
6021     CPU (h_cbit) = opval;
6022     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6023   }
6024   {
6025     BI opval = LTSI (tmp_newpc, 0);
6026     CPU (h_nbit) = opval;
6027     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6028   }
6029   {
6030     BI opval = ANDIF (EQSI (tmp_newpc, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6031     CPU (h_zbit) = opval;
6032     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6033   }
6034   {
6035     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_offs, 0), LTSI (tmp_oldpc, 0)), GESI (tmp_newpc, 0)), ANDIF (ANDIF (GESI (tmp_offs, 0), GESI (tmp_oldpc, 0)), LTSI (tmp_newpc, 0)));
6036     CPU (h_vbit) = opval;
6037     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6038   }
6039 {
6040   {
6041     BI opval = 0;
6042     CPU (h_xbit) = opval;
6043     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6044   }
6045   {
6046     BI opval = 0;
6047     SET_H_INSN_PREFIXED_P (opval);
6048     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6049   }
6050 }
6051 }
6052 }
6053
6054   SEM_BRANCH_FINI (vpc);
6055 #undef FLD
6056 }
6057   NEXT (vpc);
6058
6059   CASE (sem, INSN_ADDS_B_R) : /* adds.b $Rs,$Rd */
6060 {
6061   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6062   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6063 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6064   int UNUSED written = 0;
6065   IADDR UNUSED pc = abuf->addr;
6066   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6067
6068 {
6069   SI tmp_tmpopd;
6070   SI tmp_tmpops;
6071   BI tmp_carry;
6072   SI tmp_newval;
6073   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6074   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6075   tmp_carry = CPU (h_cbit);
6076   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6077   {
6078     SI opval = tmp_newval;
6079     SET_H_GR (FLD (f_operand2), opval);
6080     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6081   }
6082 {
6083   {
6084     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6085     CPU (h_cbit) = opval;
6086     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6087   }
6088   {
6089     BI opval = LTSI (tmp_newval, 0);
6090     CPU (h_nbit) = opval;
6091     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6092   }
6093   {
6094     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6095     CPU (h_zbit) = opval;
6096     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6097   }
6098   {
6099     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6100     CPU (h_vbit) = opval;
6101     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6102   }
6103 {
6104   {
6105     BI opval = 0;
6106     CPU (h_xbit) = opval;
6107     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6108   }
6109   {
6110     BI opval = 0;
6111     SET_H_INSN_PREFIXED_P (opval);
6112     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6113   }
6114 }
6115 }
6116 }
6117
6118 #undef FLD
6119 }
6120   NEXT (vpc);
6121
6122   CASE (sem, INSN_ADDS_W_R) : /* adds.w $Rs,$Rd */
6123 {
6124   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6125   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6126 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6127   int UNUSED written = 0;
6128   IADDR UNUSED pc = abuf->addr;
6129   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6130
6131 {
6132   SI tmp_tmpopd;
6133   SI tmp_tmpops;
6134   BI tmp_carry;
6135   SI tmp_newval;
6136   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6137   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6138   tmp_carry = CPU (h_cbit);
6139   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6140   {
6141     SI opval = tmp_newval;
6142     SET_H_GR (FLD (f_operand2), opval);
6143     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6144   }
6145 {
6146   {
6147     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6148     CPU (h_cbit) = opval;
6149     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6150   }
6151   {
6152     BI opval = LTSI (tmp_newval, 0);
6153     CPU (h_nbit) = opval;
6154     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6155   }
6156   {
6157     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6158     CPU (h_zbit) = opval;
6159     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6160   }
6161   {
6162     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6163     CPU (h_vbit) = opval;
6164     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6165   }
6166 {
6167   {
6168     BI opval = 0;
6169     CPU (h_xbit) = opval;
6170     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6171   }
6172   {
6173     BI opval = 0;
6174     SET_H_INSN_PREFIXED_P (opval);
6175     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6176   }
6177 }
6178 }
6179 }
6180
6181 #undef FLD
6182 }
6183   NEXT (vpc);
6184
6185   CASE (sem, INSN_ADDS_M_B_M) : /* adds-m.b [${Rs}${inc}],$Rd */
6186 {
6187   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6188   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6189 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6190   int UNUSED written = 0;
6191   IADDR UNUSED pc = abuf->addr;
6192   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6193
6194 {
6195   SI tmp_tmpopd;
6196   SI tmp_tmpops;
6197   BI tmp_carry;
6198   SI tmp_newval;
6199   tmp_tmpops = EXTQISI (({   SI tmp_addr;
6200   QI tmp_tmp_mem;
6201   BI tmp_postinc;
6202   tmp_postinc = FLD (f_memmode);
6203 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6204 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6205 ; if (NEBI (tmp_postinc, 0)) {
6206 {
6207 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6208   tmp_addr = ADDSI (tmp_addr, 1);
6209 }
6210   {
6211     SI opval = tmp_addr;
6212     SET_H_GR (FLD (f_operand1), opval);
6213     written |= (1 << 11);
6214     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6215   }
6216 }
6217 }
6218 ; tmp_tmp_mem; }));
6219   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6220   tmp_carry = CPU (h_cbit);
6221   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6222   {
6223     SI opval = tmp_newval;
6224     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6225     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6226   }
6227 {
6228   {
6229     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6230     CPU (h_cbit) = opval;
6231     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6232   }
6233   {
6234     BI opval = LTSI (tmp_newval, 0);
6235     CPU (h_nbit) = opval;
6236     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6237   }
6238   {
6239     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6240     CPU (h_zbit) = opval;
6241     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6242   }
6243   {
6244     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6245     CPU (h_vbit) = opval;
6246     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6247   }
6248 {
6249   {
6250     BI opval = 0;
6251     CPU (h_xbit) = opval;
6252     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6253   }
6254   {
6255     BI opval = 0;
6256     SET_H_INSN_PREFIXED_P (opval);
6257     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6258   }
6259 }
6260 }
6261 }
6262
6263   abuf->written = written;
6264 #undef FLD
6265 }
6266   NEXT (vpc);
6267
6268   CASE (sem, INSN_ADDS_M_W_M) : /* adds-m.w [${Rs}${inc}],$Rd */
6269 {
6270   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6271   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6272 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6273   int UNUSED written = 0;
6274   IADDR UNUSED pc = abuf->addr;
6275   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6276
6277 {
6278   SI tmp_tmpopd;
6279   SI tmp_tmpops;
6280   BI tmp_carry;
6281   SI tmp_newval;
6282   tmp_tmpops = EXTHISI (({   SI tmp_addr;
6283   HI tmp_tmp_mem;
6284   BI tmp_postinc;
6285   tmp_postinc = FLD (f_memmode);
6286 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6287 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6288 ; if (NEBI (tmp_postinc, 0)) {
6289 {
6290 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6291   tmp_addr = ADDSI (tmp_addr, 2);
6292 }
6293   {
6294     SI opval = tmp_addr;
6295     SET_H_GR (FLD (f_operand1), opval);
6296     written |= (1 << 11);
6297     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6298   }
6299 }
6300 }
6301 ; tmp_tmp_mem; }));
6302   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6303   tmp_carry = CPU (h_cbit);
6304   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6305   {
6306     SI opval = tmp_newval;
6307     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6308     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6309   }
6310 {
6311   {
6312     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6313     CPU (h_cbit) = opval;
6314     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6315   }
6316   {
6317     BI opval = LTSI (tmp_newval, 0);
6318     CPU (h_nbit) = opval;
6319     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6320   }
6321   {
6322     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6323     CPU (h_zbit) = opval;
6324     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6325   }
6326   {
6327     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6328     CPU (h_vbit) = opval;
6329     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6330   }
6331 {
6332   {
6333     BI opval = 0;
6334     CPU (h_xbit) = opval;
6335     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6336   }
6337   {
6338     BI opval = 0;
6339     SET_H_INSN_PREFIXED_P (opval);
6340     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6341   }
6342 }
6343 }
6344 }
6345
6346   abuf->written = written;
6347 #undef FLD
6348 }
6349   NEXT (vpc);
6350
6351   CASE (sem, INSN_ADDSCBR) : /* [${Rs}${inc}],$Rd */
6352 {
6353   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6354   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6355 #define FLD(f) abuf->fields.sfmt_addcbr.f
6356   int UNUSED written = 0;
6357   IADDR UNUSED pc = abuf->addr;
6358   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6359
6360 {
6361   SI tmp_tmpopd;
6362   SI tmp_tmpops;
6363   BI tmp_carry;
6364   SI tmp_newval;
6365   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6366   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6367   tmp_carry = CPU (h_cbit);
6368   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6369   {
6370     SI opval = tmp_newval;
6371     SET_H_GR (FLD (f_operand2), opval);
6372     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6373   }
6374 {
6375   {
6376     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6377     CPU (h_cbit) = opval;
6378     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6379   }
6380   {
6381     BI opval = LTSI (tmp_newval, 0);
6382     CPU (h_nbit) = opval;
6383     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6384   }
6385   {
6386     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6387     CPU (h_zbit) = opval;
6388     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6389   }
6390   {
6391     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6392     CPU (h_vbit) = opval;
6393     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6394   }
6395 {
6396   {
6397     BI opval = 0;
6398     CPU (h_xbit) = opval;
6399     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6400   }
6401   {
6402     BI opval = 0;
6403     SET_H_INSN_PREFIXED_P (opval);
6404     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6405   }
6406 }
6407 }
6408 }
6409
6410 #undef FLD
6411 }
6412   NEXT (vpc);
6413
6414   CASE (sem, INSN_ADDSCWR) : /* [${Rs}${inc}],$Rd */
6415 {
6416   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6417   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6418 #define FLD(f) abuf->fields.sfmt_addcwr.f
6419   int UNUSED written = 0;
6420   IADDR UNUSED pc = abuf->addr;
6421   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6422
6423 {
6424   SI tmp_tmpopd;
6425   SI tmp_tmpops;
6426   BI tmp_carry;
6427   SI tmp_newval;
6428   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6429   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6430   tmp_carry = CPU (h_cbit);
6431   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6432   {
6433     SI opval = tmp_newval;
6434     SET_H_GR (FLD (f_operand2), opval);
6435     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6436   }
6437 {
6438   {
6439     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6440     CPU (h_cbit) = opval;
6441     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6442   }
6443   {
6444     BI opval = LTSI (tmp_newval, 0);
6445     CPU (h_nbit) = opval;
6446     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6447   }
6448   {
6449     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6450     CPU (h_zbit) = opval;
6451     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6452   }
6453   {
6454     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6455     CPU (h_vbit) = opval;
6456     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6457   }
6458 {
6459   {
6460     BI opval = 0;
6461     CPU (h_xbit) = opval;
6462     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6463   }
6464   {
6465     BI opval = 0;
6466     SET_H_INSN_PREFIXED_P (opval);
6467     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6468   }
6469 }
6470 }
6471 }
6472
6473 #undef FLD
6474 }
6475   NEXT (vpc);
6476
6477   CASE (sem, INSN_ADDSPCPC) : /* adds.w [PC],PC */
6478 {
6479   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6480   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6481 #define FLD(f) abuf->fields.fmt_empty.f
6482   int UNUSED written = 0;
6483   IADDR UNUSED pc = abuf->addr;
6484   SEM_BRANCH_INIT
6485   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6486
6487 {
6488   SI tmp_newpc;
6489   SI tmp_oldpc;
6490   HI tmp_offs;
6491 if (NOTBI (GET_H_INSN_PREFIXED_P ())) {
6492 cgen_rtx_error (current_cpu, "Unexpected adds.w [PC],PC without prefix");
6493 }
6494   tmp_offs = GETMEMHI (current_cpu, pc, CPU (h_prefixreg_pre_v32));
6495   tmp_oldpc = ADDSI (pc, 2);
6496   tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
6497   {
6498     USI opval = tmp_newpc;
6499     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
6500     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
6501   }
6502 {
6503   {
6504     BI opval = ORIF (ANDIF (LTSI (EXTHISI (tmp_offs), 0), LTSI (tmp_oldpc, 0)), ORIF (ANDIF (LTSI (tmp_oldpc, 0), GESI (tmp_newpc, 0)), ANDIF (LTSI (EXTHISI (tmp_offs), 0), GESI (tmp_newpc, 0))));
6505     CPU (h_cbit) = opval;
6506     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6507   }
6508   {
6509     BI opval = LTSI (tmp_newpc, 0);
6510     CPU (h_nbit) = opval;
6511     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6512   }
6513   {
6514     BI opval = ANDIF (EQSI (tmp_newpc, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6515     CPU (h_zbit) = opval;
6516     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6517   }
6518   {
6519     BI opval = ORIF (ANDIF (ANDIF (LTSI (EXTHISI (tmp_offs), 0), LTSI (tmp_oldpc, 0)), GESI (tmp_newpc, 0)), ANDIF (ANDIF (GESI (EXTHISI (tmp_offs), 0), GESI (tmp_oldpc, 0)), LTSI (tmp_newpc, 0)));
6520     CPU (h_vbit) = opval;
6521     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6522   }
6523 {
6524   {
6525     BI opval = 0;
6526     CPU (h_xbit) = opval;
6527     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6528   }
6529   {
6530     BI opval = 0;
6531     SET_H_INSN_PREFIXED_P (opval);
6532     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6533   }
6534 }
6535 }
6536 }
6537
6538   SEM_BRANCH_FINI (vpc);
6539 #undef FLD
6540 }
6541   NEXT (vpc);
6542
6543   CASE (sem, INSN_ADDU_B_R) : /* addu.b $Rs,$Rd */
6544 {
6545   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6546   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6547 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6548   int UNUSED written = 0;
6549   IADDR UNUSED pc = abuf->addr;
6550   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6551
6552 {
6553   SI tmp_tmpopd;
6554   SI tmp_tmpops;
6555   BI tmp_carry;
6556   SI tmp_newval;
6557   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6558   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6559   tmp_carry = CPU (h_cbit);
6560   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6561   {
6562     SI opval = tmp_newval;
6563     SET_H_GR (FLD (f_operand2), opval);
6564     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6565   }
6566 {
6567   {
6568     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6569     CPU (h_cbit) = opval;
6570     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6571   }
6572   {
6573     BI opval = LTSI (tmp_newval, 0);
6574     CPU (h_nbit) = opval;
6575     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6576   }
6577   {
6578     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6579     CPU (h_zbit) = opval;
6580     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6581   }
6582   {
6583     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6584     CPU (h_vbit) = opval;
6585     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6586   }
6587 {
6588   {
6589     BI opval = 0;
6590     CPU (h_xbit) = opval;
6591     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6592   }
6593   {
6594     BI opval = 0;
6595     SET_H_INSN_PREFIXED_P (opval);
6596     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6597   }
6598 }
6599 }
6600 }
6601
6602 #undef FLD
6603 }
6604   NEXT (vpc);
6605
6606   CASE (sem, INSN_ADDU_W_R) : /* addu.w $Rs,$Rd */
6607 {
6608   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6609   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6610 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6611   int UNUSED written = 0;
6612   IADDR UNUSED pc = abuf->addr;
6613   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6614
6615 {
6616   SI tmp_tmpopd;
6617   SI tmp_tmpops;
6618   BI tmp_carry;
6619   SI tmp_newval;
6620   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6621   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6622   tmp_carry = CPU (h_cbit);
6623   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6624   {
6625     SI opval = tmp_newval;
6626     SET_H_GR (FLD (f_operand2), opval);
6627     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6628   }
6629 {
6630   {
6631     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6632     CPU (h_cbit) = opval;
6633     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6634   }
6635   {
6636     BI opval = LTSI (tmp_newval, 0);
6637     CPU (h_nbit) = opval;
6638     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6639   }
6640   {
6641     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6642     CPU (h_zbit) = opval;
6643     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6644   }
6645   {
6646     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6647     CPU (h_vbit) = opval;
6648     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6649   }
6650 {
6651   {
6652     BI opval = 0;
6653     CPU (h_xbit) = opval;
6654     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6655   }
6656   {
6657     BI opval = 0;
6658     SET_H_INSN_PREFIXED_P (opval);
6659     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6660   }
6661 }
6662 }
6663 }
6664
6665 #undef FLD
6666 }
6667   NEXT (vpc);
6668
6669   CASE (sem, INSN_ADDU_M_B_M) : /* addu-m.b [${Rs}${inc}],$Rd */
6670 {
6671   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6672   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6673 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6674   int UNUSED written = 0;
6675   IADDR UNUSED pc = abuf->addr;
6676   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6677
6678 {
6679   SI tmp_tmpopd;
6680   SI tmp_tmpops;
6681   BI tmp_carry;
6682   SI tmp_newval;
6683   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
6684   QI tmp_tmp_mem;
6685   BI tmp_postinc;
6686   tmp_postinc = FLD (f_memmode);
6687 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6688 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6689 ; if (NEBI (tmp_postinc, 0)) {
6690 {
6691 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6692   tmp_addr = ADDSI (tmp_addr, 1);
6693 }
6694   {
6695     SI opval = tmp_addr;
6696     SET_H_GR (FLD (f_operand1), opval);
6697     written |= (1 << 11);
6698     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6699   }
6700 }
6701 }
6702 ; tmp_tmp_mem; }));
6703   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6704   tmp_carry = CPU (h_cbit);
6705   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6706   {
6707     SI opval = tmp_newval;
6708     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6709     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6710   }
6711 {
6712   {
6713     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6714     CPU (h_cbit) = opval;
6715     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6716   }
6717   {
6718     BI opval = LTSI (tmp_newval, 0);
6719     CPU (h_nbit) = opval;
6720     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6721   }
6722   {
6723     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6724     CPU (h_zbit) = opval;
6725     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6726   }
6727   {
6728     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6729     CPU (h_vbit) = opval;
6730     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6731   }
6732 {
6733   {
6734     BI opval = 0;
6735     CPU (h_xbit) = opval;
6736     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6737   }
6738   {
6739     BI opval = 0;
6740     SET_H_INSN_PREFIXED_P (opval);
6741     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6742   }
6743 }
6744 }
6745 }
6746
6747   abuf->written = written;
6748 #undef FLD
6749 }
6750   NEXT (vpc);
6751
6752   CASE (sem, INSN_ADDU_M_W_M) : /* addu-m.w [${Rs}${inc}],$Rd */
6753 {
6754   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6755   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6756 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6757   int UNUSED written = 0;
6758   IADDR UNUSED pc = abuf->addr;
6759   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6760
6761 {
6762   SI tmp_tmpopd;
6763   SI tmp_tmpops;
6764   BI tmp_carry;
6765   SI tmp_newval;
6766   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
6767   HI tmp_tmp_mem;
6768   BI tmp_postinc;
6769   tmp_postinc = FLD (f_memmode);
6770 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6771 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6772 ; if (NEBI (tmp_postinc, 0)) {
6773 {
6774 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6775   tmp_addr = ADDSI (tmp_addr, 2);
6776 }
6777   {
6778     SI opval = tmp_addr;
6779     SET_H_GR (FLD (f_operand1), opval);
6780     written |= (1 << 11);
6781     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6782   }
6783 }
6784 }
6785 ; tmp_tmp_mem; }));
6786   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6787   tmp_carry = CPU (h_cbit);
6788   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6789   {
6790     SI opval = tmp_newval;
6791     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6792     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6793   }
6794 {
6795   {
6796     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6797     CPU (h_cbit) = opval;
6798     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6799   }
6800   {
6801     BI opval = LTSI (tmp_newval, 0);
6802     CPU (h_nbit) = opval;
6803     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6804   }
6805   {
6806     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6807     CPU (h_zbit) = opval;
6808     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6809   }
6810   {
6811     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6812     CPU (h_vbit) = opval;
6813     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6814   }
6815 {
6816   {
6817     BI opval = 0;
6818     CPU (h_xbit) = opval;
6819     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6820   }
6821   {
6822     BI opval = 0;
6823     SET_H_INSN_PREFIXED_P (opval);
6824     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6825   }
6826 }
6827 }
6828 }
6829
6830   abuf->written = written;
6831 #undef FLD
6832 }
6833   NEXT (vpc);
6834
6835   CASE (sem, INSN_ADDUCBR) : /* [${Rs}${inc}],$Rd */
6836 {
6837   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6838   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6839 #define FLD(f) abuf->fields.sfmt_addcbr.f
6840   int UNUSED written = 0;
6841   IADDR UNUSED pc = abuf->addr;
6842   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6843
6844 {
6845   SI tmp_tmpopd;
6846   SI tmp_tmpops;
6847   BI tmp_carry;
6848   SI tmp_newval;
6849   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6850   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6851   tmp_carry = CPU (h_cbit);
6852   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6853   {
6854     SI opval = tmp_newval;
6855     SET_H_GR (FLD (f_operand2), opval);
6856     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6857   }
6858 {
6859   {
6860     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6861     CPU (h_cbit) = opval;
6862     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6863   }
6864   {
6865     BI opval = LTSI (tmp_newval, 0);
6866     CPU (h_nbit) = opval;
6867     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6868   }
6869   {
6870     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6871     CPU (h_zbit) = opval;
6872     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6873   }
6874   {
6875     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6876     CPU (h_vbit) = opval;
6877     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6878   }
6879 {
6880   {
6881     BI opval = 0;
6882     CPU (h_xbit) = opval;
6883     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6884   }
6885   {
6886     BI opval = 0;
6887     SET_H_INSN_PREFIXED_P (opval);
6888     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6889   }
6890 }
6891 }
6892 }
6893
6894 #undef FLD
6895 }
6896   NEXT (vpc);
6897
6898   CASE (sem, INSN_ADDUCWR) : /* [${Rs}${inc}],$Rd */
6899 {
6900   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6901   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6902 #define FLD(f) abuf->fields.sfmt_addcwr.f
6903   int UNUSED written = 0;
6904   IADDR UNUSED pc = abuf->addr;
6905   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6906
6907 {
6908   SI tmp_tmpopd;
6909   SI tmp_tmpops;
6910   BI tmp_carry;
6911   SI tmp_newval;
6912   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6913   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6914   tmp_carry = CPU (h_cbit);
6915   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6916   {
6917     SI opval = tmp_newval;
6918     SET_H_GR (FLD (f_operand2), opval);
6919     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6920   }
6921 {
6922   {
6923     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6924     CPU (h_cbit) = opval;
6925     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6926   }
6927   {
6928     BI opval = LTSI (tmp_newval, 0);
6929     CPU (h_nbit) = opval;
6930     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6931   }
6932   {
6933     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6934     CPU (h_zbit) = opval;
6935     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6936   }
6937   {
6938     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6939     CPU (h_vbit) = opval;
6940     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6941   }
6942 {
6943   {
6944     BI opval = 0;
6945     CPU (h_xbit) = opval;
6946     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6947   }
6948   {
6949     BI opval = 0;
6950     SET_H_INSN_PREFIXED_P (opval);
6951     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6952   }
6953 }
6954 }
6955 }
6956
6957 #undef FLD
6958 }
6959   NEXT (vpc);
6960
6961   CASE (sem, INSN_SUB_B_R) : /* sub.b $Rs,$Rd */
6962 {
6963   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6964   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6965 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6966   int UNUSED written = 0;
6967   IADDR UNUSED pc = abuf->addr;
6968   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6969
6970 {
6971   QI tmp_tmpopd;
6972   QI tmp_tmpops;
6973   BI tmp_carry;
6974   QI tmp_newval;
6975   tmp_tmpops = GET_H_GR (FLD (f_operand1));
6976   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6977   tmp_carry = CPU (h_cbit);
6978   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6979 {
6980   SI tmp_oldregval;
6981   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
6982   {
6983     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
6984     SET_H_GR (FLD (f_operand2), opval);
6985     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6986   }
6987 }
6988 {
6989   {
6990     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
6991     CPU (h_cbit) = opval;
6992     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6993   }
6994   {
6995     BI opval = LTQI (tmp_newval, 0);
6996     CPU (h_nbit) = opval;
6997     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6998   }
6999   {
7000     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7001     CPU (h_zbit) = opval;
7002     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7003   }
7004   {
7005     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7006     CPU (h_vbit) = opval;
7007     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7008   }
7009 {
7010   {
7011     BI opval = 0;
7012     CPU (h_xbit) = opval;
7013     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7014   }
7015   {
7016     BI opval = 0;
7017     SET_H_INSN_PREFIXED_P (opval);
7018     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7019   }
7020 }
7021 }
7022 }
7023
7024 #undef FLD
7025 }
7026   NEXT (vpc);
7027
7028   CASE (sem, INSN_SUB_W_R) : /* sub.w $Rs,$Rd */
7029 {
7030   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7031   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7032 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7033   int UNUSED written = 0;
7034   IADDR UNUSED pc = abuf->addr;
7035   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7036
7037 {
7038   HI tmp_tmpopd;
7039   HI tmp_tmpops;
7040   BI tmp_carry;
7041   HI tmp_newval;
7042   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7043   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7044   tmp_carry = CPU (h_cbit);
7045   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7046 {
7047   SI tmp_oldregval;
7048   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
7049   {
7050     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7051     SET_H_GR (FLD (f_operand2), opval);
7052     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7053   }
7054 }
7055 {
7056   {
7057     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7058     CPU (h_cbit) = opval;
7059     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7060   }
7061   {
7062     BI opval = LTHI (tmp_newval, 0);
7063     CPU (h_nbit) = opval;
7064     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7065   }
7066   {
7067     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7068     CPU (h_zbit) = opval;
7069     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7070   }
7071   {
7072     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7073     CPU (h_vbit) = opval;
7074     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7075   }
7076 {
7077   {
7078     BI opval = 0;
7079     CPU (h_xbit) = opval;
7080     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7081   }
7082   {
7083     BI opval = 0;
7084     SET_H_INSN_PREFIXED_P (opval);
7085     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7086   }
7087 }
7088 }
7089 }
7090
7091 #undef FLD
7092 }
7093   NEXT (vpc);
7094
7095   CASE (sem, INSN_SUB_D_R) : /* sub.d $Rs,$Rd */
7096 {
7097   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7098   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7099 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7100   int UNUSED written = 0;
7101   IADDR UNUSED pc = abuf->addr;
7102   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7103
7104 {
7105   SI tmp_tmpopd;
7106   SI tmp_tmpops;
7107   BI tmp_carry;
7108   SI tmp_newval;
7109   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7110   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7111   tmp_carry = CPU (h_cbit);
7112   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7113   {
7114     SI opval = tmp_newval;
7115     SET_H_GR (FLD (f_operand2), opval);
7116     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7117   }
7118 {
7119   {
7120     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7121     CPU (h_cbit) = opval;
7122     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7123   }
7124   {
7125     BI opval = LTSI (tmp_newval, 0);
7126     CPU (h_nbit) = opval;
7127     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7128   }
7129   {
7130     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7131     CPU (h_zbit) = opval;
7132     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7133   }
7134   {
7135     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7136     CPU (h_vbit) = opval;
7137     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7138   }
7139 {
7140   {
7141     BI opval = 0;
7142     CPU (h_xbit) = opval;
7143     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7144   }
7145   {
7146     BI opval = 0;
7147     SET_H_INSN_PREFIXED_P (opval);
7148     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7149   }
7150 }
7151 }
7152 }
7153
7154 #undef FLD
7155 }
7156   NEXT (vpc);
7157
7158   CASE (sem, INSN_SUB_M_B_M) : /* sub-m.b [${Rs}${inc}],${Rd} */
7159 {
7160   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7161   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7162 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7163   int UNUSED written = 0;
7164   IADDR UNUSED pc = abuf->addr;
7165   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7166
7167 {
7168   QI tmp_tmpopd;
7169   QI tmp_tmpops;
7170   BI tmp_carry;
7171   QI tmp_newval;
7172   tmp_tmpops = ({   SI tmp_addr;
7173   QI tmp_tmp_mem;
7174   BI tmp_postinc;
7175   tmp_postinc = FLD (f_memmode);
7176 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7177 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7178 ; if (NEBI (tmp_postinc, 0)) {
7179 {
7180 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7181   tmp_addr = ADDSI (tmp_addr, 1);
7182 }
7183   {
7184     SI opval = tmp_addr;
7185     SET_H_GR (FLD (f_operand1), opval);
7186     written |= (1 << 12);
7187     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7188   }
7189 }
7190 }
7191 ; tmp_tmp_mem; });
7192   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7193   tmp_carry = CPU (h_cbit);
7194   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7195 {
7196   SI tmp_oldregval;
7197   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7198   {
7199     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7200     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7201     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7202   }
7203 }
7204 {
7205   {
7206     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7207     CPU (h_cbit) = opval;
7208     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7209   }
7210   {
7211     BI opval = LTQI (tmp_newval, 0);
7212     CPU (h_nbit) = opval;
7213     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7214   }
7215   {
7216     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7217     CPU (h_zbit) = opval;
7218     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7219   }
7220   {
7221     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7222     CPU (h_vbit) = opval;
7223     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7224   }
7225 {
7226   {
7227     BI opval = 0;
7228     CPU (h_xbit) = opval;
7229     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7230   }
7231   {
7232     BI opval = 0;
7233     SET_H_INSN_PREFIXED_P (opval);
7234     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7235   }
7236 }
7237 }
7238 }
7239
7240   abuf->written = written;
7241 #undef FLD
7242 }
7243   NEXT (vpc);
7244
7245   CASE (sem, INSN_SUB_M_W_M) : /* sub-m.w [${Rs}${inc}],${Rd} */
7246 {
7247   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7248   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7249 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7250   int UNUSED written = 0;
7251   IADDR UNUSED pc = abuf->addr;
7252   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7253
7254 {
7255   HI tmp_tmpopd;
7256   HI tmp_tmpops;
7257   BI tmp_carry;
7258   HI tmp_newval;
7259   tmp_tmpops = ({   SI tmp_addr;
7260   HI tmp_tmp_mem;
7261   BI tmp_postinc;
7262   tmp_postinc = FLD (f_memmode);
7263 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7264 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7265 ; if (NEBI (tmp_postinc, 0)) {
7266 {
7267 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7268   tmp_addr = ADDSI (tmp_addr, 2);
7269 }
7270   {
7271     SI opval = tmp_addr;
7272     SET_H_GR (FLD (f_operand1), opval);
7273     written |= (1 << 12);
7274     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7275   }
7276 }
7277 }
7278 ; tmp_tmp_mem; });
7279   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7280   tmp_carry = CPU (h_cbit);
7281   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7282 {
7283   SI tmp_oldregval;
7284   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7285   {
7286     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7287     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7288     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7289   }
7290 }
7291 {
7292   {
7293     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7294     CPU (h_cbit) = opval;
7295     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7296   }
7297   {
7298     BI opval = LTHI (tmp_newval, 0);
7299     CPU (h_nbit) = opval;
7300     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7301   }
7302   {
7303     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7304     CPU (h_zbit) = opval;
7305     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7306   }
7307   {
7308     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7309     CPU (h_vbit) = opval;
7310     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7311   }
7312 {
7313   {
7314     BI opval = 0;
7315     CPU (h_xbit) = opval;
7316     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7317   }
7318   {
7319     BI opval = 0;
7320     SET_H_INSN_PREFIXED_P (opval);
7321     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7322   }
7323 }
7324 }
7325 }
7326
7327   abuf->written = written;
7328 #undef FLD
7329 }
7330   NEXT (vpc);
7331
7332   CASE (sem, INSN_SUB_M_D_M) : /* sub-m.d [${Rs}${inc}],${Rd} */
7333 {
7334   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7335   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7336 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7337   int UNUSED written = 0;
7338   IADDR UNUSED pc = abuf->addr;
7339   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7340
7341 {
7342   SI tmp_tmpopd;
7343   SI tmp_tmpops;
7344   BI tmp_carry;
7345   SI tmp_newval;
7346   tmp_tmpops = ({   SI tmp_addr;
7347   SI tmp_tmp_mem;
7348   BI tmp_postinc;
7349   tmp_postinc = FLD (f_memmode);
7350 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7351 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
7352 ; if (NEBI (tmp_postinc, 0)) {
7353 {
7354 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7355   tmp_addr = ADDSI (tmp_addr, 4);
7356 }
7357   {
7358     SI opval = tmp_addr;
7359     SET_H_GR (FLD (f_operand1), opval);
7360     written |= (1 << 11);
7361     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7362   }
7363 }
7364 }
7365 ; tmp_tmp_mem; });
7366   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7367   tmp_carry = CPU (h_cbit);
7368   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7369   {
7370     SI opval = tmp_newval;
7371     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7372     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7373   }
7374 {
7375   {
7376     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7377     CPU (h_cbit) = opval;
7378     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7379   }
7380   {
7381     BI opval = LTSI (tmp_newval, 0);
7382     CPU (h_nbit) = opval;
7383     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7384   }
7385   {
7386     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7387     CPU (h_zbit) = opval;
7388     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7389   }
7390   {
7391     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7392     CPU (h_vbit) = opval;
7393     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7394   }
7395 {
7396   {
7397     BI opval = 0;
7398     CPU (h_xbit) = opval;
7399     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7400   }
7401   {
7402     BI opval = 0;
7403     SET_H_INSN_PREFIXED_P (opval);
7404     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7405   }
7406 }
7407 }
7408 }
7409
7410   abuf->written = written;
7411 #undef FLD
7412 }
7413   NEXT (vpc);
7414
7415   CASE (sem, INSN_SUBCBR) : /* sub.b ${sconst8}],${Rd} */
7416 {
7417   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7418   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7419 #define FLD(f) abuf->fields.sfmt_addcbr.f
7420   int UNUSED written = 0;
7421   IADDR UNUSED pc = abuf->addr;
7422   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7423
7424 {
7425   QI tmp_tmpopd;
7426   QI tmp_tmpops;
7427   BI tmp_carry;
7428   QI tmp_newval;
7429   tmp_tmpops = FLD (f_indir_pc__byte);
7430   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7431   tmp_carry = CPU (h_cbit);
7432   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7433 {
7434   SI tmp_oldregval;
7435   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
7436   {
7437     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7438     SET_H_GR (FLD (f_operand2), opval);
7439     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7440   }
7441 }
7442 {
7443   {
7444     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7445     CPU (h_cbit) = opval;
7446     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7447   }
7448   {
7449     BI opval = LTQI (tmp_newval, 0);
7450     CPU (h_nbit) = opval;
7451     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7452   }
7453   {
7454     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7455     CPU (h_zbit) = opval;
7456     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7457   }
7458   {
7459     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7460     CPU (h_vbit) = opval;
7461     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7462   }
7463 {
7464   {
7465     BI opval = 0;
7466     CPU (h_xbit) = opval;
7467     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7468   }
7469   {
7470     BI opval = 0;
7471     SET_H_INSN_PREFIXED_P (opval);
7472     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7473   }
7474 }
7475 }
7476 }
7477
7478 #undef FLD
7479 }
7480   NEXT (vpc);
7481
7482   CASE (sem, INSN_SUBCWR) : /* sub.w ${sconst16}],${Rd} */
7483 {
7484   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7485   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7486 #define FLD(f) abuf->fields.sfmt_addcwr.f
7487   int UNUSED written = 0;
7488   IADDR UNUSED pc = abuf->addr;
7489   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7490
7491 {
7492   HI tmp_tmpopd;
7493   HI tmp_tmpops;
7494   BI tmp_carry;
7495   HI tmp_newval;
7496   tmp_tmpops = FLD (f_indir_pc__word);
7497   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7498   tmp_carry = CPU (h_cbit);
7499   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7500 {
7501   SI tmp_oldregval;
7502   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
7503   {
7504     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7505     SET_H_GR (FLD (f_operand2), opval);
7506     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7507   }
7508 }
7509 {
7510   {
7511     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7512     CPU (h_cbit) = opval;
7513     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7514   }
7515   {
7516     BI opval = LTHI (tmp_newval, 0);
7517     CPU (h_nbit) = opval;
7518     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7519   }
7520   {
7521     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7522     CPU (h_zbit) = opval;
7523     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7524   }
7525   {
7526     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7527     CPU (h_vbit) = opval;
7528     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7529   }
7530 {
7531   {
7532     BI opval = 0;
7533     CPU (h_xbit) = opval;
7534     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7535   }
7536   {
7537     BI opval = 0;
7538     SET_H_INSN_PREFIXED_P (opval);
7539     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7540   }
7541 }
7542 }
7543 }
7544
7545 #undef FLD
7546 }
7547   NEXT (vpc);
7548
7549   CASE (sem, INSN_SUBCDR) : /* sub.d ${const32}],${Rd} */
7550 {
7551   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7552   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7553 #define FLD(f) abuf->fields.sfmt_addcdr.f
7554   int UNUSED written = 0;
7555   IADDR UNUSED pc = abuf->addr;
7556   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
7557
7558 {
7559   SI tmp_tmpopd;
7560   SI tmp_tmpops;
7561   BI tmp_carry;
7562   SI tmp_newval;
7563   tmp_tmpops = FLD (f_indir_pc__dword);
7564   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7565   tmp_carry = CPU (h_cbit);
7566   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7567   {
7568     SI opval = tmp_newval;
7569     SET_H_GR (FLD (f_operand2), opval);
7570     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7571   }
7572 {
7573   {
7574     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7575     CPU (h_cbit) = opval;
7576     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7577   }
7578   {
7579     BI opval = LTSI (tmp_newval, 0);
7580     CPU (h_nbit) = opval;
7581     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7582   }
7583   {
7584     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7585     CPU (h_zbit) = opval;
7586     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7587   }
7588   {
7589     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7590     CPU (h_vbit) = opval;
7591     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7592   }
7593 {
7594   {
7595     BI opval = 0;
7596     CPU (h_xbit) = opval;
7597     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7598   }
7599   {
7600     BI opval = 0;
7601     SET_H_INSN_PREFIXED_P (opval);
7602     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7603   }
7604 }
7605 }
7606 }
7607
7608 #undef FLD
7609 }
7610   NEXT (vpc);
7611
7612   CASE (sem, INSN_SUBS_B_R) : /* subs.b $Rs,$Rd */
7613 {
7614   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7615   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7616 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7617   int UNUSED written = 0;
7618   IADDR UNUSED pc = abuf->addr;
7619   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7620
7621 {
7622   SI tmp_tmpopd;
7623   SI tmp_tmpops;
7624   BI tmp_carry;
7625   SI tmp_newval;
7626   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
7627   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7628   tmp_carry = CPU (h_cbit);
7629   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7630   {
7631     SI opval = tmp_newval;
7632     SET_H_GR (FLD (f_operand2), opval);
7633     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7634   }
7635 {
7636   {
7637     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7638     CPU (h_cbit) = opval;
7639     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7640   }
7641   {
7642     BI opval = LTSI (tmp_newval, 0);
7643     CPU (h_nbit) = opval;
7644     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7645   }
7646   {
7647     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7648     CPU (h_zbit) = opval;
7649     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7650   }
7651   {
7652     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7653     CPU (h_vbit) = opval;
7654     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7655   }
7656 {
7657   {
7658     BI opval = 0;
7659     CPU (h_xbit) = opval;
7660     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7661   }
7662   {
7663     BI opval = 0;
7664     SET_H_INSN_PREFIXED_P (opval);
7665     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7666   }
7667 }
7668 }
7669 }
7670
7671 #undef FLD
7672 }
7673   NEXT (vpc);
7674
7675   CASE (sem, INSN_SUBS_W_R) : /* subs.w $Rs,$Rd */
7676 {
7677   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7678   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7679 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7680   int UNUSED written = 0;
7681   IADDR UNUSED pc = abuf->addr;
7682   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7683
7684 {
7685   SI tmp_tmpopd;
7686   SI tmp_tmpops;
7687   BI tmp_carry;
7688   SI tmp_newval;
7689   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
7690   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7691   tmp_carry = CPU (h_cbit);
7692   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7693   {
7694     SI opval = tmp_newval;
7695     SET_H_GR (FLD (f_operand2), opval);
7696     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7697   }
7698 {
7699   {
7700     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7701     CPU (h_cbit) = opval;
7702     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7703   }
7704   {
7705     BI opval = LTSI (tmp_newval, 0);
7706     CPU (h_nbit) = opval;
7707     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7708   }
7709   {
7710     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7711     CPU (h_zbit) = opval;
7712     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7713   }
7714   {
7715     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7716     CPU (h_vbit) = opval;
7717     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7718   }
7719 {
7720   {
7721     BI opval = 0;
7722     CPU (h_xbit) = opval;
7723     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7724   }
7725   {
7726     BI opval = 0;
7727     SET_H_INSN_PREFIXED_P (opval);
7728     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7729   }
7730 }
7731 }
7732 }
7733
7734 #undef FLD
7735 }
7736   NEXT (vpc);
7737
7738   CASE (sem, INSN_SUBS_M_B_M) : /* subs-m.b [${Rs}${inc}],$Rd */
7739 {
7740   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7741   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7742 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7743   int UNUSED written = 0;
7744   IADDR UNUSED pc = abuf->addr;
7745   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7746
7747 {
7748   SI tmp_tmpopd;
7749   SI tmp_tmpops;
7750   BI tmp_carry;
7751   SI tmp_newval;
7752   tmp_tmpops = EXTQISI (({   SI tmp_addr;
7753   QI tmp_tmp_mem;
7754   BI tmp_postinc;
7755   tmp_postinc = FLD (f_memmode);
7756 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7757 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7758 ; if (NEBI (tmp_postinc, 0)) {
7759 {
7760 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7761   tmp_addr = ADDSI (tmp_addr, 1);
7762 }
7763   {
7764     SI opval = tmp_addr;
7765     SET_H_GR (FLD (f_operand1), opval);
7766     written |= (1 << 11);
7767     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7768   }
7769 }
7770 }
7771 ; tmp_tmp_mem; }));
7772   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7773   tmp_carry = CPU (h_cbit);
7774   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7775   {
7776     SI opval = tmp_newval;
7777     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7778     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7779   }
7780 {
7781   {
7782     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7783     CPU (h_cbit) = opval;
7784     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7785   }
7786   {
7787     BI opval = LTSI (tmp_newval, 0);
7788     CPU (h_nbit) = opval;
7789     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7790   }
7791   {
7792     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7793     CPU (h_zbit) = opval;
7794     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7795   }
7796   {
7797     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7798     CPU (h_vbit) = opval;
7799     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7800   }
7801 {
7802   {
7803     BI opval = 0;
7804     CPU (h_xbit) = opval;
7805     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7806   }
7807   {
7808     BI opval = 0;
7809     SET_H_INSN_PREFIXED_P (opval);
7810     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7811   }
7812 }
7813 }
7814 }
7815
7816   abuf->written = written;
7817 #undef FLD
7818 }
7819   NEXT (vpc);
7820
7821   CASE (sem, INSN_SUBS_M_W_M) : /* subs-m.w [${Rs}${inc}],$Rd */
7822 {
7823   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7824   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7825 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7826   int UNUSED written = 0;
7827   IADDR UNUSED pc = abuf->addr;
7828   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7829
7830 {
7831   SI tmp_tmpopd;
7832   SI tmp_tmpops;
7833   BI tmp_carry;
7834   SI tmp_newval;
7835   tmp_tmpops = EXTHISI (({   SI tmp_addr;
7836   HI tmp_tmp_mem;
7837   BI tmp_postinc;
7838   tmp_postinc = FLD (f_memmode);
7839 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7840 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7841 ; if (NEBI (tmp_postinc, 0)) {
7842 {
7843 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7844   tmp_addr = ADDSI (tmp_addr, 2);
7845 }
7846   {
7847     SI opval = tmp_addr;
7848     SET_H_GR (FLD (f_operand1), opval);
7849     written |= (1 << 11);
7850     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7851   }
7852 }
7853 }
7854 ; tmp_tmp_mem; }));
7855   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7856   tmp_carry = CPU (h_cbit);
7857   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7858   {
7859     SI opval = tmp_newval;
7860     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7861     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7862   }
7863 {
7864   {
7865     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7866     CPU (h_cbit) = opval;
7867     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7868   }
7869   {
7870     BI opval = LTSI (tmp_newval, 0);
7871     CPU (h_nbit) = opval;
7872     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7873   }
7874   {
7875     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7876     CPU (h_zbit) = opval;
7877     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7878   }
7879   {
7880     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7881     CPU (h_vbit) = opval;
7882     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7883   }
7884 {
7885   {
7886     BI opval = 0;
7887     CPU (h_xbit) = opval;
7888     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7889   }
7890   {
7891     BI opval = 0;
7892     SET_H_INSN_PREFIXED_P (opval);
7893     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7894   }
7895 }
7896 }
7897 }
7898
7899   abuf->written = written;
7900 #undef FLD
7901 }
7902   NEXT (vpc);
7903
7904   CASE (sem, INSN_SUBSCBR) : /* [${Rs}${inc}],$Rd */
7905 {
7906   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7907   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7908 #define FLD(f) abuf->fields.sfmt_addcbr.f
7909   int UNUSED written = 0;
7910   IADDR UNUSED pc = abuf->addr;
7911   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7912
7913 {
7914   SI tmp_tmpopd;
7915   SI tmp_tmpops;
7916   BI tmp_carry;
7917   SI tmp_newval;
7918   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
7919   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7920   tmp_carry = CPU (h_cbit);
7921   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7922   {
7923     SI opval = tmp_newval;
7924     SET_H_GR (FLD (f_operand2), opval);
7925     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7926   }
7927 {
7928   {
7929     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7930     CPU (h_cbit) = opval;
7931     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7932   }
7933   {
7934     BI opval = LTSI (tmp_newval, 0);
7935     CPU (h_nbit) = opval;
7936     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7937   }
7938   {
7939     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7940     CPU (h_zbit) = opval;
7941     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7942   }
7943   {
7944     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7945     CPU (h_vbit) = opval;
7946     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7947   }
7948 {
7949   {
7950     BI opval = 0;
7951     CPU (h_xbit) = opval;
7952     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7953   }
7954   {
7955     BI opval = 0;
7956     SET_H_INSN_PREFIXED_P (opval);
7957     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7958   }
7959 }
7960 }
7961 }
7962
7963 #undef FLD
7964 }
7965   NEXT (vpc);
7966
7967   CASE (sem, INSN_SUBSCWR) : /* [${Rs}${inc}],$Rd */
7968 {
7969   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7970   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7971 #define FLD(f) abuf->fields.sfmt_addcwr.f
7972   int UNUSED written = 0;
7973   IADDR UNUSED pc = abuf->addr;
7974   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7975
7976 {
7977   SI tmp_tmpopd;
7978   SI tmp_tmpops;
7979   BI tmp_carry;
7980   SI tmp_newval;
7981   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
7982   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7983   tmp_carry = CPU (h_cbit);
7984   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7985   {
7986     SI opval = tmp_newval;
7987     SET_H_GR (FLD (f_operand2), opval);
7988     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7989   }
7990 {
7991   {
7992     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7993     CPU (h_cbit) = opval;
7994     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7995   }
7996   {
7997     BI opval = LTSI (tmp_newval, 0);
7998     CPU (h_nbit) = opval;
7999     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8000   }
8001   {
8002     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8003     CPU (h_zbit) = opval;
8004     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8005   }
8006   {
8007     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8008     CPU (h_vbit) = opval;
8009     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8010   }
8011 {
8012   {
8013     BI opval = 0;
8014     CPU (h_xbit) = opval;
8015     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8016   }
8017   {
8018     BI opval = 0;
8019     SET_H_INSN_PREFIXED_P (opval);
8020     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8021   }
8022 }
8023 }
8024 }
8025
8026 #undef FLD
8027 }
8028   NEXT (vpc);
8029
8030   CASE (sem, INSN_SUBU_B_R) : /* subu.b $Rs,$Rd */
8031 {
8032   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8033   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8034 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8035   int UNUSED written = 0;
8036   IADDR UNUSED pc = abuf->addr;
8037   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8038
8039 {
8040   SI tmp_tmpopd;
8041   SI tmp_tmpops;
8042   BI tmp_carry;
8043   SI tmp_newval;
8044   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
8045   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8046   tmp_carry = CPU (h_cbit);
8047   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8048   {
8049     SI opval = tmp_newval;
8050     SET_H_GR (FLD (f_operand2), opval);
8051     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8052   }
8053 {
8054   {
8055     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8056     CPU (h_cbit) = opval;
8057     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8058   }
8059   {
8060     BI opval = LTSI (tmp_newval, 0);
8061     CPU (h_nbit) = opval;
8062     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8063   }
8064   {
8065     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8066     CPU (h_zbit) = opval;
8067     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8068   }
8069   {
8070     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8071     CPU (h_vbit) = opval;
8072     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8073   }
8074 {
8075   {
8076     BI opval = 0;
8077     CPU (h_xbit) = opval;
8078     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8079   }
8080   {
8081     BI opval = 0;
8082     SET_H_INSN_PREFIXED_P (opval);
8083     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8084   }
8085 }
8086 }
8087 }
8088
8089 #undef FLD
8090 }
8091   NEXT (vpc);
8092
8093   CASE (sem, INSN_SUBU_W_R) : /* subu.w $Rs,$Rd */
8094 {
8095   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8096   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8097 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8098   int UNUSED written = 0;
8099   IADDR UNUSED pc = abuf->addr;
8100   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8101
8102 {
8103   SI tmp_tmpopd;
8104   SI tmp_tmpops;
8105   BI tmp_carry;
8106   SI tmp_newval;
8107   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
8108   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8109   tmp_carry = CPU (h_cbit);
8110   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8111   {
8112     SI opval = tmp_newval;
8113     SET_H_GR (FLD (f_operand2), opval);
8114     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8115   }
8116 {
8117   {
8118     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8119     CPU (h_cbit) = opval;
8120     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8121   }
8122   {
8123     BI opval = LTSI (tmp_newval, 0);
8124     CPU (h_nbit) = opval;
8125     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8126   }
8127   {
8128     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8129     CPU (h_zbit) = opval;
8130     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8131   }
8132   {
8133     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8134     CPU (h_vbit) = opval;
8135     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8136   }
8137 {
8138   {
8139     BI opval = 0;
8140     CPU (h_xbit) = opval;
8141     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8142   }
8143   {
8144     BI opval = 0;
8145     SET_H_INSN_PREFIXED_P (opval);
8146     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8147   }
8148 }
8149 }
8150 }
8151
8152 #undef FLD
8153 }
8154   NEXT (vpc);
8155
8156   CASE (sem, INSN_SUBU_M_B_M) : /* subu-m.b [${Rs}${inc}],$Rd */
8157 {
8158   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8159   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8160 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8161   int UNUSED written = 0;
8162   IADDR UNUSED pc = abuf->addr;
8163   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8164
8165 {
8166   SI tmp_tmpopd;
8167   SI tmp_tmpops;
8168   BI tmp_carry;
8169   SI tmp_newval;
8170   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
8171   QI tmp_tmp_mem;
8172   BI tmp_postinc;
8173   tmp_postinc = FLD (f_memmode);
8174 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8175 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
8176 ; if (NEBI (tmp_postinc, 0)) {
8177 {
8178 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8179   tmp_addr = ADDSI (tmp_addr, 1);
8180 }
8181   {
8182     SI opval = tmp_addr;
8183     SET_H_GR (FLD (f_operand1), opval);
8184     written |= (1 << 11);
8185     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8186   }
8187 }
8188 }
8189 ; tmp_tmp_mem; }));
8190   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8191   tmp_carry = CPU (h_cbit);
8192   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8193   {
8194     SI opval = tmp_newval;
8195     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8196     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8197   }
8198 {
8199   {
8200     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8201     CPU (h_cbit) = opval;
8202     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8203   }
8204   {
8205     BI opval = LTSI (tmp_newval, 0);
8206     CPU (h_nbit) = opval;
8207     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8208   }
8209   {
8210     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8211     CPU (h_zbit) = opval;
8212     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8213   }
8214   {
8215     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8216     CPU (h_vbit) = opval;
8217     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8218   }
8219 {
8220   {
8221     BI opval = 0;
8222     CPU (h_xbit) = opval;
8223     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8224   }
8225   {
8226     BI opval = 0;
8227     SET_H_INSN_PREFIXED_P (opval);
8228     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8229   }
8230 }
8231 }
8232 }
8233
8234   abuf->written = written;
8235 #undef FLD
8236 }
8237   NEXT (vpc);
8238
8239   CASE (sem, INSN_SUBU_M_W_M) : /* subu-m.w [${Rs}${inc}],$Rd */
8240 {
8241   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8242   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8243 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8244   int UNUSED written = 0;
8245   IADDR UNUSED pc = abuf->addr;
8246   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8247
8248 {
8249   SI tmp_tmpopd;
8250   SI tmp_tmpops;
8251   BI tmp_carry;
8252   SI tmp_newval;
8253   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
8254   HI tmp_tmp_mem;
8255   BI tmp_postinc;
8256   tmp_postinc = FLD (f_memmode);
8257 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8258 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
8259 ; if (NEBI (tmp_postinc, 0)) {
8260 {
8261 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8262   tmp_addr = ADDSI (tmp_addr, 2);
8263 }
8264   {
8265     SI opval = tmp_addr;
8266     SET_H_GR (FLD (f_operand1), opval);
8267     written |= (1 << 11);
8268     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8269   }
8270 }
8271 }
8272 ; tmp_tmp_mem; }));
8273   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8274   tmp_carry = CPU (h_cbit);
8275   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8276   {
8277     SI opval = tmp_newval;
8278     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8279     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8280   }
8281 {
8282   {
8283     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8284     CPU (h_cbit) = opval;
8285     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8286   }
8287   {
8288     BI opval = LTSI (tmp_newval, 0);
8289     CPU (h_nbit) = opval;
8290     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8291   }
8292   {
8293     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8294     CPU (h_zbit) = opval;
8295     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8296   }
8297   {
8298     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8299     CPU (h_vbit) = opval;
8300     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8301   }
8302 {
8303   {
8304     BI opval = 0;
8305     CPU (h_xbit) = opval;
8306     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8307   }
8308   {
8309     BI opval = 0;
8310     SET_H_INSN_PREFIXED_P (opval);
8311     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8312   }
8313 }
8314 }
8315 }
8316
8317   abuf->written = written;
8318 #undef FLD
8319 }
8320   NEXT (vpc);
8321
8322   CASE (sem, INSN_SUBUCBR) : /* [${Rs}${inc}],$Rd */
8323 {
8324   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8325   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8326 #define FLD(f) abuf->fields.sfmt_addcbr.f
8327   int UNUSED written = 0;
8328   IADDR UNUSED pc = abuf->addr;
8329   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8330
8331 {
8332   SI tmp_tmpopd;
8333   SI tmp_tmpops;
8334   BI tmp_carry;
8335   SI tmp_newval;
8336   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
8337   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8338   tmp_carry = CPU (h_cbit);
8339   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8340   {
8341     SI opval = tmp_newval;
8342     SET_H_GR (FLD (f_operand2), opval);
8343     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8344   }
8345 {
8346   {
8347     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8348     CPU (h_cbit) = opval;
8349     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8350   }
8351   {
8352     BI opval = LTSI (tmp_newval, 0);
8353     CPU (h_nbit) = opval;
8354     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8355   }
8356   {
8357     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8358     CPU (h_zbit) = opval;
8359     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8360   }
8361   {
8362     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8363     CPU (h_vbit) = opval;
8364     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8365   }
8366 {
8367   {
8368     BI opval = 0;
8369     CPU (h_xbit) = opval;
8370     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8371   }
8372   {
8373     BI opval = 0;
8374     SET_H_INSN_PREFIXED_P (opval);
8375     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8376   }
8377 }
8378 }
8379 }
8380
8381 #undef FLD
8382 }
8383   NEXT (vpc);
8384
8385   CASE (sem, INSN_SUBUCWR) : /* [${Rs}${inc}],$Rd */
8386 {
8387   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8388   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8389 #define FLD(f) abuf->fields.sfmt_addcwr.f
8390   int UNUSED written = 0;
8391   IADDR UNUSED pc = abuf->addr;
8392   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8393
8394 {
8395   SI tmp_tmpopd;
8396   SI tmp_tmpops;
8397   BI tmp_carry;
8398   SI tmp_newval;
8399   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
8400   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8401   tmp_carry = CPU (h_cbit);
8402   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8403   {
8404     SI opval = tmp_newval;
8405     SET_H_GR (FLD (f_operand2), opval);
8406     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8407   }
8408 {
8409   {
8410     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8411     CPU (h_cbit) = opval;
8412     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8413   }
8414   {
8415     BI opval = LTSI (tmp_newval, 0);
8416     CPU (h_nbit) = opval;
8417     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8418   }
8419   {
8420     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8421     CPU (h_zbit) = opval;
8422     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8423   }
8424   {
8425     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8426     CPU (h_vbit) = opval;
8427     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8428   }
8429 {
8430   {
8431     BI opval = 0;
8432     CPU (h_xbit) = opval;
8433     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8434   }
8435   {
8436     BI opval = 0;
8437     SET_H_INSN_PREFIXED_P (opval);
8438     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8439   }
8440 }
8441 }
8442 }
8443
8444 #undef FLD
8445 }
8446   NEXT (vpc);
8447
8448   CASE (sem, INSN_ADDI_B_R) : /* addi.b ${Rs-dfield}.m,${Rd-sfield} */
8449 {
8450   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8451   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8452 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8453   int UNUSED written = 0;
8454   IADDR UNUSED pc = abuf->addr;
8455   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8456
8457 {
8458   {
8459     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
8460     SET_H_GR (FLD (f_operand1), opval);
8461     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8462   }
8463 {
8464   {
8465     BI opval = 0;
8466     CPU (h_xbit) = opval;
8467     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8468   }
8469   {
8470     BI opval = 0;
8471     SET_H_INSN_PREFIXED_P (opval);
8472     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8473   }
8474 }
8475 }
8476
8477 #undef FLD
8478 }
8479   NEXT (vpc);
8480
8481   CASE (sem, INSN_ADDI_W_R) : /* addi.w ${Rs-dfield}.m,${Rd-sfield} */
8482 {
8483   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8484   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8485 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8486   int UNUSED written = 0;
8487   IADDR UNUSED pc = abuf->addr;
8488   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8489
8490 {
8491   {
8492     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
8493     SET_H_GR (FLD (f_operand1), opval);
8494     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8495   }
8496 {
8497   {
8498     BI opval = 0;
8499     CPU (h_xbit) = opval;
8500     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8501   }
8502   {
8503     BI opval = 0;
8504     SET_H_INSN_PREFIXED_P (opval);
8505     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8506   }
8507 }
8508 }
8509
8510 #undef FLD
8511 }
8512   NEXT (vpc);
8513
8514   CASE (sem, INSN_ADDI_D_R) : /* addi.d ${Rs-dfield}.m,${Rd-sfield} */
8515 {
8516   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8517   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8518 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8519   int UNUSED written = 0;
8520   IADDR UNUSED pc = abuf->addr;
8521   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8522
8523 {
8524   {
8525     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
8526     SET_H_GR (FLD (f_operand1), opval);
8527     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8528   }
8529 {
8530   {
8531     BI opval = 0;
8532     CPU (h_xbit) = opval;
8533     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8534   }
8535   {
8536     BI opval = 0;
8537     SET_H_INSN_PREFIXED_P (opval);
8538     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8539   }
8540 }
8541 }
8542
8543 #undef FLD
8544 }
8545   NEXT (vpc);
8546
8547   CASE (sem, INSN_NEG_B_R) : /* neg.b $Rs,$Rd */
8548 {
8549   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8550   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8551 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8552   int UNUSED written = 0;
8553   IADDR UNUSED pc = abuf->addr;
8554   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8555
8556 {
8557   QI tmp_tmpopd;
8558   QI tmp_tmpops;
8559   BI tmp_carry;
8560   QI tmp_newval;
8561   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8562   tmp_tmpopd = 0;
8563   tmp_carry = CPU (h_cbit);
8564   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8565 {
8566   SI tmp_oldregval;
8567   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
8568   {
8569     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
8570     SET_H_GR (FLD (f_operand2), opval);
8571     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8572   }
8573 }
8574 {
8575   {
8576     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
8577     CPU (h_cbit) = opval;
8578     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8579   }
8580   {
8581     BI opval = LTQI (tmp_newval, 0);
8582     CPU (h_nbit) = opval;
8583     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8584   }
8585   {
8586     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8587     CPU (h_zbit) = opval;
8588     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8589   }
8590   {
8591     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
8592     CPU (h_vbit) = opval;
8593     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8594   }
8595 {
8596   {
8597     BI opval = 0;
8598     CPU (h_xbit) = opval;
8599     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8600   }
8601   {
8602     BI opval = 0;
8603     SET_H_INSN_PREFIXED_P (opval);
8604     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8605   }
8606 }
8607 }
8608 }
8609
8610 #undef FLD
8611 }
8612   NEXT (vpc);
8613
8614   CASE (sem, INSN_NEG_W_R) : /* neg.w $Rs,$Rd */
8615 {
8616   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8617   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8618 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8619   int UNUSED written = 0;
8620   IADDR UNUSED pc = abuf->addr;
8621   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8622
8623 {
8624   HI tmp_tmpopd;
8625   HI tmp_tmpops;
8626   BI tmp_carry;
8627   HI tmp_newval;
8628   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8629   tmp_tmpopd = 0;
8630   tmp_carry = CPU (h_cbit);
8631   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8632 {
8633   SI tmp_oldregval;
8634   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
8635   {
8636     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
8637     SET_H_GR (FLD (f_operand2), opval);
8638     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8639   }
8640 }
8641 {
8642   {
8643     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
8644     CPU (h_cbit) = opval;
8645     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8646   }
8647   {
8648     BI opval = LTHI (tmp_newval, 0);
8649     CPU (h_nbit) = opval;
8650     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8651   }
8652   {
8653     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8654     CPU (h_zbit) = opval;
8655     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8656   }
8657   {
8658     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
8659     CPU (h_vbit) = opval;
8660     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8661   }
8662 {
8663   {
8664     BI opval = 0;
8665     CPU (h_xbit) = opval;
8666     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8667   }
8668   {
8669     BI opval = 0;
8670     SET_H_INSN_PREFIXED_P (opval);
8671     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8672   }
8673 }
8674 }
8675 }
8676
8677 #undef FLD
8678 }
8679   NEXT (vpc);
8680
8681   CASE (sem, INSN_NEG_D_R) : /* neg.d $Rs,$Rd */
8682 {
8683   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8684   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8685 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8686   int UNUSED written = 0;
8687   IADDR UNUSED pc = abuf->addr;
8688   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8689
8690 {
8691   SI tmp_tmpopd;
8692   SI tmp_tmpops;
8693   BI tmp_carry;
8694   SI tmp_newval;
8695   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8696   tmp_tmpopd = 0;
8697   tmp_carry = CPU (h_cbit);
8698   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8699   {
8700     SI opval = tmp_newval;
8701     SET_H_GR (FLD (f_operand2), opval);
8702     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8703   }
8704 {
8705   {
8706     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8707     CPU (h_cbit) = opval;
8708     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8709   }
8710   {
8711     BI opval = LTSI (tmp_newval, 0);
8712     CPU (h_nbit) = opval;
8713     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8714   }
8715   {
8716     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8717     CPU (h_zbit) = opval;
8718     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8719   }
8720   {
8721     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8722     CPU (h_vbit) = opval;
8723     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8724   }
8725 {
8726   {
8727     BI opval = 0;
8728     CPU (h_xbit) = opval;
8729     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8730   }
8731   {
8732     BI opval = 0;
8733     SET_H_INSN_PREFIXED_P (opval);
8734     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8735   }
8736 }
8737 }
8738 }
8739
8740 #undef FLD
8741 }
8742   NEXT (vpc);
8743
8744   CASE (sem, INSN_TEST_M_B_M) : /* test-m.b [${Rs}${inc}] */
8745 {
8746   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8747   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8748 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
8749   int UNUSED written = 0;
8750   IADDR UNUSED pc = abuf->addr;
8751   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8752
8753 {
8754   QI tmp_tmpd;
8755   tmp_tmpd = ({   SI tmp_addr;
8756   QI tmp_tmp_mem;
8757   BI tmp_postinc;
8758   tmp_postinc = FLD (f_memmode);
8759 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8760 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
8761 ; if (NEBI (tmp_postinc, 0)) {
8762 {
8763 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8764   tmp_addr = ADDSI (tmp_addr, 1);
8765 }
8766   {
8767     SI opval = tmp_addr;
8768     SET_H_GR (FLD (f_operand1), opval);
8769     written |= (1 << 8);
8770     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8771   }
8772 }
8773 }
8774 ; tmp_tmp_mem; });
8775 {
8776   QI tmp_tmpopd;
8777   QI tmp_tmpops;
8778   BI tmp_carry;
8779   QI tmp_newval;
8780   tmp_tmpops = 0;
8781   tmp_tmpopd = tmp_tmpd;
8782   tmp_carry = CPU (h_cbit);
8783   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8784 ((void) 0); /*nop*/
8785 {
8786   {
8787     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
8788     CPU (h_cbit) = opval;
8789     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8790   }
8791   {
8792     BI opval = LTQI (tmp_newval, 0);
8793     CPU (h_nbit) = opval;
8794     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8795   }
8796   {
8797     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8798     CPU (h_zbit) = opval;
8799     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8800   }
8801   {
8802     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
8803     CPU (h_vbit) = opval;
8804     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8805   }
8806 {
8807   {
8808     BI opval = 0;
8809     CPU (h_xbit) = opval;
8810     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8811   }
8812   {
8813     BI opval = 0;
8814     SET_H_INSN_PREFIXED_P (opval);
8815     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8816   }
8817 }
8818 }
8819 }
8820 }
8821
8822   abuf->written = written;
8823 #undef FLD
8824 }
8825   NEXT (vpc);
8826
8827   CASE (sem, INSN_TEST_M_W_M) : /* test-m.w [${Rs}${inc}] */
8828 {
8829   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8830   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8831 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
8832   int UNUSED written = 0;
8833   IADDR UNUSED pc = abuf->addr;
8834   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8835
8836 {
8837   HI tmp_tmpd;
8838   tmp_tmpd = ({   SI tmp_addr;
8839   HI tmp_tmp_mem;
8840   BI tmp_postinc;
8841   tmp_postinc = FLD (f_memmode);
8842 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8843 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
8844 ; if (NEBI (tmp_postinc, 0)) {
8845 {
8846 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8847   tmp_addr = ADDSI (tmp_addr, 2);
8848 }
8849   {
8850     SI opval = tmp_addr;
8851     SET_H_GR (FLD (f_operand1), opval);
8852     written |= (1 << 8);
8853     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8854   }
8855 }
8856 }
8857 ; tmp_tmp_mem; });
8858 {
8859   HI tmp_tmpopd;
8860   HI tmp_tmpops;
8861   BI tmp_carry;
8862   HI tmp_newval;
8863   tmp_tmpops = 0;
8864   tmp_tmpopd = tmp_tmpd;
8865   tmp_carry = CPU (h_cbit);
8866   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8867 ((void) 0); /*nop*/
8868 {
8869   {
8870     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
8871     CPU (h_cbit) = opval;
8872     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8873   }
8874   {
8875     BI opval = LTHI (tmp_newval, 0);
8876     CPU (h_nbit) = opval;
8877     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8878   }
8879   {
8880     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8881     CPU (h_zbit) = opval;
8882     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8883   }
8884   {
8885     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
8886     CPU (h_vbit) = opval;
8887     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8888   }
8889 {
8890   {
8891     BI opval = 0;
8892     CPU (h_xbit) = opval;
8893     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8894   }
8895   {
8896     BI opval = 0;
8897     SET_H_INSN_PREFIXED_P (opval);
8898     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8899   }
8900 }
8901 }
8902 }
8903 }
8904
8905   abuf->written = written;
8906 #undef FLD
8907 }
8908   NEXT (vpc);
8909
8910   CASE (sem, INSN_TEST_M_D_M) : /* test-m.d [${Rs}${inc}] */
8911 {
8912   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8913   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8914 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
8915   int UNUSED written = 0;
8916   IADDR UNUSED pc = abuf->addr;
8917   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8918
8919 {
8920   SI tmp_tmpd;
8921   tmp_tmpd = ({   SI tmp_addr;
8922   SI tmp_tmp_mem;
8923   BI tmp_postinc;
8924   tmp_postinc = FLD (f_memmode);
8925 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8926 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
8927 ; if (NEBI (tmp_postinc, 0)) {
8928 {
8929 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8930   tmp_addr = ADDSI (tmp_addr, 4);
8931 }
8932   {
8933     SI opval = tmp_addr;
8934     SET_H_GR (FLD (f_operand1), opval);
8935     written |= (1 << 8);
8936     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8937   }
8938 }
8939 }
8940 ; tmp_tmp_mem; });
8941 {
8942   SI tmp_tmpopd;
8943   SI tmp_tmpops;
8944   BI tmp_carry;
8945   SI tmp_newval;
8946   tmp_tmpops = 0;
8947   tmp_tmpopd = tmp_tmpd;
8948   tmp_carry = CPU (h_cbit);
8949   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8950 ((void) 0); /*nop*/
8951 {
8952   {
8953     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8954     CPU (h_cbit) = opval;
8955     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8956   }
8957   {
8958     BI opval = LTSI (tmp_newval, 0);
8959     CPU (h_nbit) = opval;
8960     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8961   }
8962   {
8963     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8964     CPU (h_zbit) = opval;
8965     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8966   }
8967   {
8968     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8969     CPU (h_vbit) = opval;
8970     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8971   }
8972 {
8973   {
8974     BI opval = 0;
8975     CPU (h_xbit) = opval;
8976     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8977   }
8978   {
8979     BI opval = 0;
8980     SET_H_INSN_PREFIXED_P (opval);
8981     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8982   }
8983 }
8984 }
8985 }
8986 }
8987
8988   abuf->written = written;
8989 #undef FLD
8990 }
8991   NEXT (vpc);
8992
8993   CASE (sem, INSN_MOVE_R_M_B_M) : /* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
8994 {
8995   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8996   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8997 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8998   int UNUSED written = 0;
8999   IADDR UNUSED pc = abuf->addr;
9000   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9001
9002 {
9003   QI tmp_tmpd;
9004   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9005 {
9006   SI tmp_addr;
9007   BI tmp_postinc;
9008   tmp_postinc = FLD (f_memmode);
9009   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9010 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
9011 if (EQBI (CPU (h_pbit), 0)) {
9012 {
9013   {
9014     QI opval = tmp_tmpd;
9015     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9016     written |= (1 << 10);
9017     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9018   }
9019   {
9020     BI opval = CPU (h_pbit);
9021     CPU (h_cbit) = opval;
9022     written |= (1 << 9);
9023     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9024   }
9025 }
9026 } else {
9027   {
9028     BI opval = 1;
9029     CPU (h_cbit) = opval;
9030     written |= (1 << 9);
9031     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9032   }
9033 }
9034 } else {
9035   {
9036     QI opval = tmp_tmpd;
9037     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9038     written |= (1 << 10);
9039     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9040   }
9041 }
9042 if (NEBI (tmp_postinc, 0)) {
9043 {
9044 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9045   tmp_addr = ADDSI (tmp_addr, 1);
9046 }
9047   {
9048     SI opval = tmp_addr;
9049     SET_H_GR (FLD (f_operand1), opval);
9050     written |= (1 << 8);
9051     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9052   }
9053 }
9054 }
9055 }
9056 {
9057   {
9058     BI opval = 0;
9059     CPU (h_xbit) = opval;
9060     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9061   }
9062   {
9063     BI opval = 0;
9064     SET_H_INSN_PREFIXED_P (opval);
9065     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9066   }
9067 }
9068 }
9069
9070   abuf->written = written;
9071 #undef FLD
9072 }
9073   NEXT (vpc);
9074
9075   CASE (sem, INSN_MOVE_R_M_W_M) : /* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
9076 {
9077   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9078   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9079 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
9080   int UNUSED written = 0;
9081   IADDR UNUSED pc = abuf->addr;
9082   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9083
9084 {
9085   HI tmp_tmpd;
9086   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9087 {
9088   SI tmp_addr;
9089   BI tmp_postinc;
9090   tmp_postinc = FLD (f_memmode);
9091   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9092 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
9093 if (EQBI (CPU (h_pbit), 0)) {
9094 {
9095   {
9096     HI opval = tmp_tmpd;
9097     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9098     written |= (1 << 10);
9099     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9100   }
9101   {
9102     BI opval = CPU (h_pbit);
9103     CPU (h_cbit) = opval;
9104     written |= (1 << 9);
9105     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9106   }
9107 }
9108 } else {
9109   {
9110     BI opval = 1;
9111     CPU (h_cbit) = opval;
9112     written |= (1 << 9);
9113     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9114   }
9115 }
9116 } else {
9117   {
9118     HI opval = tmp_tmpd;
9119     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9120     written |= (1 << 10);
9121     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9122   }
9123 }
9124 if (NEBI (tmp_postinc, 0)) {
9125 {
9126 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9127   tmp_addr = ADDSI (tmp_addr, 2);
9128 }
9129   {
9130     SI opval = tmp_addr;
9131     SET_H_GR (FLD (f_operand1), opval);
9132     written |= (1 << 8);
9133     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9134   }
9135 }
9136 }
9137 }
9138 {
9139   {
9140     BI opval = 0;
9141     CPU (h_xbit) = opval;
9142     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9143   }
9144   {
9145     BI opval = 0;
9146     SET_H_INSN_PREFIXED_P (opval);
9147     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9148   }
9149 }
9150 }
9151
9152   abuf->written = written;
9153 #undef FLD
9154 }
9155   NEXT (vpc);
9156
9157   CASE (sem, INSN_MOVE_R_M_D_M) : /* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
9158 {
9159   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9160   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9161 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
9162   int UNUSED written = 0;
9163   IADDR UNUSED pc = abuf->addr;
9164   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9165
9166 {
9167   SI tmp_tmpd;
9168   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9169 {
9170   SI tmp_addr;
9171   BI tmp_postinc;
9172   tmp_postinc = FLD (f_memmode);
9173   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9174 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
9175 if (EQBI (CPU (h_pbit), 0)) {
9176 {
9177   {
9178     SI opval = tmp_tmpd;
9179     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9180     written |= (1 << 10);
9181     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9182   }
9183   {
9184     BI opval = CPU (h_pbit);
9185     CPU (h_cbit) = opval;
9186     written |= (1 << 9);
9187     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9188   }
9189 }
9190 } else {
9191   {
9192     BI opval = 1;
9193     CPU (h_cbit) = opval;
9194     written |= (1 << 9);
9195     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9196   }
9197 }
9198 } else {
9199   {
9200     SI opval = tmp_tmpd;
9201     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9202     written |= (1 << 10);
9203     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9204   }
9205 }
9206 if (NEBI (tmp_postinc, 0)) {
9207 {
9208 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9209   tmp_addr = ADDSI (tmp_addr, 4);
9210 }
9211   {
9212     SI opval = tmp_addr;
9213     SET_H_GR (FLD (f_operand1), opval);
9214     written |= (1 << 8);
9215     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9216   }
9217 }
9218 }
9219 }
9220 {
9221   {
9222     BI opval = 0;
9223     CPU (h_xbit) = opval;
9224     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9225   }
9226   {
9227     BI opval = 0;
9228     SET_H_INSN_PREFIXED_P (opval);
9229     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9230   }
9231 }
9232 }
9233
9234   abuf->written = written;
9235 #undef FLD
9236 }
9237   NEXT (vpc);
9238
9239   CASE (sem, INSN_MULS_B) : /* muls.b $Rs,$Rd */
9240 {
9241   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9242   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9243 #define FLD(f) abuf->fields.sfmt_muls_b.f
9244   int UNUSED written = 0;
9245   IADDR UNUSED pc = abuf->addr;
9246   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9247
9248 {
9249   DI tmp_src1;
9250   DI tmp_src2;
9251   DI tmp_tmpr;
9252   tmp_src1 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9253   tmp_src2 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9254   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9255   {
9256     SI opval = TRUNCDISI (tmp_tmpr);
9257     SET_H_GR (FLD (f_operand2), opval);
9258     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9259   }
9260   {
9261     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9262     SET_H_SR (((UINT) 7), opval);
9263     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9264   }
9265 {
9266   {
9267     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9268     CPU (h_cbit) = opval;
9269     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9270   }
9271   {
9272     BI opval = LTDI (tmp_tmpr, 0);
9273     CPU (h_nbit) = opval;
9274     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9275   }
9276   {
9277     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9278     CPU (h_zbit) = opval;
9279     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9280   }
9281   {
9282     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9283     CPU (h_vbit) = opval;
9284     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9285   }
9286 {
9287   {
9288     BI opval = 0;
9289     CPU (h_xbit) = opval;
9290     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9291   }
9292   {
9293     BI opval = 0;
9294     SET_H_INSN_PREFIXED_P (opval);
9295     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9296   }
9297 }
9298 }
9299 }
9300
9301 #undef FLD
9302 }
9303   NEXT (vpc);
9304
9305   CASE (sem, INSN_MULS_W) : /* muls.w $Rs,$Rd */
9306 {
9307   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9308   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9309 #define FLD(f) abuf->fields.sfmt_muls_b.f
9310   int UNUSED written = 0;
9311   IADDR UNUSED pc = abuf->addr;
9312   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9313
9314 {
9315   DI tmp_src1;
9316   DI tmp_src2;
9317   DI tmp_tmpr;
9318   tmp_src1 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9319   tmp_src2 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9320   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9321   {
9322     SI opval = TRUNCDISI (tmp_tmpr);
9323     SET_H_GR (FLD (f_operand2), opval);
9324     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9325   }
9326   {
9327     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9328     SET_H_SR (((UINT) 7), opval);
9329     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9330   }
9331 {
9332   {
9333     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9334     CPU (h_cbit) = opval;
9335     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9336   }
9337   {
9338     BI opval = LTDI (tmp_tmpr, 0);
9339     CPU (h_nbit) = opval;
9340     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9341   }
9342   {
9343     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9344     CPU (h_zbit) = opval;
9345     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9346   }
9347   {
9348     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9349     CPU (h_vbit) = opval;
9350     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9351   }
9352 {
9353   {
9354     BI opval = 0;
9355     CPU (h_xbit) = opval;
9356     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9357   }
9358   {
9359     BI opval = 0;
9360     SET_H_INSN_PREFIXED_P (opval);
9361     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9362   }
9363 }
9364 }
9365 }
9366
9367 #undef FLD
9368 }
9369   NEXT (vpc);
9370
9371   CASE (sem, INSN_MULS_D) : /* muls.d $Rs,$Rd */
9372 {
9373   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9374   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9375 #define FLD(f) abuf->fields.sfmt_muls_b.f
9376   int UNUSED written = 0;
9377   IADDR UNUSED pc = abuf->addr;
9378   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9379
9380 {
9381   DI tmp_src1;
9382   DI tmp_src2;
9383   DI tmp_tmpr;
9384   tmp_src1 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9385   tmp_src2 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9386   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9387   {
9388     SI opval = TRUNCDISI (tmp_tmpr);
9389     SET_H_GR (FLD (f_operand2), opval);
9390     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9391   }
9392   {
9393     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9394     SET_H_SR (((UINT) 7), opval);
9395     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9396   }
9397 {
9398   {
9399     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9400     CPU (h_cbit) = opval;
9401     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9402   }
9403   {
9404     BI opval = LTDI (tmp_tmpr, 0);
9405     CPU (h_nbit) = opval;
9406     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9407   }
9408   {
9409     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9410     CPU (h_zbit) = opval;
9411     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9412   }
9413   {
9414     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9415     CPU (h_vbit) = opval;
9416     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9417   }
9418 {
9419   {
9420     BI opval = 0;
9421     CPU (h_xbit) = opval;
9422     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9423   }
9424   {
9425     BI opval = 0;
9426     SET_H_INSN_PREFIXED_P (opval);
9427     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9428   }
9429 }
9430 }
9431 }
9432
9433 #undef FLD
9434 }
9435   NEXT (vpc);
9436
9437   CASE (sem, INSN_MULU_B) : /* mulu.b $Rs,$Rd */
9438 {
9439   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9440   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9441 #define FLD(f) abuf->fields.sfmt_muls_b.f
9442   int UNUSED written = 0;
9443   IADDR UNUSED pc = abuf->addr;
9444   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9445
9446 {
9447   DI tmp_src1;
9448   DI tmp_src2;
9449   DI tmp_tmpr;
9450   tmp_src1 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9451   tmp_src2 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9452   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9453   {
9454     SI opval = TRUNCDISI (tmp_tmpr);
9455     SET_H_GR (FLD (f_operand2), opval);
9456     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9457   }
9458   {
9459     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9460     SET_H_SR (((UINT) 7), opval);
9461     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9462   }
9463 {
9464   {
9465     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9466     CPU (h_cbit) = opval;
9467     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9468   }
9469   {
9470     BI opval = LTDI (tmp_tmpr, 0);
9471     CPU (h_nbit) = opval;
9472     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9473   }
9474   {
9475     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9476     CPU (h_zbit) = opval;
9477     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9478   }
9479   {
9480     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9481     CPU (h_vbit) = opval;
9482     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9483   }
9484 {
9485   {
9486     BI opval = 0;
9487     CPU (h_xbit) = opval;
9488     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9489   }
9490   {
9491     BI opval = 0;
9492     SET_H_INSN_PREFIXED_P (opval);
9493     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9494   }
9495 }
9496 }
9497 }
9498
9499 #undef FLD
9500 }
9501   NEXT (vpc);
9502
9503   CASE (sem, INSN_MULU_W) : /* mulu.w $Rs,$Rd */
9504 {
9505   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9506   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9507 #define FLD(f) abuf->fields.sfmt_muls_b.f
9508   int UNUSED written = 0;
9509   IADDR UNUSED pc = abuf->addr;
9510   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9511
9512 {
9513   DI tmp_src1;
9514   DI tmp_src2;
9515   DI tmp_tmpr;
9516   tmp_src1 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9517   tmp_src2 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9518   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9519   {
9520     SI opval = TRUNCDISI (tmp_tmpr);
9521     SET_H_GR (FLD (f_operand2), opval);
9522     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9523   }
9524   {
9525     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9526     SET_H_SR (((UINT) 7), opval);
9527     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9528   }
9529 {
9530   {
9531     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9532     CPU (h_cbit) = opval;
9533     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9534   }
9535   {
9536     BI opval = LTDI (tmp_tmpr, 0);
9537     CPU (h_nbit) = opval;
9538     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9539   }
9540   {
9541     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9542     CPU (h_zbit) = opval;
9543     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9544   }
9545   {
9546     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9547     CPU (h_vbit) = opval;
9548     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9549   }
9550 {
9551   {
9552     BI opval = 0;
9553     CPU (h_xbit) = opval;
9554     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9555   }
9556   {
9557     BI opval = 0;
9558     SET_H_INSN_PREFIXED_P (opval);
9559     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9560   }
9561 }
9562 }
9563 }
9564
9565 #undef FLD
9566 }
9567   NEXT (vpc);
9568
9569   CASE (sem, INSN_MULU_D) : /* mulu.d $Rs,$Rd */
9570 {
9571   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9572   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9573 #define FLD(f) abuf->fields.sfmt_muls_b.f
9574   int UNUSED written = 0;
9575   IADDR UNUSED pc = abuf->addr;
9576   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9577
9578 {
9579   DI tmp_src1;
9580   DI tmp_src2;
9581   DI tmp_tmpr;
9582   tmp_src1 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9583   tmp_src2 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9584   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9585   {
9586     SI opval = TRUNCDISI (tmp_tmpr);
9587     SET_H_GR (FLD (f_operand2), opval);
9588     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9589   }
9590   {
9591     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9592     SET_H_SR (((UINT) 7), opval);
9593     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9594   }
9595 {
9596   {
9597     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9598     CPU (h_cbit) = opval;
9599     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9600   }
9601   {
9602     BI opval = LTDI (tmp_tmpr, 0);
9603     CPU (h_nbit) = opval;
9604     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9605   }
9606   {
9607     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9608     CPU (h_zbit) = opval;
9609     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9610   }
9611   {
9612     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9613     CPU (h_vbit) = opval;
9614     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9615   }
9616 {
9617   {
9618     BI opval = 0;
9619     CPU (h_xbit) = opval;
9620     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9621   }
9622   {
9623     BI opval = 0;
9624     SET_H_INSN_PREFIXED_P (opval);
9625     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9626   }
9627 }
9628 }
9629 }
9630
9631 #undef FLD
9632 }
9633   NEXT (vpc);
9634
9635   CASE (sem, INSN_MSTEP) : /* mstep $Rs,$Rd */
9636 {
9637   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9638   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9639 #define FLD(f) abuf->fields.sfmt_muls_b.f
9640   int UNUSED written = 0;
9641   IADDR UNUSED pc = abuf->addr;
9642   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9643
9644 {
9645   SI tmp_tmpd;
9646   SI tmp_tmps;
9647   tmp_tmps = GET_H_GR (FLD (f_operand1));
9648   tmp_tmpd = ADDSI (SLLSI (GET_H_GR (FLD (f_operand2)), 1), ((CPU (h_nbit)) ? (tmp_tmps) : (0)));
9649   {
9650     SI opval = tmp_tmpd;
9651     SET_H_GR (FLD (f_operand2), opval);
9652     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9653   }
9654 {
9655   {
9656     BI opval = LTSI (tmp_tmpd, 0);
9657     CPU (h_nbit) = opval;
9658     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9659   }
9660   {
9661     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9662     CPU (h_zbit) = opval;
9663     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9664   }
9665 SET_H_CBIT_MOVE (0);
9666 SET_H_VBIT_MOVE (0);
9667 {
9668   {
9669     BI opval = 0;
9670     CPU (h_xbit) = opval;
9671     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9672   }
9673   {
9674     BI opval = 0;
9675     SET_H_INSN_PREFIXED_P (opval);
9676     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9677   }
9678 }
9679 }
9680 }
9681
9682 #undef FLD
9683 }
9684   NEXT (vpc);
9685
9686   CASE (sem, INSN_DSTEP) : /* dstep $Rs,$Rd */
9687 {
9688   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9689   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9690 #define FLD(f) abuf->fields.sfmt_muls_b.f
9691   int UNUSED written = 0;
9692   IADDR UNUSED pc = abuf->addr;
9693   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9694
9695 {
9696   SI tmp_tmp;
9697   SI tmp_tmps;
9698   SI tmp_tmpd;
9699   tmp_tmps = GET_H_GR (FLD (f_operand1));
9700   tmp_tmp = SLLSI (GET_H_GR (FLD (f_operand2)), 1);
9701   tmp_tmpd = ((GEUSI (tmp_tmp, tmp_tmps)) ? (SUBSI (tmp_tmp, tmp_tmps)) : (tmp_tmp));
9702   {
9703     SI opval = tmp_tmpd;
9704     SET_H_GR (FLD (f_operand2), opval);
9705     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9706   }
9707 {
9708   {
9709     BI opval = LTSI (tmp_tmpd, 0);
9710     CPU (h_nbit) = opval;
9711     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9712   }
9713   {
9714     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9715     CPU (h_zbit) = opval;
9716     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9717   }
9718 SET_H_CBIT_MOVE (0);
9719 SET_H_VBIT_MOVE (0);
9720 {
9721   {
9722     BI opval = 0;
9723     CPU (h_xbit) = opval;
9724     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9725   }
9726   {
9727     BI opval = 0;
9728     SET_H_INSN_PREFIXED_P (opval);
9729     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9730   }
9731 }
9732 }
9733 }
9734
9735 #undef FLD
9736 }
9737   NEXT (vpc);
9738
9739   CASE (sem, INSN_ABS) : /* abs $Rs,$Rd */
9740 {
9741   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9742   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9743 #define FLD(f) abuf->fields.sfmt_muls_b.f
9744   int UNUSED written = 0;
9745   IADDR UNUSED pc = abuf->addr;
9746   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9747
9748 {
9749   SI tmp_tmpd;
9750   tmp_tmpd = ABSSI (GET_H_GR (FLD (f_operand1)));
9751   {
9752     SI opval = tmp_tmpd;
9753     SET_H_GR (FLD (f_operand2), opval);
9754     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9755   }
9756 {
9757   {
9758     BI opval = LTSI (tmp_tmpd, 0);
9759     CPU (h_nbit) = opval;
9760     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9761   }
9762   {
9763     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9764     CPU (h_zbit) = opval;
9765     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9766   }
9767 SET_H_CBIT_MOVE (0);
9768 SET_H_VBIT_MOVE (0);
9769 {
9770   {
9771     BI opval = 0;
9772     CPU (h_xbit) = opval;
9773     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9774   }
9775   {
9776     BI opval = 0;
9777     SET_H_INSN_PREFIXED_P (opval);
9778     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9779   }
9780 }
9781 }
9782 }
9783
9784 #undef FLD
9785 }
9786   NEXT (vpc);
9787
9788   CASE (sem, INSN_AND_B_R) : /* and.b $Rs,$Rd */
9789 {
9790   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9791   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9792 #define FLD(f) abuf->fields.sfmt_add_b_r.f
9793   int UNUSED written = 0;
9794   IADDR UNUSED pc = abuf->addr;
9795   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9796
9797 {
9798   QI tmp_tmpd;
9799   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
9800 {
9801   SI tmp_oldregval;
9802   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
9803   {
9804     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
9805     SET_H_GR (FLD (f_operand2), opval);
9806     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9807   }
9808 }
9809 {
9810   {
9811     BI opval = LTQI (tmp_tmpd, 0);
9812     CPU (h_nbit) = opval;
9813     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9814   }
9815   {
9816     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9817     CPU (h_zbit) = opval;
9818     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9819   }
9820 SET_H_CBIT_MOVE (0);
9821 SET_H_VBIT_MOVE (0);
9822 {
9823   {
9824     BI opval = 0;
9825     CPU (h_xbit) = opval;
9826     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9827   }
9828   {
9829     BI opval = 0;
9830     SET_H_INSN_PREFIXED_P (opval);
9831     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9832   }
9833 }
9834 }
9835 }
9836
9837 #undef FLD
9838 }
9839   NEXT (vpc);
9840
9841   CASE (sem, INSN_AND_W_R) : /* and.w $Rs,$Rd */
9842 {
9843   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9844   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9845 #define FLD(f) abuf->fields.sfmt_add_b_r.f
9846   int UNUSED written = 0;
9847   IADDR UNUSED pc = abuf->addr;
9848   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9849
9850 {
9851   HI tmp_tmpd;
9852   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
9853 {
9854   SI tmp_oldregval;
9855   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
9856   {
9857     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
9858     SET_H_GR (FLD (f_operand2), opval);
9859     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9860   }
9861 }
9862 {
9863   {
9864     BI opval = LTHI (tmp_tmpd, 0);
9865     CPU (h_nbit) = opval;
9866     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9867   }
9868   {
9869     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9870     CPU (h_zbit) = opval;
9871     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9872   }
9873 SET_H_CBIT_MOVE (0);
9874 SET_H_VBIT_MOVE (0);
9875 {
9876   {
9877     BI opval = 0;
9878     CPU (h_xbit) = opval;
9879     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9880   }
9881   {
9882     BI opval = 0;
9883     SET_H_INSN_PREFIXED_P (opval);
9884     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9885   }
9886 }
9887 }
9888 }
9889
9890 #undef FLD
9891 }
9892   NEXT (vpc);
9893
9894   CASE (sem, INSN_AND_D_R) : /* and.d $Rs,$Rd */
9895 {
9896   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9897   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9898 #define FLD(f) abuf->fields.sfmt_add_b_r.f
9899   int UNUSED written = 0;
9900   IADDR UNUSED pc = abuf->addr;
9901   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9902
9903 {
9904   SI tmp_tmpd;
9905   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
9906   {
9907     SI opval = tmp_tmpd;
9908     SET_H_GR (FLD (f_operand2), opval);
9909     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9910   }
9911 {
9912   {
9913     BI opval = LTSI (tmp_tmpd, 0);
9914     CPU (h_nbit) = opval;
9915     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9916   }
9917   {
9918     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9919     CPU (h_zbit) = opval;
9920     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9921   }
9922 SET_H_CBIT_MOVE (0);
9923 SET_H_VBIT_MOVE (0);
9924 {
9925   {
9926     BI opval = 0;
9927     CPU (h_xbit) = opval;
9928     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9929   }
9930   {
9931     BI opval = 0;
9932     SET_H_INSN_PREFIXED_P (opval);
9933     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9934   }
9935 }
9936 }
9937 }
9938
9939 #undef FLD
9940 }
9941   NEXT (vpc);
9942
9943   CASE (sem, INSN_AND_M_B_M) : /* and-m.b [${Rs}${inc}],${Rd} */
9944 {
9945   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9946   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9947 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
9948   int UNUSED written = 0;
9949   IADDR UNUSED pc = abuf->addr;
9950   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9951
9952 {
9953   QI tmp_tmpd;
9954   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
9955   QI tmp_tmp_mem;
9956   BI tmp_postinc;
9957   tmp_postinc = FLD (f_memmode);
9958 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9959 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
9960 ; if (NEBI (tmp_postinc, 0)) {
9961 {
9962 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9963   tmp_addr = ADDSI (tmp_addr, 1);
9964 }
9965   {
9966     SI opval = tmp_addr;
9967     SET_H_GR (FLD (f_operand1), opval);
9968     written |= (1 << 11);
9969     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9970   }
9971 }
9972 }
9973 ; tmp_tmp_mem; }));
9974 {
9975   SI tmp_oldregval;
9976   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
9977   {
9978     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
9979     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
9980     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9981   }
9982 }
9983 {
9984   {
9985     BI opval = LTQI (tmp_tmpd, 0);
9986     CPU (h_nbit) = opval;
9987     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9988   }
9989   {
9990     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9991     CPU (h_zbit) = opval;
9992     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9993   }
9994 SET_H_CBIT_MOVE (0);
9995 SET_H_VBIT_MOVE (0);
9996 {
9997   {
9998     BI opval = 0;
9999     CPU (h_xbit) = opval;
10000     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10001   }
10002   {
10003     BI opval = 0;
10004     SET_H_INSN_PREFIXED_P (opval);
10005     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10006   }
10007 }
10008 }
10009 }
10010
10011   abuf->written = written;
10012 #undef FLD
10013 }
10014   NEXT (vpc);
10015
10016   CASE (sem, INSN_AND_M_W_M) : /* and-m.w [${Rs}${inc}],${Rd} */
10017 {
10018   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10019   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10020 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10021   int UNUSED written = 0;
10022   IADDR UNUSED pc = abuf->addr;
10023   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10024
10025 {
10026   HI tmp_tmpd;
10027   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10028   HI tmp_tmp_mem;
10029   BI tmp_postinc;
10030   tmp_postinc = FLD (f_memmode);
10031 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10032 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10033 ; if (NEBI (tmp_postinc, 0)) {
10034 {
10035 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10036   tmp_addr = ADDSI (tmp_addr, 2);
10037 }
10038   {
10039     SI opval = tmp_addr;
10040     SET_H_GR (FLD (f_operand1), opval);
10041     written |= (1 << 11);
10042     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10043   }
10044 }
10045 }
10046 ; tmp_tmp_mem; }));
10047 {
10048   SI tmp_oldregval;
10049   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10050   {
10051     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10052     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10053     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10054   }
10055 }
10056 {
10057   {
10058     BI opval = LTHI (tmp_tmpd, 0);
10059     CPU (h_nbit) = opval;
10060     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10061   }
10062   {
10063     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10064     CPU (h_zbit) = opval;
10065     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10066   }
10067 SET_H_CBIT_MOVE (0);
10068 SET_H_VBIT_MOVE (0);
10069 {
10070   {
10071     BI opval = 0;
10072     CPU (h_xbit) = opval;
10073     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10074   }
10075   {
10076     BI opval = 0;
10077     SET_H_INSN_PREFIXED_P (opval);
10078     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10079   }
10080 }
10081 }
10082 }
10083
10084   abuf->written = written;
10085 #undef FLD
10086 }
10087   NEXT (vpc);
10088
10089   CASE (sem, INSN_AND_M_D_M) : /* and-m.d [${Rs}${inc}],${Rd} */
10090 {
10091   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10092   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10093 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10094   int UNUSED written = 0;
10095   IADDR UNUSED pc = abuf->addr;
10096   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10097
10098 {
10099   SI tmp_tmpd;
10100   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10101   SI tmp_tmp_mem;
10102   BI tmp_postinc;
10103   tmp_postinc = FLD (f_memmode);
10104 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10105 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10106 ; if (NEBI (tmp_postinc, 0)) {
10107 {
10108 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10109   tmp_addr = ADDSI (tmp_addr, 4);
10110 }
10111   {
10112     SI opval = tmp_addr;
10113     SET_H_GR (FLD (f_operand1), opval);
10114     written |= (1 << 10);
10115     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10116   }
10117 }
10118 }
10119 ; tmp_tmp_mem; }));
10120   {
10121     SI opval = tmp_tmpd;
10122     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10123     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10124   }
10125 {
10126   {
10127     BI opval = LTSI (tmp_tmpd, 0);
10128     CPU (h_nbit) = opval;
10129     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10130   }
10131   {
10132     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10133     CPU (h_zbit) = opval;
10134     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10135   }
10136 SET_H_CBIT_MOVE (0);
10137 SET_H_VBIT_MOVE (0);
10138 {
10139   {
10140     BI opval = 0;
10141     CPU (h_xbit) = opval;
10142     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10143   }
10144   {
10145     BI opval = 0;
10146     SET_H_INSN_PREFIXED_P (opval);
10147     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10148   }
10149 }
10150 }
10151 }
10152
10153   abuf->written = written;
10154 #undef FLD
10155 }
10156   NEXT (vpc);
10157
10158   CASE (sem, INSN_ANDCBR) : /* and.b ${sconst8}],${Rd} */
10159 {
10160   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10161   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10162 #define FLD(f) abuf->fields.sfmt_addcbr.f
10163   int UNUSED written = 0;
10164   IADDR UNUSED pc = abuf->addr;
10165   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10166
10167 {
10168   QI tmp_tmpd;
10169   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
10170 {
10171   SI tmp_oldregval;
10172   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10173   {
10174     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10175     SET_H_GR (FLD (f_operand2), opval);
10176     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10177   }
10178 }
10179 {
10180   {
10181     BI opval = LTQI (tmp_tmpd, 0);
10182     CPU (h_nbit) = opval;
10183     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10184   }
10185   {
10186     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10187     CPU (h_zbit) = opval;
10188     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10189   }
10190 SET_H_CBIT_MOVE (0);
10191 SET_H_VBIT_MOVE (0);
10192 {
10193   {
10194     BI opval = 0;
10195     CPU (h_xbit) = opval;
10196     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10197   }
10198   {
10199     BI opval = 0;
10200     SET_H_INSN_PREFIXED_P (opval);
10201     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10202   }
10203 }
10204 }
10205 }
10206
10207 #undef FLD
10208 }
10209   NEXT (vpc);
10210
10211   CASE (sem, INSN_ANDCWR) : /* and.w ${sconst16}],${Rd} */
10212 {
10213   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10214   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10215 #define FLD(f) abuf->fields.sfmt_addcwr.f
10216   int UNUSED written = 0;
10217   IADDR UNUSED pc = abuf->addr;
10218   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10219
10220 {
10221   HI tmp_tmpd;
10222   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
10223 {
10224   SI tmp_oldregval;
10225   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10226   {
10227     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10228     SET_H_GR (FLD (f_operand2), opval);
10229     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10230   }
10231 }
10232 {
10233   {
10234     BI opval = LTHI (tmp_tmpd, 0);
10235     CPU (h_nbit) = opval;
10236     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10237   }
10238   {
10239     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10240     CPU (h_zbit) = opval;
10241     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10242   }
10243 SET_H_CBIT_MOVE (0);
10244 SET_H_VBIT_MOVE (0);
10245 {
10246   {
10247     BI opval = 0;
10248     CPU (h_xbit) = opval;
10249     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10250   }
10251   {
10252     BI opval = 0;
10253     SET_H_INSN_PREFIXED_P (opval);
10254     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10255   }
10256 }
10257 }
10258 }
10259
10260 #undef FLD
10261 }
10262   NEXT (vpc);
10263
10264   CASE (sem, INSN_ANDCDR) : /* and.d ${const32}],${Rd} */
10265 {
10266   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10267   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10268 #define FLD(f) abuf->fields.sfmt_addcdr.f
10269   int UNUSED written = 0;
10270   IADDR UNUSED pc = abuf->addr;
10271   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
10272
10273 {
10274   SI tmp_tmpd;
10275   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
10276   {
10277     SI opval = tmp_tmpd;
10278     SET_H_GR (FLD (f_operand2), opval);
10279     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10280   }
10281 {
10282   {
10283     BI opval = LTSI (tmp_tmpd, 0);
10284     CPU (h_nbit) = opval;
10285     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10286   }
10287   {
10288     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10289     CPU (h_zbit) = opval;
10290     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10291   }
10292 SET_H_CBIT_MOVE (0);
10293 SET_H_VBIT_MOVE (0);
10294 {
10295   {
10296     BI opval = 0;
10297     CPU (h_xbit) = opval;
10298     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10299   }
10300   {
10301     BI opval = 0;
10302     SET_H_INSN_PREFIXED_P (opval);
10303     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10304   }
10305 }
10306 }
10307 }
10308
10309 #undef FLD
10310 }
10311   NEXT (vpc);
10312
10313   CASE (sem, INSN_ANDQ) : /* andq $i,$Rd */
10314 {
10315   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10316   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10317 #define FLD(f) abuf->fields.sfmt_andq.f
10318   int UNUSED written = 0;
10319   IADDR UNUSED pc = abuf->addr;
10320   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10321
10322 {
10323   SI tmp_tmpd;
10324   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
10325   {
10326     SI opval = tmp_tmpd;
10327     SET_H_GR (FLD (f_operand2), opval);
10328     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10329   }
10330 {
10331   {
10332     BI opval = LTSI (tmp_tmpd, 0);
10333     CPU (h_nbit) = opval;
10334     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10335   }
10336   {
10337     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10338     CPU (h_zbit) = opval;
10339     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10340   }
10341 SET_H_CBIT_MOVE (0);
10342 SET_H_VBIT_MOVE (0);
10343 {
10344   {
10345     BI opval = 0;
10346     CPU (h_xbit) = opval;
10347     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10348   }
10349   {
10350     BI opval = 0;
10351     SET_H_INSN_PREFIXED_P (opval);
10352     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10353   }
10354 }
10355 }
10356 }
10357
10358 #undef FLD
10359 }
10360   NEXT (vpc);
10361
10362   CASE (sem, INSN_ORR_B_R) : /* orr.b $Rs,$Rd */
10363 {
10364   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10365   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10366 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10367   int UNUSED written = 0;
10368   IADDR UNUSED pc = abuf->addr;
10369   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10370
10371 {
10372   QI tmp_tmpd;
10373   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10374 {
10375   SI tmp_oldregval;
10376   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10377   {
10378     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10379     SET_H_GR (FLD (f_operand2), opval);
10380     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10381   }
10382 }
10383 {
10384   {
10385     BI opval = LTQI (tmp_tmpd, 0);
10386     CPU (h_nbit) = opval;
10387     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10388   }
10389   {
10390     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10391     CPU (h_zbit) = opval;
10392     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10393   }
10394 SET_H_CBIT_MOVE (0);
10395 SET_H_VBIT_MOVE (0);
10396 {
10397   {
10398     BI opval = 0;
10399     CPU (h_xbit) = opval;
10400     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10401   }
10402   {
10403     BI opval = 0;
10404     SET_H_INSN_PREFIXED_P (opval);
10405     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10406   }
10407 }
10408 }
10409 }
10410
10411 #undef FLD
10412 }
10413   NEXT (vpc);
10414
10415   CASE (sem, INSN_ORR_W_R) : /* orr.w $Rs,$Rd */
10416 {
10417   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10418   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10419 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10420   int UNUSED written = 0;
10421   IADDR UNUSED pc = abuf->addr;
10422   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10423
10424 {
10425   HI tmp_tmpd;
10426   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10427 {
10428   SI tmp_oldregval;
10429   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10430   {
10431     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10432     SET_H_GR (FLD (f_operand2), opval);
10433     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10434   }
10435 }
10436 {
10437   {
10438     BI opval = LTHI (tmp_tmpd, 0);
10439     CPU (h_nbit) = opval;
10440     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10441   }
10442   {
10443     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10444     CPU (h_zbit) = opval;
10445     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10446   }
10447 SET_H_CBIT_MOVE (0);
10448 SET_H_VBIT_MOVE (0);
10449 {
10450   {
10451     BI opval = 0;
10452     CPU (h_xbit) = opval;
10453     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10454   }
10455   {
10456     BI opval = 0;
10457     SET_H_INSN_PREFIXED_P (opval);
10458     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10459   }
10460 }
10461 }
10462 }
10463
10464 #undef FLD
10465 }
10466   NEXT (vpc);
10467
10468   CASE (sem, INSN_ORR_D_R) : /* orr.d $Rs,$Rd */
10469 {
10470   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10471   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10472 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10473   int UNUSED written = 0;
10474   IADDR UNUSED pc = abuf->addr;
10475   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10476
10477 {
10478   SI tmp_tmpd;
10479   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10480   {
10481     SI opval = tmp_tmpd;
10482     SET_H_GR (FLD (f_operand2), opval);
10483     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10484   }
10485 {
10486   {
10487     BI opval = LTSI (tmp_tmpd, 0);
10488     CPU (h_nbit) = opval;
10489     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10490   }
10491   {
10492     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10493     CPU (h_zbit) = opval;
10494     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10495   }
10496 SET_H_CBIT_MOVE (0);
10497 SET_H_VBIT_MOVE (0);
10498 {
10499   {
10500     BI opval = 0;
10501     CPU (h_xbit) = opval;
10502     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10503   }
10504   {
10505     BI opval = 0;
10506     SET_H_INSN_PREFIXED_P (opval);
10507     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10508   }
10509 }
10510 }
10511 }
10512
10513 #undef FLD
10514 }
10515   NEXT (vpc);
10516
10517   CASE (sem, INSN_OR_M_B_M) : /* or-m.b [${Rs}${inc}],${Rd} */
10518 {
10519   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10520   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10521 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10522   int UNUSED written = 0;
10523   IADDR UNUSED pc = abuf->addr;
10524   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10525
10526 {
10527   QI tmp_tmpd;
10528   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10529   QI tmp_tmp_mem;
10530   BI tmp_postinc;
10531   tmp_postinc = FLD (f_memmode);
10532 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10533 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
10534 ; if (NEBI (tmp_postinc, 0)) {
10535 {
10536 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10537   tmp_addr = ADDSI (tmp_addr, 1);
10538 }
10539   {
10540     SI opval = tmp_addr;
10541     SET_H_GR (FLD (f_operand1), opval);
10542     written |= (1 << 11);
10543     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10544   }
10545 }
10546 }
10547 ; tmp_tmp_mem; }));
10548 {
10549   SI tmp_oldregval;
10550   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10551   {
10552     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10553     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10554     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10555   }
10556 }
10557 {
10558   {
10559     BI opval = LTQI (tmp_tmpd, 0);
10560     CPU (h_nbit) = opval;
10561     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10562   }
10563   {
10564     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10565     CPU (h_zbit) = opval;
10566     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10567   }
10568 SET_H_CBIT_MOVE (0);
10569 SET_H_VBIT_MOVE (0);
10570 {
10571   {
10572     BI opval = 0;
10573     CPU (h_xbit) = opval;
10574     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10575   }
10576   {
10577     BI opval = 0;
10578     SET_H_INSN_PREFIXED_P (opval);
10579     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10580   }
10581 }
10582 }
10583 }
10584
10585   abuf->written = written;
10586 #undef FLD
10587 }
10588   NEXT (vpc);
10589
10590   CASE (sem, INSN_OR_M_W_M) : /* or-m.w [${Rs}${inc}],${Rd} */
10591 {
10592   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10593   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10594 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10595   int UNUSED written = 0;
10596   IADDR UNUSED pc = abuf->addr;
10597   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10598
10599 {
10600   HI tmp_tmpd;
10601   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10602   HI tmp_tmp_mem;
10603   BI tmp_postinc;
10604   tmp_postinc = FLD (f_memmode);
10605 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10606 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10607 ; if (NEBI (tmp_postinc, 0)) {
10608 {
10609 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10610   tmp_addr = ADDSI (tmp_addr, 2);
10611 }
10612   {
10613     SI opval = tmp_addr;
10614     SET_H_GR (FLD (f_operand1), opval);
10615     written |= (1 << 11);
10616     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10617   }
10618 }
10619 }
10620 ; tmp_tmp_mem; }));
10621 {
10622   SI tmp_oldregval;
10623   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10624   {
10625     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10626     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10627     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10628   }
10629 }
10630 {
10631   {
10632     BI opval = LTHI (tmp_tmpd, 0);
10633     CPU (h_nbit) = opval;
10634     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10635   }
10636   {
10637     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10638     CPU (h_zbit) = opval;
10639     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10640   }
10641 SET_H_CBIT_MOVE (0);
10642 SET_H_VBIT_MOVE (0);
10643 {
10644   {
10645     BI opval = 0;
10646     CPU (h_xbit) = opval;
10647     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10648   }
10649   {
10650     BI opval = 0;
10651     SET_H_INSN_PREFIXED_P (opval);
10652     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10653   }
10654 }
10655 }
10656 }
10657
10658   abuf->written = written;
10659 #undef FLD
10660 }
10661   NEXT (vpc);
10662
10663   CASE (sem, INSN_OR_M_D_M) : /* or-m.d [${Rs}${inc}],${Rd} */
10664 {
10665   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10666   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10667 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10668   int UNUSED written = 0;
10669   IADDR UNUSED pc = abuf->addr;
10670   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10671
10672 {
10673   SI tmp_tmpd;
10674   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10675   SI tmp_tmp_mem;
10676   BI tmp_postinc;
10677   tmp_postinc = FLD (f_memmode);
10678 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10679 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10680 ; if (NEBI (tmp_postinc, 0)) {
10681 {
10682 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10683   tmp_addr = ADDSI (tmp_addr, 4);
10684 }
10685   {
10686     SI opval = tmp_addr;
10687     SET_H_GR (FLD (f_operand1), opval);
10688     written |= (1 << 10);
10689     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10690   }
10691 }
10692 }
10693 ; tmp_tmp_mem; }));
10694   {
10695     SI opval = tmp_tmpd;
10696     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10697     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10698   }
10699 {
10700   {
10701     BI opval = LTSI (tmp_tmpd, 0);
10702     CPU (h_nbit) = opval;
10703     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10704   }
10705   {
10706     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10707     CPU (h_zbit) = opval;
10708     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10709   }
10710 SET_H_CBIT_MOVE (0);
10711 SET_H_VBIT_MOVE (0);
10712 {
10713   {
10714     BI opval = 0;
10715     CPU (h_xbit) = opval;
10716     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10717   }
10718   {
10719     BI opval = 0;
10720     SET_H_INSN_PREFIXED_P (opval);
10721     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10722   }
10723 }
10724 }
10725 }
10726
10727   abuf->written = written;
10728 #undef FLD
10729 }
10730   NEXT (vpc);
10731
10732   CASE (sem, INSN_ORCBR) : /* or.b ${sconst8}],${Rd} */
10733 {
10734   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10735   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10736 #define FLD(f) abuf->fields.sfmt_addcbr.f
10737   int UNUSED written = 0;
10738   IADDR UNUSED pc = abuf->addr;
10739   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10740
10741 {
10742   QI tmp_tmpd;
10743   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
10744 {
10745   SI tmp_oldregval;
10746   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10747   {
10748     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10749     SET_H_GR (FLD (f_operand2), opval);
10750     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10751   }
10752 }
10753 {
10754   {
10755     BI opval = LTQI (tmp_tmpd, 0);
10756     CPU (h_nbit) = opval;
10757     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10758   }
10759   {
10760     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10761     CPU (h_zbit) = opval;
10762     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10763   }
10764 SET_H_CBIT_MOVE (0);
10765 SET_H_VBIT_MOVE (0);
10766 {
10767   {
10768     BI opval = 0;
10769     CPU (h_xbit) = opval;
10770     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10771   }
10772   {
10773     BI opval = 0;
10774     SET_H_INSN_PREFIXED_P (opval);
10775     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10776   }
10777 }
10778 }
10779 }
10780
10781 #undef FLD
10782 }
10783   NEXT (vpc);
10784
10785   CASE (sem, INSN_ORCWR) : /* or.w ${sconst16}],${Rd} */
10786 {
10787   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10788   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10789 #define FLD(f) abuf->fields.sfmt_addcwr.f
10790   int UNUSED written = 0;
10791   IADDR UNUSED pc = abuf->addr;
10792   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10793
10794 {
10795   HI tmp_tmpd;
10796   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
10797 {
10798   SI tmp_oldregval;
10799   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10800   {
10801     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10802     SET_H_GR (FLD (f_operand2), opval);
10803     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10804   }
10805 }
10806 {
10807   {
10808     BI opval = LTHI (tmp_tmpd, 0);
10809     CPU (h_nbit) = opval;
10810     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10811   }
10812   {
10813     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10814     CPU (h_zbit) = opval;
10815     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10816   }
10817 SET_H_CBIT_MOVE (0);
10818 SET_H_VBIT_MOVE (0);
10819 {
10820   {
10821     BI opval = 0;
10822     CPU (h_xbit) = opval;
10823     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10824   }
10825   {
10826     BI opval = 0;
10827     SET_H_INSN_PREFIXED_P (opval);
10828     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10829   }
10830 }
10831 }
10832 }
10833
10834 #undef FLD
10835 }
10836   NEXT (vpc);
10837
10838   CASE (sem, INSN_ORCDR) : /* or.d ${const32}],${Rd} */
10839 {
10840   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10841   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10842 #define FLD(f) abuf->fields.sfmt_addcdr.f
10843   int UNUSED written = 0;
10844   IADDR UNUSED pc = abuf->addr;
10845   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
10846
10847 {
10848   SI tmp_tmpd;
10849   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
10850   {
10851     SI opval = tmp_tmpd;
10852     SET_H_GR (FLD (f_operand2), opval);
10853     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10854   }
10855 {
10856   {
10857     BI opval = LTSI (tmp_tmpd, 0);
10858     CPU (h_nbit) = opval;
10859     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10860   }
10861   {
10862     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10863     CPU (h_zbit) = opval;
10864     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10865   }
10866 SET_H_CBIT_MOVE (0);
10867 SET_H_VBIT_MOVE (0);
10868 {
10869   {
10870     BI opval = 0;
10871     CPU (h_xbit) = opval;
10872     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10873   }
10874   {
10875     BI opval = 0;
10876     SET_H_INSN_PREFIXED_P (opval);
10877     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10878   }
10879 }
10880 }
10881 }
10882
10883 #undef FLD
10884 }
10885   NEXT (vpc);
10886
10887   CASE (sem, INSN_ORQ) : /* orq $i,$Rd */
10888 {
10889   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10890   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10891 #define FLD(f) abuf->fields.sfmt_andq.f
10892   int UNUSED written = 0;
10893   IADDR UNUSED pc = abuf->addr;
10894   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10895
10896 {
10897   SI tmp_tmpd;
10898   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
10899   {
10900     SI opval = tmp_tmpd;
10901     SET_H_GR (FLD (f_operand2), opval);
10902     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10903   }
10904 {
10905   {
10906     BI opval = LTSI (tmp_tmpd, 0);
10907     CPU (h_nbit) = opval;
10908     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10909   }
10910   {
10911     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10912     CPU (h_zbit) = opval;
10913     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10914   }
10915 SET_H_CBIT_MOVE (0);
10916 SET_H_VBIT_MOVE (0);
10917 {
10918   {
10919     BI opval = 0;
10920     CPU (h_xbit) = opval;
10921     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10922   }
10923   {
10924     BI opval = 0;
10925     SET_H_INSN_PREFIXED_P (opval);
10926     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10927   }
10928 }
10929 }
10930 }
10931
10932 #undef FLD
10933 }
10934   NEXT (vpc);
10935
10936   CASE (sem, INSN_XOR) : /* xor $Rs,$Rd */
10937 {
10938   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10939   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10940 #define FLD(f) abuf->fields.sfmt_muls_b.f
10941   int UNUSED written = 0;
10942   IADDR UNUSED pc = abuf->addr;
10943   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10944
10945 {
10946   SI tmp_tmpd;
10947   tmp_tmpd = XORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10948   {
10949     SI opval = tmp_tmpd;
10950     SET_H_GR (FLD (f_operand2), opval);
10951     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10952   }
10953 {
10954   {
10955     BI opval = LTSI (tmp_tmpd, 0);
10956     CPU (h_nbit) = opval;
10957     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10958   }
10959   {
10960     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10961     CPU (h_zbit) = opval;
10962     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10963   }
10964 SET_H_CBIT_MOVE (0);
10965 SET_H_VBIT_MOVE (0);
10966 {
10967   {
10968     BI opval = 0;
10969     CPU (h_xbit) = opval;
10970     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10971   }
10972   {
10973     BI opval = 0;
10974     SET_H_INSN_PREFIXED_P (opval);
10975     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10976   }
10977 }
10978 }
10979 }
10980
10981 #undef FLD
10982 }
10983   NEXT (vpc);
10984
10985   CASE (sem, INSN_SWAP) : /* swap${swapoption} ${Rs} */
10986 {
10987   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10988   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10989 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
10990   int UNUSED written = 0;
10991   IADDR UNUSED pc = abuf->addr;
10992   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10993
10994 {
10995   SI tmp_tmps;
10996   SI tmp_tmpd;
10997   tmp_tmps = GET_H_GR (FLD (f_operand1));
10998   tmp_tmpd = ({   SI tmp_tmpcode;
10999   SI tmp_tmpval;
11000   SI tmp_tmpres;
11001   tmp_tmpcode = FLD (f_operand2);
11002 ;   tmp_tmpval = tmp_tmps;
11003 ; if (EQSI (tmp_tmpcode, 0)) {
11004   tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
11005 }
11006  else if (EQSI (tmp_tmpcode, 1)) {
11007   tmp_tmpres = ({   SI tmp_tmpr;
11008   tmp_tmpr = tmp_tmpval;
11009 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11010 }
11011  else if (EQSI (tmp_tmpcode, 2)) {
11012   tmp_tmpres = ({   SI tmp_tmpb;
11013   tmp_tmpb = tmp_tmpval;
11014 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11015 }
11016  else if (EQSI (tmp_tmpcode, 3)) {
11017   tmp_tmpres = ({   SI tmp_tmpr;
11018   tmp_tmpr = ({   SI tmp_tmpb;
11019   tmp_tmpb = tmp_tmpval;
11020 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11021 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11022 }
11023  else if (EQSI (tmp_tmpcode, 4)) {
11024   tmp_tmpres = ({   SI tmp_tmpb;
11025   tmp_tmpb = tmp_tmpval;
11026 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11027 }
11028  else if (EQSI (tmp_tmpcode, 5)) {
11029   tmp_tmpres = ({   SI tmp_tmpr;
11030   tmp_tmpr = ({   SI tmp_tmpb;
11031   tmp_tmpb = tmp_tmpval;
11032 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11033 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11034 }
11035  else if (EQSI (tmp_tmpcode, 6)) {
11036   tmp_tmpres = ({   SI tmp_tmpb;
11037   tmp_tmpb = ({   SI tmp_tmpb;
11038   tmp_tmpb = tmp_tmpval;
11039 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11040 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11041 }
11042  else if (EQSI (tmp_tmpcode, 7)) {
11043   tmp_tmpres = ({   SI tmp_tmpr;
11044   tmp_tmpr = ({   SI tmp_tmpb;
11045   tmp_tmpb = ({   SI tmp_tmpb;
11046   tmp_tmpb = tmp_tmpval;
11047 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11048 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11049 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11050 }
11051  else if (EQSI (tmp_tmpcode, 8)) {
11052   tmp_tmpres = INVSI (tmp_tmpval);
11053 }
11054  else if (EQSI (tmp_tmpcode, 9)) {
11055   tmp_tmpres = ({   SI tmp_tmpr;
11056   tmp_tmpr = INVSI (tmp_tmpval);
11057 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11058 }
11059  else if (EQSI (tmp_tmpcode, 10)) {
11060   tmp_tmpres = ({   SI tmp_tmpb;
11061   tmp_tmpb = INVSI (tmp_tmpval);
11062 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11063 }
11064  else if (EQSI (tmp_tmpcode, 11)) {
11065   tmp_tmpres = ({   SI tmp_tmpr;
11066   tmp_tmpr = ({   SI tmp_tmpb;
11067   tmp_tmpb = INVSI (tmp_tmpval);
11068 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11069 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11070 }
11071  else if (EQSI (tmp_tmpcode, 12)) {
11072   tmp_tmpres = ({   SI tmp_tmpb;
11073   tmp_tmpb = INVSI (tmp_tmpval);
11074 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11075 }
11076  else if (EQSI (tmp_tmpcode, 13)) {
11077   tmp_tmpres = ({   SI tmp_tmpr;
11078   tmp_tmpr = ({   SI tmp_tmpb;
11079   tmp_tmpb = INVSI (tmp_tmpval);
11080 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11081 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11082 }
11083  else if (EQSI (tmp_tmpcode, 14)) {
11084   tmp_tmpres = ({   SI tmp_tmpb;
11085   tmp_tmpb = ({   SI tmp_tmpb;
11086   tmp_tmpb = INVSI (tmp_tmpval);
11087 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11088 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11089 }
11090  else if (EQSI (tmp_tmpcode, 15)) {
11091   tmp_tmpres = ({   SI tmp_tmpr;
11092   tmp_tmpr = ({   SI tmp_tmpb;
11093   tmp_tmpb = ({   SI tmp_tmpb;
11094   tmp_tmpb = INVSI (tmp_tmpval);
11095 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11096 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11097 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11098 }
11099 ; tmp_tmpres; });
11100   {
11101     SI opval = tmp_tmpd;
11102     SET_H_GR (FLD (f_operand1), opval);
11103     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11104   }
11105 {
11106   {
11107     BI opval = LTSI (tmp_tmpd, 0);
11108     CPU (h_nbit) = opval;
11109     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11110   }
11111   {
11112     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11113     CPU (h_zbit) = opval;
11114     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11115   }
11116 SET_H_CBIT_MOVE (0);
11117 SET_H_VBIT_MOVE (0);
11118 {
11119   {
11120     BI opval = 0;
11121     CPU (h_xbit) = opval;
11122     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11123   }
11124   {
11125     BI opval = 0;
11126     SET_H_INSN_PREFIXED_P (opval);
11127     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11128   }
11129 }
11130 }
11131 }
11132
11133 #undef FLD
11134 }
11135   NEXT (vpc);
11136
11137   CASE (sem, INSN_ASRR_B_R) : /* asrr.b $Rs,$Rd */
11138 {
11139   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11140   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11141 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11142   int UNUSED written = 0;
11143   IADDR UNUSED pc = abuf->addr;
11144   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11145
11146 {
11147   QI tmp_tmpd;
11148   SI tmp_cnt1;
11149   SI tmp_cnt2;
11150   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11151   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11152   tmp_tmpd = SRASI (EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11153 {
11154   SI tmp_oldregval;
11155   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11156   {
11157     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11158     SET_H_GR (FLD (f_operand2), opval);
11159     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11160   }
11161 }
11162 {
11163   {
11164     BI opval = LTQI (tmp_tmpd, 0);
11165     CPU (h_nbit) = opval;
11166     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11167   }
11168   {
11169     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11170     CPU (h_zbit) = opval;
11171     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11172   }
11173 SET_H_CBIT_MOVE (0);
11174 SET_H_VBIT_MOVE (0);
11175 {
11176   {
11177     BI opval = 0;
11178     CPU (h_xbit) = opval;
11179     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11180   }
11181   {
11182     BI opval = 0;
11183     SET_H_INSN_PREFIXED_P (opval);
11184     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11185   }
11186 }
11187 }
11188 }
11189
11190 #undef FLD
11191 }
11192   NEXT (vpc);
11193
11194   CASE (sem, INSN_ASRR_W_R) : /* asrr.w $Rs,$Rd */
11195 {
11196   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11197   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11198 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11199   int UNUSED written = 0;
11200   IADDR UNUSED pc = abuf->addr;
11201   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11202
11203 {
11204   HI tmp_tmpd;
11205   SI tmp_cnt1;
11206   SI tmp_cnt2;
11207   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11208   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11209   tmp_tmpd = SRASI (EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11210 {
11211   SI tmp_oldregval;
11212   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11213   {
11214     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11215     SET_H_GR (FLD (f_operand2), opval);
11216     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11217   }
11218 }
11219 {
11220   {
11221     BI opval = LTHI (tmp_tmpd, 0);
11222     CPU (h_nbit) = opval;
11223     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11224   }
11225   {
11226     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11227     CPU (h_zbit) = opval;
11228     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11229   }
11230 SET_H_CBIT_MOVE (0);
11231 SET_H_VBIT_MOVE (0);
11232 {
11233   {
11234     BI opval = 0;
11235     CPU (h_xbit) = opval;
11236     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11237   }
11238   {
11239     BI opval = 0;
11240     SET_H_INSN_PREFIXED_P (opval);
11241     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11242   }
11243 }
11244 }
11245 }
11246
11247 #undef FLD
11248 }
11249   NEXT (vpc);
11250
11251   CASE (sem, INSN_ASRR_D_R) : /* asrr.d $Rs,$Rd */
11252 {
11253   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11254   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11255 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11256   int UNUSED written = 0;
11257   IADDR UNUSED pc = abuf->addr;
11258   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11259
11260 {
11261   SI tmp_tmpd;
11262   SI tmp_cnt1;
11263   SI tmp_cnt2;
11264   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11265   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11266   tmp_tmpd = SRASI (EXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11267   {
11268     SI opval = tmp_tmpd;
11269     SET_H_GR (FLD (f_operand2), opval);
11270     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11271   }
11272 {
11273   {
11274     BI opval = LTSI (tmp_tmpd, 0);
11275     CPU (h_nbit) = opval;
11276     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11277   }
11278   {
11279     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11280     CPU (h_zbit) = opval;
11281     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11282   }
11283 SET_H_CBIT_MOVE (0);
11284 SET_H_VBIT_MOVE (0);
11285 {
11286   {
11287     BI opval = 0;
11288     CPU (h_xbit) = opval;
11289     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11290   }
11291   {
11292     BI opval = 0;
11293     SET_H_INSN_PREFIXED_P (opval);
11294     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11295   }
11296 }
11297 }
11298 }
11299
11300 #undef FLD
11301 }
11302   NEXT (vpc);
11303
11304   CASE (sem, INSN_ASRQ) : /* asrq $c,${Rd} */
11305 {
11306   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11307   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11308 #define FLD(f) abuf->fields.sfmt_asrq.f
11309   int UNUSED written = 0;
11310   IADDR UNUSED pc = abuf->addr;
11311   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11312
11313 {
11314   SI tmp_tmpd;
11315   tmp_tmpd = SRASI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11316   {
11317     SI opval = tmp_tmpd;
11318     SET_H_GR (FLD (f_operand2), opval);
11319     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11320   }
11321 {
11322   {
11323     BI opval = LTSI (tmp_tmpd, 0);
11324     CPU (h_nbit) = opval;
11325     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11326   }
11327   {
11328     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11329     CPU (h_zbit) = opval;
11330     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11331   }
11332 SET_H_CBIT_MOVE (0);
11333 SET_H_VBIT_MOVE (0);
11334 {
11335   {
11336     BI opval = 0;
11337     CPU (h_xbit) = opval;
11338     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11339   }
11340   {
11341     BI opval = 0;
11342     SET_H_INSN_PREFIXED_P (opval);
11343     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11344   }
11345 }
11346 }
11347 }
11348
11349 #undef FLD
11350 }
11351   NEXT (vpc);
11352
11353   CASE (sem, INSN_LSRR_B_R) : /* lsrr.b $Rs,$Rd */
11354 {
11355   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11356   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11357 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11358   int UNUSED written = 0;
11359   IADDR UNUSED pc = abuf->addr;
11360   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11361
11362 {
11363   SI tmp_tmpd;
11364   SI tmp_cnt;
11365   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11366   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11367 {
11368   SI tmp_oldregval;
11369   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11370   {
11371     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11372     SET_H_GR (FLD (f_operand2), opval);
11373     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11374   }
11375 }
11376 {
11377   {
11378     BI opval = LTQI (tmp_tmpd, 0);
11379     CPU (h_nbit) = opval;
11380     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11381   }
11382   {
11383     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11384     CPU (h_zbit) = opval;
11385     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11386   }
11387 SET_H_CBIT_MOVE (0);
11388 SET_H_VBIT_MOVE (0);
11389 {
11390   {
11391     BI opval = 0;
11392     CPU (h_xbit) = opval;
11393     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11394   }
11395   {
11396     BI opval = 0;
11397     SET_H_INSN_PREFIXED_P (opval);
11398     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11399   }
11400 }
11401 }
11402 }
11403
11404 #undef FLD
11405 }
11406   NEXT (vpc);
11407
11408   CASE (sem, INSN_LSRR_W_R) : /* lsrr.w $Rs,$Rd */
11409 {
11410   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11411   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11412 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11413   int UNUSED written = 0;
11414   IADDR UNUSED pc = abuf->addr;
11415   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11416
11417 {
11418   SI tmp_tmpd;
11419   SI tmp_cnt;
11420   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11421   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11422 {
11423   SI tmp_oldregval;
11424   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11425   {
11426     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11427     SET_H_GR (FLD (f_operand2), opval);
11428     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11429   }
11430 }
11431 {
11432   {
11433     BI opval = LTHI (tmp_tmpd, 0);
11434     CPU (h_nbit) = opval;
11435     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11436   }
11437   {
11438     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11439     CPU (h_zbit) = opval;
11440     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11441   }
11442 SET_H_CBIT_MOVE (0);
11443 SET_H_VBIT_MOVE (0);
11444 {
11445   {
11446     BI opval = 0;
11447     CPU (h_xbit) = opval;
11448     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11449   }
11450   {
11451     BI opval = 0;
11452     SET_H_INSN_PREFIXED_P (opval);
11453     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11454   }
11455 }
11456 }
11457 }
11458
11459 #undef FLD
11460 }
11461   NEXT (vpc);
11462
11463   CASE (sem, INSN_LSRR_D_R) : /* lsrr.d $Rs,$Rd */
11464 {
11465   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11466   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11467 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11468   int UNUSED written = 0;
11469   IADDR UNUSED pc = abuf->addr;
11470   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11471
11472 {
11473   SI tmp_tmpd;
11474   SI tmp_cnt;
11475   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11476   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11477   {
11478     SI opval = tmp_tmpd;
11479     SET_H_GR (FLD (f_operand2), opval);
11480     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11481   }
11482 {
11483   {
11484     BI opval = LTSI (tmp_tmpd, 0);
11485     CPU (h_nbit) = opval;
11486     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11487   }
11488   {
11489     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11490     CPU (h_zbit) = opval;
11491     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11492   }
11493 SET_H_CBIT_MOVE (0);
11494 SET_H_VBIT_MOVE (0);
11495 {
11496   {
11497     BI opval = 0;
11498     CPU (h_xbit) = opval;
11499     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11500   }
11501   {
11502     BI opval = 0;
11503     SET_H_INSN_PREFIXED_P (opval);
11504     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11505   }
11506 }
11507 }
11508 }
11509
11510 #undef FLD
11511 }
11512   NEXT (vpc);
11513
11514   CASE (sem, INSN_LSRQ) : /* lsrq $c,${Rd} */
11515 {
11516   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11517   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11518 #define FLD(f) abuf->fields.sfmt_asrq.f
11519   int UNUSED written = 0;
11520   IADDR UNUSED pc = abuf->addr;
11521   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11522
11523 {
11524   SI tmp_tmpd;
11525   tmp_tmpd = SRLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11526   {
11527     SI opval = tmp_tmpd;
11528     SET_H_GR (FLD (f_operand2), opval);
11529     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11530   }
11531 {
11532   {
11533     BI opval = LTSI (tmp_tmpd, 0);
11534     CPU (h_nbit) = opval;
11535     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11536   }
11537   {
11538     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11539     CPU (h_zbit) = opval;
11540     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11541   }
11542 SET_H_CBIT_MOVE (0);
11543 SET_H_VBIT_MOVE (0);
11544 {
11545   {
11546     BI opval = 0;
11547     CPU (h_xbit) = opval;
11548     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11549   }
11550   {
11551     BI opval = 0;
11552     SET_H_INSN_PREFIXED_P (opval);
11553     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11554   }
11555 }
11556 }
11557 }
11558
11559 #undef FLD
11560 }
11561   NEXT (vpc);
11562
11563   CASE (sem, INSN_LSLR_B_R) : /* lslr.b $Rs,$Rd */
11564 {
11565   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11566   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11567 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11568   int UNUSED written = 0;
11569   IADDR UNUSED pc = abuf->addr;
11570   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11571
11572 {
11573   SI tmp_tmpd;
11574   SI tmp_cnt;
11575   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11576   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11577 {
11578   SI tmp_oldregval;
11579   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11580   {
11581     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11582     SET_H_GR (FLD (f_operand2), opval);
11583     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11584   }
11585 }
11586 {
11587   {
11588     BI opval = LTQI (tmp_tmpd, 0);
11589     CPU (h_nbit) = opval;
11590     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11591   }
11592   {
11593     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11594     CPU (h_zbit) = opval;
11595     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11596   }
11597 SET_H_CBIT_MOVE (0);
11598 SET_H_VBIT_MOVE (0);
11599 {
11600   {
11601     BI opval = 0;
11602     CPU (h_xbit) = opval;
11603     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11604   }
11605   {
11606     BI opval = 0;
11607     SET_H_INSN_PREFIXED_P (opval);
11608     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11609   }
11610 }
11611 }
11612 }
11613
11614 #undef FLD
11615 }
11616   NEXT (vpc);
11617
11618   CASE (sem, INSN_LSLR_W_R) : /* lslr.w $Rs,$Rd */
11619 {
11620   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11621   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11622 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11623   int UNUSED written = 0;
11624   IADDR UNUSED pc = abuf->addr;
11625   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11626
11627 {
11628   SI tmp_tmpd;
11629   SI tmp_cnt;
11630   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11631   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11632 {
11633   SI tmp_oldregval;
11634   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11635   {
11636     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11637     SET_H_GR (FLD (f_operand2), opval);
11638     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11639   }
11640 }
11641 {
11642   {
11643     BI opval = LTHI (tmp_tmpd, 0);
11644     CPU (h_nbit) = opval;
11645     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11646   }
11647   {
11648     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11649     CPU (h_zbit) = opval;
11650     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11651   }
11652 SET_H_CBIT_MOVE (0);
11653 SET_H_VBIT_MOVE (0);
11654 {
11655   {
11656     BI opval = 0;
11657     CPU (h_xbit) = opval;
11658     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11659   }
11660   {
11661     BI opval = 0;
11662     SET_H_INSN_PREFIXED_P (opval);
11663     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11664   }
11665 }
11666 }
11667 }
11668
11669 #undef FLD
11670 }
11671   NEXT (vpc);
11672
11673   CASE (sem, INSN_LSLR_D_R) : /* lslr.d $Rs,$Rd */
11674 {
11675   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11676   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11677 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11678   int UNUSED written = 0;
11679   IADDR UNUSED pc = abuf->addr;
11680   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11681
11682 {
11683   SI tmp_tmpd;
11684   SI tmp_cnt;
11685   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11686   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11687   {
11688     SI opval = tmp_tmpd;
11689     SET_H_GR (FLD (f_operand2), opval);
11690     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11691   }
11692 {
11693   {
11694     BI opval = LTSI (tmp_tmpd, 0);
11695     CPU (h_nbit) = opval;
11696     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11697   }
11698   {
11699     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11700     CPU (h_zbit) = opval;
11701     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11702   }
11703 SET_H_CBIT_MOVE (0);
11704 SET_H_VBIT_MOVE (0);
11705 {
11706   {
11707     BI opval = 0;
11708     CPU (h_xbit) = opval;
11709     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11710   }
11711   {
11712     BI opval = 0;
11713     SET_H_INSN_PREFIXED_P (opval);
11714     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11715   }
11716 }
11717 }
11718 }
11719
11720 #undef FLD
11721 }
11722   NEXT (vpc);
11723
11724   CASE (sem, INSN_LSLQ) : /* lslq $c,${Rd} */
11725 {
11726   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11727   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11728 #define FLD(f) abuf->fields.sfmt_asrq.f
11729   int UNUSED written = 0;
11730   IADDR UNUSED pc = abuf->addr;
11731   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11732
11733 {
11734   SI tmp_tmpd;
11735   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11736   {
11737     SI opval = tmp_tmpd;
11738     SET_H_GR (FLD (f_operand2), opval);
11739     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11740   }
11741 {
11742   {
11743     BI opval = LTSI (tmp_tmpd, 0);
11744     CPU (h_nbit) = opval;
11745     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11746   }
11747   {
11748     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11749     CPU (h_zbit) = opval;
11750     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11751   }
11752 SET_H_CBIT_MOVE (0);
11753 SET_H_VBIT_MOVE (0);
11754 {
11755   {
11756     BI opval = 0;
11757     CPU (h_xbit) = opval;
11758     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11759   }
11760   {
11761     BI opval = 0;
11762     SET_H_INSN_PREFIXED_P (opval);
11763     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11764   }
11765 }
11766 }
11767 }
11768
11769 #undef FLD
11770 }
11771   NEXT (vpc);
11772
11773   CASE (sem, INSN_BTST) : /* $Rs,$Rd */
11774 {
11775   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11776   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11777 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11778   int UNUSED written = 0;
11779   IADDR UNUSED pc = abuf->addr;
11780   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11781
11782 {
11783   SI tmp_tmpd;
11784   SI tmp_cnt;
11785   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, ANDSI (GET_H_GR (FLD (f_operand1)), 31)));
11786 {
11787   {
11788     BI opval = LTSI (tmp_tmpd, 0);
11789     CPU (h_nbit) = opval;
11790     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11791   }
11792   {
11793     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11794     CPU (h_zbit) = opval;
11795     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11796   }
11797 SET_H_CBIT_MOVE (0);
11798 SET_H_VBIT_MOVE (0);
11799 {
11800   {
11801     BI opval = 0;
11802     CPU (h_xbit) = opval;
11803     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11804   }
11805   {
11806     BI opval = 0;
11807     SET_H_INSN_PREFIXED_P (opval);
11808     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11809   }
11810 }
11811 }
11812 }
11813
11814 #undef FLD
11815 }
11816   NEXT (vpc);
11817
11818   CASE (sem, INSN_BTSTQ) : /* btstq $c,${Rd} */
11819 {
11820   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11821   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11822 #define FLD(f) abuf->fields.sfmt_asrq.f
11823   int UNUSED written = 0;
11824   IADDR UNUSED pc = abuf->addr;
11825   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11826
11827 {
11828   SI tmp_tmpd;
11829   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, FLD (f_u5)));
11830 {
11831   {
11832     BI opval = LTSI (tmp_tmpd, 0);
11833     CPU (h_nbit) = opval;
11834     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11835   }
11836   {
11837     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11838     CPU (h_zbit) = opval;
11839     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11840   }
11841 SET_H_CBIT_MOVE (0);
11842 SET_H_VBIT_MOVE (0);
11843 {
11844   {
11845     BI opval = 0;
11846     CPU (h_xbit) = opval;
11847     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11848   }
11849   {
11850     BI opval = 0;
11851     SET_H_INSN_PREFIXED_P (opval);
11852     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11853   }
11854 }
11855 }
11856 }
11857
11858 #undef FLD
11859 }
11860   NEXT (vpc);
11861
11862   CASE (sem, INSN_SETF) : /* setf ${list-of-flags} */
11863 {
11864   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11865   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11866 #define FLD(f) abuf->fields.sfmt_setf.f
11867   int UNUSED written = 0;
11868   IADDR UNUSED pc = abuf->addr;
11869   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11870
11871 {
11872   SI tmp_tmp;
11873   tmp_tmp = FLD (f_dstsrc);
11874 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
11875   {
11876     BI opval = 1;
11877     CPU (h_cbit) = opval;
11878     written |= (1 << 1);
11879     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
11880   }
11881 }
11882 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
11883   {
11884     BI opval = 1;
11885     CPU (h_vbit) = opval;
11886     written |= (1 << 7);
11887     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
11888   }
11889 }
11890 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
11891   {
11892     BI opval = 1;
11893     CPU (h_zbit) = opval;
11894     written |= (1 << 9);
11895     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11896   }
11897 }
11898 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
11899   {
11900     BI opval = 1;
11901     CPU (h_nbit) = opval;
11902     written |= (1 << 3);
11903     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11904   }
11905 }
11906 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
11907   {
11908     BI opval = 1;
11909     CPU (h_xbit) = opval;
11910     written |= (1 << 8);
11911     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11912   }
11913 }
11914 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
11915   {
11916     BI opval = 1;
11917     SET_H_IBIT (opval);
11918     written |= (1 << 2);
11919     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
11920   }
11921 }
11922 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
11923   {
11924     BI opval = 1;
11925     SET_H_UBIT (opval);
11926     written |= (1 << 6);
11927     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
11928   }
11929 }
11930 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
11931   {
11932     BI opval = 1;
11933     CPU (h_pbit) = opval;
11934     written |= (1 << 4);
11935     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
11936   }
11937 }
11938   {
11939     BI opval = 0;
11940     SET_H_INSN_PREFIXED_P (opval);
11941     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11942   }
11943 if (EQSI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
11944   {
11945     BI opval = 0;
11946     CPU (h_xbit) = opval;
11947     written |= (1 << 8);
11948     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11949   }
11950 }
11951 }
11952
11953   abuf->written = written;
11954 #undef FLD
11955 }
11956   NEXT (vpc);
11957
11958   CASE (sem, INSN_CLEARF) : /* clearf ${list-of-flags} */
11959 {
11960   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11961   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11962 #define FLD(f) abuf->fields.sfmt_setf.f
11963   int UNUSED written = 0;
11964   IADDR UNUSED pc = abuf->addr;
11965   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11966
11967 {
11968   SI tmp_tmp;
11969   tmp_tmp = FLD (f_dstsrc);
11970 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
11971   {
11972     BI opval = 0;
11973     CPU (h_cbit) = opval;
11974     written |= (1 << 1);
11975     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
11976   }
11977 }
11978 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
11979   {
11980     BI opval = 0;
11981     CPU (h_vbit) = opval;
11982     written |= (1 << 7);
11983     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
11984   }
11985 }
11986 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
11987   {
11988     BI opval = 0;
11989     CPU (h_zbit) = opval;
11990     written |= (1 << 9);
11991     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11992   }
11993 }
11994 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
11995   {
11996     BI opval = 0;
11997     CPU (h_nbit) = opval;
11998     written |= (1 << 3);
11999     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12000   }
12001 }
12002 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12003   {
12004     BI opval = 0;
12005     CPU (h_xbit) = opval;
12006     written |= (1 << 8);
12007     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12008   }
12009 }
12010 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
12011   {
12012     BI opval = 0;
12013     SET_H_IBIT (opval);
12014     written |= (1 << 2);
12015     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
12016   }
12017 }
12018 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
12019   {
12020     BI opval = 0;
12021     SET_H_UBIT (opval);
12022     written |= (1 << 6);
12023     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
12024   }
12025 }
12026 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
12027   {
12028     BI opval = 0;
12029     CPU (h_pbit) = opval;
12030     written |= (1 << 4);
12031     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
12032   }
12033 }
12034 {
12035   {
12036     BI opval = 0;
12037     CPU (h_xbit) = opval;
12038     written |= (1 << 8);
12039     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12040   }
12041   {
12042     BI opval = 0;
12043     SET_H_INSN_PREFIXED_P (opval);
12044     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12045   }
12046 }
12047 }
12048
12049   abuf->written = written;
12050 #undef FLD
12051 }
12052   NEXT (vpc);
12053
12054   CASE (sem, INSN_BCC_B) : /* b${cc} ${o-pcrel} */
12055 {
12056   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12057   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12058 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12059   int UNUSED written = 0;
12060   IADDR UNUSED pc = abuf->addr;
12061   SEM_BRANCH_INIT
12062   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12063
12064 {
12065   BI tmp_truthval;
12066   tmp_truthval = ({   SI tmp_tmpcond;
12067   BI tmp_condres;
12068   tmp_tmpcond = FLD (f_operand2);
12069 ; if (EQSI (tmp_tmpcond, 0)) {
12070   tmp_condres = NOTBI (CPU (h_cbit));
12071 }
12072  else if (EQSI (tmp_tmpcond, 1)) {
12073   tmp_condres = CPU (h_cbit);
12074 }
12075  else if (EQSI (tmp_tmpcond, 2)) {
12076   tmp_condres = NOTBI (CPU (h_zbit));
12077 }
12078  else if (EQSI (tmp_tmpcond, 3)) {
12079   tmp_condres = CPU (h_zbit);
12080 }
12081  else if (EQSI (tmp_tmpcond, 4)) {
12082   tmp_condres = NOTBI (CPU (h_vbit));
12083 }
12084  else if (EQSI (tmp_tmpcond, 5)) {
12085   tmp_condres = CPU (h_vbit);
12086 }
12087  else if (EQSI (tmp_tmpcond, 6)) {
12088   tmp_condres = NOTBI (CPU (h_nbit));
12089 }
12090  else if (EQSI (tmp_tmpcond, 7)) {
12091   tmp_condres = CPU (h_nbit);
12092 }
12093  else if (EQSI (tmp_tmpcond, 8)) {
12094   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12095 }
12096  else if (EQSI (tmp_tmpcond, 9)) {
12097   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12098 }
12099  else if (EQSI (tmp_tmpcond, 10)) {
12100   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12101 }
12102  else if (EQSI (tmp_tmpcond, 11)) {
12103   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12104 }
12105  else if (EQSI (tmp_tmpcond, 12)) {
12106   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12107 }
12108  else if (EQSI (tmp_tmpcond, 13)) {
12109   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12110 }
12111  else if (EQSI (tmp_tmpcond, 14)) {
12112   tmp_condres = 1;
12113 }
12114  else if (EQSI (tmp_tmpcond, 15)) {
12115   tmp_condres = CPU (h_pbit);
12116 }
12117 ; tmp_condres; });
12118 crisv10f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval);
12119 {
12120   {
12121     BI opval = 0;
12122     CPU (h_xbit) = opval;
12123     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12124   }
12125   {
12126     BI opval = 0;
12127     SET_H_INSN_PREFIXED_P (opval);
12128     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12129   }
12130 }
12131 if (tmp_truthval) {
12132 {
12133   {
12134     USI opval = FLD (i_o_pcrel);
12135     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12136     written |= (1 << 8);
12137     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12138   }
12139 }
12140 }
12141 }
12142
12143   abuf->written = written;
12144   SEM_BRANCH_FINI (vpc);
12145 #undef FLD
12146 }
12147   NEXT (vpc);
12148
12149   CASE (sem, INSN_BA_B) : /* ba ${o-pcrel} */
12150 {
12151   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12152   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12153 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12154   int UNUSED written = 0;
12155   IADDR UNUSED pc = abuf->addr;
12156   SEM_BRANCH_INIT
12157   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12158
12159 {
12160 {
12161   {
12162     BI opval = 0;
12163     CPU (h_xbit) = opval;
12164     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12165   }
12166   {
12167     BI opval = 0;
12168     SET_H_INSN_PREFIXED_P (opval);
12169     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12170   }
12171 }
12172 {
12173   {
12174     USI opval = FLD (i_o_pcrel);
12175     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12176     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12177   }
12178 }
12179 }
12180
12181   SEM_BRANCH_FINI (vpc);
12182 #undef FLD
12183 }
12184   NEXT (vpc);
12185
12186   CASE (sem, INSN_BCC_W) : /* b${cc} ${o-word-pcrel} */
12187 {
12188   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12189   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12190 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12191   int UNUSED written = 0;
12192   IADDR UNUSED pc = abuf->addr;
12193   SEM_BRANCH_INIT
12194   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12195
12196 {
12197   BI tmp_truthval;
12198   tmp_truthval = ({   SI tmp_tmpcond;
12199   BI tmp_condres;
12200   tmp_tmpcond = FLD (f_operand2);
12201 ; if (EQSI (tmp_tmpcond, 0)) {
12202   tmp_condres = NOTBI (CPU (h_cbit));
12203 }
12204  else if (EQSI (tmp_tmpcond, 1)) {
12205   tmp_condres = CPU (h_cbit);
12206 }
12207  else if (EQSI (tmp_tmpcond, 2)) {
12208   tmp_condres = NOTBI (CPU (h_zbit));
12209 }
12210  else if (EQSI (tmp_tmpcond, 3)) {
12211   tmp_condres = CPU (h_zbit);
12212 }
12213  else if (EQSI (tmp_tmpcond, 4)) {
12214   tmp_condres = NOTBI (CPU (h_vbit));
12215 }
12216  else if (EQSI (tmp_tmpcond, 5)) {
12217   tmp_condres = CPU (h_vbit);
12218 }
12219  else if (EQSI (tmp_tmpcond, 6)) {
12220   tmp_condres = NOTBI (CPU (h_nbit));
12221 }
12222  else if (EQSI (tmp_tmpcond, 7)) {
12223   tmp_condres = CPU (h_nbit);
12224 }
12225  else if (EQSI (tmp_tmpcond, 8)) {
12226   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12227 }
12228  else if (EQSI (tmp_tmpcond, 9)) {
12229   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12230 }
12231  else if (EQSI (tmp_tmpcond, 10)) {
12232   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12233 }
12234  else if (EQSI (tmp_tmpcond, 11)) {
12235   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12236 }
12237  else if (EQSI (tmp_tmpcond, 12)) {
12238   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12239 }
12240  else if (EQSI (tmp_tmpcond, 13)) {
12241   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12242 }
12243  else if (EQSI (tmp_tmpcond, 14)) {
12244   tmp_condres = 1;
12245 }
12246  else if (EQSI (tmp_tmpcond, 15)) {
12247   tmp_condres = CPU (h_pbit);
12248 }
12249 ; tmp_condres; });
12250 crisv10f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval);
12251 {
12252   {
12253     BI opval = 0;
12254     CPU (h_xbit) = opval;
12255     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12256   }
12257   {
12258     BI opval = 0;
12259     SET_H_INSN_PREFIXED_P (opval);
12260     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12261   }
12262 }
12263 if (tmp_truthval) {
12264 {
12265   {
12266     USI opval = FLD (i_o_word_pcrel);
12267     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12268     written |= (1 << 8);
12269     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12270   }
12271 }
12272 }
12273 }
12274
12275   abuf->written = written;
12276   SEM_BRANCH_FINI (vpc);
12277 #undef FLD
12278 }
12279   NEXT (vpc);
12280
12281   CASE (sem, INSN_BA_W) : /* ba ${o-word-pcrel} */
12282 {
12283   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12284   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12285 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12286   int UNUSED written = 0;
12287   IADDR UNUSED pc = abuf->addr;
12288   SEM_BRANCH_INIT
12289   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12290
12291 {
12292 {
12293   {
12294     BI opval = 0;
12295     CPU (h_xbit) = opval;
12296     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12297   }
12298   {
12299     BI opval = 0;
12300     SET_H_INSN_PREFIXED_P (opval);
12301     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12302   }
12303 }
12304 {
12305   {
12306     USI opval = FLD (i_o_word_pcrel);
12307     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12308     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12309   }
12310 }
12311 }
12312
12313   SEM_BRANCH_FINI (vpc);
12314 #undef FLD
12315 }
12316   NEXT (vpc);
12317
12318   CASE (sem, INSN_JUMP_R) : /* jump/jsr/jir ${Rs} */
12319 {
12320   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12321   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12322 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
12323   int UNUSED written = 0;
12324   IADDR UNUSED pc = abuf->addr;
12325   SEM_BRANCH_INIT
12326   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12327
12328 {
12329   {
12330     SI opval = ADDSI (pc, 2);
12331     SET_H_SR (FLD (f_operand2), opval);
12332     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12333   }
12334   {
12335     USI opval = GET_H_GR (FLD (f_operand1));
12336     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12337     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12338   }
12339 {
12340   {
12341     BI opval = 0;
12342     CPU (h_xbit) = opval;
12343     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12344   }
12345   {
12346     BI opval = 0;
12347     SET_H_INSN_PREFIXED_P (opval);
12348     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12349   }
12350 }
12351 }
12352
12353   SEM_BRANCH_FINI (vpc);
12354 #undef FLD
12355 }
12356   NEXT (vpc);
12357
12358   CASE (sem, INSN_JUMP_M) : /* jump/jsr/jir [${Rs}${inc}] */
12359 {
12360   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12361   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12362 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
12363   int UNUSED written = 0;
12364   IADDR UNUSED pc = abuf->addr;
12365   SEM_BRANCH_INIT
12366   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12367
12368 {
12369   {
12370     SI opval = ADDSI (pc, 2);
12371     SET_H_SR (FLD (f_operand2), opval);
12372     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12373   }
12374   {
12375     USI opval = ({   SI tmp_addr;
12376   SI tmp_tmp_mem;
12377   BI tmp_postinc;
12378   tmp_postinc = FLD (f_memmode);
12379 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12380 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
12381 ; if (NEBI (tmp_postinc, 0)) {
12382 {
12383 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12384   tmp_addr = ADDSI (tmp_addr, 4);
12385 }
12386   {
12387     SI opval = tmp_addr;
12388     SET_H_GR (FLD (f_operand1), opval);
12389     written |= (1 << 7);
12390     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12391   }
12392 }
12393 }
12394 ; tmp_tmp_mem; });
12395     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12396     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12397   }
12398 {
12399   {
12400     BI opval = 0;
12401     CPU (h_xbit) = opval;
12402     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12403   }
12404   {
12405     BI opval = 0;
12406     SET_H_INSN_PREFIXED_P (opval);
12407     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12408   }
12409 }
12410 }
12411
12412   abuf->written = written;
12413   SEM_BRANCH_FINI (vpc);
12414 #undef FLD
12415 }
12416   NEXT (vpc);
12417
12418   CASE (sem, INSN_JUMP_C) : /* jump/jsr/jir ${const32} */
12419 {
12420   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12421   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12422 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
12423   int UNUSED written = 0;
12424   IADDR UNUSED pc = abuf->addr;
12425   SEM_BRANCH_INIT
12426   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12427
12428 {
12429   {
12430     SI opval = ADDSI (pc, 6);
12431     SET_H_SR (FLD (f_operand2), opval);
12432     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12433   }
12434   {
12435     USI opval = FLD (f_indir_pc__dword);
12436     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12437     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12438   }
12439 {
12440   {
12441     BI opval = 0;
12442     CPU (h_xbit) = opval;
12443     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12444   }
12445   {
12446     BI opval = 0;
12447     SET_H_INSN_PREFIXED_P (opval);
12448     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12449   }
12450 }
12451 }
12452
12453   SEM_BRANCH_FINI (vpc);
12454 #undef FLD
12455 }
12456   NEXT (vpc);
12457
12458   CASE (sem, INSN_BREAK) : /* break $n */
12459 {
12460   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12461   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12462 #define FLD(f) abuf->fields.sfmt_break.f
12463   int UNUSED written = 0;
12464   IADDR UNUSED pc = abuf->addr;
12465   SEM_BRANCH_INIT
12466   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12467
12468 {
12469 {
12470   {
12471     BI opval = 0;
12472     CPU (h_xbit) = opval;
12473     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12474   }
12475   {
12476     BI opval = 0;
12477     SET_H_INSN_PREFIXED_P (opval);
12478     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12479   }
12480 }
12481   {
12482     USI opval = crisv10f_break_handler (current_cpu, FLD (f_u4), pc);
12483     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12484     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12485   }
12486 }
12487
12488   SEM_BRANCH_FINI (vpc);
12489 #undef FLD
12490 }
12491   NEXT (vpc);
12492
12493   CASE (sem, INSN_BOUND_R_B_R) : /* bound-r.b ${Rs},${Rd} */
12494 {
12495   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12496   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12497 #define FLD(f) abuf->fields.sfmt_muls_b.f
12498   int UNUSED written = 0;
12499   IADDR UNUSED pc = abuf->addr;
12500   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12501
12502 {
12503   SI tmp_tmpopd;
12504   SI tmp_tmpops;
12505   SI tmp_newval;
12506   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
12507   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12508   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12509   {
12510     SI opval = tmp_newval;
12511     SET_H_GR (FLD (f_operand2), opval);
12512     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12513   }
12514 {
12515   {
12516     BI opval = LTSI (tmp_newval, 0);
12517     CPU (h_nbit) = opval;
12518     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12519   }
12520   {
12521     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12522     CPU (h_zbit) = opval;
12523     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12524   }
12525 SET_H_CBIT_MOVE (0);
12526 SET_H_VBIT_MOVE (0);
12527 {
12528   {
12529     BI opval = 0;
12530     CPU (h_xbit) = opval;
12531     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12532   }
12533   {
12534     BI opval = 0;
12535     SET_H_INSN_PREFIXED_P (opval);
12536     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12537   }
12538 }
12539 }
12540 }
12541
12542 #undef FLD
12543 }
12544   NEXT (vpc);
12545
12546   CASE (sem, INSN_BOUND_R_W_R) : /* bound-r.w ${Rs},${Rd} */
12547 {
12548   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12549   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12550 #define FLD(f) abuf->fields.sfmt_muls_b.f
12551   int UNUSED written = 0;
12552   IADDR UNUSED pc = abuf->addr;
12553   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12554
12555 {
12556   SI tmp_tmpopd;
12557   SI tmp_tmpops;
12558   SI tmp_newval;
12559   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
12560   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12561   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12562   {
12563     SI opval = tmp_newval;
12564     SET_H_GR (FLD (f_operand2), opval);
12565     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12566   }
12567 {
12568   {
12569     BI opval = LTSI (tmp_newval, 0);
12570     CPU (h_nbit) = opval;
12571     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12572   }
12573   {
12574     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12575     CPU (h_zbit) = opval;
12576     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12577   }
12578 SET_H_CBIT_MOVE (0);
12579 SET_H_VBIT_MOVE (0);
12580 {
12581   {
12582     BI opval = 0;
12583     CPU (h_xbit) = opval;
12584     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12585   }
12586   {
12587     BI opval = 0;
12588     SET_H_INSN_PREFIXED_P (opval);
12589     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12590   }
12591 }
12592 }
12593 }
12594
12595 #undef FLD
12596 }
12597   NEXT (vpc);
12598
12599   CASE (sem, INSN_BOUND_R_D_R) : /* bound-r.d ${Rs},${Rd} */
12600 {
12601   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12602   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12603 #define FLD(f) abuf->fields.sfmt_muls_b.f
12604   int UNUSED written = 0;
12605   IADDR UNUSED pc = abuf->addr;
12606   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12607
12608 {
12609   SI tmp_tmpopd;
12610   SI tmp_tmpops;
12611   SI tmp_newval;
12612   tmp_tmpops = TRUNCSISI (GET_H_GR (FLD (f_operand1)));
12613   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12614   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12615   {
12616     SI opval = tmp_newval;
12617     SET_H_GR (FLD (f_operand2), opval);
12618     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12619   }
12620 {
12621   {
12622     BI opval = LTSI (tmp_newval, 0);
12623     CPU (h_nbit) = opval;
12624     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12625   }
12626   {
12627     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12628     CPU (h_zbit) = opval;
12629     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12630   }
12631 SET_H_CBIT_MOVE (0);
12632 SET_H_VBIT_MOVE (0);
12633 {
12634   {
12635     BI opval = 0;
12636     CPU (h_xbit) = opval;
12637     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12638   }
12639   {
12640     BI opval = 0;
12641     SET_H_INSN_PREFIXED_P (opval);
12642     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12643   }
12644 }
12645 }
12646 }
12647
12648 #undef FLD
12649 }
12650   NEXT (vpc);
12651
12652   CASE (sem, INSN_BOUND_M_B_M) : /* bound-m.b [${Rs}${inc}],${Rd} */
12653 {
12654   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12655   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12656 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
12657   int UNUSED written = 0;
12658   IADDR UNUSED pc = abuf->addr;
12659   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12660
12661 {
12662   SI tmp_tmpopd;
12663   SI tmp_tmpops;
12664   SI tmp_newval;
12665   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
12666   QI tmp_tmp_mem;
12667   BI tmp_postinc;
12668   tmp_postinc = FLD (f_memmode);
12669 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12670 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
12671 ; if (NEBI (tmp_postinc, 0)) {
12672 {
12673 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12674   tmp_addr = ADDSI (tmp_addr, 1);
12675 }
12676   {
12677     SI opval = tmp_addr;
12678     SET_H_GR (FLD (f_operand1), opval);
12679     written |= (1 << 9);
12680     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12681   }
12682 }
12683 }
12684 ; tmp_tmp_mem; }));
12685   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12686   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12687 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
12688   {
12689     SI opval = tmp_newval;
12690     SET_H_GR (FLD (f_operand1), opval);
12691     written |= (1 << 9);
12692     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12693   }
12694 } else {
12695   {
12696     SI opval = tmp_newval;
12697     SET_H_GR (FLD (f_operand2), opval);
12698     written |= (1 << 8);
12699     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12700   }
12701 }
12702 {
12703   {
12704     BI opval = LTSI (tmp_newval, 0);
12705     CPU (h_nbit) = opval;
12706     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12707   }
12708   {
12709     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12710     CPU (h_zbit) = opval;
12711     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12712   }
12713 SET_H_CBIT_MOVE (0);
12714 SET_H_VBIT_MOVE (0);
12715 {
12716   {
12717     BI opval = 0;
12718     CPU (h_xbit) = opval;
12719     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12720   }
12721   {
12722     BI opval = 0;
12723     SET_H_INSN_PREFIXED_P (opval);
12724     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12725   }
12726 }
12727 }
12728 }
12729
12730   abuf->written = written;
12731 #undef FLD
12732 }
12733   NEXT (vpc);
12734
12735   CASE (sem, INSN_BOUND_M_W_M) : /* bound-m.w [${Rs}${inc}],${Rd} */
12736 {
12737   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12738   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12739 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
12740   int UNUSED written = 0;
12741   IADDR UNUSED pc = abuf->addr;
12742   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12743
12744 {
12745   SI tmp_tmpopd;
12746   SI tmp_tmpops;
12747   SI tmp_newval;
12748   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
12749   HI tmp_tmp_mem;
12750   BI tmp_postinc;
12751   tmp_postinc = FLD (f_memmode);
12752 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12753 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
12754 ; if (NEBI (tmp_postinc, 0)) {
12755 {
12756 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12757   tmp_addr = ADDSI (tmp_addr, 2);
12758 }
12759   {
12760     SI opval = tmp_addr;
12761     SET_H_GR (FLD (f_operand1), opval);
12762     written |= (1 << 9);
12763     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12764   }
12765 }
12766 }
12767 ; tmp_tmp_mem; }));
12768   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12769   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12770 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
12771   {
12772     SI opval = tmp_newval;
12773     SET_H_GR (FLD (f_operand1), opval);
12774     written |= (1 << 9);
12775     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12776   }
12777 } else {
12778   {
12779     SI opval = tmp_newval;
12780     SET_H_GR (FLD (f_operand2), opval);
12781     written |= (1 << 8);
12782     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12783   }
12784 }
12785 {
12786   {
12787     BI opval = LTSI (tmp_newval, 0);
12788     CPU (h_nbit) = opval;
12789     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12790   }
12791   {
12792     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12793     CPU (h_zbit) = opval;
12794     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12795   }
12796 SET_H_CBIT_MOVE (0);
12797 SET_H_VBIT_MOVE (0);
12798 {
12799   {
12800     BI opval = 0;
12801     CPU (h_xbit) = opval;
12802     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12803   }
12804   {
12805     BI opval = 0;
12806     SET_H_INSN_PREFIXED_P (opval);
12807     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12808   }
12809 }
12810 }
12811 }
12812
12813   abuf->written = written;
12814 #undef FLD
12815 }
12816   NEXT (vpc);
12817
12818   CASE (sem, INSN_BOUND_M_D_M) : /* bound-m.d [${Rs}${inc}],${Rd} */
12819 {
12820   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12821   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12822 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
12823   int UNUSED written = 0;
12824   IADDR UNUSED pc = abuf->addr;
12825   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12826
12827 {
12828   SI tmp_tmpopd;
12829   SI tmp_tmpops;
12830   SI tmp_newval;
12831   tmp_tmpops = ({   SI tmp_addr;
12832   SI tmp_tmp_mem;
12833   BI tmp_postinc;
12834   tmp_postinc = FLD (f_memmode);
12835 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12836 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
12837 ; if (NEBI (tmp_postinc, 0)) {
12838 {
12839 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12840   tmp_addr = ADDSI (tmp_addr, 4);
12841 }
12842   {
12843     SI opval = tmp_addr;
12844     SET_H_GR (FLD (f_operand1), opval);
12845     written |= (1 << 9);
12846     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12847   }
12848 }
12849 }
12850 ; tmp_tmp_mem; });
12851   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12852   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12853 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
12854   {
12855     SI opval = tmp_newval;
12856     SET_H_GR (FLD (f_operand1), opval);
12857     written |= (1 << 9);
12858     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12859   }
12860 } else {
12861   {
12862     SI opval = tmp_newval;
12863     SET_H_GR (FLD (f_operand2), opval);
12864     written |= (1 << 8);
12865     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12866   }
12867 }
12868 {
12869   {
12870     BI opval = LTSI (tmp_newval, 0);
12871     CPU (h_nbit) = opval;
12872     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12873   }
12874   {
12875     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12876     CPU (h_zbit) = opval;
12877     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12878   }
12879 SET_H_CBIT_MOVE (0);
12880 SET_H_VBIT_MOVE (0);
12881 {
12882   {
12883     BI opval = 0;
12884     CPU (h_xbit) = opval;
12885     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12886   }
12887   {
12888     BI opval = 0;
12889     SET_H_INSN_PREFIXED_P (opval);
12890     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12891   }
12892 }
12893 }
12894 }
12895
12896   abuf->written = written;
12897 #undef FLD
12898 }
12899   NEXT (vpc);
12900
12901   CASE (sem, INSN_BOUND_CB) : /* bound.b [PC+],${Rd} */
12902 {
12903   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12904   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12905 #define FLD(f) abuf->fields.sfmt_bound_cb.f
12906   int UNUSED written = 0;
12907   IADDR UNUSED pc = abuf->addr;
12908   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12909
12910 {
12911   SI tmp_tmpopd;
12912   SI tmp_tmpops;
12913   SI tmp_newval;
12914   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
12915   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12916   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12917   {
12918     SI opval = tmp_newval;
12919     SET_H_GR (FLD (f_operand2), opval);
12920     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12921   }
12922 {
12923   {
12924     BI opval = LTSI (tmp_newval, 0);
12925     CPU (h_nbit) = opval;
12926     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12927   }
12928   {
12929     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12930     CPU (h_zbit) = opval;
12931     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12932   }
12933 SET_H_CBIT_MOVE (0);
12934 SET_H_VBIT_MOVE (0);
12935 {
12936   {
12937     BI opval = 0;
12938     CPU (h_xbit) = opval;
12939     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12940   }
12941   {
12942     BI opval = 0;
12943     SET_H_INSN_PREFIXED_P (opval);
12944     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12945   }
12946 }
12947 }
12948 }
12949
12950 #undef FLD
12951 }
12952   NEXT (vpc);
12953
12954   CASE (sem, INSN_BOUND_CW) : /* bound.w [PC+],${Rd} */
12955 {
12956   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12957   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12958 #define FLD(f) abuf->fields.sfmt_bound_cw.f
12959   int UNUSED written = 0;
12960   IADDR UNUSED pc = abuf->addr;
12961   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12962
12963 {
12964   SI tmp_tmpopd;
12965   SI tmp_tmpops;
12966   SI tmp_newval;
12967   tmp_tmpops = ZEXTSISI (FLD (f_indir_pc__word));
12968   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12969   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12970   {
12971     SI opval = tmp_newval;
12972     SET_H_GR (FLD (f_operand2), opval);
12973     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12974   }
12975 {
12976   {
12977     BI opval = LTSI (tmp_newval, 0);
12978     CPU (h_nbit) = opval;
12979     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12980   }
12981   {
12982     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12983     CPU (h_zbit) = opval;
12984     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12985   }
12986 SET_H_CBIT_MOVE (0);
12987 SET_H_VBIT_MOVE (0);
12988 {
12989   {
12990     BI opval = 0;
12991     CPU (h_xbit) = opval;
12992     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12993   }
12994   {
12995     BI opval = 0;
12996     SET_H_INSN_PREFIXED_P (opval);
12997     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12998   }
12999 }
13000 }
13001 }
13002
13003 #undef FLD
13004 }
13005   NEXT (vpc);
13006
13007   CASE (sem, INSN_BOUND_CD) : /* bound.d [PC+],${Rd} */
13008 {
13009   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13010   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13011 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13012   int UNUSED written = 0;
13013   IADDR UNUSED pc = abuf->addr;
13014   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13015
13016 {
13017   SI tmp_tmpopd;
13018   SI tmp_tmpops;
13019   SI tmp_newval;
13020   tmp_tmpops = FLD (f_indir_pc__dword);
13021   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13022   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13023   {
13024     SI opval = tmp_newval;
13025     SET_H_GR (FLD (f_operand2), opval);
13026     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13027   }
13028 {
13029   {
13030     BI opval = LTSI (tmp_newval, 0);
13031     CPU (h_nbit) = opval;
13032     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13033   }
13034   {
13035     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13036     CPU (h_zbit) = opval;
13037     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13038   }
13039 SET_H_CBIT_MOVE (0);
13040 SET_H_VBIT_MOVE (0);
13041 {
13042   {
13043     BI opval = 0;
13044     CPU (h_xbit) = opval;
13045     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13046   }
13047   {
13048     BI opval = 0;
13049     SET_H_INSN_PREFIXED_P (opval);
13050     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13051   }
13052 }
13053 }
13054 }
13055
13056 #undef FLD
13057 }
13058   NEXT (vpc);
13059
13060   CASE (sem, INSN_SCC) : /* s${cc} ${Rd-sfield} */
13061 {
13062   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13063   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13064 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
13065   int UNUSED written = 0;
13066   IADDR UNUSED pc = abuf->addr;
13067   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13068
13069 {
13070   BI tmp_truthval;
13071   tmp_truthval = ({   SI tmp_tmpcond;
13072   BI tmp_condres;
13073   tmp_tmpcond = FLD (f_operand2);
13074 ; if (EQSI (tmp_tmpcond, 0)) {
13075   tmp_condres = NOTBI (CPU (h_cbit));
13076 }
13077  else if (EQSI (tmp_tmpcond, 1)) {
13078   tmp_condres = CPU (h_cbit);
13079 }
13080  else if (EQSI (tmp_tmpcond, 2)) {
13081   tmp_condres = NOTBI (CPU (h_zbit));
13082 }
13083  else if (EQSI (tmp_tmpcond, 3)) {
13084   tmp_condres = CPU (h_zbit);
13085 }
13086  else if (EQSI (tmp_tmpcond, 4)) {
13087   tmp_condres = NOTBI (CPU (h_vbit));
13088 }
13089  else if (EQSI (tmp_tmpcond, 5)) {
13090   tmp_condres = CPU (h_vbit);
13091 }
13092  else if (EQSI (tmp_tmpcond, 6)) {
13093   tmp_condres = NOTBI (CPU (h_nbit));
13094 }
13095  else if (EQSI (tmp_tmpcond, 7)) {
13096   tmp_condres = CPU (h_nbit);
13097 }
13098  else if (EQSI (tmp_tmpcond, 8)) {
13099   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
13100 }
13101  else if (EQSI (tmp_tmpcond, 9)) {
13102   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
13103 }
13104  else if (EQSI (tmp_tmpcond, 10)) {
13105   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
13106 }
13107  else if (EQSI (tmp_tmpcond, 11)) {
13108   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
13109 }
13110  else if (EQSI (tmp_tmpcond, 12)) {
13111   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
13112 }
13113  else if (EQSI (tmp_tmpcond, 13)) {
13114   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
13115 }
13116  else if (EQSI (tmp_tmpcond, 14)) {
13117   tmp_condres = 1;
13118 }
13119  else if (EQSI (tmp_tmpcond, 15)) {
13120   tmp_condres = CPU (h_pbit);
13121 }
13122 ; tmp_condres; });
13123   {
13124     SI opval = ZEXTBISI (tmp_truthval);
13125     SET_H_GR (FLD (f_operand1), opval);
13126     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13127   }
13128 {
13129   {
13130     BI opval = 0;
13131     CPU (h_xbit) = opval;
13132     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13133   }
13134   {
13135     BI opval = 0;
13136     SET_H_INSN_PREFIXED_P (opval);
13137     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13138   }
13139 }
13140 }
13141
13142 #undef FLD
13143 }
13144   NEXT (vpc);
13145
13146   CASE (sem, INSN_LZ) : /* lz ${Rs},${Rd} */
13147 {
13148   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13149   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13150 #define FLD(f) abuf->fields.sfmt_muls_b.f
13151   int UNUSED written = 0;
13152   IADDR UNUSED pc = abuf->addr;
13153   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13154
13155 {
13156   SI tmp_tmpd;
13157   SI tmp_tmp;
13158   tmp_tmp = GET_H_GR (FLD (f_operand1));
13159   tmp_tmpd = 0;
13160 {
13161 if (GESI (tmp_tmp, 0)) {
13162 {
13163   tmp_tmp = SLLSI (tmp_tmp, 1);
13164   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13165 }
13166 }
13167 if (GESI (tmp_tmp, 0)) {
13168 {
13169   tmp_tmp = SLLSI (tmp_tmp, 1);
13170   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13171 }
13172 }
13173 if (GESI (tmp_tmp, 0)) {
13174 {
13175   tmp_tmp = SLLSI (tmp_tmp, 1);
13176   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13177 }
13178 }
13179 if (GESI (tmp_tmp, 0)) {
13180 {
13181   tmp_tmp = SLLSI (tmp_tmp, 1);
13182   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13183 }
13184 }
13185 if (GESI (tmp_tmp, 0)) {
13186 {
13187   tmp_tmp = SLLSI (tmp_tmp, 1);
13188   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13189 }
13190 }
13191 if (GESI (tmp_tmp, 0)) {
13192 {
13193   tmp_tmp = SLLSI (tmp_tmp, 1);
13194   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13195 }
13196 }
13197 if (GESI (tmp_tmp, 0)) {
13198 {
13199   tmp_tmp = SLLSI (tmp_tmp, 1);
13200   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13201 }
13202 }
13203 if (GESI (tmp_tmp, 0)) {
13204 {
13205   tmp_tmp = SLLSI (tmp_tmp, 1);
13206   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13207 }
13208 }
13209 if (GESI (tmp_tmp, 0)) {
13210 {
13211   tmp_tmp = SLLSI (tmp_tmp, 1);
13212   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13213 }
13214 }
13215 if (GESI (tmp_tmp, 0)) {
13216 {
13217   tmp_tmp = SLLSI (tmp_tmp, 1);
13218   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13219 }
13220 }
13221 if (GESI (tmp_tmp, 0)) {
13222 {
13223   tmp_tmp = SLLSI (tmp_tmp, 1);
13224   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13225 }
13226 }
13227 if (GESI (tmp_tmp, 0)) {
13228 {
13229   tmp_tmp = SLLSI (tmp_tmp, 1);
13230   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13231 }
13232 }
13233 if (GESI (tmp_tmp, 0)) {
13234 {
13235   tmp_tmp = SLLSI (tmp_tmp, 1);
13236   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13237 }
13238 }
13239 if (GESI (tmp_tmp, 0)) {
13240 {
13241   tmp_tmp = SLLSI (tmp_tmp, 1);
13242   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13243 }
13244 }
13245 if (GESI (tmp_tmp, 0)) {
13246 {
13247   tmp_tmp = SLLSI (tmp_tmp, 1);
13248   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13249 }
13250 }
13251 if (GESI (tmp_tmp, 0)) {
13252 {
13253   tmp_tmp = SLLSI (tmp_tmp, 1);
13254   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13255 }
13256 }
13257 if (GESI (tmp_tmp, 0)) {
13258 {
13259   tmp_tmp = SLLSI (tmp_tmp, 1);
13260   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13261 }
13262 }
13263 if (GESI (tmp_tmp, 0)) {
13264 {
13265   tmp_tmp = SLLSI (tmp_tmp, 1);
13266   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13267 }
13268 }
13269 if (GESI (tmp_tmp, 0)) {
13270 {
13271   tmp_tmp = SLLSI (tmp_tmp, 1);
13272   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13273 }
13274 }
13275 if (GESI (tmp_tmp, 0)) {
13276 {
13277   tmp_tmp = SLLSI (tmp_tmp, 1);
13278   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13279 }
13280 }
13281 if (GESI (tmp_tmp, 0)) {
13282 {
13283   tmp_tmp = SLLSI (tmp_tmp, 1);
13284   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13285 }
13286 }
13287 if (GESI (tmp_tmp, 0)) {
13288 {
13289   tmp_tmp = SLLSI (tmp_tmp, 1);
13290   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13291 }
13292 }
13293 if (GESI (tmp_tmp, 0)) {
13294 {
13295   tmp_tmp = SLLSI (tmp_tmp, 1);
13296   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13297 }
13298 }
13299 if (GESI (tmp_tmp, 0)) {
13300 {
13301   tmp_tmp = SLLSI (tmp_tmp, 1);
13302   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13303 }
13304 }
13305 if (GESI (tmp_tmp, 0)) {
13306 {
13307   tmp_tmp = SLLSI (tmp_tmp, 1);
13308   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13309 }
13310 }
13311 if (GESI (tmp_tmp, 0)) {
13312 {
13313   tmp_tmp = SLLSI (tmp_tmp, 1);
13314   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13315 }
13316 }
13317 if (GESI (tmp_tmp, 0)) {
13318 {
13319   tmp_tmp = SLLSI (tmp_tmp, 1);
13320   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13321 }
13322 }
13323 if (GESI (tmp_tmp, 0)) {
13324 {
13325   tmp_tmp = SLLSI (tmp_tmp, 1);
13326   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13327 }
13328 }
13329 if (GESI (tmp_tmp, 0)) {
13330 {
13331   tmp_tmp = SLLSI (tmp_tmp, 1);
13332   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13333 }
13334 }
13335 if (GESI (tmp_tmp, 0)) {
13336 {
13337   tmp_tmp = SLLSI (tmp_tmp, 1);
13338   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13339 }
13340 }
13341 if (GESI (tmp_tmp, 0)) {
13342 {
13343   tmp_tmp = SLLSI (tmp_tmp, 1);
13344   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13345 }
13346 }
13347 if (GESI (tmp_tmp, 0)) {
13348 {
13349   tmp_tmp = SLLSI (tmp_tmp, 1);
13350   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13351 }
13352 }
13353 }
13354   {
13355     SI opval = tmp_tmpd;
13356     SET_H_GR (FLD (f_operand2), opval);
13357     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13358   }
13359 {
13360   {
13361     BI opval = LTSI (tmp_tmpd, 0);
13362     CPU (h_nbit) = opval;
13363     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13364   }
13365   {
13366     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13367     CPU (h_zbit) = opval;
13368     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13369   }
13370 SET_H_CBIT_MOVE (0);
13371 SET_H_VBIT_MOVE (0);
13372 {
13373   {
13374     BI opval = 0;
13375     CPU (h_xbit) = opval;
13376     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13377   }
13378   {
13379     BI opval = 0;
13380     SET_H_INSN_PREFIXED_P (opval);
13381     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13382   }
13383 }
13384 }
13385 }
13386
13387 #undef FLD
13388 }
13389   NEXT (vpc);
13390
13391   CASE (sem, INSN_ADDOQ) : /* addoq $o,$Rs,ACR */
13392 {
13393   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13394   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13395 #define FLD(f) abuf->fields.sfmt_addoq.f
13396   int UNUSED written = 0;
13397   IADDR UNUSED pc = abuf->addr;
13398   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13399
13400 {
13401   {
13402     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s8));
13403     CPU (h_prefixreg_pre_v32) = opval;
13404     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13405   }
13406   {
13407     BI opval = 1;
13408     SET_H_INSN_PREFIXED_P (opval);
13409     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13410   }
13411 }
13412
13413 #undef FLD
13414 }
13415   NEXT (vpc);
13416
13417   CASE (sem, INSN_BDAPQPC) : /* bdapq $o,PC */
13418 {
13419   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13420   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13421 #define FLD(f) abuf->fields.sfmt_addoq.f
13422   int UNUSED written = 0;
13423   IADDR UNUSED pc = abuf->addr;
13424   SEM_BRANCH_INIT
13425   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13426
13427 {
13428   {
13429     SI opval = ADDSI (ADDSI (pc, 2), FLD (f_s8));
13430     CPU (h_prefixreg_pre_v32) = opval;
13431     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13432   }
13433   {
13434     BI opval = 1;
13435     SET_H_INSN_PREFIXED_P (opval);
13436     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13437   }
13438 cris_flush_simulator_decode_cache (current_cpu, pc);
13439 }
13440
13441   SEM_BRANCH_FINI (vpc);
13442 #undef FLD
13443 }
13444   NEXT (vpc);
13445
13446   CASE (sem, INSN_BDAP_32_PC) : /* bdap ${sconst32},PC */
13447 {
13448   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13449   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13450 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
13451   int UNUSED written = 0;
13452   IADDR UNUSED pc = abuf->addr;
13453   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13454
13455 {
13456   SI tmp_newpc;
13457   SI tmp_oldpc;
13458   SI tmp_offs;
13459   tmp_offs = FLD (f_indir_pc__dword);
13460   tmp_oldpc = ADDSI (pc, 6);
13461   tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
13462   {
13463     SI opval = tmp_newpc;
13464     CPU (h_prefixreg_pre_v32) = opval;
13465     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13466   }
13467   {
13468     BI opval = 1;
13469     SET_H_INSN_PREFIXED_P (opval);
13470     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13471   }
13472 }
13473
13474 #undef FLD
13475 }
13476   NEXT (vpc);
13477
13478   CASE (sem, INSN_MOVE_M_PCPLUS_P0) : /* move [PC+],P0 */
13479 {
13480   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13481   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13482 #define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f
13483   int UNUSED written = 0;
13484   IADDR UNUSED pc = abuf->addr;
13485   SEM_BRANCH_INIT
13486   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13487
13488 if (GET_H_INSN_PREFIXED_P ()) {
13489 {
13490   QI tmp_dummy;
13491   tmp_dummy = ({   SI tmp_addr;
13492   QI tmp_tmp_mem;
13493   BI tmp_postinc;
13494   tmp_postinc = FLD (f_memmode);
13495 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (pc) : (CPU (h_prefixreg_pre_v32)));
13496 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
13497 ; if (NEBI (tmp_postinc, 0)) {
13498 {
13499 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13500   tmp_addr = ADDSI (tmp_addr, 1);
13501 }
13502   {
13503     USI opval = tmp_addr;
13504     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13505     written |= (1 << 5);
13506     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13507   }
13508 }
13509 }
13510 ; tmp_tmp_mem; });
13511 {
13512   {
13513     BI opval = 0;
13514     CPU (h_xbit) = opval;
13515     written |= (1 << 7);
13516     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13517   }
13518   {
13519     BI opval = 0;
13520     SET_H_INSN_PREFIXED_P (opval);
13521     written |= (1 << 6);
13522     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13523   }
13524 }
13525 }
13526 } else {
13527 cgen_rtx_error (current_cpu, "move [PC+],P0 without prefix is not implemented");
13528 }
13529
13530   abuf->written = written;
13531   SEM_BRANCH_FINI (vpc);
13532 #undef FLD
13533 }
13534   NEXT (vpc);
13535
13536   CASE (sem, INSN_MOVE_M_SPPLUS_P8) : /* move [SP+],P8 */
13537 {
13538   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13539   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13540 #define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f
13541   int UNUSED written = 0;
13542   IADDR UNUSED pc = abuf->addr;
13543   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13544
13545 if (GET_H_INSN_PREFIXED_P ()) {
13546 {
13547   SI tmp_dummy;
13548   tmp_dummy = ({   SI tmp_addr;
13549   SI tmp_tmp_mem;
13550   BI tmp_postinc;
13551   tmp_postinc = FLD (f_memmode);
13552 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (((UINT) 14))) : (CPU (h_prefixreg_pre_v32)));
13553 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13554 ; if (NEBI (tmp_postinc, 0)) {
13555 {
13556 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13557   tmp_addr = ADDSI (tmp_addr, 4);
13558 }
13559   {
13560     SI opval = tmp_addr;
13561     SET_H_GR (((UINT) 14), opval);
13562     written |= (1 << 5);
13563     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13564   }
13565 }
13566 }
13567 ; tmp_tmp_mem; });
13568 {
13569   {
13570     BI opval = 0;
13571     CPU (h_xbit) = opval;
13572     written |= (1 << 7);
13573     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13574   }
13575   {
13576     BI opval = 0;
13577     SET_H_INSN_PREFIXED_P (opval);
13578     written |= (1 << 6);
13579     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13580   }
13581 }
13582 }
13583 } else {
13584 cgen_rtx_error (current_cpu, "move [SP+],P8 without prefix is not implemented");
13585 }
13586
13587   abuf->written = written;
13588 #undef FLD
13589 }
13590   NEXT (vpc);
13591
13592   CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */
13593 {
13594   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13595   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13596 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
13597   int UNUSED written = 0;
13598   IADDR UNUSED pc = abuf->addr;
13599   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13600
13601 {
13602   QI tmp_tmps;
13603   tmp_tmps = ({   SI tmp_addr;
13604   QI tmp_tmp_mem;
13605   BI tmp_postinc;
13606   tmp_postinc = FLD (f_memmode);
13607 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13608 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
13609 ; if (NEBI (tmp_postinc, 0)) {
13610 {
13611 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13612   tmp_addr = ADDSI (tmp_addr, 1);
13613 }
13614   {
13615     SI opval = tmp_addr;
13616     SET_H_GR (FLD (f_operand1), opval);
13617     written |= (1 << 6);
13618     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13619   }
13620 }
13621 }
13622 ; tmp_tmp_mem; });
13623   {
13624     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (tmp_tmps));
13625     CPU (h_prefixreg_pre_v32) = opval;
13626     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13627   }
13628   {
13629     BI opval = 1;
13630     SET_H_INSN_PREFIXED_P (opval);
13631     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13632   }
13633 }
13634
13635   abuf->written = written;
13636 #undef FLD
13637 }
13638   NEXT (vpc);
13639
13640   CASE (sem, INSN_ADDO_M_W_M) : /* addo-m.w [${Rs}${inc}],$Rd,ACR */
13641 {
13642   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13643   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13644 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
13645   int UNUSED written = 0;
13646   IADDR UNUSED pc = abuf->addr;
13647   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13648
13649 {
13650   HI tmp_tmps;
13651   tmp_tmps = ({   SI tmp_addr;
13652   HI tmp_tmp_mem;
13653   BI tmp_postinc;
13654   tmp_postinc = FLD (f_memmode);
13655 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13656 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
13657 ; if (NEBI (tmp_postinc, 0)) {
13658 {
13659 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13660   tmp_addr = ADDSI (tmp_addr, 2);
13661 }
13662   {
13663     SI opval = tmp_addr;
13664     SET_H_GR (FLD (f_operand1), opval);
13665     written |= (1 << 6);
13666     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13667   }
13668 }
13669 }
13670 ; tmp_tmp_mem; });
13671   {
13672     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (tmp_tmps));
13673     CPU (h_prefixreg_pre_v32) = opval;
13674     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13675   }
13676   {
13677     BI opval = 1;
13678     SET_H_INSN_PREFIXED_P (opval);
13679     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13680   }
13681 }
13682
13683   abuf->written = written;
13684 #undef FLD
13685 }
13686   NEXT (vpc);
13687
13688   CASE (sem, INSN_ADDO_M_D_M) : /* addo-m.d [${Rs}${inc}],$Rd,ACR */
13689 {
13690   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13691   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13692 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
13693   int UNUSED written = 0;
13694   IADDR UNUSED pc = abuf->addr;
13695   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13696
13697 {
13698   SI tmp_tmps;
13699   tmp_tmps = ({   SI tmp_addr;
13700   SI tmp_tmp_mem;
13701   BI tmp_postinc;
13702   tmp_postinc = FLD (f_memmode);
13703 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13704 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13705 ; if (NEBI (tmp_postinc, 0)) {
13706 {
13707 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13708   tmp_addr = ADDSI (tmp_addr, 4);
13709 }
13710   {
13711     SI opval = tmp_addr;
13712     SET_H_GR (FLD (f_operand1), opval);
13713     written |= (1 << 6);
13714     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13715   }
13716 }
13717 }
13718 ; tmp_tmp_mem; });
13719   {
13720     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), tmp_tmps);
13721     CPU (h_prefixreg_pre_v32) = opval;
13722     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13723   }
13724   {
13725     BI opval = 1;
13726     SET_H_INSN_PREFIXED_P (opval);
13727     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13728   }
13729 }
13730
13731   abuf->written = written;
13732 #undef FLD
13733 }
13734   NEXT (vpc);
13735
13736   CASE (sem, INSN_ADDO_CB) : /* addo.b [PC+],$Rd,ACR */
13737 {
13738   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13739   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13740 #define FLD(f) abuf->fields.sfmt_bound_cb.f
13741   int UNUSED written = 0;
13742   IADDR UNUSED pc = abuf->addr;
13743   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13744
13745 {
13746   {
13747     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))));
13748     CPU (h_prefixreg_pre_v32) = opval;
13749     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13750   }
13751   {
13752     BI opval = 1;
13753     SET_H_INSN_PREFIXED_P (opval);
13754     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13755   }
13756 }
13757
13758 #undef FLD
13759 }
13760   NEXT (vpc);
13761
13762   CASE (sem, INSN_ADDO_CW) : /* addo.w [PC+],$Rd,ACR */
13763 {
13764   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13765   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13766 #define FLD(f) abuf->fields.sfmt_bound_cw.f
13767   int UNUSED written = 0;
13768   IADDR UNUSED pc = abuf->addr;
13769   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13770
13771 {
13772   {
13773     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))));
13774     CPU (h_prefixreg_pre_v32) = opval;
13775     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13776   }
13777   {
13778     BI opval = 1;
13779     SET_H_INSN_PREFIXED_P (opval);
13780     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13781   }
13782 }
13783
13784 #undef FLD
13785 }
13786   NEXT (vpc);
13787
13788   CASE (sem, INSN_ADDO_CD) : /* addo.d [PC+],$Rd,ACR */
13789 {
13790   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13791   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13792 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13793   int UNUSED written = 0;
13794   IADDR UNUSED pc = abuf->addr;
13795   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13796
13797 {
13798   {
13799     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
13800     CPU (h_prefixreg_pre_v32) = opval;
13801     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13802   }
13803   {
13804     BI opval = 1;
13805     SET_H_INSN_PREFIXED_P (opval);
13806     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13807   }
13808 }
13809
13810 #undef FLD
13811 }
13812   NEXT (vpc);
13813
13814   CASE (sem, INSN_DIP_M) : /* dip [${Rs}${inc}] */
13815 {
13816   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13817   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13818 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
13819   int UNUSED written = 0;
13820   IADDR UNUSED pc = abuf->addr;
13821   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13822
13823 {
13824   SI tmp_tmps;
13825   tmp_tmps = ({   SI tmp_addr;
13826   SI tmp_tmp_mem;
13827   BI tmp_postinc;
13828   tmp_postinc = FLD (f_memmode);
13829 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13830 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13831 ; if (NEBI (tmp_postinc, 0)) {
13832 {
13833 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13834   tmp_addr = ADDSI (tmp_addr, 4);
13835 }
13836   {
13837     SI opval = tmp_addr;
13838     SET_H_GR (FLD (f_operand1), opval);
13839     written |= (1 << 5);
13840     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13841   }
13842 }
13843 }
13844 ; tmp_tmp_mem; });
13845   {
13846     SI opval = tmp_tmps;
13847     CPU (h_prefixreg_pre_v32) = opval;
13848     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13849   }
13850   {
13851     BI opval = 1;
13852     SET_H_INSN_PREFIXED_P (opval);
13853     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13854   }
13855 }
13856
13857   abuf->written = written;
13858 #undef FLD
13859 }
13860   NEXT (vpc);
13861
13862   CASE (sem, INSN_DIP_C) : /* dip [PC+] */
13863 {
13864   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13865   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13866 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
13867   int UNUSED written = 0;
13868   IADDR UNUSED pc = abuf->addr;
13869   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13870
13871 {
13872   {
13873     SI opval = FLD (f_indir_pc__dword);
13874     CPU (h_prefixreg_pre_v32) = opval;
13875     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13876   }
13877   {
13878     BI opval = 1;
13879     SET_H_INSN_PREFIXED_P (opval);
13880     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13881   }
13882 }
13883
13884 #undef FLD
13885 }
13886   NEXT (vpc);
13887
13888   CASE (sem, INSN_ADDI_ACR_B_R) : /* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
13889 {
13890   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13891   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13892 #define FLD(f) abuf->fields.sfmt_add_b_r.f
13893   int UNUSED written = 0;
13894   IADDR UNUSED pc = abuf->addr;
13895   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13896
13897 {
13898   {
13899     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
13900     CPU (h_prefixreg_pre_v32) = opval;
13901     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13902   }
13903   {
13904     BI opval = 1;
13905     SET_H_INSN_PREFIXED_P (opval);
13906     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13907   }
13908 }
13909
13910 #undef FLD
13911 }
13912   NEXT (vpc);
13913
13914   CASE (sem, INSN_ADDI_ACR_W_R) : /* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
13915 {
13916   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13917   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13918 #define FLD(f) abuf->fields.sfmt_add_b_r.f
13919   int UNUSED written = 0;
13920   IADDR UNUSED pc = abuf->addr;
13921   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13922
13923 {
13924   {
13925     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
13926     CPU (h_prefixreg_pre_v32) = opval;
13927     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13928   }
13929   {
13930     BI opval = 1;
13931     SET_H_INSN_PREFIXED_P (opval);
13932     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13933   }
13934 }
13935
13936 #undef FLD
13937 }
13938   NEXT (vpc);
13939
13940   CASE (sem, INSN_ADDI_ACR_D_R) : /* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
13941 {
13942   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13943   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13944 #define FLD(f) abuf->fields.sfmt_add_b_r.f
13945   int UNUSED written = 0;
13946   IADDR UNUSED pc = abuf->addr;
13947   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13948
13949 {
13950   {
13951     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
13952     CPU (h_prefixreg_pre_v32) = opval;
13953     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13954   }
13955   {
13956     BI opval = 1;
13957     SET_H_INSN_PREFIXED_P (opval);
13958     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13959   }
13960 }
13961
13962 #undef FLD
13963 }
13964   NEXT (vpc);
13965
13966   CASE (sem, INSN_BIAP_PC_B_R) : /* biap-pc.b ${Rs-dfield}.m,PC */
13967 {
13968   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13969   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13970 #define FLD(f) abuf->fields.sfmt_addoq.f
13971   int UNUSED written = 0;
13972   IADDR UNUSED pc = abuf->addr;
13973   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13974
13975 {
13976   {
13977     SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 1));
13978     CPU (h_prefixreg_pre_v32) = opval;
13979     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13980   }
13981   {
13982     BI opval = 1;
13983     SET_H_INSN_PREFIXED_P (opval);
13984     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13985   }
13986 }
13987
13988 #undef FLD
13989 }
13990   NEXT (vpc);
13991
13992   CASE (sem, INSN_BIAP_PC_W_R) : /* biap-pc.w ${Rs-dfield}.m,PC */
13993 {
13994   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13995   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13996 #define FLD(f) abuf->fields.sfmt_addoq.f
13997   int UNUSED written = 0;
13998   IADDR UNUSED pc = abuf->addr;
13999   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14000
14001 {
14002   {
14003     SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 2));
14004     CPU (h_prefixreg_pre_v32) = opval;
14005     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14006   }
14007   {
14008     BI opval = 1;
14009     SET_H_INSN_PREFIXED_P (opval);
14010     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14011   }
14012 }
14013
14014 #undef FLD
14015 }
14016   NEXT (vpc);
14017
14018   CASE (sem, INSN_BIAP_PC_D_R) : /* biap-pc.d ${Rs-dfield}.m,PC */
14019 {
14020   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14021   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14022 #define FLD(f) abuf->fields.sfmt_addoq.f
14023   int UNUSED written = 0;
14024   IADDR UNUSED pc = abuf->addr;
14025   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14026
14027 {
14028   {
14029     SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 4));
14030     CPU (h_prefixreg_pre_v32) = opval;
14031     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14032   }
14033   {
14034     BI opval = 1;
14035     SET_H_INSN_PREFIXED_P (opval);
14036     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14037   }
14038 }
14039
14040 #undef FLD
14041 }
14042   NEXT (vpc);
14043
14044
14045     }
14046   ENDSWITCH (sem) /* End of semantic switch.  */
14047
14048   /* At this point `vpc' contains the next insn to execute.  */
14049 }
14050
14051 #undef DEFINE_SWITCH
14052 #endif /* DEFINE_SWITCH */