sim/cris/cris-desc.h

   1 /* CPU data header for cris.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2007 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifndef CRIS_CPU_H
  26 #define CRIS_CPU_H
  27
  28 #include "opcode/cgen-bitset.h"
  29
  30 #define CGEN_ARCH cris
  31
  32 /* Given symbol S, return cris_cgen_<S>.  */
  33 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
  34 #define CGEN_SYM(s) cris##_cgen_##s
  35 #else
  36 #define CGEN_SYM(s) cris/**/_cgen_/**/s
  37 #endif
  38
  39
  40 /* Selected cpu families.  */
  41 #define HAVE_CPU_CRISV0F
  42 #define HAVE_CPU_CRISV3F
  43 #define HAVE_CPU_CRISV8F
  44 #define HAVE_CPU_CRISV10F
  45 #define HAVE_CPU_CRISV32F
  46
  47 #define CGEN_INSN_LSB0_P 1
  48
  49 /* Minimum size of any insn (in bytes).  */
  50 #define CGEN_MIN_INSN_SIZE 2
  51
  52 /* Maximum size of any insn (in bytes).  */
  53 #define CGEN_MAX_INSN_SIZE 6
  54
  55 #define CGEN_INT_INSN_P 0
  56
  57 /* Maximum number of syntax elements in an instruction.  */
  58 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22
  59
  60 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  61    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  62    we can't hash on everything up to the space.  */
  63 #define CGEN_MNEMONIC_OPERANDS
  64
  65 /* Maximum number of fields in an instruction.  */
  66 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 6
  67
  68 /* Enums.  */
  69
  70 /* Enum declaration for .  */
  71 typedef enum gr_names_pcreg {
  72   H_GR_REAL_PC_PC = 15, H_GR_REAL_PC_SP = 14, H_GR_REAL_PC_R0 = 0, H_GR_REAL_PC_R1 = 1
  73  , H_GR_REAL_PC_R2 = 2, H_GR_REAL_PC_R3 = 3, H_GR_REAL_PC_R4 = 4, H_GR_REAL_PC_R5 = 5
  74  , H_GR_REAL_PC_R6 = 6, H_GR_REAL_PC_R7 = 7, H_GR_REAL_PC_R8 = 8, H_GR_REAL_PC_R9 = 9
  75  , H_GR_REAL_PC_R10 = 10, H_GR_REAL_PC_R11 = 11, H_GR_REAL_PC_R12 = 12, H_GR_REAL_PC_R13 = 13
  76  , H_GR_REAL_PC_R14 = 14
  77 } GR_NAMES_PCREG;
  78
  79 /* Enum declaration for .  */
  80 typedef enum gr_names_acr {
  81   H_GR_ACR = 15, H_GR_SP = 14, H_GR_R0 = 0, H_GR_R1 = 1
  82  , H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5
  83  , H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9
  84  , H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13
  85  , H_GR_R14 = 14
  86 } GR_NAMES_ACR;
  87
  88 /* Enum declaration for .  */
  89 typedef enum gr_names_v32 {
  90   H_GR_V32_ACR = 15, H_GR_V32_SP = 14, H_GR_V32_R0 = 0, H_GR_V32_R1 = 1
  91  , H_GR_V32_R2 = 2, H_GR_V32_R3 = 3, H_GR_V32_R4 = 4, H_GR_V32_R5 = 5
  92  , H_GR_V32_R6 = 6, H_GR_V32_R7 = 7, H_GR_V32_R8 = 8, H_GR_V32_R9 = 9
  93  , H_GR_V32_R10 = 10, H_GR_V32_R11 = 11, H_GR_V32_R12 = 12, H_GR_V32_R13 = 13
  94  , H_GR_V32_R14 = 14
  95 } GR_NAMES_V32;
  96
  97 /* Enum declaration for .  */
  98 typedef enum p_names_v10 {
  99   H_SR_PRE_V32_CCR = 5, H_SR_PRE_V32_MOF = 7, H_SR_PRE_V32_IBR = 9, H_SR_PRE_V32_IRP = 10
 100  , H_SR_PRE_V32_BAR = 12, H_SR_PRE_V32_DCCR = 13, H_SR_PRE_V32_BRP = 14, H_SR_PRE_V32_USP = 15
 101  , H_SR_PRE_V32_VR = 1, H_SR_PRE_V32_SRP = 11, H_SR_PRE_V32_P0 = 0, H_SR_PRE_V32_P1 = 1
 102  , H_SR_PRE_V32_P2 = 2, H_SR_PRE_V32_P3 = 3, H_SR_PRE_V32_P4 = 4, H_SR_PRE_V32_P5 = 5
 103  , H_SR_PRE_V32_P6 = 6, H_SR_PRE_V32_P7 = 7, H_SR_PRE_V32_P8 = 8, H_SR_PRE_V32_P9 = 9
 104  , H_SR_PRE_V32_P10 = 10, H_SR_PRE_V32_P11 = 11, H_SR_PRE_V32_P12 = 12, H_SR_PRE_V32_P13 = 13
 105  , H_SR_PRE_V32_P14 = 14
 106 } P_NAMES_V10;
 107
 108 /* Enum declaration for .  */
 109 typedef enum p_names_v32 {
 110   H_SR_BZ = 0, H_SR_PID = 2, H_SR_SRS = 3, H_SR_WZ = 4
 111  , H_SR_EXS = 5, H_SR_EDA = 6, H_SR_MOF = 7, H_SR_DZ = 8
 112  , H_SR_EBP = 9, H_SR_ERP = 10, H_SR_NRP = 12, H_SR_CCS = 13
 113  , H_SR_USP = 14, H_SR_SPC = 15, H_SR_VR = 1, H_SR_SRP = 11
 114  , H_SR_P0 = 0, H_SR_P1 = 1, H_SR_P2 = 2, H_SR_P3 = 3
 115  , H_SR_P4 = 4, H_SR_P5 = 5, H_SR_P6 = 6, H_SR_P7 = 7
 116  , H_SR_P8 = 8, H_SR_P9 = 9, H_SR_P10 = 10, H_SR_P11 = 11
 117  , H_SR_P12 = 12, H_SR_P13 = 13, H_SR_P14 = 14
 118 } P_NAMES_V32;
 119
 120 /* Enum declaration for .  */
 121 typedef enum p_names_v32_x {
 122   H_SR_V32_BZ = 0, H_SR_V32_PID = 2, H_SR_V32_SRS = 3, H_SR_V32_WZ = 4
 123  , H_SR_V32_EXS = 5, H_SR_V32_EDA = 6, H_SR_V32_MOF = 7, H_SR_V32_DZ = 8
 124  , H_SR_V32_EBP = 9, H_SR_V32_ERP = 10, H_SR_V32_NRP = 12, H_SR_V32_CCS = 13
 125  , H_SR_V32_USP = 14, H_SR_V32_SPC = 15, H_SR_V32_VR = 1, H_SR_V32_SRP = 11
 126  , H_SR_V32_P0 = 0, H_SR_V32_P1 = 1, H_SR_V32_P2 = 2, H_SR_V32_P3 = 3
 127  , H_SR_V32_P4 = 4, H_SR_V32_P5 = 5, H_SR_V32_P6 = 6, H_SR_V32_P7 = 7
 128  , H_SR_V32_P8 = 8, H_SR_V32_P9 = 9, H_SR_V32_P10 = 10, H_SR_V32_P11 = 11
 129  , H_SR_V32_P12 = 12, H_SR_V32_P13 = 13, H_SR_V32_P14 = 14
 130 } P_NAMES_V32_X;
 131
 132 /* Enum declaration for Standard instruction operand size.  */
 133 typedef enum insn_size {
 134   SIZE_BYTE, SIZE_WORD, SIZE_DWORD, SIZE_FIXED
 135 } INSN_SIZE;
 136
 137 /* Enum declaration for Standard instruction addressing modes.  */
 138 typedef enum insn_mode {
 139   MODE_QUICK_IMMEDIATE, MODE_REGISTER, MODE_INDIRECT, MODE_AUTOINCREMENT
 140 } INSN_MODE;
 141
 142 /* Enum declaration for Whether the operand is indirect.  */
 143 typedef enum insn_memoryness_mode {
 144   MODEMEMP_NO, MODEMEMP_YES
 145 } INSN_MEMORYNESS_MODE;
 146
 147 /* Enum declaration for Whether the indirect operand is autoincrement.  */
 148 typedef enum insn_memincness_mode {
 149   MODEINCP_NO, MODEINCP_YES
 150 } INSN_MEMINCNESS_MODE;
 151
 152 /* Enum declaration for Signed instruction operand size.  */
 153 typedef enum insn_signed_size {
 154   SIGNED_UNDEF_SIZE_0, SIGNED_UNDEF_SIZE_1, SIGNED_BYTE, SIGNED_WORD
 155 } INSN_SIGNED_SIZE;
 156
 157 /* Enum declaration for Unsigned instruction operand size.  */
 158 typedef enum insn_unsigned_size {
 159   UNSIGNED_BYTE, UNSIGNED_WORD, UNSIGNED_UNDEF_SIZE_2, UNSIGNED_UNDEF_SIZE_3
 160 } INSN_UNSIGNED_SIZE;
 161
 162 /* Enum declaration for Insns for MODE_QUICK_IMMEDIATE.  */
 163 typedef enum insn_qi_opc {
 164   Q_BCC_0, Q_BCC_1, Q_BCC_2, Q_BCC_3
 165  , Q_BDAP_0, Q_BDAP_1, Q_BDAP_2, Q_BDAP_3
 166  , Q_ADDQ, Q_MOVEQ, Q_SUBQ, Q_CMPQ
 167  , Q_ANDQ, Q_ORQ, Q_ASHQ, Q_LSHQ
 168 } INSN_QI_OPC;
 169
 170 /* Enum declaration for Same as insn-qi-opc, though using only the high two bits of the opcode.  */
 171 typedef enum insn_qihi_opc {
 172   QHI_BCC, QHI_BDAP, QHI_OTHER2, QHI_OTHER3
 173 } INSN_QIHI_OPC;
 174
 175 /* Enum declaration for Insns for MODE_REGISTER and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD.  */
 176 typedef enum insn_r_opc {
 177   R_ADDX, R_MOVX, R_SUBX, R_LSL
 178  , R_ADDI, R_BIAP, R_NEG, R_BOUND
 179  , R_ADD, R_MOVE, R_SUB, R_CMP
 180  , R_AND, R_OR, R_ASR, R_LSR
 181 } INSN_R_OPC;
 182
 183 /* Enum declaration for Insns for MODE_REGISTER and SIZE_FIXED.  */
 184 typedef enum insn_rfix_opc {
 185   RFIX_ADDX, RFIX_MOVX, RFIX_SUBX, RFIX_BTST
 186  , RFIX_SCC, RFIX_ADDC, RFIX_SETF, RFIX_CLEARF
 187  , RFIX_MOVE_R_S, RFIX_MOVE_S_R, RFIX_ABS, RFIX_DSTEP
 188  , RFIX_LZ, RFIX_SWAP, RFIX_XOR, RFIX_MSTEP
 189 } INSN_RFIX_OPC;
 190
 191 /* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD.  */
 192 typedef enum insn_indir_opc {
 193   INDIR_ADDX, INDIR_MOVX, INDIR_SUBX, INDIR_CMPX
 194  , INDIR_MUL, INDIR_BDAP_M, INDIR_ADDC, INDIR_BOUND
 195  , INDIR_ADD, INDIR_MOVE_M_R, INDIR_SUB, INDIR_CMP
 196  , INDIR_AND, INDIR_OR, INDIR_TEST, INDIR_MOVE_R_M
 197 } INSN_INDIR_OPC;
 198
 199 /* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and SIZE_FIXED.  */
 200 typedef enum insn_infix_opc {
 201   INFIX_ADDX, INFIX_MOVX, INFIX_SUBX, INFIX_CMPX
 202  , INFIX_JUMP_M, INFIX_DIP, INFIX_JUMP_R, INFIX_BCC_M
 203  , INFIX_MOVE_M_S, INFIX_MOVE_S_M, INFIX_BMOD, INFIX_BSTORE
 204  , INFIX_RBF, INFIX_SBFS, INFIX_MOVEM_M_R, INFIX_MOVEM_R_M
 205 } INSN_INFIX_OPC;
 206
 207 /* Attributes.  */
 208
 209 /* Enum declaration for machine type selection.  */
 210 typedef enum mach_attr {
 211   MACH_BASE, MACH_CRISV0, MACH_CRISV3, MACH_CRISV8
 212  , MACH_CRISV10, MACH_CRISV32, MACH_MAX
 213 } MACH_ATTR;
 214
 215 /* Enum declaration for instruction set selection.  */
 216 typedef enum isa_attr {
 217   ISA_CRIS, ISA_MAX
 218 } ISA_ATTR;
 219
 220 /* Number of architecture variants.  */
 221 #define MAX_ISAS  1
 222 #define MAX_MACHS ((int) MACH_MAX)
 223
 224 /* Ifield support.  */
 225
 226 /* Ifield attribute indices.  */
 227
 228 /* Enum declaration for cgen_ifld attrs.  */
 229 typedef enum cgen_ifld_attr {
 230   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 231  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 232  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 233 } CGEN_IFLD_ATTR;
 234
 235 /* Number of non-boolean elements in cgen_ifld_attr.  */
 236 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 237
 238 /* cgen_ifld attribute accessor macros.  */
 239 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
 240 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
 241 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
 242 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
 243 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
 244 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
 245 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
 246
 247 /* Enum declaration for cris ifield types.  */
 248 typedef enum ifield_type {
 249   CRIS_F_NIL, CRIS_F_ANYOF, CRIS_F_OPERAND1, CRIS_F_SIZE
 250  , CRIS_F_OPCODE, CRIS_F_MODE, CRIS_F_OPERAND2, CRIS_F_MEMMODE
 251  , CRIS_F_MEMBIT, CRIS_F_B5, CRIS_F_OPCODE_HI, CRIS_F_DSTSRC
 252  , CRIS_F_U6, CRIS_F_S6, CRIS_F_U5, CRIS_F_U4
 253  , CRIS_F_S8, CRIS_F_DISP9_HI, CRIS_F_DISP9_LO, CRIS_F_DISP9
 254  , CRIS_F_QO, CRIS_F_INDIR_PC__BYTE, CRIS_F_INDIR_PC__WORD, CRIS_F_INDIR_PC__WORD_PCREL
 255  , CRIS_F_INDIR_PC__DWORD, CRIS_F_INDIR_PC__DWORD_PCREL, CRIS_F_MAX
 256 } IFIELD_TYPE;
 257
 258 #define MAX_IFLD ((int) CRIS_F_MAX)
 259
 260 /* Hardware attribute indices.  */
 261
 262 /* Enum declaration for cgen_hw attrs.  */
 263 typedef enum cgen_hw_attr {
 264   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 265  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 266 } CGEN_HW_ATTR;
 267
 268 /* Number of non-boolean elements in cgen_hw_attr.  */
 269 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 270
 271 /* cgen_hw attribute accessor macros.  */
 272 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
 273 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
 274 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
 275 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
 276 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
 277
 278 /* Enum declaration for cris hardware types.  */
 279 typedef enum cgen_hw_type {
 280   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 281  , HW_H_IADDR, HW_H_INC, HW_H_CCODE, HW_H_SWAP
 282  , HW_H_FLAGBITS, HW_H_V32, HW_H_PC, HW_H_GR
 283  , HW_H_GR_X, HW_H_GR_REAL_PC, HW_H_RAW_GR, HW_H_SR
 284  , HW_H_SR_X, HW_H_SUPR, HW_H_CBIT, HW_H_CBIT_MOVE
 285  , HW_H_CBIT_MOVE_X, HW_H_VBIT, HW_H_VBIT_MOVE, HW_H_VBIT_MOVE_X
 286  , HW_H_ZBIT, HW_H_ZBIT_MOVE, HW_H_ZBIT_MOVE_X, HW_H_NBIT
 287  , HW_H_NBIT_MOVE, HW_H_NBIT_MOVE_X, HW_H_XBIT, HW_H_IBIT
 288  , HW_H_IBIT_X, HW_H_PBIT, HW_H_RBIT, HW_H_UBIT
 289  , HW_H_UBIT_X, HW_H_GBIT, HW_H_KERNEL_SP, HW_H_MBIT
 290  , HW_H_QBIT, HW_H_SBIT, HW_H_INSN_PREFIXED_P, HW_H_INSN_PREFIXED_P_X
 291  , HW_H_PREFIXREG, HW_MAX
 292 } CGEN_HW_TYPE;
 293
 294 #define MAX_HW ((int) HW_MAX)
 295
 296 /* Operand attribute indices.  */
 297
 298 /* Enum declaration for cgen_operand attrs.  */
 299 typedef enum cgen_operand_attr {
 300   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 301  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 302  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
 303 } CGEN_OPERAND_ATTR;
 304
 305 /* Number of non-boolean elements in cgen_operand_attr.  */
 306 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 307
 308 /* cgen_operand attribute accessor macros.  */
 309 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
 310 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
 311 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
 312 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
 313 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
 314 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
 315 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
 316 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
 317 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
 318
 319 /* Enum declaration for cris operand types.  */
 320 typedef enum cgen_operand_type {
 321   CRIS_OPERAND_PC, CRIS_OPERAND_CBIT, CRIS_OPERAND_CBIT_MOVE, CRIS_OPERAND_VBIT
 322  , CRIS_OPERAND_VBIT_MOVE, CRIS_OPERAND_ZBIT, CRIS_OPERAND_ZBIT_MOVE, CRIS_OPERAND_NBIT
 323  , CRIS_OPERAND_NBIT_MOVE, CRIS_OPERAND_XBIT, CRIS_OPERAND_IBIT, CRIS_OPERAND_UBIT
 324  , CRIS_OPERAND_PBIT, CRIS_OPERAND_RBIT, CRIS_OPERAND_SBIT, CRIS_OPERAND_MBIT
 325  , CRIS_OPERAND_QBIT, CRIS_OPERAND_PREFIX_SET, CRIS_OPERAND_PREFIXREG, CRIS_OPERAND_RS
 326  , CRIS_OPERAND_INC, CRIS_OPERAND_PS, CRIS_OPERAND_SS, CRIS_OPERAND_SD
 327  , CRIS_OPERAND_I, CRIS_OPERAND_J, CRIS_OPERAND_C, CRIS_OPERAND_QO
 328  , CRIS_OPERAND_RD, CRIS_OPERAND_SCONST8, CRIS_OPERAND_UCONST8, CRIS_OPERAND_SCONST16
 329  , CRIS_OPERAND_UCONST16, CRIS_OPERAND_CONST32, CRIS_OPERAND_CONST32_PCREL, CRIS_OPERAND_PD
 330  , CRIS_OPERAND_O, CRIS_OPERAND_O_PCREL, CRIS_OPERAND_O_WORD_PCREL, CRIS_OPERAND_CC
 331  , CRIS_OPERAND_N, CRIS_OPERAND_SWAPOPTION, CRIS_OPERAND_LIST_OF_FLAGS, CRIS_OPERAND_MAX
 332 } CGEN_OPERAND_TYPE;
 333
 334 /* Number of operands types.  */
 335 #define MAX_OPERANDS 43
 336
 337 /* Maximum number of operands referenced by any insn.  */
 338 #define MAX_OPERAND_INSTANCES 8
 339
 340 /* Insn attribute indices.  */
 341
 342 /* Enum declaration for cgen_insn attrs.  */
 343 typedef enum cgen_insn_attr {
 344   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 345  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
 346  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
 347  , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 348 } CGEN_INSN_ATTR;
 349
 350 /* Number of non-boolean elements in cgen_insn_attr.  */
 351 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 352
 353 /* cgen_insn attribute accessor macros.  */
 354 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
 355 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
 356 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
 357 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
 358 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
 359 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
 360 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
 361 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
 362 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
 363 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
 364 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
 365
 366 /* cgen.h uses things we just defined.  */
 367 #include "opcode/cgen.h"
 368
 369 extern const struct cgen_ifld cris_cgen_ifld_table[];
 370
 371 /* Attributes.  */
 372 extern const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[];
 373 extern const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[];
 374 extern const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[];
 375 extern const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[];
 376
 377 /* Hardware decls.  */
 378
 379 extern CGEN_KEYWORD cris_cgen_opval_h_inc;
 380 extern CGEN_KEYWORD cris_cgen_opval_h_ccode;
 381 extern CGEN_KEYWORD cris_cgen_opval_h_swap;
 382 extern CGEN_KEYWORD cris_cgen_opval_h_flagbits;
 383 extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg;
 384 extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg;
 385 extern CGEN_KEYWORD cris_cgen_opval_gr_names_acr;
 386 extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
 387 extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
 388 extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
 389 extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
 390 extern CGEN_KEYWORD cris_cgen_opval_p_names_v32;
 391 extern CGEN_KEYWORD cris_cgen_opval_h_supr;
 392
 393 extern const CGEN_HW_ENTRY cris_cgen_hw_table[];
 394
 395
 396
 397 #endif /* CRIS_CPU_H */