| blob | 4acd62a73af1e5616aa2893a5848f11c741525ff |
1 # frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond
2 # mach: frv fr500 fr400
4 .include "testutils.inc"
6 start
8 .global cmqmachs
9 cmqmachs:
10 set_spr_immed 0x1b1b,cccr
12 ; Positive operands
13 set_spr_immed 0,msr0
14 set_spr_immed 0,msr1
15 set_accg_immed 0,accg0
16 set_acc_immed 0,acc0
17 set_accg_immed 0,accg1
18 set_acc_immed 0,acc1
19 set_accg_immed 0,accg2
20 set_acc_immed 0,acc2
21 set_accg_immed 0,accg3
22 set_acc_immed 0,acc3
23 set_fr_iimmed 2,3,fr8 ; multiply small numbers
24 set_fr_iimmed 3,2,fr10
25 set_fr_iimmed 0,1,fr9 ; multiply by 0
26 set_fr_iimmed 2,0,fr11
27 cmqmachs fr8,fr10,acc0,cc0,1
28 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
29 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
30 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
31 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
32 test_accg_immed 0,accg0
33 test_acc_immed 6,acc0
34 test_accg_immed 0,accg1
35 test_acc_immed 6,acc1
36 test_accg_immed 0,accg2
37 test_acc_immed 0,acc2
38 test_accg_immed 0,accg3
39 test_acc_immed 0,acc3
41 set_fr_iimmed 2,1,fr8 ; multiply by 1
42 set_fr_iimmed 1,2,fr10
43 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
44 set_fr_iimmed 2,0x3fff,fr11
45 cmqmachs fr8,fr10,acc0,cc0,1
46 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
47 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
48 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
49 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
50 test_accg_immed 0,accg0
51 test_acc_immed 8,acc0
52 test_accg_immed 0,accg1
53 test_acc_immed 8,acc1
54 test_accg_immed 0,accg2
55 test_acc_limmed 0,0x7ffe,acc2
56 test_accg_immed 0,accg3
57 test_acc_limmed 0,0x7ffe,acc3
59 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
60 set_fr_iimmed 2,0x4000,fr10
61 set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
62 set_fr_iimmed 0x7fff,0x7fff,fr11
63 cmqmachs fr8,fr10,acc0,cc0,1
64 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
65 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
66 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
67 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
68 test_accg_immed 0,accg0
69 test_acc_limmed 0x0000,0x8008,acc0
70 test_accg_immed 0,accg1
71 test_acc_limmed 0x0000,0x8008,acc1
72 test_accg_immed 0,accg2
73 test_acc_limmed 0x3fff,0x7fff,acc2
74 test_accg_immed 0,accg3
75 test_acc_limmed 0x3fff,0x7fff,acc3
77 ; Mixed operands
78 set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
79 set_fr_iimmed 0xfffd,2,fr10
80 set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
81 set_fr_iimmed 1,0xfffe,fr11
82 cmqmachs fr8,fr10,acc0,cc0,1
83 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
84 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
85 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
86 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
87 test_accg_immed 0,accg0
88 test_acc_limmed 0x0000,0x8002,acc0
89 test_accg_immed 0,accg1
90 test_acc_limmed 0x0000,0x8002,acc1
91 test_accg_immed 0,accg2
92 test_acc_limmed 0x3fff,0x7ffd,acc2
93 test_accg_immed 0,accg3
94 test_acc_limmed 0x3fff,0x7ffd,acc3
96 set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
97 set_fr_iimmed 0,0xfffe,fr10
98 set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
99 set_fr_iimmed 0xfffe,0x2001,fr11
100 cmqmachs fr8,fr10,acc0,cc0,1
101 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
102 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
103 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
104 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
105 test_accg_immed 0,accg0
106 test_acc_limmed 0x0000,0x8002,acc0
107 test_accg_immed 0,accg1
108 test_acc_limmed 0x0000,0x8002,acc1
109 test_accg_immed 0,accg2
110 test_acc_limmed 0x3fff,0x3ffb,acc2
111 test_accg_immed 0,accg3
112 test_acc_limmed 0x3fff,0x3ffb,acc3
114 set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
115 set_fr_iimmed 0xfffe,0x4000,fr10
116 set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
117 set_fr_iimmed 0x8000,0x7fff,fr11
118 cmqmachs fr8,fr10,acc0,cc4,1
119 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
120 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
121 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
122 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
123 test_accg_immed 0,accg0
124 test_acc_limmed 0x0000,0x0002,acc0
125 test_accg_immed 0,accg1
126 test_acc_limmed 0x0000,0x0002,acc1
127 test_accg_immed 0xff,accg2
128 test_acc_limmed 0xffff,0xbffb,acc2
129 test_accg_immed 0xff,accg3
130 test_acc_limmed 0xffff,0xbffb,acc3
132 ; Negative operands
133 set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
134 set_fr_iimmed 0xfffd,0xfffe,fr10
135 set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
136 set_fr_iimmed 0xfffe,0xffff,fr11
137 cmqmachs fr8,fr10,acc0,cc4,1
138 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
139 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
140 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
141 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
142 test_accg_immed 0,accg0
143 test_acc_limmed 0x0000,0x0008,acc0
144 test_accg_immed 0,accg1
145 test_acc_limmed 0x0000,0x0008,acc1
146 test_accg_immed 0xff,accg2
147 test_acc_limmed 0xffff,0xbffd,acc2
148 test_accg_immed 0xff,accg3
149 test_acc_limmed 0xffff,0xbffd,acc3
151 set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
152 set_fr_iimmed 0x8001,0x8001,fr10
153 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
154 set_fr_iimmed 0x8000,0x8000,fr11
155 cmqmachs fr8,fr10,acc0,cc4,1
156 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
157 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
158 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
159 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
160 test_accg_immed 0,accg0
161 test_acc_immed 0x3fff0009,acc0
162 test_accg_immed 0,accg1
163 test_acc_immed 0x3fff0009,acc1
164 test_accg_immed 0,accg2
165 test_acc_immed 0x3fffbffd,acc2
166 test_accg_immed 0,accg3
167 test_acc_immed 0x3fffbffd,acc3
169 set_accg_immed 0x7f,accg0 ; saturation
170 set_acc_immed 0xffffffff,acc0
171 set_accg_immed 0x7f,accg1
172 set_acc_immed 0xffffffff,acc1
173 set_accg_immed 0x7f,accg2 ; saturation
174 set_acc_immed 0xffffffff,acc2
175 set_accg_immed 0x7f,accg3
176 set_acc_immed 0xffffffff,acc3
177 set_fr_iimmed 1,1,fr8
178 set_fr_iimmed 1,1,fr10
179 set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
180 set_fr_iimmed 0x7fff,0x7fff,fr11
181 cmqmachs fr8,fr10,acc0,cc4,1
182 test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
183 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
184 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
185 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
186 test_accg_immed 0x7f,accg0
187 test_acc_limmed 0xffff,0xffff,acc0
188 test_accg_immed 0x7f,accg1
189 test_acc_limmed 0xffff,0xffff,acc1
190 test_accg_immed 0x7f,accg2
191 test_acc_limmed 0xffff,0xffff,acc2
192 test_accg_immed 0x7f,accg3
193 test_acc_limmed 0xffff,0xffff,acc3
195 set_accg_immed 0x80,accg0 ; saturation
196 set_acc_immed 0,acc0
197 set_accg_immed 0x80,accg1
198 set_acc_immed 0,acc1
199 set_accg_immed 0x80,accg2 ; saturation
200 set_acc_immed 0,acc2
201 set_accg_immed 0x80,accg3
202 set_acc_immed 0,acc3
203 set_fr_iimmed 0xffff,0,fr8
204 set_fr_iimmed 1,0xffff,fr10
205 set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
206 set_fr_iimmed 0x7fff,0x7fff,fr11
207 cmqmachs fr8,fr10,acc0,cc4,1
208 test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
209 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
210 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
211 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
212 test_accg_immed 0x80,accg0
213 test_acc_immed 0,acc0
214 test_accg_immed 0x80,accg1
215 test_acc_immed 0,acc1
216 test_accg_immed 0x80,accg2
217 test_acc_immed 0,acc2
218 test_accg_immed 0x80,accg3
219 test_acc_immed 0,acc3
221 ; Positive operands
222 set_spr_immed 0,msr0
223 set_spr_immed 0,msr1
224 set_accg_immed 0,accg0
225 set_acc_immed 0,acc0
226 set_accg_immed 0,accg1
227 set_acc_immed 0,acc1
228 set_accg_immed 0,accg2
229 set_acc_immed 0,acc2
230 set_accg_immed 0,accg3
231 set_acc_immed 0,acc3
232 set_fr_iimmed 2,3,fr8 ; multiply small numbers
233 set_fr_iimmed 3,2,fr10
234 set_fr_iimmed 0,1,fr9 ; multiply by 0
235 set_fr_iimmed 2,0,fr11
236 cmqmachs fr8,fr10,acc0,cc1,0
237 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
238 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
239 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
240 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
241 test_accg_immed 0,accg0
242 test_acc_immed 6,acc0
243 test_accg_immed 0,accg1
244 test_acc_immed 6,acc1
245 test_accg_immed 0,accg2
246 test_acc_immed 0,acc2
247 test_accg_immed 0,accg3
248 test_acc_immed 0,acc3
250 set_fr_iimmed 2,1,fr8 ; multiply by 1
251 set_fr_iimmed 1,2,fr10
252 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
253 set_fr_iimmed 2,0x3fff,fr11
254 cmqmachs fr8,fr10,acc0,cc1,0
255 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
256 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
257 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
258 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
259 test_accg_immed 0,accg0
260 test_acc_immed 8,acc0
261 test_accg_immed 0,accg1
262 test_acc_immed 8,acc1
263 test_accg_immed 0,accg2
264 test_acc_limmed 0,0x7ffe,acc2
265 test_accg_immed 0,accg3
266 test_acc_limmed 0,0x7ffe,acc3
268 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
269 set_fr_iimmed 2,0x4000,fr10
270 set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
271 set_fr_iimmed 0x7fff,0x7fff,fr11
272 cmqmachs fr8,fr10,acc0,cc1,0
273 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
274 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
275 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
276 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
277 test_accg_immed 0,accg0
278 test_acc_limmed 0x0000,0x8008,acc0
279 test_accg_immed 0,accg1
280 test_acc_limmed 0x0000,0x8008,acc1
281 test_accg_immed 0,accg2
282 test_acc_limmed 0x3fff,0x7fff,acc2
283 test_accg_immed 0,accg3
284 test_acc_limmed 0x3fff,0x7fff,acc3
286 ; Mixed operands
287 set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
288 set_fr_iimmed 0xfffd,2,fr10
289 set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
290 set_fr_iimmed 1,0xfffe,fr11
291 cmqmachs fr8,fr10,acc0,cc1,0
292 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
293 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
294 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
295 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
296 test_accg_immed 0,accg0
297 test_acc_limmed 0x0000,0x8002,acc0
298 test_accg_immed 0,accg1
299 test_acc_limmed 0x0000,0x8002,acc1
300 test_accg_immed 0,accg2
301 test_acc_limmed 0x3fff,0x7ffd,acc2
302 test_accg_immed 0,accg3
303 test_acc_limmed 0x3fff,0x7ffd,acc3
305 set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
306 set_fr_iimmed 0,0xfffe,fr10
307 set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
308 set_fr_iimmed 0xfffe,0x2001,fr11
309 cmqmachs fr8,fr10,acc0,cc1,0
310 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
311 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
312 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
313 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
314 test_accg_immed 0,accg0
315 test_acc_limmed 0x0000,0x8002,acc0
316 test_accg_immed 0,accg1
317 test_acc_limmed 0x0000,0x8002,acc1
318 test_accg_immed 0,accg2
319 test_acc_limmed 0x3fff,0x3ffb,acc2
320 test_accg_immed 0,accg3
321 test_acc_limmed 0x3fff,0x3ffb,acc3
323 set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
324 set_fr_iimmed 0xfffe,0x4000,fr10
325 set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
326 set_fr_iimmed 0x8000,0x7fff,fr11
327 cmqmachs fr8,fr10,acc0,cc5,0
328 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
329 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
330 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
331 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
332 test_accg_immed 0,accg0
333 test_acc_limmed 0x0000,0x0002,acc0
334 test_accg_immed 0,accg1
335 test_acc_limmed 0x0000,0x0002,acc1
336 test_accg_immed 0xff,accg2
337 test_acc_limmed 0xffff,0xbffb,acc2
338 test_accg_immed 0xff,accg3
339 test_acc_limmed 0xffff,0xbffb,acc3
341 ; Negative operands
342 set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
343 set_fr_iimmed 0xfffd,0xfffe,fr10
344 set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
345 set_fr_iimmed 0xfffe,0xffff,fr11
346 cmqmachs fr8,fr10,acc0,cc5,0
347 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
348 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
349 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
350 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
351 test_accg_immed 0,accg0
352 test_acc_limmed 0x0000,0x0008,acc0
353 test_accg_immed 0,accg1
354 test_acc_limmed 0x0000,0x0008,acc1
355 test_accg_immed 0xff,accg2
356 test_acc_limmed 0xffff,0xbffd,acc2
357 test_accg_immed 0xff,accg3
358 test_acc_limmed 0xffff,0xbffd,acc3
360 set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
361 set_fr_iimmed 0x8001,0x8001,fr10
362 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
363 set_fr_iimmed 0x8000,0x8000,fr11
364 cmqmachs fr8,fr10,acc0,cc5,0
365 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
366 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
367 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
368 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
369 test_accg_immed 0,accg0
370 test_acc_immed 0x3fff0009,acc0
371 test_accg_immed 0,accg1
372 test_acc_immed 0x3fff0009,acc1
373 test_accg_immed 0,accg2
374 test_acc_immed 0x3fffbffd,acc2
375 test_accg_immed 0,accg3
376 test_acc_immed 0x3fffbffd,acc3
378 set_accg_immed 0x7f,accg0 ; saturation
379 set_acc_immed 0xffffffff,acc0
380 set_accg_immed 0x7f,accg1
381 set_acc_immed 0xffffffff,acc1
382 set_accg_immed 0x7f,accg2 ; saturation
383 set_acc_immed 0xffffffff,acc2
384 set_accg_immed 0x7f,accg3
385 set_acc_immed 0xffffffff,acc3
386 set_fr_iimmed 1,1,fr8
387 set_fr_iimmed 1,1,fr10
388 set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
389 set_fr_iimmed 0x7fff,0x7fff,fr11
390 cmqmachs fr8,fr10,acc0,cc5,0
391 test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
392 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
393 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
394 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
395 test_accg_immed 0x7f,accg0
396 test_acc_limmed 0xffff,0xffff,acc0
397 test_accg_immed 0x7f,accg1
398 test_acc_limmed 0xffff,0xffff,acc1
399 test_accg_immed 0x7f,accg2
400 test_acc_limmed 0xffff,0xffff,acc2
401 test_accg_immed 0x7f,accg3
402 test_acc_limmed 0xffff,0xffff,acc3
404 set_accg_immed 0x80,accg0 ; saturation
405 set_acc_immed 0,acc0
406 set_accg_immed 0x80,accg1
407 set_acc_immed 0,acc1
408 set_accg_immed 0x80,accg2 ; saturation
409 set_acc_immed 0,acc2
410 set_accg_immed 0x80,accg3
411 set_acc_immed 0,acc3
412 set_fr_iimmed 0xffff,0,fr8
413 set_fr_iimmed 1,0xffff,fr10
414 set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
415 set_fr_iimmed 0x7fff,0x7fff,fr11
416 cmqmachs fr8,fr10,acc0,cc5,0
417 test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
418 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
419 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
420 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
421 test_accg_immed 0x80,accg0
422 test_acc_immed 0,acc0
423 test_accg_immed 0x80,accg1
424 test_acc_immed 0,acc1
425 test_accg_immed 0x80,accg2
426 test_acc_immed 0,acc2
427 test_accg_immed 0x80,accg3
428 test_acc_immed 0,acc3
430 ; Positive operands
431 set_spr_immed 0,msr0
432 set_spr_immed 0,msr1
433 set_accg_immed 0x00000011,accg0
434 set_acc_immed 0x11111111,acc0
435 set_accg_immed 0x00000022,accg1
436 set_acc_immed 0x22222222,acc1
437 set_accg_immed 0x00000033,accg2
438 set_acc_immed 0x33333333,acc2
439 set_accg_immed 0x00000044,accg3
440 set_acc_immed 0x44444444,acc3
441 set_fr_iimmed 2,3,fr8 ; multiply small numbers
442 set_fr_iimmed 3,2,fr10
443 set_fr_iimmed 0,1,fr9 ; multiply by 0
444 set_fr_iimmed 2,0,fr11
445 cmqmachs fr8,fr10,acc0,cc0,0
446 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
447 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
448 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
449 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
450 test_accg_immed 0x00000011,accg0
451 test_acc_immed 0x11111111,acc0
452 test_accg_immed 0x00000022,accg1
453 test_acc_immed 0x22222222,acc1
454 test_accg_immed 0x00000033,accg2
455 test_acc_immed 0x33333333,acc2
456 test_accg_immed 0x00000044,accg3
457 test_acc_immed 0x44444444,acc3
459 set_fr_iimmed 2,1,fr8 ; multiply by 1
460 set_fr_iimmed 1,2,fr10
461 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
462 set_fr_iimmed 2,0x3fff,fr11
463 cmqmachs fr8,fr10,acc0,cc0,0
464 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
465 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
466 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
467 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
468 test_accg_immed 0x00000011,accg0
469 test_acc_immed 0x11111111,acc0
470 test_accg_immed 0x00000022,accg1
471 test_acc_immed 0x22222222,acc1
472 test_accg_immed 0x00000033,accg2
473 test_acc_immed 0x33333333,acc2
474 test_accg_immed 0x00000044,accg3
475 test_acc_immed 0x44444444,acc3
477 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
478 set_fr_iimmed 2,0x4000,fr10
479 set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
480 set_fr_iimmed 0x7fff,0x7fff,fr11
481 cmqmachs fr8,fr10,acc0,cc0,0
482 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
483 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
484 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
485 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
486 test_accg_immed 0x00000011,accg0
487 test_acc_immed 0x11111111,acc0
488 test_accg_immed 0x00000022,accg1
489 test_acc_immed 0x22222222,acc1
490 test_accg_immed 0x00000033,accg2
491 test_acc_immed 0x33333333,acc2
492 test_accg_immed 0x00000044,accg3
493 test_acc_immed 0x44444444,acc3
495 ; Mixed operands
496 set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
497 set_fr_iimmed 0xfffd,2,fr10
498 set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
499 set_fr_iimmed 1,0xfffe,fr11
500 cmqmachs fr8,fr10,acc0,cc0,0
501 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
502 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
503 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
504 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
505 test_accg_immed 0x00000011,accg0
506 test_acc_immed 0x11111111,acc0
507 test_accg_immed 0x00000022,accg1
508 test_acc_immed 0x22222222,acc1
509 test_accg_immed 0x00000033,accg2
510 test_acc_immed 0x33333333,acc2
511 test_accg_immed 0x00000044,accg3
512 test_acc_immed 0x44444444,acc3
514 set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
515 set_fr_iimmed 0,0xfffe,fr10
516 set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
517 set_fr_iimmed 0xfffe,0x2001,fr11
518 cmqmachs fr8,fr10,acc0,cc0,0
519 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
520 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
521 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
522 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
523 test_accg_immed 0x00000011,accg0
524 test_acc_immed 0x11111111,acc0
525 test_accg_immed 0x00000022,accg1
526 test_acc_immed 0x22222222,acc1
527 test_accg_immed 0x00000033,accg2
528 test_acc_immed 0x33333333,acc2
529 test_accg_immed 0x00000044,accg3
530 test_acc_immed 0x44444444,acc3
532 set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
533 set_fr_iimmed 0xfffe,0x4000,fr10
534 set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
535 set_fr_iimmed 0x8000,0x7fff,fr11
536 cmqmachs fr8,fr10,acc0,cc4,0
537 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
538 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
539 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
540 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
541 test_accg_immed 0x00000011,accg0
542 test_acc_immed 0x11111111,acc0
543 test_accg_immed 0x00000022,accg1
544 test_acc_immed 0x22222222,acc1
545 test_accg_immed 0x00000033,accg2
546 test_acc_immed 0x33333333,acc2
547 test_accg_immed 0x00000044,accg3
548 test_acc_immed 0x44444444,acc3
550 ; Negative operands
551 set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
552 set_fr_iimmed 0xfffd,0xfffe,fr10
553 set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
554 set_fr_iimmed 0xfffe,0xffff,fr11
555 cmqmachs fr8,fr10,acc0,cc4,0
556 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
557 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
558 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
559 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
560 test_accg_immed 0x00000011,accg0
561 test_acc_immed 0x11111111,acc0
562 test_accg_immed 0x00000022,accg1
563 test_acc_immed 0x22222222,acc1
564 test_accg_immed 0x00000033,accg2
565 test_acc_immed 0x33333333,acc2
566 test_accg_immed 0x00000044,accg3
567 test_acc_immed 0x44444444,acc3
569 set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
570 set_fr_iimmed 0x8001,0x8001,fr10
571 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
572 set_fr_iimmed 0x8000,0x8000,fr11
573 cmqmachs fr8,fr10,acc0,cc4,0
574 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
575 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
576 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
577 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
578 test_accg_immed 0x00000011,accg0
579 test_acc_immed 0x11111111,acc0
580 test_accg_immed 0x00000022,accg1
581 test_acc_immed 0x22222222,acc1
582 test_accg_immed 0x00000033,accg2
583 test_acc_immed 0x33333333,acc2
584 test_accg_immed 0x00000044,accg3
585 test_acc_immed 0x44444444,acc3
587 set_accg_immed 0x7f,accg0 ; saturation
588 set_acc_immed 0xffffffff,acc0
589 set_accg_immed 0x7f,accg1
590 set_acc_immed 0xffffffff,acc1
591 set_accg_immed 0x7f,accg2 ; saturation
592 set_acc_immed 0xffffffff,acc2
593 set_accg_immed 0x7f,accg3
594 set_acc_immed 0xffffffff,acc3
595 set_fr_iimmed 1,1,fr8
596 set_fr_iimmed 1,1,fr10
597 set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
598 set_fr_iimmed 0x7fff,0x7fff,fr11
599 cmqmachs fr8,fr10,acc0,cc4,0
600 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
601 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
602 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
603 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
604 test_accg_immed 0x7f,accg0 ; saturation
605 test_acc_immed 0xffffffff,acc0
606 test_accg_immed 0x7f,accg1
607 test_acc_immed 0xffffffff,acc1
608 test_accg_immed 0x7f,accg2 ; saturation
609 test_acc_immed 0xffffffff,acc2
610 test_accg_immed 0x7f,accg3
611 test_acc_immed 0xffffffff,acc3
613 set_accg_immed 0x80,accg0 ; saturation
614 set_acc_immed 0,acc0
615 set_accg_immed 0x80,accg1
616 set_acc_immed 0,acc1
617 set_accg_immed 0x80,accg2 ; saturation
618 set_acc_immed 0,acc2
619 set_accg_immed 0x80,accg3
620 set_acc_immed 0,acc3
621 set_fr_iimmed 0xffff,0,fr8
622 set_fr_iimmed 1,0xffff,fr10
623 set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
624 set_fr_iimmed 0x7fff,0x7fff,fr11
625 cmqmachs fr8,fr10,acc0,cc4,0
626 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
627 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
628 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
629 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
630 test_accg_immed 0x80,accg0 ; saturation
631 test_acc_immed 0,acc0
632 test_accg_immed 0x80,accg1
633 test_acc_immed 0,acc1
634 test_accg_immed 0x80,accg2 ; saturation
635 test_acc_immed 0,acc2
636 test_accg_immed 0x80,accg3
637 test_acc_immed 0,acc3
639 ; Positive operands
640 set_spr_immed 0,msr0
641 set_spr_immed 0,msr1
642 set_accg_immed 0x00000011,accg0
643 set_acc_immed 0x11111111,acc0
644 set_accg_immed 0x00000022,accg1
645 set_acc_immed 0x22222222,acc1
646 set_accg_immed 0x00000033,accg2
647 set_acc_immed 0x33333333,acc2
648 set_accg_immed 0x00000044,accg3
649 set_acc_immed 0x44444444,acc3
650 set_fr_iimmed 2,3,fr8 ; multiply small numbers
651 set_fr_iimmed 3,2,fr10
652 set_fr_iimmed 0,1,fr9 ; multiply by 0
653 set_fr_iimmed 2,0,fr11
654 cmqmachs fr8,fr10,acc0,cc1,1
655 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
656 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
657 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
658 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
659 test_accg_immed 0x00000011,accg0
660 test_acc_immed 0x11111111,acc0
661 test_accg_immed 0x00000022,accg1
662 test_acc_immed 0x22222222,acc1
663 test_accg_immed 0x00000033,accg2
664 test_acc_immed 0x33333333,acc2
665 test_accg_immed 0x00000044,accg3
666 test_acc_immed 0x44444444,acc3
668 set_fr_iimmed 2,1,fr8 ; multiply by 1
669 set_fr_iimmed 1,2,fr10
670 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
671 set_fr_iimmed 2,0x3fff,fr11
672 cmqmachs fr8,fr10,acc0,cc1,1
673 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
674 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
675 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
676 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
677 test_accg_immed 0x00000011,accg0
678 test_acc_immed 0x11111111,acc0
679 test_accg_immed 0x00000022,accg1
680 test_acc_immed 0x22222222,acc1
681 test_accg_immed 0x00000033,accg2
682 test_acc_immed 0x33333333,acc2
683 test_accg_immed 0x00000044,accg3
684 test_acc_immed 0x44444444,acc3
686 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
687 set_fr_iimmed 2,0x4000,fr10
688 set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
689 set_fr_iimmed 0x7fff,0x7fff,fr11
690 cmqmachs fr8,fr10,acc0,cc1,1
691 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
692 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
693 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
694 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
695 test_accg_immed 0x00000011,accg0
696 test_acc_immed 0x11111111,acc0
697 test_accg_immed 0x00000022,accg1
698 test_acc_immed 0x22222222,acc1
699 test_accg_immed 0x00000033,accg2
700 test_acc_immed 0x33333333,acc2
701 test_accg_immed 0x00000044,accg3
702 test_acc_immed 0x44444444,acc3
704 ; Mixed operands
705 set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
706 set_fr_iimmed 0xfffd,2,fr10
707 set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
708 set_fr_iimmed 1,0xfffe,fr11
709 cmqmachs fr8,fr10,acc0,cc1,1
710 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
711 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
712 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
713 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
714 test_accg_immed 0x00000011,accg0
715 test_acc_immed 0x11111111,acc0
716 test_accg_immed 0x00000022,accg1
717 test_acc_immed 0x22222222,acc1
718 test_accg_immed 0x00000033,accg2
719 test_acc_immed 0x33333333,acc2
720 test_accg_immed 0x00000044,accg3
721 test_acc_immed 0x44444444,acc3
723 set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
724 set_fr_iimmed 0,0xfffe,fr10
725 set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
726 set_fr_iimmed 0xfffe,0x2001,fr11
727 cmqmachs fr8,fr10,acc0,cc1,1
728 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
729 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
730 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
731 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
732 test_accg_immed 0x00000011,accg0
733 test_acc_immed 0x11111111,acc0
734 test_accg_immed 0x00000022,accg1
735 test_acc_immed 0x22222222,acc1
736 test_accg_immed 0x00000033,accg2
737 test_acc_immed 0x33333333,acc2
738 test_accg_immed 0x00000044,accg3
739 test_acc_immed 0x44444444,acc3
741 set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
742 set_fr_iimmed 0xfffe,0x4000,fr10
743 set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
744 set_fr_iimmed 0x8000,0x7fff,fr11
745 cmqmachs fr8,fr10,acc0,cc5,1
746 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
747 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
748 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
749 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
750 test_accg_immed 0x00000011,accg0
751 test_acc_immed 0x11111111,acc0
752 test_accg_immed 0x00000022,accg1
753 test_acc_immed 0x22222222,acc1
754 test_accg_immed 0x00000033,accg2
755 test_acc_immed 0x33333333,acc2
756 test_accg_immed 0x00000044,accg3
757 test_acc_immed 0x44444444,acc3
759 ; Negative operands
760 set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
761 set_fr_iimmed 0xfffd,0xfffe,fr10
762 set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
763 set_fr_iimmed 0xfffe,0xffff,fr11
764 cmqmachs fr8,fr10,acc0,cc5,1
765 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
766 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
767 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
768 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
769 test_accg_immed 0x00000011,accg0
770 test_acc_immed 0x11111111,acc0
771 test_accg_immed 0x00000022,accg1
772 test_acc_immed 0x22222222,acc1
773 test_accg_immed 0x00000033,accg2
774 test_acc_immed 0x33333333,acc2
775 test_accg_immed 0x00000044,accg3
776 test_acc_immed 0x44444444,acc3
778 set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
779 set_fr_iimmed 0x8001,0x8001,fr10
780 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
781 set_fr_iimmed 0x8000,0x8000,fr11
782 cmqmachs fr8,fr10,acc0,cc5,1
783 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
784 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
785 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
786 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
787 test_accg_immed 0x00000011,accg0
788 test_acc_immed 0x11111111,acc0
789 test_accg_immed 0x00000022,accg1
790 test_acc_immed 0x22222222,acc1
791 test_accg_immed 0x00000033,accg2
792 test_acc_immed 0x33333333,acc2
793 test_accg_immed 0x00000044,accg3
794 test_acc_immed 0x44444444,acc3
796 set_accg_immed 0x7f,accg0 ; saturation
797 set_acc_immed 0xffffffff,acc0
798 set_accg_immed 0x7f,accg1
799 set_acc_immed 0xffffffff,acc1
800 set_accg_immed 0x7f,accg2 ; saturation
801 set_acc_immed 0xffffffff,acc2
802 set_accg_immed 0x7f,accg3
803 set_acc_immed 0xffffffff,acc3
804 set_fr_iimmed 1,1,fr8
805 set_fr_iimmed 1,1,fr10
806 set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
807 set_fr_iimmed 0x7fff,0x7fff,fr11
808 cmqmachs fr8,fr10,acc0,cc5,1
809 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
810 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
811 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
812 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
813 test_accg_immed 0x7f,accg0 ; saturation
814 test_acc_immed 0xffffffff,acc0
815 test_accg_immed 0x7f,accg1
816 test_acc_immed 0xffffffff,acc1
817 test_accg_immed 0x7f,accg2 ; saturation
818 test_acc_immed 0xffffffff,acc2
819 test_accg_immed 0x7f,accg3
820 test_acc_immed 0xffffffff,acc3
822 set_accg_immed 0x80,accg0 ; saturation
823 set_acc_immed 0,acc0
824 set_accg_immed 0x80,accg1
825 set_acc_immed 0,acc1
826 set_accg_immed 0x80,accg2 ; saturation
827 set_acc_immed 0,acc2
828 set_accg_immed 0x80,accg3
829 set_acc_immed 0,acc3
830 set_fr_iimmed 0xffff,0,fr8
831 set_fr_iimmed 1,0xffff,fr10
832 set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
833 set_fr_iimmed 0x7fff,0x7fff,fr11
834 cmqmachs fr8,fr10,acc0,cc5,1
835 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
836 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
837 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
838 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
839 test_accg_immed 0x80,accg0 ; saturation
840 test_acc_immed 0,acc0
841 test_accg_immed 0x80,accg1
842 test_acc_immed 0,acc1
843 test_accg_immed 0x80,accg2 ; saturation
844 test_acc_immed 0,acc2
845 test_accg_immed 0x80,accg3
846 test_acc_immed 0,acc3
848 ; Positive operands
849 set_spr_immed 0,msr0
850 set_spr_immed 0,msr1
851 set_accg_immed 0x00000011,accg0
852 set_acc_immed 0x11111111,acc0
853 set_accg_immed 0x00000022,accg1
854 set_acc_immed 0x22222222,acc1
855 set_accg_immed 0x00000033,accg2
856 set_acc_immed 0x33333333,acc2
857 set_accg_immed 0x00000044,accg3
858 set_acc_immed 0x44444444,acc3
859 set_fr_iimmed 2,3,fr8 ; multiply small numbers
860 set_fr_iimmed 3,2,fr10
861 set_fr_iimmed 0,1,fr9 ; multiply by 0
862 set_fr_iimmed 2,0,fr11
863 cmqmachs fr8,fr10,acc0,cc2,1
864 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
865 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
866 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
867 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
868 test_accg_immed 0x00000011,accg0
869 test_acc_immed 0x11111111,acc0
870 test_accg_immed 0x00000022,accg1
871 test_acc_immed 0x22222222,acc1
872 test_accg_immed 0x00000033,accg2
873 test_acc_immed 0x33333333,acc2
874 test_accg_immed 0x00000044,accg3
875 test_acc_immed 0x44444444,acc3
877 set_fr_iimmed 2,1,fr8 ; multiply by 1
878 set_fr_iimmed 1,2,fr10
879 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
880 set_fr_iimmed 2,0x3fff,fr11
881 cmqmachs fr8,fr10,acc0,cc2,1
882 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
883 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
884 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
885 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
886 test_accg_immed 0x00000011,accg0
887 test_acc_immed 0x11111111,acc0
888 test_accg_immed 0x00000022,accg1
889 test_acc_immed 0x22222222,acc1
890 test_accg_immed 0x00000033,accg2
891 test_acc_immed 0x33333333,acc2
892 test_accg_immed 0x00000044,accg3
893 test_acc_immed 0x44444444,acc3
895 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
896 set_fr_iimmed 2,0x4000,fr10
897 set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
898 set_fr_iimmed 0x7fff,0x7fff,fr11
899 cmqmachs fr8,fr10,acc0,cc2,1
900 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
901 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
902 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
903 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
904 test_accg_immed 0x00000011,accg0
905 test_acc_immed 0x11111111,acc0
906 test_accg_immed 0x00000022,accg1
907 test_acc_immed 0x22222222,acc1
908 test_accg_immed 0x00000033,accg2
909 test_acc_immed 0x33333333,acc2
910 test_accg_immed 0x00000044,accg3
911 test_acc_immed 0x44444444,acc3
913 ; Mixed operands
914 set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
915 set_fr_iimmed 0xfffd,2,fr10
916 set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
917 set_fr_iimmed 1,0xfffe,fr11
918 cmqmachs fr8,fr10,acc0,cc2,1
919 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
920 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
921 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
922 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
923 test_accg_immed 0x00000011,accg0
924 test_acc_immed 0x11111111,acc0
925 test_accg_immed 0x00000022,accg1
926 test_acc_immed 0x22222222,acc1
927 test_accg_immed 0x00000033,accg2
928 test_acc_immed 0x33333333,acc2
929 test_accg_immed 0x00000044,accg3
930 test_acc_immed 0x44444444,acc3
932 set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
933 set_fr_iimmed 0,0xfffe,fr10
934 set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
935 set_fr_iimmed 0xfffe,0x2001,fr11
936 cmqmachs fr8,fr10,acc0,cc2,1
937 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
938 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
939 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
940 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
941 test_accg_immed 0x00000011,accg0
942 test_acc_immed 0x11111111,acc0
943 test_accg_immed 0x00000022,accg1
944 test_acc_immed 0x22222222,acc1
945 test_accg_immed 0x00000033,accg2
946 test_acc_immed 0x33333333,acc2
947 test_accg_immed 0x00000044,accg3
948 test_acc_immed 0x44444444,acc3
950 set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
951 set_fr_iimmed 0xfffe,0x4000,fr10
952 set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
953 set_fr_iimmed 0x8000,0x7fff,fr11
954 cmqmachs fr8,fr10,acc0,cc6,1
955 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
956 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
957 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
958 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
959 test_accg_immed 0x00000011,accg0
960 test_acc_immed 0x11111111,acc0
961 test_accg_immed 0x00000022,accg1
962 test_acc_immed 0x22222222,acc1
963 test_accg_immed 0x00000033,accg2
964 test_acc_immed 0x33333333,acc2
965 test_accg_immed 0x00000044,accg3
966 test_acc_immed 0x44444444,acc3
968 ; Negative operands
969 set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
970 set_fr_iimmed 0xfffd,0xfffe,fr10
971 set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
972 set_fr_iimmed 0xfffe,0xffff,fr11
973 cmqmachs fr8,fr10,acc0,cc6,1
974 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
975 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
976 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
977 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
978 test_accg_immed 0x00000011,accg0
979 test_acc_immed 0x11111111,acc0
980 test_accg_immed 0x00000022,accg1
981 test_acc_immed 0x22222222,acc1
982 test_accg_immed 0x00000033,accg2
983 test_acc_immed 0x33333333,acc2
984 test_accg_immed 0x00000044,accg3
985 test_acc_immed 0x44444444,acc3
987 set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
988 set_fr_iimmed 0x8001,0x8001,fr10
989 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
990 set_fr_iimmed 0x8000,0x8000,fr11
991 cmqmachs fr8,fr10,acc0,cc6,1
992 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
993 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
994 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
995 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
996 test_accg_immed 0x00000011,accg0
997 test_acc_immed 0x11111111,acc0
998 test_accg_immed 0x00000022,accg1
999 test_acc_immed 0x22222222,acc1
1000 test_accg_immed 0x00000033,accg2
1001 test_acc_immed 0x33333333,acc2
1002 test_accg_immed 0x00000044,accg3
1003 test_acc_immed 0x44444444,acc3
1005 set_accg_immed 0x7f,accg0 ; saturation
1006 set_acc_immed 0xffffffff,acc0
1007 set_accg_immed 0x7f,accg1
1008 set_acc_immed 0xffffffff,acc1
1009 set_accg_immed 0x7f,accg2 ; saturation
1010 set_acc_immed 0xffffffff,acc2
1011 set_accg_immed 0x7f,accg3
1012 set_acc_immed 0xffffffff,acc3
1013 set_fr_iimmed 1,1,fr8
1014 set_fr_iimmed 1,1,fr10
1015 set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
1016 set_fr_iimmed 0x7fff,0x7fff,fr11
1017 cmqmachs fr8,fr10,acc0,cc6,1
1018 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
1019 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
1020 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
1021 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
1022 test_accg_immed 0x7f,accg0 ; saturation
1023 test_acc_immed 0xffffffff,acc0
1024 test_accg_immed 0x7f,accg1
1025 test_acc_immed 0xffffffff,acc1
1026 test_accg_immed 0x7f,accg2 ; saturation
1027 test_acc_immed 0xffffffff,acc2
1028 test_accg_immed 0x7f,accg3
1029 test_acc_immed 0xffffffff,acc3
1031 set_accg_immed 0x80,accg0 ; saturation
1032 set_acc_immed 0,acc0
1033 set_accg_immed 0x80,accg1
1034 set_acc_immed 0,acc1
1035 set_accg_immed 0x80,accg2 ; saturation
1036 set_acc_immed 0,acc2
1037 set_accg_immed 0x80,accg3
1038 set_acc_immed 0,acc3
1039 set_fr_iimmed 0xffff,0,fr8
1040 set_fr_iimmed 1,0xffff,fr10
1041 set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
1042 set_fr_iimmed 0x7fff,0x7fff,fr11
1043 cmqmachs fr8,fr10,acc0,cc6,1
1044 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
1045 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
1046 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
1047 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
1048 test_accg_immed 0x80,accg0 ; saturation
1049 test_acc_immed 0,acc0
1050 test_accg_immed 0x80,accg1
1051 test_acc_immed 0,acc1
1052 test_accg_immed 0x80,accg2 ; saturation
1053 test_acc_immed 0,acc2
1054 test_accg_immed 0x80,accg3
1055 test_acc_immed 0,acc3
1056 ;
1057 ; Positive operands
1058 set_spr_immed 0,msr0
1059 set_spr_immed 0,msr1
1060 set_accg_immed 0x00000011,accg0
1061 set_acc_immed 0x11111111,acc0
1062 set_accg_immed 0x00000022,accg1
1063 set_acc_immed 0x22222222,acc1
1064 set_accg_immed 0x00000033,accg2
1065 set_acc_immed 0x33333333,acc2
1066 set_accg_immed 0x00000044,accg3
1067 set_acc_immed 0x44444444,acc3
1068 set_fr_iimmed 2,3,fr8 ; multiply small numbers
1069 set_fr_iimmed 3,2,fr10
1070 set_fr_iimmed 0,1,fr9 ; multiply by 0
1071 set_fr_iimmed 2,0,fr11
1072 cmqmachs fr8,fr10,acc0,cc3,1
1073 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
1074 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
1075 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
1076 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
1077 test_accg_immed 0x00000011,accg0
1078 test_acc_immed 0x11111111,acc0
1079 test_accg_immed 0x00000022,accg1
1080 test_acc_immed 0x22222222,acc1
1081 test_accg_immed 0x00000033,accg2
1082 test_acc_immed 0x33333333,acc2
1083 test_accg_immed 0x00000044,accg3
1084 test_acc_immed 0x44444444,acc3
1086 set_fr_iimmed 2,1,fr8 ; multiply by 1
1087 set_fr_iimmed 1,2,fr10
1088 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
1089 set_fr_iimmed 2,0x3fff,fr11
1090 cmqmachs fr8,fr10,acc0,cc3,1
1091 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
1092 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
1093 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
1094 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
1095 test_accg_immed 0x00000011,accg0
1096 test_acc_immed 0x11111111,acc0
1097 test_accg_immed 0x00000022,accg1
1098 test_acc_immed 0x22222222,acc1
1099 test_accg_immed 0x00000033,accg2
1100 test_acc_immed 0x33333333,acc2
1101 test_accg_immed 0x00000044,accg3
1102 test_acc_immed 0x44444444,acc3
1104 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
1105 set_fr_iimmed 2,0x4000,fr10
1106 set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
1107 set_fr_iimmed 0x7fff,0x7fff,fr11
1108 cmqmachs fr8,fr10,acc0,cc3,1
1109 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
1110 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
1111 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
1112 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
1113 test_accg_immed 0x00000011,accg0
1114 test_acc_immed 0x11111111,acc0
1115 test_accg_immed 0x00000022,accg1
1116 test_acc_immed 0x22222222,acc1
1117 test_accg_immed 0x00000033,accg2
1118 test_acc_immed 0x33333333,acc2
1119 test_accg_immed 0x00000044,accg3
1120 test_acc_immed 0x44444444,acc3
1122 ; Mixed operands
1123 set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
1124 set_fr_iimmed 0xfffd,2,fr10
1125 set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
1126 set_fr_iimmed 1,0xfffe,fr11
1127 cmqmachs fr8,fr10,acc0,cc3,1
1128 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
1129 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
1130 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
1131 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
1132 test_accg_immed 0x00000011,accg0
1133 test_acc_immed 0x11111111,acc0
1134 test_accg_immed 0x00000022,accg1
1135 test_acc_immed 0x22222222,acc1
1136 test_accg_immed 0x00000033,accg2
1137 test_acc_immed 0x33333333,acc2
1138 test_accg_immed 0x00000044,accg3
1139 test_acc_immed 0x44444444,acc3
1141 set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
1142 set_fr_iimmed 0,0xfffe,fr10
1143 set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
1144 set_fr_iimmed 0xfffe,0x2001,fr11
1145 cmqmachs fr8,fr10,acc0,cc3,1
1146 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
1147 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
1148 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
1149 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
1150 test_accg_immed 0x00000011,accg0
1151 test_acc_immed 0x11111111,acc0
1152 test_accg_immed 0x00000022,accg1
1153 test_acc_immed 0x22222222,acc1
1154 test_accg_immed 0x00000033,accg2
1155 test_acc_immed 0x33333333,acc2
1156 test_accg_immed 0x00000044,accg3
1157 test_acc_immed 0x44444444,acc3
1159 set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
1160 set_fr_iimmed 0xfffe,0x4000,fr10
1161 set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
1162 set_fr_iimmed 0x8000,0x7fff,fr11
1163 cmqmachs fr8,fr10,acc0,cc7,1
1164 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
1165 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
1166 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
1167 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
1168 test_accg_immed 0x00000011,accg0
1169 test_acc_immed 0x11111111,acc0
1170 test_accg_immed 0x00000022,accg1
1171 test_acc_immed 0x22222222,acc1
1172 test_accg_immed 0x00000033,accg2
1173 test_acc_immed 0x33333333,acc2
1174 test_accg_immed 0x00000044,accg3
1175 test_acc_immed 0x44444444,acc3
1177 ; Negative operands
1178 set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
1179 set_fr_iimmed 0xfffd,0xfffe,fr10
1180 set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
1181 set_fr_iimmed 0xfffe,0xffff,fr11
1182 cmqmachs fr8,fr10,acc0,cc7,1
1183 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
1184 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
1185 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
1186 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
1187 test_accg_immed 0x00000011,accg0
1188 test_acc_immed 0x11111111,acc0
1189 test_accg_immed 0x00000022,accg1
1190 test_acc_immed 0x22222222,acc1
1191 test_accg_immed 0x00000033,accg2
1192 test_acc_immed 0x33333333,acc2
1193 test_accg_immed 0x00000044,accg3
1194 test_acc_immed 0x44444444,acc3
1196 set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
1197 set_fr_iimmed 0x8001,0x8001,fr10
1198 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
1199 set_fr_iimmed 0x8000,0x8000,fr11
1200 cmqmachs fr8,fr10,acc0,cc7,1
1201 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
1202 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
1203 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
1204 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
1205 test_accg_immed 0x00000011,accg0
1206 test_acc_immed 0x11111111,acc0
1207 test_accg_immed 0x00000022,accg1
1208 test_acc_immed 0x22222222,acc1
1209 test_accg_immed 0x00000033,accg2
1210 test_acc_immed 0x33333333,acc2
1211 test_accg_immed 0x00000044,accg3
1212 test_acc_immed 0x44444444,acc3
1214 set_accg_immed 0x7f,accg0 ; saturation
1215 set_acc_immed 0xffffffff,acc0
1216 set_accg_immed 0x7f,accg1
1217 set_acc_immed 0xffffffff,acc1
1218 set_accg_immed 0x7f,accg2 ; saturation
1219 set_acc_immed 0xffffffff,acc2
1220 set_accg_immed 0x7f,accg3
1221 set_acc_immed 0xffffffff,acc3
1222 set_fr_iimmed 1,1,fr8
1223 set_fr_iimmed 1,1,fr10
1224 set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
1225 set_fr_iimmed 0x7fff,0x7fff,fr11
1226 cmqmachs fr8,fr10,acc0,cc7,1
1227 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
1228 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
1229 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
1230 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
1231 test_accg_immed 0x7f,accg0 ; saturation
1232 test_acc_immed 0xffffffff,acc0
1233 test_accg_immed 0x7f,accg1
1234 test_acc_immed 0xffffffff,acc1
1235 test_accg_immed 0x7f,accg2 ; saturation
1236 test_acc_immed 0xffffffff,acc2
1237 test_accg_immed 0x7f,accg3
1238 test_acc_immed 0xffffffff,acc3
1240 set_accg_immed 0x80,accg0 ; saturation
1241 set_acc_immed 0,acc0
1242 set_accg_immed 0x80,accg1
1243 set_acc_immed 0,acc1
1244 set_accg_immed 0x80,accg2 ; saturation
1245 set_acc_immed 0,acc2
1246 set_accg_immed 0x80,accg3
1247 set_acc_immed 0,acc3
1248 set_fr_iimmed 0xffff,0,fr8
1249 set_fr_iimmed 1,0xffff,fr10
1250 set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
1251 set_fr_iimmed 0x7fff,0x7fff,fr11
1252 cmqmachs fr8,fr10,acc0,cc7,1
1253 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
1254 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
1255 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
1256 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
1257 test_accg_immed 0x80,accg0 ; saturation
1258 test_acc_immed 0,acc0
1259 test_accg_immed 0x80,accg1
1260 test_acc_immed 0,acc1
1261 test_accg_immed 0x80,accg2 ; saturation
1262 test_acc_immed 0,acc2
1263 test_accg_immed 0x80,accg3
1264 test_acc_immed 0,acc3
1266 pass