gdb/xtensa-tdep.h

   1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
   2
   3    Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20
  21 /* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
  22    whenever the "tdep" structure changes in an incompatible way.  */
  23
  24 #define XTENSA_TDEP_VERSION 0x60
  25
  26 /*  Xtensa register type.  */
  27
  28 typedef enum
  29 {
  30   xtRegisterTypeArRegfile = 1,  /* Register File ar0..arXX.  */
  31   xtRegisterTypeSpecialReg,     /* CPU states, such as PS, Booleans, (rsr).  */
  32   xtRegisterTypeUserReg,        /* User defined registers (rur).  */
  33   xtRegisterTypeTieRegfile,     /* User define register files.  */
  34   xtRegisterTypeTieState,       /* TIE States (mapped on user regs).  */
  35   xtRegisterTypeMapped,         /* Mapped on Special Registers.  */
  36   xtRegisterTypeUnmapped,       /* Special case of masked registers.  */
  37   xtRegisterTypeWindow,         /* Live window registers (a0..a15).  */
  38   xtRegisterTypeVirtual,        /* PC, FP.  */
  39   xtRegisterTypeUnknown
  40 } xtensa_register_type_t;
  41
  42
  43 /*  Xtensa register group.  */
  44
  45 #define XTENSA_MAX_COPROCESSOR  0x08  /* Number of Xtensa coprocessors.  */
  46
  47 typedef enum
  48 {
  49   xtRegisterGroupUnknown = 0,
  50   xtRegisterGroupRegFile        = 0x0001,    /* Register files without ARx.  */
  51   xtRegisterGroupAddrReg        = 0x0002,    /* ARx.  */
  52   xtRegisterGroupSpecialReg     = 0x0004,    /* SRxx.  */
  53   xtRegisterGroupUserReg        = 0x0008,    /* URxx.  */
  54   xtRegisterGroupState          = 0x0010,    /* States.  */
  55
  56   xtRegisterGroupGeneral        = 0x0100,    /* General registers, Ax, SR.  */
  57   xtRegisterGroupUser           = 0x0200,    /* User registers.  */
  58   xtRegisterGroupFloat          = 0x0400,    /* Floating Point.  */
  59   xtRegisterGroupVectra         = 0x0800,    /* Vectra.  */
  60   xtRegisterGroupSystem         = 0x1000,    /* System.  */
  61
  62   xtRegisterGroupCP0        = 0x01000000,    /* CP0.  */
  63   xtRegisterGroupCP1        = 0x02000000,    /* CP1.  */
  64   xtRegisterGroupCP2        = 0x04000000,    /* CP2.  */
  65   xtRegisterGroupCP3        = 0x08000000,    /* CP3.  */
  66   xtRegisterGroupCP4        = 0x10000000,    /* CP4.  */
  67   xtRegisterGroupCP5        = 0x20000000,    /* CP5.  */
  68   xtRegisterGroupCP6        = 0x40000000,    /* CP6.  */
  69   xtRegisterGroupCP7        = 0x80000000,    /* CP7.  */
  70
  71 } xtensa_register_group_t;
  72
  73
  74 /*  Xtensa target flags.  */
  75
  76 typedef enum
  77 {
  78   xtTargetFlagsNonVisibleRegs   = 0x0001,
  79   xtTargetFlagsUseFetchStore    = 0x0002,
  80 } xtensa_target_flags_t;
  81
  82
  83 /* Xtensa ELF core file register set representation ('.reg' section).
  84    Copied from target-side ELF header <xtensa/elf.h>.  */
  85
  86 typedef unsigned long xtensa_elf_greg_t;
  87
  88 typedef struct
  89 {
  90   xtensa_elf_greg_t xchal_config_id0;
  91   xtensa_elf_greg_t xchal_config_id1;
  92   xtensa_elf_greg_t cpux;
  93   xtensa_elf_greg_t cpuy;
  94   xtensa_elf_greg_t pc;
  95   xtensa_elf_greg_t ps;
  96   xtensa_elf_greg_t exccause;
  97   xtensa_elf_greg_t excvaddr;
  98   xtensa_elf_greg_t windowbase;
  99   xtensa_elf_greg_t windowstart;
 100   xtensa_elf_greg_t lbeg;
 101   xtensa_elf_greg_t lend;
 102   xtensa_elf_greg_t lcount;
 103   xtensa_elf_greg_t sar;
 104   xtensa_elf_greg_t syscall;
 105   xtensa_elf_greg_t ar[0];      /* variable size (per config).  */
 106 } xtensa_elf_gregset_t;
 107
 108
 109 /*  Mask.  */
 110
 111 typedef struct
 112 {
 113   int reg_num;
 114   int bit_start;
 115   int bit_size;
 116 } xtensa_reg_mask_t;
 117
 118 typedef struct
 119 {
 120   int count;
 121   xtensa_reg_mask_t *mask;
 122 } xtensa_mask_t;
 123
 124
 125 /*  Xtensa register representation.  */
 126
 127 typedef struct
 128 {
 129   char* name;                   /* Register name.  */
 130   int offset;                   /* Offset.  */
 131   xtensa_register_type_t type;  /* Register type.  */
 132   xtensa_register_group_t group;/* Register group.  */
 133   struct type* ctype;           /* C-type.  */
 134   int bit_size;                 /* The actual bit size in the target.  */
 135   int byte_size;                /* Actual space allocated in registers[].  */
 136   int align;                    /* Alignment for this register.  */
 137
 138   unsigned int target_number;   /* Register target number.  */
 139
 140   int flags;                    /* Flags.  */
 141
 142   const xtensa_mask_t *mask;    /* Register is a compilation of other regs.  */
 143   const char *fetch;            /* Instruction sequence to fetch register.  */
 144   const char *store;            /* Instruction sequence to store register.  */
 145 } xtensa_register_t;
 146
 147
 148 #define XTENSA_REGISTER_FLAGS_PRIVILEDGED       0x0001
 149 #define XTENSA_REGISTER_FLAGS_READABLE          0x0002
 150 #define XTENSA_REGISTER_FLAGS_WRITABLE          0x0004
 151 #define XTENSA_REGISTER_FLAGS_VOLATILE          0x0008
 152
 153
 154 /*  Call-ABI for stack frame.  */
 155
 156 typedef enum
 157 {
 158   CallAbiDefault = 0,           /* Any 'callX' instructions; default stack.  */
 159   CallAbiCall0Only,             /* Only 'call0' instructions; flat stack.  */
 160 } call_abi_t;
 161
 162
 163 /*  Xtensa-specific target dependencies.  */
 164
 165 struct gdbarch_tdep
 166 {
 167   unsigned int target_flags;
 168
 169   /* Spill location for TIE register files under ocd.  */
 170
 171   unsigned int spill_location;
 172   unsigned int spill_size;
 173
 174   char *unused;                         /* Placeholder for compatibility.  */
 175   call_abi_t call_abi;                  /* Calling convention.  */
 176
 177   /* CPU configuration.  */
 178
 179   unsigned int debug_interrupt_level;
 180
 181   unsigned int icache_line_bytes;
 182   unsigned int dcache_line_bytes;
 183   unsigned int dcache_writeback;
 184
 185   unsigned int isa_use_windowed_registers;
 186   unsigned int isa_use_density_instructions;
 187   unsigned int isa_use_exceptions;
 188   unsigned int isa_use_ext_l32r;
 189   unsigned int isa_max_insn_size;       /* Maximum instruction length.  */
 190   unsigned int debug_num_ibreaks;       /* Number of IBREAKs.  */
 191   unsigned int debug_num_dbreaks;
 192
 193   /* Register map.  */
 194
 195   xtensa_register_t* regmap;
 196
 197   unsigned int num_regs;        /* Number of registers in regmap.  */
 198   unsigned int num_pseudo_regs; /* Number of pseudo registers.  */
 199   unsigned int num_aregs;       /* Size of register file.  */
 200   unsigned int num_contexts;
 201
 202   int ar_base;                  /* Register number for AR0.  */
 203   int a0_base;                  /* Register number for A0 (pseudo).  */
 204   int wb_regnum;                /* Register number for WB.  */
 205   int ws_regnum;                /* Register number for WS.  */
 206   int pc_regnum;                /* Register number for PC.  */
 207   int ps_regnum;                /* Register number for PS.  */
 208   int lbeg_regnum;              /* Register numbers for count regs.  */
 209   int lend_regnum;
 210   int lcount_regnum;
 211   int sar_regnum;               /* Register number of SAR.  */
 212   int litbase_regnum;           /* Register number of LITBASE.  */
 213
 214   int interrupt_regnum;         /* Register number for interrupt.  */
 215   int interrupt2_regnum;        /* Register number for interrupt2.  */
 216   int cpenable_regnum;          /* Register number for cpenable.  */
 217   int debugcause_regnum;        /* Register number for debugcause.  */
 218   int exccause_regnum;          /* Register number for exccause.  */
 219   int excvaddr_regnum;          /* Register number for excvaddr.  */
 220
 221   int max_register_raw_size;
 222   int max_register_virtual_size;
 223   unsigned long *fp_layout;     /* Layout of custom/TIE regs in 'FP' area.  */
 224   unsigned int fp_layout_bytes; /* Size of layout information (in bytes).  */
 225   unsigned long *gregmap;
 226 };
 227
 228
 229 #define WB_SHIFT          2
 230
 231 /* We assign fixed numbers to the registers of the "current" window
 232    (i.e., relative to WB).  The registers get remapped via the reg_map
 233    data structure to their corresponding register in the AR register
 234    file (see xtensa-tdep.c).  */
 235