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1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 Contributed by Jiri Smid, SuSE Labs.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "defs.h"
24 #include "arch-utils.h"
25 #include "block.h"
26 #include "dummy-frame.h"
27 #include "frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
30 #include "inferior.h"
31 #include "gdbcmd.h"
32 #include "gdbcore.h"
33 #include "objfiles.h"
34 #include "regcache.h"
35 #include "regset.h"
36 #include "symfile.h"
38 #include "gdb_assert.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
43 /* Note that the AMD64 architecture was previously known as x86-64.
44 The latter is (forever) engraved into the canonical system name as
45 returned by config.guess, and used as the name for the AMD64 port
46 of GNU/Linux. The BSD's have renamed their ports to amd64; they
47 don't like to shout. For GDB we prefer the amd64_-prefix over the
48 x86_64_-prefix since it's so much easier to type. */
50 /* Register information. */
52 static const char *amd64_register_names[] =
54 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
56 /* %r8 is indeed register number 8. */
57 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
58 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
60 /* %st0 is register number 24. */
61 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
62 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
64 /* %xmm0 is register number 40. */
65 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
66 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
67 "mxcsr",
70 /* Total number of registers. */
71 #define AMD64_NUM_REGS ARRAY_SIZE (amd64_register_names)
73 /* Return the name of register REGNUM. */
75 const char *
76 amd64_register_name (struct gdbarch *gdbarch, int regnum)
78 if (regnum >= 0 && regnum < AMD64_NUM_REGS)
79 return amd64_register_names[regnum];
81 return NULL;
84 /* Return the GDB type object for the "standard" data type of data in
85 register REGNUM. */
87 struct type *
88 amd64_register_type (struct gdbarch *gdbarch, int regnum)
90 if (regnum >= AMD64_RAX_REGNUM && regnum <= AMD64_RDI_REGNUM)
91 return builtin_type_int64;
92 if (regnum == AMD64_RBP_REGNUM || regnum == AMD64_RSP_REGNUM)
93 return builtin_type_void_data_ptr;
94 if (regnum >= AMD64_R8_REGNUM && regnum <= AMD64_R15_REGNUM)
95 return builtin_type_int64;
96 if (regnum == AMD64_RIP_REGNUM)
97 return builtin_type_void_func_ptr;
98 if (regnum == AMD64_EFLAGS_REGNUM)
99 return i386_eflags_type;
100 if (regnum >= AMD64_CS_REGNUM && regnum <= AMD64_GS_REGNUM)
101 return builtin_type_int32;
102 if (regnum >= AMD64_ST0_REGNUM && regnum <= AMD64_ST0_REGNUM + 7)
103 return builtin_type_i387_ext;
104 if (regnum >= AMD64_FCTRL_REGNUM && regnum <= AMD64_FCTRL_REGNUM + 7)
105 return builtin_type_int32;
106 if (regnum >= AMD64_XMM0_REGNUM && regnum <= AMD64_XMM0_REGNUM + 15)
107 return i386_sse_type (gdbarch);
108 if (regnum == AMD64_MXCSR_REGNUM)
109 return i386_mxcsr_type;
111 internal_error (__FILE__, __LINE__, _("invalid regnum"));
114 /* DWARF Register Number Mapping as defined in the System V psABI,
115 section 3.6. */
117 static int amd64_dwarf_regmap[] =
119 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
120 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
121 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
122 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
124 /* Frame Pointer Register RBP. */
125 AMD64_RBP_REGNUM,
127 /* Stack Pointer Register RSP. */
128 AMD64_RSP_REGNUM,
130 /* Extended Integer Registers 8 - 15. */
131 8, 9, 10, 11, 12, 13, 14, 15,
133 /* Return Address RA. Mapped to RIP. */
134 AMD64_RIP_REGNUM,
136 /* SSE Registers 0 - 7. */
137 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
138 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
139 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
140 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
142 /* Extended SSE Registers 8 - 15. */
143 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
144 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
145 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
146 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
148 /* Floating Point Registers 0-7. */
149 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
150 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
151 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
152 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
154 /* Control and Status Flags Register. */
155 AMD64_EFLAGS_REGNUM,
157 /* Selector Registers. */
158 AMD64_ES_REGNUM,
159 AMD64_CS_REGNUM,
160 AMD64_SS_REGNUM,
161 AMD64_DS_REGNUM,
162 AMD64_FS_REGNUM,
163 AMD64_GS_REGNUM,
167 /* Segment Base Address Registers. */
173 /* Special Selector Registers. */
177 /* Floating Point Control Registers. */
178 AMD64_MXCSR_REGNUM,
179 AMD64_FCTRL_REGNUM,
180 AMD64_FSTAT_REGNUM
183 static const int amd64_dwarf_regmap_len =
184 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
186 /* Convert DWARF register number REG to the appropriate register
187 number used by GDB. */
189 static int
190 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
192 int regnum = -1;
194 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
195 regnum = amd64_dwarf_regmap[reg];
197 if (regnum == -1)
198 warning (_("Unmapped DWARF Register #%d encountered."), reg);
200 return regnum;
205 /* Register classes as defined in the psABI. */
207 enum amd64_reg_class
209 AMD64_INTEGER,
210 AMD64_SSE,
211 AMD64_SSEUP,
212 AMD64_X87,
213 AMD64_X87UP,
214 AMD64_COMPLEX_X87,
215 AMD64_NO_CLASS,
216 AMD64_MEMORY
219 /* Return the union class of CLASS1 and CLASS2. See the psABI for
220 details. */
222 static enum amd64_reg_class
223 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
225 /* Rule (a): If both classes are equal, this is the resulting class. */
226 if (class1 == class2)
227 return class1;
229 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
230 is the other class. */
231 if (class1 == AMD64_NO_CLASS)
232 return class2;
233 if (class2 == AMD64_NO_CLASS)
234 return class1;
236 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
237 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
238 return AMD64_MEMORY;
240 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
241 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
242 return AMD64_INTEGER;
244 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
245 MEMORY is used as class. */
246 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
247 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
248 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
249 return AMD64_MEMORY;
251 /* Rule (f): Otherwise class SSE is used. */
252 return AMD64_SSE;
255 static void amd64_classify (struct type *type, enum amd64_reg_class class[2]);
257 /* Return non-zero if TYPE is a non-POD structure or union type. */
259 static int
260 amd64_non_pod_p (struct type *type)
262 /* ??? A class with a base class certainly isn't POD, but does this
263 catch all non-POD structure types? */
264 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
265 return 1;
267 return 0;
270 /* Classify TYPE according to the rules for aggregate (structures and
271 arrays) and union types, and store the result in CLASS. */
273 static void
274 amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
276 int len = TYPE_LENGTH (type);
278 /* 1. If the size of an object is larger than two eightbytes, or in
279 C++, is a non-POD structure or union type, or contains
280 unaligned fields, it has class memory. */
281 if (len > 16 || amd64_non_pod_p (type))
283 class[0] = class[1] = AMD64_MEMORY;
284 return;
287 /* 2. Both eightbytes get initialized to class NO_CLASS. */
288 class[0] = class[1] = AMD64_NO_CLASS;
290 /* 3. Each field of an object is classified recursively so that
291 always two fields are considered. The resulting class is
292 calculated according to the classes of the fields in the
293 eightbyte: */
295 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
297 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
299 /* All fields in an array have the same type. */
300 amd64_classify (subtype, class);
301 if (len > 8 && class[1] == AMD64_NO_CLASS)
302 class[1] = class[0];
304 else
306 int i;
308 /* Structure or union. */
309 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
310 || TYPE_CODE (type) == TYPE_CODE_UNION);
312 for (i = 0; i < TYPE_NFIELDS (type); i++)
314 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
315 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
316 enum amd64_reg_class subclass[2];
318 /* Ignore static fields. */
319 if (TYPE_FIELD_STATIC (type, i))
320 continue;
322 gdb_assert (pos == 0 || pos == 1);
324 amd64_classify (subtype, subclass);
325 class[pos] = amd64_merge_classes (class[pos], subclass[0]);
326 if (pos == 0)
327 class[1] = amd64_merge_classes (class[1], subclass[1]);
331 /* 4. Then a post merger cleanup is done: */
333 /* Rule (a): If one of the classes is MEMORY, the whole argument is
334 passed in memory. */
335 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
336 class[0] = class[1] = AMD64_MEMORY;
338 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
339 SSE. */
340 if (class[0] == AMD64_SSEUP)
341 class[0] = AMD64_SSE;
342 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
343 class[1] = AMD64_SSE;
346 /* Classify TYPE, and store the result in CLASS. */
348 static void
349 amd64_classify (struct type *type, enum amd64_reg_class class[2])
351 enum type_code code = TYPE_CODE (type);
352 int len = TYPE_LENGTH (type);
354 class[0] = class[1] = AMD64_NO_CLASS;
356 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
357 long, long long, and pointers are in the INTEGER class. Similarly,
358 range types, used by languages such as Ada, are also in the INTEGER
359 class. */
360 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
361 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
362 || code == TYPE_CODE_CHAR
363 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
364 && (len == 1 || len == 2 || len == 4 || len == 8))
365 class[0] = AMD64_INTEGER;
367 /* Arguments of types float, double and __m64 are in class SSE. */
368 else if (code == TYPE_CODE_FLT && (len == 4 || len == 8))
369 /* FIXME: __m64 . */
370 class[0] = AMD64_SSE;
372 /* Arguments of types __float128 and __m128 are split into two
373 halves. The least significant ones belong to class SSE, the most
374 significant one to class SSEUP. */
375 /* FIXME: __float128, __m128. */
377 /* The 64-bit mantissa of arguments of type long double belongs to
378 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
379 class X87UP. */
380 else if (code == TYPE_CODE_FLT && len == 16)
381 /* Class X87 and X87UP. */
382 class[0] = AMD64_X87, class[1] = AMD64_X87UP;
384 /* Aggregates. */
385 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
386 || code == TYPE_CODE_UNION)
387 amd64_classify_aggregate (type, class);
390 static enum return_value_convention
391 amd64_return_value (struct gdbarch *gdbarch, struct type *type,
392 struct regcache *regcache,
393 gdb_byte *readbuf, const gdb_byte *writebuf)
395 enum amd64_reg_class class[2];
396 int len = TYPE_LENGTH (type);
397 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
398 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
399 int integer_reg = 0;
400 int sse_reg = 0;
401 int i;
403 gdb_assert (!(readbuf && writebuf));
405 /* 1. Classify the return type with the classification algorithm. */
406 amd64_classify (type, class);
408 /* 2. If the type has class MEMORY, then the caller provides space
409 for the return value and passes the address of this storage in
410 %rdi as if it were the first argument to the function. In effect,
411 this address becomes a hidden first argument.
413 On return %rax will contain the address that has been passed in
414 by the caller in %rdi. */
415 if (class[0] == AMD64_MEMORY)
417 /* As indicated by the comment above, the ABI guarantees that we
418 can always find the return value just after the function has
419 returned. */
421 if (readbuf)
423 ULONGEST addr;
425 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
426 read_memory (addr, readbuf, TYPE_LENGTH (type));
429 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
432 gdb_assert (class[1] != AMD64_MEMORY);
433 gdb_assert (len <= 16);
435 for (i = 0; len > 0; i++, len -= 8)
437 int regnum = -1;
438 int offset = 0;
440 switch (class[i])
442 case AMD64_INTEGER:
443 /* 3. If the class is INTEGER, the next available register
444 of the sequence %rax, %rdx is used. */
445 regnum = integer_regnum[integer_reg++];
446 break;
448 case AMD64_SSE:
449 /* 4. If the class is SSE, the next available SSE register
450 of the sequence %xmm0, %xmm1 is used. */
451 regnum = sse_regnum[sse_reg++];
452 break;
454 case AMD64_SSEUP:
455 /* 5. If the class is SSEUP, the eightbyte is passed in the
456 upper half of the last used SSE register. */
457 gdb_assert (sse_reg > 0);
458 regnum = sse_regnum[sse_reg - 1];
459 offset = 8;
460 break;
462 case AMD64_X87:
463 /* 6. If the class is X87, the value is returned on the X87
464 stack in %st0 as 80-bit x87 number. */
465 regnum = AMD64_ST0_REGNUM;
466 if (writebuf)
467 i387_return_value (gdbarch, regcache);
468 break;
470 case AMD64_X87UP:
471 /* 7. If the class is X87UP, the value is returned together
472 with the previous X87 value in %st0. */
473 gdb_assert (i > 0 && class[0] == AMD64_X87);
474 regnum = AMD64_ST0_REGNUM;
475 offset = 8;
476 len = 2;
477 break;
479 case AMD64_NO_CLASS:
480 continue;
482 default:
483 gdb_assert (!"Unexpected register class.");
486 gdb_assert (regnum != -1);
488 if (readbuf)
489 regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
490 readbuf + i * 8);
491 if (writebuf)
492 regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
493 writebuf + i * 8);
496 return RETURN_VALUE_REGISTER_CONVENTION;
500 static CORE_ADDR
501 amd64_push_arguments (struct regcache *regcache, int nargs,
502 struct value **args, CORE_ADDR sp, int struct_return)
504 static int integer_regnum[] =
506 AMD64_RDI_REGNUM, /* %rdi */
507 AMD64_RSI_REGNUM, /* %rsi */
508 AMD64_RDX_REGNUM, /* %rdx */
509 AMD64_RCX_REGNUM, /* %rcx */
510 8, /* %r8 */
511 9 /* %r9 */
513 static int sse_regnum[] =
515 /* %xmm0 ... %xmm7 */
516 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
517 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
518 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
519 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
521 struct value **stack_args = alloca (nargs * sizeof (struct value *));
522 int num_stack_args = 0;
523 int num_elements = 0;
524 int element = 0;
525 int integer_reg = 0;
526 int sse_reg = 0;
527 int i;
529 /* Reserve a register for the "hidden" argument. */
530 if (struct_return)
531 integer_reg++;
533 for (i = 0; i < nargs; i++)
535 struct type *type = value_type (args[i]);
536 int len = TYPE_LENGTH (type);
537 enum amd64_reg_class class[2];
538 int needed_integer_regs = 0;
539 int needed_sse_regs = 0;
540 int j;
542 /* Classify argument. */
543 amd64_classify (type, class);
545 /* Calculate the number of integer and SSE registers needed for
546 this argument. */
547 for (j = 0; j < 2; j++)
549 if (class[j] == AMD64_INTEGER)
550 needed_integer_regs++;
551 else if (class[j] == AMD64_SSE)
552 needed_sse_regs++;
555 /* Check whether enough registers are available, and if the
556 argument should be passed in registers at all. */
557 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
558 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
559 || (needed_integer_regs == 0 && needed_sse_regs == 0))
561 /* The argument will be passed on the stack. */
562 num_elements += ((len + 7) / 8);
563 stack_args[num_stack_args++] = args[i];
565 else
567 /* The argument will be passed in registers. */
568 const gdb_byte *valbuf = value_contents (args[i]);
569 gdb_byte buf[8];
571 gdb_assert (len <= 16);
573 for (j = 0; len > 0; j++, len -= 8)
575 int regnum = -1;
576 int offset = 0;
578 switch (class[j])
580 case AMD64_INTEGER:
581 regnum = integer_regnum[integer_reg++];
582 break;
584 case AMD64_SSE:
585 regnum = sse_regnum[sse_reg++];
586 break;
588 case AMD64_SSEUP:
589 gdb_assert (sse_reg > 0);
590 regnum = sse_regnum[sse_reg - 1];
591 offset = 8;
592 break;
594 default:
595 gdb_assert (!"Unexpected register class.");
598 gdb_assert (regnum != -1);
599 memset (buf, 0, sizeof buf);
600 memcpy (buf, valbuf + j * 8, min (len, 8));
601 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
606 /* Allocate space for the arguments on the stack. */
607 sp -= num_elements * 8;
609 /* The psABI says that "The end of the input argument area shall be
610 aligned on a 16 byte boundary." */
611 sp &= ~0xf;
613 /* Write out the arguments to the stack. */
614 for (i = 0; i < num_stack_args; i++)
616 struct type *type = value_type (stack_args[i]);
617 const gdb_byte *valbuf = value_contents (stack_args[i]);
618 int len = TYPE_LENGTH (type);
620 write_memory (sp + element * 8, valbuf, len);
621 element += ((len + 7) / 8);
624 /* The psABI says that "For calls that may call functions that use
625 varargs or stdargs (prototype-less calls or calls to functions
626 containing ellipsis (...) in the declaration) %al is used as
627 hidden argument to specify the number of SSE registers used. */
628 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
629 return sp;
632 static CORE_ADDR
633 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
634 struct regcache *regcache, CORE_ADDR bp_addr,
635 int nargs, struct value **args, CORE_ADDR sp,
636 int struct_return, CORE_ADDR struct_addr)
638 gdb_byte buf[8];
640 /* Pass arguments. */
641 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
643 /* Pass "hidden" argument". */
644 if (struct_return)
646 store_unsigned_integer (buf, 8, struct_addr);
647 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
650 /* Store return address. */
651 sp -= 8;
652 store_unsigned_integer (buf, 8, bp_addr);
653 write_memory (sp, buf, 8);
655 /* Finally, update the stack pointer... */
656 store_unsigned_integer (buf, 8, sp);
657 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
659 /* ...and fake a frame pointer. */
660 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
662 return sp + 16;
666 /* The maximum number of saved registers. This should include %rip. */
667 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
669 struct amd64_frame_cache
671 /* Base address. */
672 CORE_ADDR base;
673 CORE_ADDR sp_offset;
674 CORE_ADDR pc;
676 /* Saved registers. */
677 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
678 CORE_ADDR saved_sp;
680 /* Do we have a frame? */
681 int frameless_p;
684 /* Initialize a frame cache. */
686 static void
687 amd64_init_frame_cache (struct amd64_frame_cache *cache)
689 int i;
691 /* Base address. */
692 cache->base = 0;
693 cache->sp_offset = -8;
694 cache->pc = 0;
696 /* Saved registers. We initialize these to -1 since zero is a valid
697 offset (that's where %rbp is supposed to be stored). */
698 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
699 cache->saved_regs[i] = -1;
700 cache->saved_sp = 0;
702 /* Frameless until proven otherwise. */
703 cache->frameless_p = 1;
706 /* Allocate and initialize a frame cache. */
708 static struct amd64_frame_cache *
709 amd64_alloc_frame_cache (void)
711 struct amd64_frame_cache *cache;
713 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
714 amd64_init_frame_cache (cache);
715 return cache;
718 /* Do a limited analysis of the prologue at PC and update CACHE
719 accordingly. Bail out early if CURRENT_PC is reached. Return the
720 address where the analysis stopped.
722 We will handle only functions beginning with:
724 pushq %rbp 0x55
725 movq %rsp, %rbp 0x48 0x89 0xe5
727 Any function that doesn't start with this sequence will be assumed
728 to have no prologue and thus no valid frame pointer in %rbp. */
730 static CORE_ADDR
731 amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
732 struct amd64_frame_cache *cache)
734 static gdb_byte proto[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */
735 gdb_byte buf[3];
736 gdb_byte op;
738 if (current_pc <= pc)
739 return current_pc;
741 op = read_memory_unsigned_integer (pc, 1);
743 if (op == 0x55) /* pushq %rbp */
745 /* Take into account that we've executed the `pushq %rbp' that
746 starts this instruction sequence. */
747 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
748 cache->sp_offset += 8;
750 /* If that's all, return now. */
751 if (current_pc <= pc + 1)
752 return current_pc;
754 /* Check for `movq %rsp, %rbp'. */
755 read_memory (pc + 1, buf, 3);
756 if (memcmp (buf, proto, 3) != 0)
757 return pc + 1;
759 /* OK, we actually have a frame. */
760 cache->frameless_p = 0;
761 return pc + 4;
764 return pc;
767 /* Return PC of first real instruction. */
769 static CORE_ADDR
770 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
772 struct amd64_frame_cache cache;
773 CORE_ADDR pc;
775 amd64_init_frame_cache (&cache);
776 pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffffLL, &cache);
777 if (cache.frameless_p)
778 return start_pc;
780 return pc;
784 /* Normal frames. */
786 static struct amd64_frame_cache *
787 amd64_frame_cache (struct frame_info *next_frame, void **this_cache)
789 struct amd64_frame_cache *cache;
790 gdb_byte buf[8];
791 int i;
793 if (*this_cache)
794 return *this_cache;
796 cache = amd64_alloc_frame_cache ();
797 *this_cache = cache;
799 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
800 if (cache->pc != 0)
801 amd64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
803 if (cache->frameless_p)
805 /* We didn't find a valid frame. If we're at the start of a
806 function, or somewhere half-way its prologue, the function's
807 frame probably hasn't been fully setup yet. Try to
808 reconstruct the base address for the stack frame by looking
809 at the stack pointer. For truly "frameless" functions this
810 might work too. */
812 frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf);
813 cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset;
815 else
817 frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf);
818 cache->base = extract_unsigned_integer (buf, 8);
821 /* Now that we have the base address for the stack frame we can
822 calculate the value of %rsp in the calling frame. */
823 cache->saved_sp = cache->base + 16;
825 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
826 frame we find it at the same offset from the reconstructed base
827 address. */
828 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
830 /* Adjust all the saved registers such that they contain addresses
831 instead of offsets. */
832 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
833 if (cache->saved_regs[i] != -1)
834 cache->saved_regs[i] += cache->base;
836 return cache;
839 static void
840 amd64_frame_this_id (struct frame_info *next_frame, void **this_cache,
841 struct frame_id *this_id)
843 struct amd64_frame_cache *cache =
844 amd64_frame_cache (next_frame, this_cache);
846 /* This marks the outermost frame. */
847 if (cache->base == 0)
848 return;
850 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
853 static void
854 amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
855 int regnum, int *optimizedp,
856 enum lval_type *lvalp, CORE_ADDR *addrp,
857 int *realnump, gdb_byte *valuep)
859 struct gdbarch *gdbarch = get_frame_arch (next_frame);
860 struct amd64_frame_cache *cache =
861 amd64_frame_cache (next_frame, this_cache);
863 gdb_assert (regnum >= 0);
865 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
867 *optimizedp = 0;
868 *lvalp = not_lval;
869 *addrp = 0;
870 *realnump = -1;
871 if (valuep)
873 /* Store the value. */
874 store_unsigned_integer (valuep, 8, cache->saved_sp);
876 return;
879 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
881 *optimizedp = 0;
882 *lvalp = lval_memory;
883 *addrp = cache->saved_regs[regnum];
884 *realnump = -1;
885 if (valuep)
887 /* Read the value in from memory. */
888 read_memory (*addrp, valuep,
889 register_size (gdbarch, regnum));
891 return;
894 *optimizedp = 0;
895 *lvalp = lval_register;
896 *addrp = 0;
897 *realnump = regnum;
898 if (valuep)
899 frame_unwind_register (next_frame, (*realnump), valuep);
902 static const struct frame_unwind amd64_frame_unwind =
904 NORMAL_FRAME,
905 amd64_frame_this_id,
906 amd64_frame_prev_register
909 static const struct frame_unwind *
910 amd64_frame_sniffer (struct frame_info *next_frame)
912 return &amd64_frame_unwind;
916 /* Signal trampolines. */
918 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
919 64-bit variants. This would require using identical frame caches
920 on both platforms. */
922 static struct amd64_frame_cache *
923 amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
925 struct amd64_frame_cache *cache;
926 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
927 CORE_ADDR addr;
928 gdb_byte buf[8];
929 int i;
931 if (*this_cache)
932 return *this_cache;
934 cache = amd64_alloc_frame_cache ();
936 frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf);
937 cache->base = extract_unsigned_integer (buf, 8) - 8;
939 addr = tdep->sigcontext_addr (next_frame);
940 gdb_assert (tdep->sc_reg_offset);
941 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
942 for (i = 0; i < tdep->sc_num_regs; i++)
943 if (tdep->sc_reg_offset[i] != -1)
944 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
946 *this_cache = cache;
947 return cache;
950 static void
951 amd64_sigtramp_frame_this_id (struct frame_info *next_frame,
952 void **this_cache, struct frame_id *this_id)
954 struct amd64_frame_cache *cache =
955 amd64_sigtramp_frame_cache (next_frame, this_cache);
957 (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame));
960 static void
961 amd64_sigtramp_frame_prev_register (struct frame_info *next_frame,
962 void **this_cache,
963 int regnum, int *optimizedp,
964 enum lval_type *lvalp, CORE_ADDR *addrp,
965 int *realnump, gdb_byte *valuep)
967 /* Make sure we've initialized the cache. */
968 amd64_sigtramp_frame_cache (next_frame, this_cache);
970 amd64_frame_prev_register (next_frame, this_cache, regnum,
971 optimizedp, lvalp, addrp, realnump, valuep);
974 static const struct frame_unwind amd64_sigtramp_frame_unwind =
976 SIGTRAMP_FRAME,
977 amd64_sigtramp_frame_this_id,
978 amd64_sigtramp_frame_prev_register
981 static const struct frame_unwind *
982 amd64_sigtramp_frame_sniffer (struct frame_info *next_frame)
984 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
986 /* We shouldn't even bother if we don't have a sigcontext_addr
987 handler. */
988 if (tdep->sigcontext_addr == NULL)
989 return NULL;
991 if (tdep->sigtramp_p != NULL)
993 if (tdep->sigtramp_p (next_frame))
994 return &amd64_sigtramp_frame_unwind;
997 if (tdep->sigtramp_start != 0)
999 CORE_ADDR pc = frame_pc_unwind (next_frame);
1001 gdb_assert (tdep->sigtramp_end != 0);
1002 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
1003 return &amd64_sigtramp_frame_unwind;
1006 return NULL;
1010 static CORE_ADDR
1011 amd64_frame_base_address (struct frame_info *next_frame, void **this_cache)
1013 struct amd64_frame_cache *cache =
1014 amd64_frame_cache (next_frame, this_cache);
1016 return cache->base;
1019 static const struct frame_base amd64_frame_base =
1021 &amd64_frame_unwind,
1022 amd64_frame_base_address,
1023 amd64_frame_base_address,
1024 amd64_frame_base_address
1027 static struct frame_id
1028 amd64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1030 gdb_byte buf[8];
1031 CORE_ADDR fp;
1033 frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf);
1034 fp = extract_unsigned_integer (buf, 8);
1036 return frame_id_build (fp + 16, frame_pc_unwind (next_frame));
1039 /* 16 byte align the SP per frame requirements. */
1041 static CORE_ADDR
1042 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1044 return sp & -(CORE_ADDR)16;
1048 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
1049 in the floating-point register set REGSET to register cache
1050 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
1052 static void
1053 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
1054 int regnum, const void *fpregs, size_t len)
1056 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
1058 gdb_assert (len == tdep->sizeof_fpregset);
1059 amd64_supply_fxsave (regcache, regnum, fpregs);
1062 /* Collect register REGNUM from the register cache REGCACHE and store
1063 it in the buffer specified by FPREGS and LEN as described by the
1064 floating-point register set REGSET. If REGNUM is -1, do this for
1065 all registers in REGSET. */
1067 static void
1068 amd64_collect_fpregset (const struct regset *regset,
1069 const struct regcache *regcache,
1070 int regnum, void *fpregs, size_t len)
1072 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
1074 gdb_assert (len == tdep->sizeof_fpregset);
1075 amd64_collect_fxsave (regcache, regnum, fpregs);
1078 /* Return the appropriate register set for the core section identified
1079 by SECT_NAME and SECT_SIZE. */
1081 static const struct regset *
1082 amd64_regset_from_core_section (struct gdbarch *gdbarch,
1083 const char *sect_name, size_t sect_size)
1085 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1087 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
1089 if (tdep->fpregset == NULL)
1090 tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset,
1091 amd64_collect_fpregset);
1093 return tdep->fpregset;
1096 return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
1100 void
1101 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
1103 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1105 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
1106 floating-point registers. */
1107 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
1109 /* AMD64 has an FPU and 16 SSE registers. */
1110 tdep->st0_regnum = AMD64_ST0_REGNUM;
1111 tdep->num_xmm_regs = 16;
1113 /* This is what all the fuss is about. */
1114 set_gdbarch_long_bit (gdbarch, 64);
1115 set_gdbarch_long_long_bit (gdbarch, 64);
1116 set_gdbarch_ptr_bit (gdbarch, 64);
1118 /* In contrast to the i386, on AMD64 a `long double' actually takes
1119 up 128 bits, even though it's still based on the i387 extended
1120 floating-point format which has only 80 significant bits. */
1121 set_gdbarch_long_double_bit (gdbarch, 128);
1123 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
1124 set_gdbarch_register_name (gdbarch, amd64_register_name);
1125 set_gdbarch_register_type (gdbarch, amd64_register_type);
1127 /* Register numbers of various important registers. */
1128 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
1129 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
1130 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
1131 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
1133 /* The "default" register numbering scheme for AMD64 is referred to
1134 as the "DWARF Register Number Mapping" in the System V psABI.
1135 The preferred debugging format for all known AMD64 targets is
1136 actually DWARF2, and GCC doesn't seem to support DWARF (that is
1137 DWARF-1), but we provide the same mapping just in case. This
1138 mapping is also used for stabs, which GCC does support. */
1139 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1140 set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1141 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1143 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1144 be in use on any of the supported AMD64 targets. */
1146 /* Call dummy code. */
1147 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
1148 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
1149 set_gdbarch_frame_red_zone_size (gdbarch, 128);
1151 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
1152 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
1153 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
1155 set_gdbarch_return_value (gdbarch, amd64_return_value);
1157 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
1159 /* Avoid wiring in the MMX registers for now. */
1160 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1161 tdep->mm0_regnum = -1;
1163 set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id);
1165 frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer);
1166 frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer);
1167 frame_base_set_default (gdbarch, &amd64_frame_base);
1169 /* If we have a register mapping, enable the generic core file support. */
1170 if (tdep->gregset_reg_offset)
1171 set_gdbarch_regset_from_core_section (gdbarch,
1172 amd64_regset_from_core_section);
1176 #define I387_ST0_REGNUM AMD64_ST0_REGNUM
1178 /* The 64-bit FXSAVE format differs from the 32-bit format in the
1179 sense that the instruction pointer and data pointer are simply
1180 64-bit offsets into the code segment and the data segment instead
1181 of a selector offset pair. The functions below store the upper 32
1182 bits of these pointers (instead of just the 16-bits of the segment
1183 selector). */
1185 /* Fill register REGNUM in REGCACHE with the appropriate
1186 floating-point or SSE register value from *FXSAVE. If REGNUM is
1187 -1, do this for all registers. This function masks off any of the
1188 reserved bits in *FXSAVE. */
1190 void
1191 amd64_supply_fxsave (struct regcache *regcache, int regnum,
1192 const void *fxsave)
1194 i387_supply_fxsave (regcache, regnum, fxsave);
1196 if (fxsave && gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1198 const gdb_byte *regs = fxsave;
1200 if (regnum == -1 || regnum == I387_FISEG_REGNUM)
1201 regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12);
1202 if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
1203 regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20);
1207 /* Fill register REGNUM (if it is a floating-point or SSE register) in
1208 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
1209 all registers. This function doesn't touch any of the reserved
1210 bits in *FXSAVE. */
1212 void
1213 amd64_collect_fxsave (const struct regcache *regcache, int regnum,
1214 void *fxsave)
1216 gdb_byte *regs = fxsave;
1218 i387_collect_fxsave (regcache, regnum, fxsave);
1220 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1222 if (regnum == -1 || regnum == I387_FISEG_REGNUM)
1223 regcache_raw_collect (regcache, I387_FISEG_REGNUM, regs + 12);
1224 if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
1225 regcache_raw_collect (regcache, I387_FOSEG_REGNUM, regs + 20);