1 /* $NetBSD: if_admsw.c,v 1.3 2007/04/22 19:26:25 dyoung Exp $ */
4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
7 * Redistribution and use in source and binary forms, with or
8 * without modification, are permitted provided that the following
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above
13 * copyright notice, this list of conditions and the following
14 * disclaimer in the documentation and/or other materials provided
15 * with the distribution.
16 * 3. The names of the authors may not be used to endorse or promote
17 * products derived from this software without specific prior
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
34 * Copyright (c) 2001 Wasabi Systems, Inc.
35 * All rights reserved.
37 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * 2. Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in the
46 * documentation and/or other materials provided with the distribution.
47 * 3. All advertising materials mentioning features or use of this software
48 * must display the following acknowledgement:
49 * This product includes software developed for the NetBSD Project by
50 * Wasabi Systems, Inc.
51 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
52 * or promote products derived from this software without specific prior
55 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
65 * POSSIBILITY OF SUCH DAMAGE.
69 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media
74 * Better Rx buffer management; we want to get new Rx buffers
75 * to the chip more quickly than we currently do.
78 #include <sys/cdefs.h>
79 __FBSDID("$FreeBSD$");
81 #include <sys/param.h>
82 #include <sys/systm.h>
84 #include <sys/kernel.h>
86 #include <sys/malloc.h>
87 #include <sys/module.h>
89 #include <sys/socket.h>
90 #include <sys/sockio.h>
91 #include <sys/sysctl.h>
92 #include <machine/bus.h>
94 #include <net/ethernet.h>
96 #include <net/if_arp.h>
97 #include <net/if_dl.h>
98 #include <net/if_media.h>
99 #include <net/if_mib.h>
100 #include <net/if_types.h>
101 #include <net/if_var.h>
104 #include <netinet/in.h>
105 #include <netinet/in_systm.h>
106 #include <netinet/in_var.h>
107 #include <netinet/ip.h>
111 #include <net/bpfdesc.h>
113 #include <mips/adm5120/adm5120reg.h>
114 #include <mips/adm5120/if_admswreg.h>
115 #include <mips/adm5120/if_admswvar.h>
117 /* TODO: add locking */
118 #define ADMSW_LOCK(sc) do {} while(0);
119 #define ADMSW_UNLOCK(sc) do {} while(0);
121 static uint8_t vlan_matrix
[SW_DEVS
] = {
122 (1 << 6) | (1 << 0), /* CPU + port0 */
123 (1 << 6) | (1 << 1), /* CPU + port1 */
124 (1 << 6) | (1 << 2), /* CPU + port2 */
125 (1 << 6) | (1 << 3), /* CPU + port3 */
126 (1 << 6) | (1 << 4), /* CPU + port4 */
127 (1 << 6) | (1 << 5), /* CPU + port5 */
130 /* ifnet entry points */
131 static void admsw_start(struct ifnet
*);
132 static void admsw_watchdog(void *);
133 static int admsw_ioctl(struct ifnet
*, u_long
, caddr_t
);
134 static void admsw_init(void *);
135 static void admsw_stop(struct ifnet
*, int);
137 static void admsw_reset(struct admsw_softc
*);
138 static void admsw_set_filter(struct admsw_softc
*);
140 static void admsw_txintr(struct admsw_softc
*, int);
141 static void admsw_rxintr(struct admsw_softc
*, int);
142 static int admsw_add_rxbuf(struct admsw_softc
*, int, int);
143 #define admsw_add_rxhbuf(sc, idx) admsw_add_rxbuf(sc, idx, 1)
144 #define admsw_add_rxlbuf(sc, idx) admsw_add_rxbuf(sc, idx, 0)
146 static int admsw_mediachange(struct ifnet
*);
147 static void admsw_mediastatus(struct ifnet
*, struct ifmediareq
*);
149 static int admsw_intr(void *);
151 /* bus entry points */
152 static int admsw_probe(device_t dev
);
153 static int admsw_attach(device_t dev
);
154 static int admsw_detach(device_t dev
);
155 static int admsw_shutdown(device_t dev
);
158 admsw_dma_map_addr(void *arg
, bus_dma_segment_t
*segs
, int nseg
, int error
)
165 KASSERT(nseg
== 1, ("too many DMA segments, %d should be 1", nseg
));
167 *addr
= segs
->ds_addr
;
171 admsw_rxbuf_map_addr(void *arg
, bus_dma_segment_t
*segs
, int nseg
, int error
)
173 struct admsw_descsoft
*ds
;
178 KASSERT(nseg
== 1, ("too many DMA segments, %d should be 1", nseg
));
182 ds
->ds_addr
[0] = segs
[0].ds_addr
;
183 ds
->ds_len
[0] = segs
[0].ds_len
;
188 admsw_mbuf_map_addr(void *arg
, bus_dma_segment_t
*segs
, int nseg
,
189 bus_size_t mapsize
, int error
)
191 struct admsw_descsoft
*ds
;
198 if((nseg
!= 1) && (nseg
!= 2))
199 panic("%s: nseg == %d\n", __func__
, nseg
);
202 ds
->ds_addr
[0] = segs
[0].ds_addr
;
203 ds
->ds_len
[0] = segs
[0].ds_len
;
206 ds
->ds_addr
[1] = segs
[1].ds_addr
;
207 ds
->ds_len
[1] = segs
[1].ds_len
;
214 admsw_probe(device_t dev
)
217 device_set_desc(dev
, "ADM5120 Switch Engine");
221 #define REG_READ(o) bus_read_4((sc)->mem_res, (o))
222 #define REG_WRITE(o,v) bus_write_4((sc)->mem_res, (o),(v))
225 admsw_init_bufs(struct admsw_softc
*sc
)
228 struct admsw_desc
*desc
;
230 for (i
= 0; i
< ADMSW_NTXHDESC
; i
++) {
231 if (sc
->sc_txhsoft
[i
].ds_mbuf
!= NULL
) {
232 m_freem(sc
->sc_txhsoft
[i
].ds_mbuf
);
233 sc
->sc_txhsoft
[i
].ds_mbuf
= NULL
;
235 desc
= &sc
->sc_txhdescs
[i
];
238 desc
->len
= MAC_BUFLEN
;
240 ADMSW_CDTXHSYNC(sc
, i
,
241 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
243 sc
->sc_txhdescs
[ADMSW_NTXHDESC
- 1].data
|= ADM5120_DMA_RINGEND
;
244 ADMSW_CDTXHSYNC(sc
, ADMSW_NTXHDESC
- 1,
245 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
247 for (i
= 0; i
< ADMSW_NRXHDESC
; i
++) {
248 if (sc
->sc_rxhsoft
[i
].ds_mbuf
== NULL
) {
249 if (admsw_add_rxhbuf(sc
, i
) != 0)
250 panic("admsw_init_bufs\n");
252 ADMSW_INIT_RXHDESC(sc
, i
);
255 for (i
= 0; i
< ADMSW_NTXLDESC
; i
++) {
256 if (sc
->sc_txlsoft
[i
].ds_mbuf
!= NULL
) {
257 m_freem(sc
->sc_txlsoft
[i
].ds_mbuf
);
258 sc
->sc_txlsoft
[i
].ds_mbuf
= NULL
;
260 desc
= &sc
->sc_txldescs
[i
];
263 desc
->len
= MAC_BUFLEN
;
265 ADMSW_CDTXLSYNC(sc
, i
,
266 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
268 sc
->sc_txldescs
[ADMSW_NTXLDESC
- 1].data
|= ADM5120_DMA_RINGEND
;
269 ADMSW_CDTXLSYNC(sc
, ADMSW_NTXLDESC
- 1,
270 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
272 for (i
= 0; i
< ADMSW_NRXLDESC
; i
++) {
273 if (sc
->sc_rxlsoft
[i
].ds_mbuf
== NULL
) {
274 if (admsw_add_rxlbuf(sc
, i
) != 0)
275 panic("admsw_init_bufs\n");
277 ADMSW_INIT_RXLDESC(sc
, i
);
280 REG_WRITE(SEND_HBADDR_REG
, ADMSW_CDTXHADDR(sc
, 0));
281 REG_WRITE(SEND_LBADDR_REG
, ADMSW_CDTXLADDR(sc
, 0));
282 REG_WRITE(RECV_HBADDR_REG
, ADMSW_CDRXHADDR(sc
, 0));
283 REG_WRITE(RECV_LBADDR_REG
, ADMSW_CDRXLADDR(sc
, 0));
285 sc
->sc_txfree
= ADMSW_NTXLDESC
;
292 admsw_setvlan(struct admsw_softc
*sc
, char matrix
[6])
296 i
= matrix
[0] + (matrix
[1] << 8) + (matrix
[2] << 16) + (matrix
[3] << 24);
297 REG_WRITE(VLAN_G1_REG
, i
);
298 i
= matrix
[4] + (matrix
[5] << 8);
299 REG_WRITE(VLAN_G2_REG
, i
);
303 admsw_reset(struct admsw_softc
*sc
)
308 REG_WRITE(PORT_CONF0_REG
,
309 REG_READ(PORT_CONF0_REG
) | PORT_CONF0_DP_MASK
);
310 REG_WRITE(CPUP_CONF_REG
,
311 REG_READ(CPUP_CONF_REG
) | CPUP_CONF_DCPUP
);
313 /* Wait for DMA to complete. Overkill. In 3ms, we can
314 * send at least two entire 1500-byte packets at 10 Mb/s.
318 /* The datasheet recommends that we move all PHYs to reset
319 * state prior to software reset.
321 REG_WRITE(PHY_CNTL2_REG
,
322 REG_READ(PHY_CNTL2_REG
) & ~PHY_CNTL2_PHYR_MASK
);
324 /* Reset the switch. */
325 REG_WRITE(ADMSW_SW_RES
, 0x1);
329 REG_WRITE(ADMSW_BOOT_DONE
, ADMSW_BOOT_DONE_BO
);
332 REG_WRITE(CPUP_CONF_REG
,
333 CPUP_CONF_DCPUP
| CPUP_CONF_CRCP
| CPUP_CONF_DUNP_MASK
|
334 CPUP_CONF_DMCP_MASK
);
336 REG_WRITE(PORT_CONF0_REG
, PORT_CONF0_EMCP_MASK
| PORT_CONF0_EMBP_MASK
);
338 REG_WRITE(PHY_CNTL2_REG
,
339 REG_READ(PHY_CNTL2_REG
) | PHY_CNTL2_ANE_MASK
| PHY_CNTL2_PHYR_MASK
|
340 PHY_CNTL2_AMDIX_MASK
);
342 REG_WRITE(PHY_CNTL3_REG
, REG_READ(PHY_CNTL3_REG
) | PHY_CNTL3_RNT
);
344 REG_WRITE(ADMSW_INT_MASK
, INT_MASK
);
345 REG_WRITE(ADMSW_INT_ST
, INT_MASK
);
348 * While in DDB, we stop servicing interrupts, RX ring
349 * fills up and when free block counter falls behind FC
350 * threshold, the switch starts to emit 802.3x PAUSE
351 * frames. This can upset peer switches.
353 * Stop this from happening by disabling FC and D2
357 REG_READ(FC_TH_REG
) & ~(FC_TH_FCS_MASK
| FC_TH_D2S_MASK
));
359 admsw_setvlan(sc
, vlan_matrix
);
361 for (i
= 0; i
< SW_DEVS
; i
++) {
362 REG_WRITE(MAC_WT1_REG
,
364 (sc
->sc_enaddr
[3]<<8) |
365 (sc
->sc_enaddr
[4]<<16) |
366 ((sc
->sc_enaddr
[5]+i
)<<24));
367 REG_WRITE(MAC_WT0_REG
, (i
<<MAC_WT0_VLANID_SHIFT
) |
368 (sc
->sc_enaddr
[0]<<16) | (sc
->sc_enaddr
[1]<<24) |
369 MAC_WT0_WRITE
| MAC_WT0_VLANID_EN
);
371 while (!(REG_READ(MAC_WT0_REG
) & MAC_WT0_WRITE_DONE
));
374 wdog1
= REG_READ(ADM5120_WDOG1
);
375 REG_WRITE(ADM5120_WDOG1
, wdog1
& ~ADM5120_WDOG1_WDE
);
379 admsw_attach(device_t dev
)
381 uint8_t enaddr
[ETHER_ADDR_LEN
];
382 struct admsw_softc
*sc
= (struct admsw_softc
*) device_get_softc(dev
);
387 device_printf(dev
, "ADM5120 Switch Engine, %d ports\n", SW_DEVS
);
390 /* XXXMIPS: fix it */
398 memcpy(sc
->sc_enaddr
, enaddr
, sizeof(sc
->sc_enaddr
));
400 device_printf(sc
->sc_dev
, "base Ethernet address %s\n",
401 ether_sprintf(enaddr
));
402 callout_init(&sc
->sc_watchdog
, 1);
405 if ((sc
->mem_res
= bus_alloc_resource_any(dev
, SYS_RES_MEMORY
, &rid
,
406 RF_ACTIVE
)) == NULL
) {
407 device_printf(dev
, "unable to allocate memory resource\n");
411 /* Hook up the interrupt handler. */
413 if ((sc
->irq_res
= bus_alloc_resource_any(dev
, SYS_RES_IRQ
, &rid
,
414 RF_SHAREABLE
| RF_ACTIVE
)) == NULL
) {
415 device_printf(dev
, "unable to allocate IRQ resource\n");
419 if ((error
= bus_setup_intr(dev
, sc
->irq_res
, INTR_TYPE_NET
,
420 admsw_intr
, NULL
, sc
, &sc
->sc_ih
)) != 0) {
422 "WARNING: unable to register interrupt handler\n");
427 * Allocate the control data structures, and create and load the
430 if ((error
= bus_dma_tag_create(NULL
, 4, 0,
431 BUS_SPACE_MAXADDR_32BIT
, BUS_SPACE_MAXADDR
,
432 NULL
, NULL
, sizeof(struct admsw_control_data
), 1,
433 sizeof(struct admsw_control_data
), 0, NULL
, NULL
,
434 &sc
->sc_control_dmat
)) != 0) {
435 device_printf(sc
->sc_dev
,
436 "unable to create control data DMA map, error = %d\n",
441 if ((error
= bus_dmamem_alloc(sc
->sc_control_dmat
,
442 (void **)&sc
->sc_control_data
, BUS_DMA_NOWAIT
,
443 &sc
->sc_cddmamap
)) != 0) {
444 device_printf(sc
->sc_dev
,
445 "unable to allocate control data, error = %d\n", error
);
449 if ((error
= bus_dmamap_load(sc
->sc_control_dmat
, sc
->sc_cddmamap
,
450 sc
->sc_control_data
, sizeof(struct admsw_control_data
),
451 admsw_dma_map_addr
, &sc
->sc_cddma
, 0)) != 0) {
452 device_printf(sc
->sc_dev
,
453 "unable to load control data DMA map, error = %d\n", error
);
458 * Create the transmit buffer DMA maps.
460 if ((error
= bus_dma_tag_create(NULL
, 1, 0,
461 BUS_SPACE_MAXADDR_32BIT
, BUS_SPACE_MAXADDR
,
462 NULL
, NULL
, MCLBYTES
, 1, MCLBYTES
, 0, NULL
, NULL
,
463 &sc
->sc_bufs_dmat
)) != 0) {
464 device_printf(sc
->sc_dev
,
465 "unable to create control data DMA map, error = %d\n",
470 for (i
= 0; i
< ADMSW_NTXHDESC
; i
++) {
471 if ((error
= bus_dmamap_create(sc
->sc_bufs_dmat
, 0,
472 &sc
->sc_txhsoft
[i
].ds_dmamap
)) != 0) {
473 device_printf(sc
->sc_dev
,
474 "unable to create txh DMA map %d, error = %d\n",
478 sc
->sc_txhsoft
[i
].ds_mbuf
= NULL
;
481 for (i
= 0; i
< ADMSW_NTXLDESC
; i
++) {
482 if ((error
= bus_dmamap_create(sc
->sc_bufs_dmat
, 0,
483 &sc
->sc_txlsoft
[i
].ds_dmamap
)) != 0) {
484 device_printf(sc
->sc_dev
,
485 "unable to create txl DMA map %d, error = %d\n",
489 sc
->sc_txlsoft
[i
].ds_mbuf
= NULL
;
493 * Create the receive buffer DMA maps.
495 for (i
= 0; i
< ADMSW_NRXHDESC
; i
++) {
496 if ((error
= bus_dmamap_create(sc
->sc_bufs_dmat
, 0,
497 &sc
->sc_rxhsoft
[i
].ds_dmamap
)) != 0) {
498 device_printf(sc
->sc_dev
,
499 "unable to create rxh DMA map %d, error = %d\n",
503 sc
->sc_rxhsoft
[i
].ds_mbuf
= NULL
;
506 for (i
= 0; i
< ADMSW_NRXLDESC
; i
++) {
507 if ((error
= bus_dmamap_create(sc
->sc_bufs_dmat
, 0,
508 &sc
->sc_rxlsoft
[i
].ds_dmamap
)) != 0) {
509 device_printf(sc
->sc_dev
,
510 "unable to create rxl DMA map %d, error = %d\n",
514 sc
->sc_rxlsoft
[i
].ds_mbuf
= NULL
;
520 for (i
= 0; i
< SW_DEVS
; i
++) {
521 ifmedia_init(&sc
->sc_ifmedia
[i
], 0, admsw_mediachange
,
523 ifmedia_add(&sc
->sc_ifmedia
[i
], IFM_ETHER
|IFM_10_T
, 0, NULL
);
524 ifmedia_add(&sc
->sc_ifmedia
[i
],
525 IFM_ETHER
|IFM_10_T
|IFM_FDX
, 0, NULL
);
526 ifmedia_add(&sc
->sc_ifmedia
[i
], IFM_ETHER
|IFM_100_TX
, 0, NULL
);
527 ifmedia_add(&sc
->sc_ifmedia
[i
],
528 IFM_ETHER
|IFM_100_TX
|IFM_FDX
, 0, NULL
);
529 ifmedia_add(&sc
->sc_ifmedia
[i
], IFM_ETHER
|IFM_AUTO
, 0, NULL
);
530 ifmedia_set(&sc
->sc_ifmedia
[i
], IFM_ETHER
|IFM_AUTO
);
532 ifp
= sc
->sc_ifnet
[i
] = if_alloc(IFT_ETHER
);
534 /* Setup interface parameters */
536 if_initname(ifp
, device_get_name(dev
), i
);
537 ifp
->if_flags
= IFF_BROADCAST
| IFF_SIMPLEX
| IFF_MULTICAST
;
538 ifp
->if_ioctl
= admsw_ioctl
;
539 ifp
->if_output
= ether_output
;
540 ifp
->if_start
= admsw_start
;
541 ifp
->if_init
= admsw_init
;
542 ifp
->if_mtu
= ETHERMTU
;
543 ifp
->if_baudrate
= IF_Mbps(100);
544 IFQ_SET_MAXLEN(&ifp
->if_snd
, max(ADMSW_NTXLDESC
, ifqmaxlen
));
545 ifp
->if_snd
.ifq_drv_maxlen
= max(ADMSW_NTXLDESC
, ifqmaxlen
);
546 IFQ_SET_READY(&ifp
->if_snd
);
547 ifp
->if_capabilities
|= IFCAP_VLAN_MTU
;
549 /* Attach the interface. */
550 ether_ifattach(ifp
, enaddr
);
554 /* XXX: admwdog_attach(sc); */
556 /* leave interrupts and cpu port disabled */
561 admsw_detach(device_t dev
)
564 printf("TODO: DETACH\n");
571 * Make sure the interface is stopped at reboot time.
574 admsw_shutdown(device_t dev
)
576 struct admsw_softc
*sc
;
579 sc
= device_get_softc(dev
);
580 for (i
= 0; i
< SW_DEVS
; i
++)
581 admsw_stop(sc
->sc_ifnet
[i
], 1);
587 * admsw_start: [ifnet interface function]
589 * Start packet transmission on the interface.
592 admsw_start(struct ifnet
*ifp
)
594 struct admsw_softc
*sc
= ifp
->if_softc
;
596 struct admsw_descsoft
*ds
;
597 struct admsw_desc
*desc
;
599 struct ether_header
*eh
;
600 int error
, nexttx
, len
, i
;
604 * Loop through the send queues, setting up transmit descriptors
605 * unitl we drain the queues, or use up all available transmit
614 ifp
= sc
->sc_ifnet
[i
];
615 if ((ifp
->if_drv_flags
& (IFF_DRV_RUNNING
|IFF_DRV_OACTIVE
))
616 == IFF_DRV_RUNNING
) {
617 /* Grab a packet off the queue. */
618 IF_DEQUEUE(&ifp
->if_snd
, m0
);
631 /* Get a spare descriptor. */
632 if (sc
->sc_txfree
== 0) {
633 /* No more slots left; notify upper layer. */
634 ifp
->if_drv_flags
|= IFF_DRV_OACTIVE
;
637 nexttx
= sc
->sc_txnext
;
638 desc
= &sc
->sc_txldescs
[nexttx
];
639 ds
= &sc
->sc_txlsoft
[nexttx
];
640 dmamap
= ds
->ds_dmamap
;
643 * Load the DMA map. If this fails, the packet either
644 * didn't fit in the alloted number of segments, or we
645 * were short on resources. In this case, we'll copy
648 if (m0
->m_pkthdr
.len
< ETHER_MIN_LEN
||
649 bus_dmamap_load_mbuf(sc
->sc_bufs_dmat
, dmamap
, m0
,
650 admsw_mbuf_map_addr
, ds
, BUS_DMA_NOWAIT
) != 0) {
651 MGETHDR(m
, M_NOWAIT
, MT_DATA
);
653 device_printf(sc
->sc_dev
,
654 "unable to allocate Tx mbuf\n");
657 if (m0
->m_pkthdr
.len
> MHLEN
) {
658 if (!(MCLGET(m
, M_NOWAIT
))) {
659 device_printf(sc
->sc_dev
,
660 "unable to allocate Tx cluster\n");
665 m
->m_pkthdr
.csum_flags
= m0
->m_pkthdr
.csum_flags
;
666 m_copydata(m0
, 0, m0
->m_pkthdr
.len
, mtod(m
, void *));
667 m
->m_pkthdr
.len
= m
->m_len
= m0
->m_pkthdr
.len
;
668 if (m
->m_pkthdr
.len
< ETHER_MIN_LEN
) {
669 if (M_TRAILINGSPACE(m
) < ETHER_MIN_LEN
- m
->m_pkthdr
.len
)
670 panic("admsw_start: M_TRAILINGSPACE\n");
671 memset(mtod(m
, uint8_t *) + m
->m_pkthdr
.len
, 0,
672 ETHER_MIN_LEN
- ETHER_CRC_LEN
- m
->m_pkthdr
.len
);
673 m
->m_pkthdr
.len
= m
->m_len
= ETHER_MIN_LEN
;
675 error
= bus_dmamap_load_mbuf(sc
->sc_bufs_dmat
,
676 dmamap
, m
, admsw_mbuf_map_addr
, ds
, BUS_DMA_NOWAIT
);
678 device_printf(sc
->sc_dev
,
679 "unable to load Tx buffer, error = %d\n",
691 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
694 /* Sync the DMA map. */
695 bus_dmamap_sync(sc
->sc_bufs_dmat
, dmamap
, BUS_DMASYNC_PREWRITE
);
697 if (ds
->ds_nsegs
!= 1 && ds
->ds_nsegs
!= 2)
698 panic("admsw_start: nsegs == %d\n", ds
->ds_nsegs
);
699 desc
->data
= ds
->ds_addr
[0];
700 desc
->len
= len
= ds
->ds_len
[0];
701 if (ds
->ds_nsegs
> 1) {
702 len
+= ds
->ds_len
[1];
703 desc
->cntl
= ds
->ds_addr
[1] | ADM5120_DMA_BUF2ENABLE
;
706 desc
->status
= (len
<< ADM5120_DMA_LENSHIFT
) | (1 << vlan
);
707 eh
= mtod(m0
, struct ether_header
*);
708 if (ntohs(eh
->ether_type
) == ETHERTYPE_IP
&&
709 m0
->m_pkthdr
.csum_flags
& CSUM_IP
)
710 desc
->status
|= ADM5120_DMA_CSUM
;
711 if (nexttx
== ADMSW_NTXLDESC
- 1)
712 desc
->data
|= ADM5120_DMA_RINGEND
;
713 desc
->data
|= ADM5120_DMA_OWN
;
715 /* Sync the descriptor. */
716 ADMSW_CDTXLSYNC(sc
, nexttx
,
717 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
719 REG_WRITE(SEND_TRIG_REG
, 1);
720 /* printf("send slot %d\n",nexttx); */
723 * Store a pointer to the packet so we can free it later.
727 /* Advance the Tx pointer. */
729 sc
->sc_txnext
= ADMSW_NEXTTXL(nexttx
);
731 /* Pass the packet to any BPF listeners. */
734 /* Set a watchdog timer in case the chip flakes out. */
740 * admsw_watchdog: [ifnet interface function]
742 * Watchdog timer handler.
745 admsw_watchdog(void *arg
)
747 struct admsw_softc
*sc
= arg
;
751 callout_reset(&sc
->sc_watchdog
, hz
, admsw_watchdog
, sc
);
752 if (sc
->sc_timer
== 0 || --sc
->sc_timer
> 0)
755 /* Check if an interrupt was lost. */
756 if (sc
->sc_txfree
== ADMSW_NTXLDESC
) {
757 device_printf(sc
->sc_dev
, "watchdog false alarm\n");
760 if (sc
->sc_timer
!= 0)
761 device_printf(sc
->sc_dev
, "watchdog timer is %d!\n",
764 if (sc
->sc_txfree
== ADMSW_NTXLDESC
) {
765 device_printf(sc
->sc_dev
, "tx IRQ lost (queue empty)\n");
768 if (sc
->sc_timer
!= 0) {
769 device_printf(sc
->sc_dev
, "tx IRQ lost (timer recharged)\n");
773 device_printf(sc
->sc_dev
, "device timeout, txfree = %d\n",
775 for (vlan
= 0; vlan
< SW_DEVS
; vlan
++)
776 admsw_stop(sc
->sc_ifnet
[vlan
], 0);
779 ifp
= sc
->sc_ifnet
[0];
781 /* Try to get more packets going. */
786 * admsw_ioctl: [ifnet interface function]
788 * Handle control requests from the operator.
791 admsw_ioctl(struct ifnet
*ifp
, u_long cmd
, caddr_t data
)
793 struct admsw_softc
*sc
= ifp
->if_softc
;
803 while(port
< SW_DEVS
)
804 if(ifp
== sc
->sc_ifnet
[port
])
811 error
= ifmedia_ioctl(ifp
, (struct ifreq
*)data
,
812 &sc
->sc_ifmedia
[port
], cmd
);
817 ifd
= (struct ifdrv
*) data
;
818 if (ifd
->ifd_cmd
!= 0 || ifd
->ifd_len
!= sizeof(vlan_matrix
)) {
822 if (cmd
== SIOCGDRVSPEC
) {
823 error
= copyout(vlan_matrix
, ifd
->ifd_data
,
824 sizeof(vlan_matrix
));
826 error
= copyin(ifd
->ifd_data
, vlan_matrix
,
827 sizeof(vlan_matrix
));
828 admsw_setvlan(sc
, vlan_matrix
);
833 error
= ether_ioctl(ifp
, cmd
, data
);
834 if (error
== ENETRESET
) {
836 * Multicast list has changed; set the hardware filter
839 admsw_set_filter(sc
);
845 /* Try to get more packets going. */
856 * Interrupt service routine.
859 admsw_intr(void *arg
)
861 struct admsw_softc
*sc
= arg
;
864 pending
= REG_READ(ADMSW_INT_ST
);
865 REG_WRITE(ADMSW_INT_ST
, pending
);
868 return (FILTER_STRAY
);
870 if ((pending
& ADMSW_INTR_RHD
) != 0)
873 if ((pending
& ADMSW_INTR_RLD
) != 0)
876 if ((pending
& ADMSW_INTR_SHD
) != 0)
879 if ((pending
& ADMSW_INTR_SLD
) != 0)
882 return (FILTER_HANDLED
);
888 * Helper; handle transmit interrupts.
891 admsw_txintr(struct admsw_softc
*sc
, int prio
)
894 struct admsw_desc
*desc
;
895 struct admsw_descsoft
*ds
;
899 /* printf("txintr: txdirty: %d, txfree: %d\n",sc->sc_txdirty, sc->sc_txfree); */
900 for (i
= sc
->sc_txdirty
; sc
->sc_txfree
!= ADMSW_NTXLDESC
;
901 i
= ADMSW_NEXTTXL(i
)) {
903 ADMSW_CDTXLSYNC(sc
, i
,
904 BUS_DMASYNC_POSTREAD
|BUS_DMASYNC_POSTWRITE
);
906 desc
= &sc
->sc_txldescs
[i
];
907 ds
= &sc
->sc_txlsoft
[i
];
908 if (desc
->data
& ADM5120_DMA_OWN
) {
909 ADMSW_CDTXLSYNC(sc
, i
,
910 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
914 bus_dmamap_sync(sc
->sc_bufs_dmat
, ds
->ds_dmamap
,
915 BUS_DMASYNC_POSTWRITE
);
916 bus_dmamap_unload(sc
->sc_bufs_dmat
, ds
->ds_dmamap
);
917 m_freem(ds
->ds_mbuf
);
920 vlan
= ffs(desc
->status
& 0x3f) - 1;
921 if (vlan
< 0 || vlan
>= SW_DEVS
)
922 panic("admsw_txintr: bad vlan\n");
923 ifp
= sc
->sc_ifnet
[vlan
];
925 /* printf("clear tx slot %d\n",i); */
927 if_inc_counter(ifp
, IFCOUNTER_OPACKETS
, 1);
934 for (vlan
= 0; vlan
< SW_DEVS
; vlan
++)
935 sc
->sc_ifnet
[vlan
]->if_drv_flags
&= ~IFF_DRV_OACTIVE
;
937 ifp
= sc
->sc_ifnet
[0];
939 /* Try to queue more packets. */
943 * If there are no more pending transmissions,
944 * cancel the watchdog timer.
946 if (sc
->sc_txfree
== ADMSW_NTXLDESC
)
951 /* printf("txintr end: txdirty: %d, txfree: %d\n",sc->sc_txdirty, sc->sc_txfree); */
957 * Helper; handle receive interrupts.
960 admsw_rxintr(struct admsw_softc
*sc
, int high
)
963 struct admsw_descsoft
*ds
;
966 int i
, len
, port
, vlan
;
968 /* printf("rxintr\n"); */
971 panic("admsw_rxintr: high priority packet\n");
974 ADMSW_CDRXLSYNC(sc
, sc
->sc_rxptr
,
975 BUS_DMASYNC_POSTREAD
|BUS_DMASYNC_POSTWRITE
);
976 if ((sc
->sc_rxldescs
[sc
->sc_rxptr
].data
& ADM5120_DMA_OWN
) == 0)
977 ADMSW_CDRXLSYNC(sc
, sc
->sc_rxptr
,
978 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
982 ADMSW_CDRXLSYNC(sc
, i
,
983 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
984 i
= ADMSW_NEXTRXL(i
);
985 /* the ring is empty, just return. */
986 if (i
== sc
->sc_rxptr
)
988 ADMSW_CDRXLSYNC(sc
, i
,
989 BUS_DMASYNC_POSTREAD
|BUS_DMASYNC_POSTWRITE
);
990 } while (sc
->sc_rxldescs
[i
].data
& ADM5120_DMA_OWN
);
992 ADMSW_CDRXLSYNC(sc
, i
,
993 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
995 ADMSW_CDRXLSYNC(sc
, sc
->sc_rxptr
,
996 BUS_DMASYNC_POSTREAD
|BUS_DMASYNC_POSTWRITE
);
998 if ((sc
->sc_rxldescs
[sc
->sc_rxptr
].data
& ADM5120_DMA_OWN
) == 0)
999 ADMSW_CDRXLSYNC(sc
, sc
->sc_rxptr
,
1000 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
1002 ADMSW_CDRXLSYNC(sc
, sc
->sc_rxptr
,
1003 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
1004 /* We've fallen behind the chip: catch it. */
1006 device_printf(sc
->sc_dev
,
1007 "RX ring resync, base=%x, work=%x, %d -> %d\n",
1008 REG_READ(RECV_LBADDR_REG
),
1009 REG_READ(RECV_LWADDR_REG
), sc
->sc_rxptr
, i
);
1012 /* ADMSW_EVCNT_INCR(&sc->sc_ev_rxsync); */
1016 for (i
= sc
->sc_rxptr
;; i
= ADMSW_NEXTRXL(i
)) {
1017 ds
= &sc
->sc_rxlsoft
[i
];
1019 ADMSW_CDRXLSYNC(sc
, i
,
1020 BUS_DMASYNC_POSTREAD
|BUS_DMASYNC_POSTWRITE
);
1022 if (sc
->sc_rxldescs
[i
].data
& ADM5120_DMA_OWN
) {
1023 ADMSW_CDRXLSYNC(sc
, i
,
1024 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
1028 /* printf("process slot %d\n",i); */
1030 bus_dmamap_sync(sc
->sc_bufs_dmat
, ds
->ds_dmamap
,
1031 BUS_DMASYNC_POSTREAD
);
1033 stat
= sc
->sc_rxldescs
[i
].status
;
1034 len
= (stat
& ADM5120_DMA_LEN
) >> ADM5120_DMA_LENSHIFT
;
1035 len
-= ETHER_CRC_LEN
;
1036 port
= (stat
& ADM5120_DMA_PORTID
) >> ADM5120_DMA_PORTSHIFT
;
1038 for (vlan
= 0; vlan
< SW_DEVS
; vlan
++)
1039 if ((1 << port
) & vlan_matrix
[vlan
])
1042 if (vlan
== SW_DEVS
)
1045 ifp
= sc
->sc_ifnet
[vlan
];
1048 if (admsw_add_rxlbuf(sc
, i
) != 0) {
1049 if_inc_counter(ifp
, IFCOUNTER_IERRORS
, 1);
1050 ADMSW_INIT_RXLDESC(sc
, i
);
1051 bus_dmamap_sync(sc
->sc_bufs_dmat
, ds
->ds_dmamap
,
1052 BUS_DMASYNC_PREREAD
);
1056 m
->m_pkthdr
.rcvif
= ifp
;
1057 m
->m_pkthdr
.len
= m
->m_len
= len
;
1058 if ((stat
& ADM5120_DMA_TYPE
) == ADM5120_DMA_TYPE_IP
) {
1059 m
->m_pkthdr
.csum_flags
|= CSUM_IP_CHECKED
;
1060 if (!(stat
& ADM5120_DMA_CSUMFAIL
))
1061 m
->m_pkthdr
.csum_flags
|= CSUM_IP_VALID
;
1067 (*ifp
->if_input
)(ifp
, m
);
1068 if_inc_counter(ifp
, IFCOUNTER_IPACKETS
, 1);
1071 /* Update the receive pointer. */
1076 * admsw_init: [ifnet interface function]
1078 * Initialize the interface.
1081 admsw_init(void *xsc
)
1083 struct admsw_softc
*sc
= xsc
;
1087 for (i
= 0; i
< SW_DEVS
; i
++) {
1088 ifp
= sc
->sc_ifnet
[i
];
1089 if ((ifp
->if_drv_flags
& IFF_DRV_RUNNING
) == 0) {
1090 if (sc
->ndevs
== 0) {
1091 admsw_init_bufs(sc
);
1093 REG_WRITE(CPUP_CONF_REG
,
1094 CPUP_CONF_CRCP
| CPUP_CONF_DUNP_MASK
|
1095 CPUP_CONF_DMCP_MASK
);
1096 /* clear all pending interrupts */
1097 REG_WRITE(ADMSW_INT_ST
, INT_MASK
);
1099 /* enable needed interrupts */
1100 REG_WRITE(ADMSW_INT_MASK
,
1101 REG_READ(ADMSW_INT_MASK
) &
1102 ~(ADMSW_INTR_SHD
| ADMSW_INTR_SLD
|
1103 ADMSW_INTR_RHD
| ADMSW_INTR_RLD
|
1104 ADMSW_INTR_HDF
| ADMSW_INTR_LDF
));
1106 callout_reset(&sc
->sc_watchdog
, hz
,
1107 admsw_watchdog
, sc
);
1113 /* mark iface as running */
1114 ifp
->if_drv_flags
|= IFF_DRV_RUNNING
;
1115 ifp
->if_drv_flags
&= ~IFF_DRV_OACTIVE
;
1118 /* Set the receive filter. */
1119 admsw_set_filter(sc
);
1123 * admsw_stop: [ifnet interface function]
1125 * Stop transmission on the interface.
1128 admsw_stop(struct ifnet
*ifp
, int disable
)
1130 struct admsw_softc
*sc
= ifp
->if_softc
;
1132 if (!(ifp
->if_drv_flags
& IFF_DRV_RUNNING
))
1135 if (--sc
->ndevs
== 0) {
1136 /* printf("debug: de-initializing hardware\n"); */
1138 /* disable cpu port */
1139 REG_WRITE(CPUP_CONF_REG
,
1140 CPUP_CONF_DCPUP
| CPUP_CONF_CRCP
|
1141 CPUP_CONF_DUNP_MASK
| CPUP_CONF_DMCP_MASK
);
1143 /* XXX We should disable, then clear? --dyoung */
1144 /* clear all pending interrupts */
1145 REG_WRITE(ADMSW_INT_ST
, INT_MASK
);
1147 /* disable interrupts */
1148 REG_WRITE(ADMSW_INT_MASK
, INT_MASK
);
1150 /* Cancel the watchdog timer. */
1152 callout_stop(&sc
->sc_watchdog
);
1155 /* Mark the interface as down. */
1156 ifp
->if_drv_flags
&= ~(IFF_DRV_RUNNING
| IFF_DRV_OACTIVE
);
1164 * Set up the receive filter.
1167 admsw_set_filter(struct admsw_softc
*sc
)
1170 uint32_t allmc
, anymc
, conf
, promisc
;
1172 struct ifmultiaddr
*ifma
;
1174 /* Find which ports should be operated in promisc mode. */
1175 allmc
= anymc
= promisc
= 0;
1176 for (i
= 0; i
< SW_DEVS
; i
++) {
1177 ifp
= sc
->sc_ifnet
[i
];
1178 if (ifp
->if_flags
& IFF_PROMISC
)
1179 promisc
|= vlan_matrix
[i
];
1181 ifp
->if_flags
&= ~IFF_ALLMULTI
;
1183 if_maddr_rlock(ifp
);
1184 TAILQ_FOREACH(ifma
, &ifp
->if_multiaddrs
, ifma_link
)
1186 if (ifma
->ifma_addr
->sa_family
!= AF_LINK
)
1189 anymc
|= vlan_matrix
[i
];
1191 if_maddr_runlock(ifp
);
1194 conf
= REG_READ(CPUP_CONF_REG
);
1195 /* 1 Disable forwarding of unknown & multicast packets to
1197 * 2 Enable forwarding of unknown & multicast packets to
1198 * CPU on ports where IFF_PROMISC or IFF_ALLMULTI is set.
1200 conf
|= CPUP_CONF_DUNP_MASK
| CPUP_CONF_DMCP_MASK
;
1201 /* Enable forwarding of unknown packets to CPU on selected ports. */
1202 conf
^= ((promisc
<< CPUP_CONF_DUNP_SHIFT
) & CPUP_CONF_DUNP_MASK
);
1203 conf
^= ((allmc
<< CPUP_CONF_DMCP_SHIFT
) & CPUP_CONF_DMCP_MASK
);
1204 conf
^= ((anymc
<< CPUP_CONF_DMCP_SHIFT
) & CPUP_CONF_DMCP_MASK
);
1205 REG_WRITE(CPUP_CONF_REG
, conf
);
1211 * Add a receive buffer to the indicated descriptor.
1214 admsw_add_rxbuf(struct admsw_softc
*sc
, int idx
, int high
)
1216 struct admsw_descsoft
*ds
;
1221 ds
= &sc
->sc_rxhsoft
[idx
];
1223 ds
= &sc
->sc_rxlsoft
[idx
];
1225 MGETHDR(m
, M_NOWAIT
, MT_DATA
);
1229 if (!(MCLGET(m
, M_NOWAIT
))) {
1234 if (ds
->ds_mbuf
!= NULL
)
1235 bus_dmamap_unload(sc
->sc_bufs_dmat
, ds
->ds_dmamap
);
1239 error
= bus_dmamap_load(sc
->sc_bufs_dmat
, ds
->ds_dmamap
,
1240 m
->m_ext
.ext_buf
, m
->m_ext
.ext_size
, admsw_rxbuf_map_addr
,
1241 ds
, BUS_DMA_NOWAIT
);
1243 device_printf(sc
->sc_dev
,
1244 "can't load rx DMA map %d, error = %d\n", idx
, error
);
1245 panic("admsw_add_rxbuf"); /* XXX */
1248 bus_dmamap_sync(sc
->sc_bufs_dmat
, ds
->ds_dmamap
, BUS_DMASYNC_PREREAD
);
1251 ADMSW_INIT_RXHDESC(sc
, idx
);
1253 ADMSW_INIT_RXLDESC(sc
, idx
);
1259 admsw_mediachange(struct ifnet
*ifp
)
1261 struct admsw_softc
*sc
= ifp
->if_softc
;
1263 struct ifmedia
*ifm
;
1266 while(port
< SW_DEVS
) {
1267 if(ifp
== sc
->sc_ifnet
[port
])
1273 ifm
= &sc
->sc_ifmedia
[port
];
1275 if (IFM_TYPE(ifm
->ifm_media
) != IFM_ETHER
)
1278 if (IFM_SUBTYPE(ifm
->ifm_media
) == IFM_AUTO
) {
1279 val
= PHY_CNTL2_AUTONEG
|PHY_CNTL2_100M
|PHY_CNTL2_FDX
;
1280 } else if (IFM_SUBTYPE(ifm
->ifm_media
) == IFM_100_TX
) {
1281 if ((ifm
->ifm_media
& IFM_GMASK
) == IFM_FDX
)
1282 val
= PHY_CNTL2_100M
|PHY_CNTL2_FDX
;
1284 val
= PHY_CNTL2_100M
;
1285 } else if (IFM_SUBTYPE(ifm
->ifm_media
) == IFM_10_T
) {
1286 if ((ifm
->ifm_media
& IFM_GMASK
) == IFM_FDX
)
1287 val
= PHY_CNTL2_FDX
;
1293 old
= REG_READ(PHY_CNTL2_REG
);
1294 new = old
& ~((PHY_CNTL2_AUTONEG
|PHY_CNTL2_100M
|PHY_CNTL2_FDX
) << port
);
1295 new |= (val
<< port
);
1298 REG_WRITE(PHY_CNTL2_REG
, new);
1304 admsw_mediastatus(struct ifnet
*ifp
, struct ifmediareq
*ifmr
)
1306 struct admsw_softc
*sc
= ifp
->if_softc
;
1310 while(port
< SW_DEVS
) {
1311 if(ifp
== sc
->sc_ifnet
[port
])
1317 ifmr
->ifm_status
= IFM_AVALID
;
1318 ifmr
->ifm_active
= IFM_ETHER
;
1320 status
= REG_READ(PHY_ST_REG
) >> port
;
1322 if ((status
& PHY_ST_LINKUP
) == 0) {
1323 ifmr
->ifm_active
|= IFM_NONE
;
1327 ifmr
->ifm_status
|= IFM_ACTIVE
;
1328 ifmr
->ifm_active
|= (status
& PHY_ST_100M
) ? IFM_100_TX
: IFM_10_T
;
1329 if (status
& PHY_ST_FDX
)
1330 ifmr
->ifm_active
|= IFM_FDX
;
1333 static device_method_t admsw_methods
[] = {
1334 /* Device interface */
1335 DEVMETHOD(device_probe
, admsw_probe
),
1336 DEVMETHOD(device_attach
, admsw_attach
),
1337 DEVMETHOD(device_detach
, admsw_detach
),
1338 DEVMETHOD(device_shutdown
, admsw_shutdown
),
1343 static devclass_t admsw_devclass
;
1345 static driver_t admsw_driver
= {
1348 sizeof(struct admsw_softc
),
1351 DRIVER_MODULE(admsw
, obio
, admsw_driver
, admsw_devclass
, 0, 0);
1352 MODULE_DEPEND(admsw
, ether
, 1, 1, 1);