sys/mips/rt305x/uart_dev_rt305x.c

   1 /* $NetBSD: uart.c,v 1.2 2007/03/23 20:05:47 dogcow Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2010 Aleksandr Rybalko.
   5  * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
   6  * Copyright (c) 2007 Oleksandr Tymoshenko.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or
  10  * without modification, are permitted provided that the following
  11  * conditions are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above
  15  *    copyright notice, this list of conditions and the following
  16  *    disclaimer in the documentation and/or other materials provided
  17  *    with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
  20  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  21  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  22  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
  24  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  25  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  26  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  28  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  29  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  30  * OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include "opt_ddb.h"
  37
  38 #include <sys/param.h>
  39 #include <sys/systm.h>
  40 #include <sys/bus.h>
  41 #include <sys/conf.h>
  42 #include <sys/kdb.h>
  43 #include <sys/reboot.h>
  44 #include <sys/sysctl.h>
  45 #include <sys/kernel.h>
  46 #include <machine/bus.h>
  47
  48 #include <dev/uart/uart.h>
  49 #include <dev/uart/uart_cpu.h>
  50 #include <dev/uart/uart_bus.h>
  51
  52 #include <mips/rt305x/uart_dev_rt305x.h>
  53 #include <mips/rt305x/rt305xreg.h>
  54
  55 #include "uart_if.h"
  56 /*
  57  * Low-level UART interface.
  58  */
  59 static int rt305x_uart_probe(struct uart_bas *bas);
  60 static void rt305x_uart_init(struct uart_bas *bas, int, int, int, int);
  61 static void rt305x_uart_term(struct uart_bas *bas);
  62 static void rt305x_uart_putc(struct uart_bas *bas, int);
  63 static int rt305x_uart_rxready(struct uart_bas *bas);
  64 static int rt305x_uart_getc(struct uart_bas *bas, struct mtx *);
  65
  66 static struct uart_ops uart_rt305x_uart_ops = {
  67         .probe = rt305x_uart_probe,
  68         .init = rt305x_uart_init,
  69         .term = rt305x_uart_term,
  70         .putc = rt305x_uart_putc,
  71         .rxready = rt305x_uart_rxready,
  72         .getc = rt305x_uart_getc,
  73 };
  74
  75 static int      uart_output = 1;
  76 SYSCTL_INT(_kern, OID_AUTO, uart_output, CTLFLAG_RWTUN,
  77     &uart_output, 0, "UART output enabled.");
  78
  79 static int
  80 rt305x_uart_probe(struct uart_bas *bas)
  81 {
  82
  83         return (0);
  84 }
  85
  86 static void
  87 rt305x_uart_init(struct uart_bas *bas, int baudrate, int databits,
  88     int stopbits, int parity)
  89 {
  90 #ifdef notyet
  91         /* CLKDIV  = 384000000/ 3/ 16/ br */
  92         /* for 384MHz CLKDIV = 8000000 / baudrate; */
  93         switch (databits) {
  94         case 5:
  95                 databits = UART_LCR_5B;
  96                 break;
  97         case 6:
  98                 databits = UART_LCR_6B;
  99                 break;
 100         case 7:
 101                 databits = UART_LCR_7B;
 102                 break;
 103         case 8:
 104                 databits = UART_LCR_8B;
 105                 break;
 106         default:
 107                 /* Unsupported */
 108                 return;
 109         }
 110         switch (parity) {
 111         case UART_PARITY_EVEN:  parity = (UART_LCR_PEN|UART_LCR_EVEN); break;
 112         case UART_PARITY_NONE:  parity = (UART_LCR_PEN); break;
 113         case UART_PARITY_ODD:   parity = 0; break;
 114         /* Unsupported */
 115         default:                return;
 116         }
 117         uart_setreg(bas, UART_CDDL_REG, 8000000/baudrate);
 118         uart_barrier(bas);
 119         uart_setreg(bas, UART_LCR_REG, databits | (stopbits==1?0:4) | parity);
 120         uart_barrier(bas);
 121 #endif
 122 }
 123
 124 static void
 125 rt305x_uart_term(struct uart_bas *bas)
 126 {
 127         uart_setreg(bas, UART_MCR_REG, 0);
 128         uart_barrier(bas);
 129 }
 130
 131 static void
 132 rt305x_uart_putc(struct uart_bas *bas, int c)
 133 {
 134         char chr;
 135         if (!uart_output) return;
 136         chr = c;
 137         while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
 138         uart_setreg(bas, UART_TX_REG, c);
 139         uart_barrier(bas);
 140         while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
 141 }
 142
 143 static int
 144 rt305x_uart_rxready(struct uart_bas *bas)
 145 {
 146 #ifdef notyet
 147         if (uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)
 148                 return (1);
 149
 150         return (0);
 151 #else
 152         return (1);
 153 #endif
 154 }
 155
 156 static int
 157 rt305x_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
 158 {
 159         int c;
 160
 161         uart_lock(hwmtx);
 162
 163         while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)) {
 164                 uart_unlock(hwmtx);
 165                 DELAY(10);
 166                 uart_lock(hwmtx);
 167         }
 168
 169         c = uart_getreg(bas, UART_RX_REG);
 170
 171         uart_unlock(hwmtx);
 172
 173         return (c);
 174 }
 175
 176 /*
 177  * High-level UART interface.
 178  */
 179 struct rt305x_uart_softc {
 180         struct uart_softc base;
 181 };
 182
 183 static int rt305x_uart_bus_attach(struct uart_softc *);
 184 static int rt305x_uart_bus_detach(struct uart_softc *);
 185 static int rt305x_uart_bus_flush(struct uart_softc *, int);
 186 static int rt305x_uart_bus_getsig(struct uart_softc *);
 187 static int rt305x_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
 188 static int rt305x_uart_bus_ipend(struct uart_softc *);
 189 static int rt305x_uart_bus_param(struct uart_softc *, int, int, int, int);
 190 static int rt305x_uart_bus_probe(struct uart_softc *);
 191 static int rt305x_uart_bus_receive(struct uart_softc *);
 192 static int rt305x_uart_bus_setsig(struct uart_softc *, int);
 193 static int rt305x_uart_bus_transmit(struct uart_softc *);
 194 static void rt305x_uart_bus_grab(struct uart_softc *);
 195 static void rt305x_uart_bus_ungrab(struct uart_softc *);
 196
 197 static kobj_method_t rt305x_uart_methods[] = {
 198         KOBJMETHOD(uart_attach,         rt305x_uart_bus_attach),
 199         KOBJMETHOD(uart_detach,         rt305x_uart_bus_detach),
 200         KOBJMETHOD(uart_flush,          rt305x_uart_bus_flush),
 201         KOBJMETHOD(uart_getsig,         rt305x_uart_bus_getsig),
 202         KOBJMETHOD(uart_ioctl,          rt305x_uart_bus_ioctl),
 203         KOBJMETHOD(uart_ipend,          rt305x_uart_bus_ipend),
 204         KOBJMETHOD(uart_param,          rt305x_uart_bus_param),
 205         KOBJMETHOD(uart_probe,          rt305x_uart_bus_probe),
 206         KOBJMETHOD(uart_receive,        rt305x_uart_bus_receive),
 207         KOBJMETHOD(uart_setsig,         rt305x_uart_bus_setsig),
 208         KOBJMETHOD(uart_transmit,       rt305x_uart_bus_transmit),
 209         KOBJMETHOD(uart_grab,           rt305x_uart_bus_grab),
 210         KOBJMETHOD(uart_ungrab,         rt305x_uart_bus_ungrab),
 211         { 0, 0 }
 212 };
 213
 214 struct uart_class uart_rt305x_uart_class = {
 215         "rt305x",
 216         rt305x_uart_methods,
 217         sizeof(struct rt305x_uart_softc),
 218         .uc_ops = &uart_rt305x_uart_ops,
 219         .uc_range = 1, /* use hinted range */
 220         .uc_rclk = SYSTEM_CLOCK,
 221         .uc_rshift = 0
 222 };
 223
 224 #define SIGCHG(c, i, s, d)                              \
 225         if (c) {                                        \
 226                 i |= (i & s) ? s : s | d;               \
 227         } else {                                        \
 228                 i = (i & s) ? (i & ~s) | d : i;         \
 229         }
 230
 231 /*
 232  * Disable TX interrupt. uart should be locked
 233  */
 234 static __inline void
 235 rt305x_uart_disable_txintr(struct uart_softc *sc)
 236 {
 237         struct uart_bas *bas = &sc->sc_bas;
 238         uint8_t cr;
 239
 240         cr = uart_getreg(bas, UART_IER_REG);
 241         cr &= ~UART_IER_ETBEI;
 242         uart_setreg(bas, UART_IER_REG, cr);
 243         uart_barrier(bas);
 244 }
 245
 246 /*
 247  * Enable TX interrupt. uart should be locked
 248  */
 249 static __inline void
 250 rt305x_uart_enable_txintr(struct uart_softc *sc)
 251 {
 252         struct uart_bas *bas = &sc->sc_bas;
 253         uint8_t cr;
 254
 255         cr = uart_getreg(bas, UART_IER_REG);
 256         cr |= UART_IER_ETBEI;
 257         uart_setreg(bas, UART_IER_REG, cr);
 258         uart_barrier(bas);
 259 }
 260
 261 static int
 262 rt305x_uart_bus_attach(struct uart_softc *sc)
 263 {
 264         struct uart_bas *bas;
 265         struct uart_devinfo *di;
 266
 267         bas = &sc->sc_bas;
 268         if (sc->sc_sysdev != NULL) {
 269                 di = sc->sc_sysdev;
 270                 rt305x_uart_init(bas, di->baudrate, di->databits, di->stopbits,
 271                     di->parity);
 272         } else {
 273                 rt305x_uart_init(bas, 115200, 8, 1, 0);
 274         }
 275
 276         (void)rt305x_uart_bus_getsig(sc);
 277
 278         /* Enable FIFO */
 279         uart_setreg(bas, UART_FCR_REG,
 280             uart_getreg(bas, UART_FCR_REG) |
 281             UART_FCR_FIFOEN | UART_FCR_TXTGR_1 | UART_FCR_RXTGR_1);
 282         uart_barrier(bas);
 283         /* Enable interrupts */
 284         uart_setreg(bas, UART_IER_REG,
 285             UART_IER_EDSSI | UART_IER_ELSI | UART_IER_ERBFI);
 286         uart_barrier(bas);
 287
 288         return (0);
 289 }
 290
 291 static int
 292 rt305x_uart_bus_detach(struct uart_softc *sc)
 293 {
 294
 295         return (0);
 296 }
 297
 298 static int
 299 rt305x_uart_bus_flush(struct uart_softc *sc, int what)
 300 {
 301         struct uart_bas *bas = &sc->sc_bas;
 302         uint32_t fcr = uart_getreg(bas, UART_FCR_REG);
 303         if (what & UART_FLUSH_TRANSMITTER) {
 304                 uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_TXRST);
 305                 uart_barrier(bas);
 306         }
 307         if (what & UART_FLUSH_RECEIVER) {
 308                 uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_RXRST);
 309                 uart_barrier(bas);
 310         }
 311         uart_setreg(bas, UART_FCR_REG, fcr);
 312         uart_barrier(bas);
 313         return (0);
 314 }
 315
 316 static int
 317 rt305x_uart_bus_getsig(struct uart_softc *sc)
 318 {
 319         uint32_t new, old, sig;
 320         uint8_t bes;
 321
 322         do {
 323                 old = sc->sc_hwsig;
 324                 sig = old;
 325                 uart_lock(sc->sc_hwmtx);
 326                 bes = uart_getreg(&sc->sc_bas, UART_MSR_REG);
 327                 uart_unlock(sc->sc_hwmtx);
 328                 /* XXX: chip can show delta */
 329                 SIGCHG(bes & UART_MSR_CTS, sig, SER_CTS, SER_DCTS);
 330                 SIGCHG(bes & UART_MSR_DCD, sig, SER_DCD, SER_DDCD);
 331                 SIGCHG(bes & UART_MSR_DSR, sig, SER_DSR, SER_DDSR);
 332                 new = sig & ~SER_MASK_DELTA;
 333         } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
 334
 335         return (sig);
 336 }
 337
 338 static int
 339 rt305x_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
 340 {
 341         struct uart_bas *bas;
 342         int baudrate, divisor, error;
 343
 344         bas = &sc->sc_bas;
 345         error = 0;
 346         uart_lock(sc->sc_hwmtx);
 347         switch (request) {
 348         case UART_IOCTL_BREAK:
 349                 /* TODO: Send BREAK */
 350                 break;
 351         case UART_IOCTL_BAUD:
 352                 divisor = uart_getreg(bas, UART_CDDL_REG);
 353                 baudrate = bas->rclk / (divisor * 16);
 354                 *(int*)data = baudrate;
 355                 break;
 356         default:
 357                 error = EINVAL;
 358                 break;
 359         }
 360         uart_unlock(sc->sc_hwmtx);
 361         return (error);
 362 }
 363
 364 static int
 365 rt305x_uart_bus_ipend(struct uart_softc *sc)
 366 {
 367         struct uart_bas *bas;
 368         int ipend;
 369         uint8_t iir, lsr, msr;
 370
 371         bas = &sc->sc_bas;
 372         ipend = 0;
 373
 374         uart_lock(sc->sc_hwmtx);
 375         iir = uart_getreg(&sc->sc_bas, UART_IIR_REG);
 376         lsr = uart_getreg(&sc->sc_bas, UART_LSR_REG);
 377         uart_setreg(&sc->sc_bas, UART_LSR_REG, lsr);
 378         msr = uart_getreg(&sc->sc_bas, UART_MSR_REG);
 379         uart_setreg(&sc->sc_bas, UART_MSR_REG, msr);
 380         if (iir & UART_IIR_INTP) {
 381                 uart_unlock(sc->sc_hwmtx);
 382                 return (0);
 383         }
 384
 385
 386         switch ((iir >> 1) & 0x07) {
 387         case UART_IIR_ID_THRE:
 388                 ipend |= SER_INT_TXIDLE;
 389                 break;
 390         case UART_IIR_ID_DR2:
 391                 rt305x_uart_bus_flush(sc, UART_FLUSH_RECEIVER);
 392                 /* passthrough */
 393         case UART_IIR_ID_DR:
 394                 ipend |= SER_INT_RXREADY;
 395                 break;
 396         case UART_IIR_ID_MST:
 397         case UART_IIR_ID_LINESTATUS:
 398                 ipend |= SER_INT_SIGCHG;
 399                 if (lsr & UART_LSR_BI)
 400                 {
 401                         ipend |= SER_INT_BREAK;
 402 #ifdef KDB
 403                         breakpoint();
 404 #endif
 405                 }
 406                 if (lsr & UART_LSR_OE)
 407                         ipend |= SER_INT_OVERRUN;
 408                 break;
 409         default:
 410                 /* XXX: maybe return error here */
 411                 break;
 412         }
 413
 414         uart_unlock(sc->sc_hwmtx);
 415
 416         return (ipend);
 417 }
 418
 419 static int
 420 rt305x_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
 421     int stopbits, int parity)
 422 {
 423         uart_lock(sc->sc_hwmtx);
 424         rt305x_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
 425         uart_unlock(sc->sc_hwmtx);
 426         return (0);
 427 }
 428
 429 static int
 430 rt305x_uart_bus_probe(struct uart_softc *sc)
 431 {
 432         char buf[80];
 433         int error;
 434
 435         error = rt305x_uart_probe(&sc->sc_bas);
 436         if (error)
 437                 return (error);
 438
 439         sc->sc_rxfifosz = 16;
 440         sc->sc_txfifosz = 16;
 441
 442         snprintf(buf, sizeof(buf), "rt305x_uart");
 443         device_set_desc_copy(sc->sc_dev, buf);
 444
 445         return (0);
 446 }
 447
 448 static int
 449 rt305x_uart_bus_receive(struct uart_softc *sc)
 450 {
 451         struct uart_bas *bas;
 452         int xc;
 453         uint8_t lsr;
 454
 455         bas = &sc->sc_bas;
 456         uart_lock(sc->sc_hwmtx);
 457         lsr = uart_getreg(bas, UART_LSR_REG);
 458         while ((lsr & UART_LSR_DR)) {
 459                 if (uart_rx_full(sc)) {
 460                         sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
 461                         break;
 462                 }
 463                 xc = 0;
 464                 xc = uart_getreg(bas, UART_RX_REG);
 465                 if (lsr & UART_LSR_FE)
 466                         xc |= UART_STAT_FRAMERR;
 467                 if (lsr & UART_LSR_PE)
 468                         xc |= UART_STAT_PARERR;
 469                 if (lsr & UART_LSR_OE)
 470                         xc |= UART_STAT_OVERRUN;
 471                 uart_barrier(bas);
 472                 uart_rx_put(sc, xc);
 473                 lsr = uart_getreg(bas, UART_LSR_REG);
 474         }
 475
 476         uart_unlock(sc->sc_hwmtx);
 477         return (0);
 478 }
 479
 480 static int
 481 rt305x_uart_bus_setsig(struct uart_softc *sc, int sig)
 482 {
 483
 484         /* TODO: implement (?) */
 485         return (0);
 486 }
 487
 488 static int
 489 rt305x_uart_bus_transmit(struct uart_softc *sc)
 490 {
 491         struct uart_bas *bas = &sc->sc_bas;
 492         int i;
 493
 494         if (!uart_output) return (0);
 495
 496         bas = &sc->sc_bas;
 497         uart_lock(sc->sc_hwmtx);
 498         while ((uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE) == 0)
 499                 ;
 500         rt305x_uart_enable_txintr(sc);
 501         for (i = 0; i < sc->sc_txdatasz; i++) {
 502                 uart_setreg(bas, UART_TX_REG, sc->sc_txbuf[i]);
 503                 uart_barrier(bas);
 504         }
 505         sc->sc_txbusy = 1;
 506         uart_unlock(sc->sc_hwmtx);
 507         return (0);
 508 }
 509
 510 static void
 511 rt305x_uart_bus_grab(struct uart_softc *sc)
 512 {
 513         struct uart_bas *bas = &sc->sc_bas;
 514
 515         /* disable interrupts -- XXX not sure which one is RX, so kill them all */
 516         uart_lock(sc->sc_hwmtx);
 517         uart_setreg(bas, UART_IER_REG, 0);
 518         uart_barrier(bas);
 519         uart_unlock(sc->sc_hwmtx);
 520 }
 521
 522 static void
 523 rt305x_uart_bus_ungrab(struct uart_softc *sc)
 524 {
 525         struct uart_bas *bas = &sc->sc_bas;
 526
 527         /* Enable interrupts */
 528         uart_lock(sc->sc_hwmtx);
 529         uart_setreg(bas, UART_IER_REG,
 530             UART_IER_EDSSI | UART_IER_ELSI | UART_IER_ERBFI);
 531         uart_barrier(bas);
 532         uart_unlock(sc->sc_hwmtx);
 533 }