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31 .Nd measurement events for
42 CPUs contain PMCs conforming to version 2 of the
44 performance measurement architecture.
45 These CPUs may contain up to two classes of PMCs:
46 .Bl -tag -width "Li PMC_CLASS_IAP"
48 Fixed-function counters that count only one hardware event per counter.
50 Programmable counters that may be configured to count one of a defined
51 set of hardware events.
54 The number of PMCs available in each class and their widths need to be
55 determined at run time by calling
58 Intel Core2 PMCs are documented in
60 .%B "IA-32 Intel(R) Architecture Software Developer's Manual"
61 .%T "Volume 3: System Programming Guide"
62 .%N "Order Number 253669-027US"
64 .%Q "Intel Corporation"
66 .Ss CORE2 FIXED FUNCTION PMCS
67 These PMCs and their supported events are documented in
69 Not all CPUs in this family implement fixed-function counters.
70 .Ss CORE2 PROGRAMMABLE PMCS
71 The programmable PMCs support the following capabilities:
72 .Bl -column "PMC_CAP_INTERRUPT" "Support"
73 .It Em Capability Ta Em Support
74 .It PMC_CAP_CASCADE Ta \&No
75 .It PMC_CAP_EDGE Ta Yes
76 .It PMC_CAP_INTERRUPT Ta Yes
77 .It PMC_CAP_INVERT Ta Yes
78 .It PMC_CAP_READ Ta Yes
79 .It PMC_CAP_PRECISE Ta \&No
80 .It PMC_CAP_SYSTEM Ta Yes
81 .It PMC_CAP_TAGGING Ta \&No
82 .It PMC_CAP_THRESHOLD Ta Yes
83 .It PMC_CAP_USER Ta Yes
84 .It PMC_CAP_WRITE Ta Yes
87 Event specifiers for these PMCs support the following common
89 .Bl -tag -width indent
90 .It Li cmask= Ns Ar value
91 Configure the PMC to increment only if the number of configured
92 events measured in a cycle is greater than or equal to
95 Configure the PMC to count the number of de-asserted to asserted
96 transitions of the conditions expressed by the other qualifiers.
97 If specified, the counter will increment only once whenever a
98 condition becomes true, irrespective of the number of clocks during
99 which the condition remains true.
101 Invert the sense of comparison when the
103 qualifier is present, making the counter increment when the number of
104 events per cycle is less than the value specified by the
108 Configure the PMC to count events happening at processor privilege
111 Configure the PMC to count events occurring at privilege levels 1, 2
119 qualifiers are specified, the default is to enable both.
121 Events that require core-specificity to be specified use a
123 .Dq Li core= Ns Ar core ,
127 .Bl -tag -width indent
129 Measure event conditions on all cores.
131 Measure event conditions on this core.
137 Events that require an agent qualifier to be specified use an
139 .Dq Li agent= Ns agent ,
143 .Bl -tag -width indent
145 Measure events associated with this bus agent.
147 Measure events caused by any bus agent.
153 Events that require a hardware prefetch qualifier to be specified use an
155 .Dq Li prefetch= Ns Ar prefetch ,
159 .Bl -tag -width "exclude"
161 Include all prefetches.
163 Only count hardware prefetches.
165 Exclude hardware prefetches.
171 Events that require a cache coherence qualifier to be specified use an
173 .Dq Li cachestate= Ns Ar state ,
176 contains one or more of the following letters:
177 .Bl -tag -width indent
179 Count cache lines in the exclusive state.
181 Count cache lines in the invalid state.
183 Count cache lines in the modified state.
185 Count cache lines in the shared state.
191 Events that require a snoop response qualifier to be specified use an
193 .Dq Li snoopresponse= Ns Ar response ,
196 comprises of the following keywords separated by
199 .Bl -tag -width indent
201 Measure CLEAN responses.
203 Measure HIT responses.
205 Measure HITM responses.
208 The default is to measure all the above responses.
210 Events that require a snoop type qualifier use an additional qualifier
211 .Dq Li snooptype= Ns Ar type ,
214 comprises the one of the following keywords:
215 .Bl -tag -width indent
217 Measure CMP2I snoops.
219 Measure CMP2S snoops.
222 The default is to measure both snoops.
223 .Ss Event Specifiers (Programmable PMCs)
224 Core2 programmable PMCs support the following events:
225 .Bl -tag -width indent
227 .Pq Event E6H , Umask 00H
228 The number of times the front end is resteered.
230 .Pq Event E4H , Umask 00H
231 The number of byte sequences mistakenly detected as taken branch
233 .It Li BR_BAC_MISSP_EXEC
234 .Pq Event 8AH , Umask 00H
235 The number of branch instructions that were mispredicted when
237 .It Li BR_CALL_MISSP_EXEC
238 .Pq Event 93H , Umask 00H
239 The number of mispredicted
241 instructions that were executed.
243 .Pq Event 92H , Umask 00H
246 instructions executed.
248 .Pq Event 8BH , Umask 00H
249 The number of conditional branches executed, but not necessarily retired.
250 .It Li BR_CND_MISSP_EXEC
251 .Pq Event 8CH , Umask 00H
252 The number of mispredicted conditional branches executed.
253 .It Li BR_IND_CALL_EXEC
254 .Pq Event 94H , Umask 00H
255 The number of indirect
257 instructions executed.
259 .Pq Event 8DH , Umask 00H
260 The number of indirect branch instructions executed.
261 .It Li BR_IND_MISSP_EXEC
262 .Pq Event 8EH , Umask 00H
263 The number of mispredicted indirect branch instructions executed.
264 .It Li BR_INST_DECODED
265 .Pq Event E0H , Umask 00H
266 The number of branch instructions decoded.
268 .Pq Event 88H , Umask 00H
269 The number of branches executed, but not necessarily retired.
270 .It Li BR_INST_RETIRED.ANY
271 .Pq Event C4H , Umask 00H
272 .Pq Alias Qq "Branch Instruction Retired"
273 The number of branch instructions retired.
274 This is an architectural performance event.
275 .It Li BR_INST_RETIRED.MISPRED
276 .Pq Event C5H , Umask 00H
277 .Pq Alias Qq "Branch Misses Retired"
278 The number of mispredicted branch instructions retired.
279 This is an architectural performance event.
280 .It Li BR_INST_RETIRED.MISPRED_NOT_TAKEN
281 .Pq Event C4H , Umask 02H
282 The number of not taken branch instructions retired that were
284 .It Li BR_INST_RETIRED.MISPRED_TAKEN
285 .Pq Event C4H , Umask 08H
286 The number taken branch instructions retired that were mispredicted.
287 .It Li BR_INST_RETIRED.PRED_NOT_TAKEN
288 .Pq Event C4H , Umask 01H
289 The number of not taken branch instructions retired that were
291 .It Li BR_INST_RETIRED.PRED_TAKEN
292 .Pq Event C4H , Umask 04H
293 The number of taken branch instructions retired that were correctly
295 .It Li BR_INST_RETIRED.TAKEN
296 .Pq Event C4H , Umask 0CH
297 The number of taken branch instructions retired.
299 .Pq Event 89H , Umask 00H
300 The number of mispredicted branch instructions that were executed.
301 .It Li BR_RET_MISSP_EXEC
302 .Pq Event 90H , Umask 00H
303 The number of mispredicted
305 instructions executed.
306 .It Li BR_RET_BAC_MISSP_EXEC
307 .Pq Event 91H , Umask 00H
310 instructions executed that were mispredicted at decode time.
312 .Pq Event 8FH , Umask 00H
315 instructions executed.
316 .It Li BR_TKN_BUBBLE_1
317 .Pq Event 97H , Umask 00H
318 The number of branch predicted taken with bubble 1.
319 .It Li BR_TKN_BUBBLE_2
320 .Pq Event 98H , Umask 00H
321 The number of branch predicted taken with bubble 2.
322 .It Li BUSQ_EMPTY Op ,core= Ns Ar core
324 The number of cycles during which the core did not have any pending
325 transactions in the bus queue.
326 .It Li BUS_BNR_DRV Op ,agent= Ns Ar agent
328 The number of Bus Not Ready signals asserted on the bus.
329 .It Li BUS_DATA_RCV Op ,core= Ns Ar core
331 The number of bus cycles during which the processor is receiving data.
332 .It Li BUS_DRDY_CLOCKS Op ,agent= Ns Ar agent
334 The number of bus cycles during which the Data Ready signal is asserted
336 .It Li BUS_HIT_DRV Op ,agent= Ns Ar agent
338 The number of bus cycles during which the processor drives the
341 .It Li BUS_HITM_DRV Op ,agent= Ns Ar agent
343 The number of bus cycles during which the processor drives the
346 .It Li BUS_IO_WAIT Op ,core= Ns Ar core
348 The number of core cycles during which I/O requests wait in the bus
350 .It Li BUS_LOCK_CLOCKS Xo
351 .Op ,agent= Ns Ar agent
352 .Op ,core= Ns Ar core
355 The number of bus cycles during which the
357 signal was asserted on the bus.
358 .It Li BUS_REQUEST_OUTSTANDING Xo
359 .Op ,agent= Ns Ar agent
360 .Op ,core= Ns Ar core
363 The number of pending full cache line read transactions on the bus
364 occurring in each cycle.
365 .It Li BUS_TRANS_P Xo
366 .Op ,agent= Ns Ar agent
367 .Op ,core= Ns Ar core
370 The number of partial bus transactions.
371 .It Li BUS_TRANS_IFETCH Xo
372 .Op ,agent= Ns Ar agent
373 .Op ,core= Ns Ar core
376 The number of instruction fetch full cache line bus transactions.
377 .It Li BUS_TRANS_INVAL Xo
378 .Op ,agent= Ns Ar agent
379 .Op ,core= Ns Ar core
382 The number of invalidate bus transactions.
383 .It Li BUS_TRANS_PWR Xo
384 .Op ,agent= Ns Ar agent
385 .Op ,core= Ns Ar core
388 The number of partial write bus transactions.
389 .It Li BUS_TRANS_DEF Xo
390 .Op ,agent= Ns Ar agent
391 .Op ,core= Ns Ar core
394 The number of deferred bus transactions.
395 .It Li BUS_TRANS_BURST Xo
396 .Op ,agent= Ns Ar agent
397 .Op ,core= Ns Ar core
400 The number of burst transactions.
401 .It Li BUS_TRANS_MEM Xo
402 .Op ,agent= Ns Ar agent
403 .Op ,core= Ns Ar core
406 The number of memory bus transactions.
407 .It Li BUS_TRANS_ANY Xo
408 .Op ,agent= Ns Ar agent
409 .Op ,core= Ns Ar core
412 The number of bus transactions of any kind.
413 .It Li BUS_TRANS_BRD Xo
414 .Op ,agent= Ns Ar agent
415 .Op ,core= Ns Ar core
418 The number of burst read transactions.
419 .It Li BUS_TRANS_IO Xo
420 .Op ,agent= Ns Ar agent
421 .Op ,core= Ns Ar core
424 The number of completed I/O bus transactions due to
429 .It Li BUS_TRANS_RFO Xo
430 .Op ,agent= Ns Ar agent
431 .Op ,core= Ns Ar core
434 The number of Read For Ownership bus transactions.
435 .It Li BUS_TRANS_WB Xo
436 .Op ,agent= Ns Ar agent
437 .Op ,core= Ns Ar core
440 The number explicit write-back bus transactions due to dirty line
443 .Op ,core= Ns Ar core
444 .Op ,snooptype= Ns Ar snoop
447 The number of times the L1 data cache is snooped by the other core in
449 .It Li CPU_CLK_UNHALTED.BUS
450 .Pq Event 3CH , Umask 01H
451 .Pq Alias Qq "Unhalted Reference Cycles"
452 The number of bus cycles when the core is not in the halt state.
453 This is an architectural performance event.
454 .It Li CPU_CLK_UNHALTED.CORE_P
455 .Pq Event 3CH , Umask 00H
456 .Pq Alias Qq "Unhalted Core Cycles"
457 The number of core cycles while the core is not in a halt state.
458 This is an architectural performance event.
459 .It Li CPU_CLK_UNHALTED.NO_OTHER
460 .Pq Event 3CH , Umask 02H
461 The number of bus cycles during which the core remains unhalted and
462 the other core is halted.
463 .It Li CYCLES_DIV_BUSY
464 .Pq Event 14H , Umask 00H
465 The number of cycles the divider is busy.
466 This event is only available on PMC0.
467 .It Li CYCLES_INT_MASKED
468 .Pq Event C6H , Umask 01H
469 The number of cycles during which interrupts are disabled.
470 .It Li CYCLES_INT_PENDING_AND_MASKED
471 .Pq Event C6H , Umask 02H
472 The number of cycles during which there were pending interrupts while
473 interrupts were disabled.
474 .It Li CYCLES_L1I_MEM_STALLED
475 .Pq Event 86H , Umask 00H
476 The number of cycles for which an instruction fetch stalls.
477 .It Li DELAYED_BYPASS.FP
478 .Pq Event 19H , Umask 00H
479 The number of floating point operations that used data immediately
480 after the data was generated by a non floating point execution unit.
481 .It Li DELAYED_BYPASS.LOAD
482 .Pq Event 19H , Umask 01H
483 The number of delayed bypass penalty cycles that a load operation incurred.
484 .It Li DELAYED_BYPASS.SIMD
485 .Pq Event 19H , Umask 02H
486 The number of times SIMD operations use data immediately after data,
487 was generated by a non-SIMD execution unit.
489 .Pq Event 13H , Umask 00H
490 The number of divide operations executed.
491 This event is only available on PMC1.
492 .It Li DTLB_MISSES.ANY
493 .Pq Event 08H , Umask 01H
494 The number of Data TLB misses, including misses that result from
495 speculative accesses.
496 .It Li DTLB_MISSES.L0_MISS_LD
497 .Pq Event 08H , Umask 04H
498 The number of level 0 DTLB misses due to load operations.
499 .It Li DTLB_MISSES.MISS_LD
500 .Pq Event 08H , Umask 02H
501 The number of Data TLB misses due to load operations.
502 .It Li DTLB_MISSES.MISS_ST
503 .Pq Event 08H , Umask 08H
504 The number of Data TLB misses due to store operations.
506 .Pq Event 3AH , Umask 00H
507 The number of Enhanced Intel SpeedStep Technology transitions.
509 .Pq Event ABH , Umask 02H
510 The number of automatic additions to the
514 .Pq Event ABH , Umask 01H
515 The number of times the
517 register was explicitly used in an address expression after
518 it is implicitly used by a
524 .Op ,agent= Ns Ar agent
525 .Op ,snoopresponse= Ns Ar response
528 The number of snoop responses to bus transactions.
530 .Pq Event 11H , Umask 00H
531 The number of floating point operations executed that needed
533 .It Li FP_COMP_OPS_EXE
534 .Pq Event 10H , Umask 00H
535 The number of floating point computational micro-ops executed.
536 The event is available only on PMC0.
537 .It Li FP_MMX_TRANS_TO_FP
538 .Pq Event CCH , Umask 02H
539 The number of transitions from MMX instructions to floating point
541 .It Li FP_MMX_TRANS_TO_MMX
542 .Pq Event CCH , Umask 01H
543 The number of transitions from floating point instructions to MMX
546 .Pq Event C8H , Umask 00H
547 The number of hardware interrupts received.
548 .It Li IDLE_DURING_DIV
549 .Pq Event 18H , Umask 00H
550 The number of cycles the divider is busy and no other execution unit
551 or load operation was in progress.
552 This event is available only on PMC0.
554 .Pq Event 87H , Umask 00H
555 The number of cycles the instruction length decoder stalled due to a
556 length changing prefix.
557 .It Li INST_QUEUE.FULL
558 .Pq Event 83H , Umask 02H
559 The number of cycles during which the instruction queue is full.
560 .It Li INST_RETIRED.ANY_P
561 .Pq Event C0H , Umask 00H
562 .Pq Alias Qq "Instruction Retired"
563 The number of instructions retired.
564 This is an architectural performance event.
565 .It Li INST_RETIRED.LOADS
566 .Pq Event C0H , Umask 01H
567 The number of instructions retired that contained a load operation.
568 .It Li INST_RETIRED.OTHER
569 .Pq Event C0H , Umask 04H
570 The number of instructions retired that did not contain a load or a
572 .It Li INST_RETIRED.STORES
573 .Pq Event C0H , Umask 02H
574 The number of instructions retired that contained a store operation.
575 .It Li INST_RETIRED.VM_H
576 .Pq Event C0H , Umask 08H
578 The number of instructions retired while in VMX root operation.
580 .Pq Event 82H , Umask 40H
581 The number of ITLB flushes.
582 .It Li ITLB.LARGE_MISS
583 .Pq Event 82H , Umask 10H
584 The number of instruction fetches from large pages that miss the
587 .Pq Event 82H , Umask 12H
588 The number of instruction fetches from both large and small pages that
590 .It Li ITLB.SMALL_MISS
591 .Pq Event 82H , Umask 02H
592 The number of instruction fetches from small pages that miss the ITLB.
593 .It Li ITLB_MISS_RETIRED
594 .Pq Event C9H , Umask 00H
595 The number of retired instructions that missed the ITLB when they were
598 .Pq Event 43H , Umask 01H
599 The number of references to L1 data cache counting loads and stores of
601 .It Li L1D_ALL_CACHE_REF
602 .Pq Event 43H , Umask 02H
603 The number of data reads and writes to cacheable memory.
604 .It Li L1D_CACHE_LOCK Op ,cachestate= Ns Ar state
606 The number of locked reads from cacheable memory.
607 .It Li L1D_CACHE_LOCK_DURATION
608 .Pq Event 42H , Umask 10H
609 The number of cycles during which any cache line is locked by any
611 .It Li L1D_CACHE_LD Op ,cachestate= Ns Ar state
613 The number of data reads from cacheable memory excluding locked
615 .It Li L1D_CACHE_ST Op ,cachestate= Ns Ar state
617 The number of data writes to cacheable memory excluding locked
620 .Pq Event 47H , Umask 00H
621 The number of modified cache lines evicted from L1 data cache.
623 .Pq Event 46H , Umask 00H
624 The number of modified lines allocated in L1 data cache.
626 .Pq Event 48H , Umask 00H
627 The total number of outstanding L1 data cache misses at any clock.
628 .It Li L1D_PREFETCH.REQUESTS
629 .Pq Event 4EH , Umask 10H
630 The number of times L1 data cache requested to prefetch a data cache
633 .Pq Event 45H , Umask 0FH
634 The number of lines brought into L1 data cache.
635 .It Li L1D_SPLIT.LOADS
636 .Pq Event 49H , Umask 01H
637 The number of load operations that span two cache lines.
638 .It Li L1D_SPLIT.STORES
639 .Pq Event 49H , Umask 02H
640 The number of store operations that span two cache lines.
642 .Pq Event 81H , Umask 00H
643 The number of instruction fetch unit misses.
645 .Pq Event 80H , Umask 00H
646 The number of instruction fetches.
647 .It Li L2_ADS Op ,core= Ns core
649 The number of cycles that the L2 address bus is in use.
650 .It Li L2_DBUS_BUSY_RD Op ,core= Ns core
652 The number of cycles during which the L2 data bus is busy transferring
655 .Op ,cachestate= Ns Ar state
656 .Op ,core= Ns Ar core
659 The number of instruction cache line requests from the instruction
662 .Op ,cachestate= Ns Ar state
663 .Op ,core= Ns Ar core
664 .Op ,prefetch= Ns Ar prefetch
667 The number of L2 cache read requests from L1 cache and L2
669 .It Li L2_LINES_IN Xo
670 .Op ,core= Ns Ar core
671 .Op ,prefetch= Ns Ar prefetch
674 The number of cache lines allocated in L2 cache.
675 .It Li L2_LINES_OUT Xo
676 .Op ,core= Ns Ar core
677 .Op ,prefetch= Ns Ar prefetch
680 The number of L2 cache lines evicted.
682 .Op ,cachestate= Ns Ar state
683 .Op ,core= Ns Ar core
686 The number of locked accesses to cache lines that miss L1 data
688 .It Li L2_M_LINES_IN Op ,core= Ns Ar core
690 The number of L2 cache line modifications.
691 .It Li L2_M_LINES_OUT Xo
692 .Op ,core= Ns Ar core
693 .Op ,prefetch= Ns Ar prefetch
696 The number of modified lines evicted from L2 cache.
697 .It Li L2_NO_REQ Op ,core= Ns Ar core
699 The number of cycles during which no L2 cache requests were pending
701 .It Li L2_REJECT_BUSQ Xo
702 .Op ,cachestate= Ns Ar state
703 .Op ,core= Ns Ar core
704 .Op ,prefetch= Ns Ar prefetch
707 The number of L2 cache requests that were rejected.
709 .Op ,cachestate= Ns Ar state
710 .Op ,core= Ns Ar core
711 .Op ,prefetch= Ns Ar prefetch
714 The number of completed L2 cache requests.
715 .It Li L2_RQSTS.SELF.DEMAND.I_STATE
716 .Pq Event 2EH , Umask 41H
717 .Pq Alias Qq "LLC Misses"
718 The number of completed L2 cache demand requests from this core that
720 This is an architectural performance event.
721 .It Li L2_RQSTS.SELF.DEMAND.MESI
722 .Pq Event 2EH , Umask 4FH
723 .Pq Alias Qq "LLC References"
724 The number of completed L2 cache demand requests from this core.
725 This is an architectural performance event.
727 .Op ,cachestate= Ns Ar state
728 .Op ,core= Ns Ar core
731 The number of store operations that miss the L1 cache and request data
733 .It Li LOAD_BLOCK.L1D
734 .Pq Event 03H , Umask 20H
735 The number of loads blocked by the L1 data cache.
736 .It Li LOAD_BLOCK.OVERLAP_STORE
737 .Pq Event 03H , Umask 08H
738 The number of loads that partially overlap an earlier store or are
739 aliased with a previous store.
740 .It Li LOAD_BLOCK.STA
741 .Pq Event 03H , Umask 02H
742 The number of loads blocked by preceding stores whose address is yet
744 .It Li LOAD_BLOCK.STD
745 .Pq Event 03H , Umask 04H
746 The number of loads blocked by preceding stores to the same address
747 whose data value is not known.
748 .It Li LOAD_BLOCK.UNTIL_RETIRE
749 .Pq Event 03H , Umask 10H
750 The number of load operations that were blocked until retirement.
752 .Pq Event 4CH , Umask 00H
753 The number of load operations that conflicted with an prefetch to the
755 .It Li MACHINE_NUKES.SMC
756 .Pq Event C3H , Umask 01H
757 The number of times a program writes to a code section.
758 .It Li MACHINE_NUKES.MEM_ORDER
759 .Pq Event C3H , Umask 04H
760 The number of times the execution pipeline was restarted due to a
761 memory ordering conflict or memory disambiguation misprediction.
762 .It Li MACRO_INSTS.CISC_DECODED
763 .Pq Event AAH , Umask 08H
764 The number of complex instructions decoded.
765 .It Li MACRO_INSTS.DECODED
766 .Pq Event AAH , Umask 01H
767 The number of instructions decoded.
768 .It Li MEMORY_DISAMBIGUATION.RESET
769 .Pq Event 09H , Umask 01H
770 The number of cycles during which memory disambiguation misprediction
772 .It Li MEMORY_DISAMBIGUATION.SUCCESS
773 .Pq Event 09H , Umask 02H
774 The number of load operations that were successfully disambiguated.
775 .It Li MEM_LOAD_RETIRED.DTLB_MISS
776 .Pq Event CBH , Umask 10H
777 The number of retired loads that missed the DTLB.
778 .It Li MEM_LOAD_RETIRED.L1D_LINE_MISS
779 .Pq Event CBH , Umask 02H
780 The number of retired load operations that missed L1 data cache and
781 that sent a request to L2 cache.
782 This event is only available on PMC0.
783 .It Li MEM_LOAD_RETIRED.L1D_MISS
784 .Pq Event CBH , Umask 01H
785 The number of retired load operations that missed L1 data cache.
786 This event is only available on PMC0.
787 .It Li MEM_LOAD_RETIRED.L2_LINE_MISS
788 .Pq Event CBH , Umask 08H
789 The number of load operations that missed L2 cache and that caused a
791 .It Li MEM_LOAD_RETIRED.L2_MISS
792 .Pq Event CBH , Umask 04H
793 The number of load operations that missed L2 cache.
795 .Pq Event 12H , Umask 00H
796 The number of multiply operations executed.
797 This event is only available on PMC1.
798 .It Li PAGE_WALKS.COUNT
799 .Pq Event 0CH , Umask 01H
800 The number of page walks executed due to an ITLB or DTLB miss.
801 .It Li PAGE_WALKS.CYCLES
802 .Pq Event 0CH , Umask 02H
803 The number of cycles spent in a page walk caused by an ITLB or DTLB
806 .Pq Event F8H , Umask 00H
807 The number of downward prefetches issued from the Data Prefetch Logic
810 .Pq Event F0H , Umask 00H
811 The number of upward prefetches issued from the Data Prefetch Logic
813 .It Li RAT_STALLS.ANY
814 .Pq Event D2H , Umask 0FH
815 The number of stall cycles due to any of
817 .Li RAT_STALLS.FPSW ,
818 .Li RAT_STALLS.PARTIAL
820 .Li RAT_STALLS.ROB_READ_PORT .
821 .It Li RAT_STALLS.FLAGS
822 .Pq Event D2H , Umask 04H
823 The number of cycles execution stalled due to a flag register induced
825 .It Li RAT_STALLS.FPSW
826 .Pq Event D2H , Umask 08H
827 The number of times the floating point status word was written.
828 .It Li RAT_STALLS.OTHER_SERIALIZATION_STALLS
829 .Pq Event D2H , Umask 10H , Tn Core2Extreme
830 The number of stalls due to other RAT resource serialization not
831 counted by umask 0FH.
832 .It Li RAT_STALLS.PARTIAL_CYCLES
833 .Pq Event D2H , Umask 02H
834 The number of cycles of added instruction execution latency due to the
835 use of a register that was partially written by previous instructions.
836 .It Li RAT_STALLS.ROB_READ_PORT
837 .Pq Event D2H , Umask 01H
838 The number of cycles when ROB read port stalls occurred.
839 .It Li RESOURCE_STALLS.ANY
840 .Pq Event DCH , Umask 1FH
841 The number of cycles during which any resource related stall
843 .It Li RESOURCE_STALLS.BR_MISS_CLEAR
844 .Pq Event DCH , Umask 10H
845 The number of cycles stalled due to branch misprediction.
846 .It Li RESOURCE_STALLS.FPCW
847 .Pq Event DCH , Umask 08H
848 The number of cycles stalled due to writing the floating point control
850 .It Li RESOURCE_STALLS.LD_ST
851 .Pq Event DCH , Umask 04H
852 The number of cycles during which the number of loads and stores in
853 the pipeline exceeded their limits.
854 .It Li RESOURCE_STALLS.ROB_FULL
855 .Pq Event DCH , Umask 01H
856 The number of cycles when the reorder buffer was full.
857 .It Li RESOURCE_STALLS.RS_FULL
858 .Pq Event DCH , Umask 02H
859 The number of cycles during which the RS was full.
860 .It Li RS_UOPS_DISPATCHED
861 .Pq Event A0H , Umask 00H
862 The number of micro-ops dispatched for execution.
863 .It Li RS_UOPS_DISPATCHED.PORT0
864 .Pq Event A1H , Umask 01H
865 The number of cycles micro-ops were dispatched for execution on port
867 .It Li RS_UOPS_DISPATCHED.PORT1
868 .Pq Event A1H , Umask 02H
869 The number of cycles micro-ops were dispatched for execution on port
871 .It Li RS_UOPS_DISPATCHED.PORT2
872 .Pq Event A1H , Umask 04H
873 The number of cycles micro-ops were dispatched for execution on port
875 .It Li RS_UOPS_DISPATCHED.PORT3
876 .Pq Event A1H , Umask 08H
877 The number of cycles micro-ops were dispatched for execution on port
879 .It Li RS_UOPS_DISPATCHED.PORT4
880 .Pq Event A1H , Umask 10H
881 The number of cycles micro-ops were dispatched for execution on port
883 .It Li RS_UOPS_DISPATCHED.PORT5
884 .Pq Event A1H , Umask 20H
885 The number of cycles micro-ops were dispatched for execution on port
887 .It Li SB_DRAIN_CYCLES
888 .Pq Event 04H , Umask 01H
889 The number of cycles while the store buffer is draining.
890 .It Li SEGMENT_REG_LOADS
891 .Pq Event 06H , Umask 00H
892 The number of segment register loads.
893 .It Li SEG_REG_RENAMES.ANY
894 .Pq Event D5H , Umask 0FH
895 The number of times the any segment register was renamed.
896 .It Li SEG_REG_RENAMES.DS
897 .Pq Event D5H , Umask 02H
898 The number of times the
901 .It Li SEG_REG_RENAMES.ES
902 .Pq Event D5H , Umask 01H
903 The number of times the
906 .It Li SEG_REG_RENAMES.FS
907 .Pq Event D5H , Umask 04H
908 The number of times the
911 .It Li SEG_REG_RENAMES.GS
912 .Pq Event D5H , Umask 08H
913 The number of times the
916 .It Li SEG_RENAME_STALLS.ANY
917 .Pq Event D4H , Umask 0FH
918 The number of stalls due to lack of resource to rename any segment
920 .It Li SEG_RENAME_STALLS.DS
921 .Pq Event D4H , Umask 02H
922 The number of stalls due to lack of renaming resources for the
925 .It Li SEG_RENAME_STALLS.ES
926 .Pq Event D4H , Umask 01H
927 The number of stalls due to lack of renaming resources for the
930 .It Li SEG_RENAME_STALLS.FS
931 .Pq Event D4H , Umask 04H
932 The number of stalls due to lack of renaming resources for the
935 .It Li SEG_RENAME_STALLS.GS
936 .Pq Event D4H , Umask 08H
937 The number of stalls due to lack of renaming resources for the
941 .Pq Event CDH , Umask 00H
942 The number SIMD assists invoked.
943 .It Li SIMD_COMP_INST_RETIRED.PACKED_DOUBLE
944 .Pq Event CAH , Umask 04H
945 Then number of computational SSE2 packed double precision instructions
947 .It Li SIMD_COMP_INST_RETIRED.PACKED_SINGLE
948 .Pq Event CAH , Umask 01H
949 Then number of computational SSE2 packed single precision instructions
951 .It Li SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE
952 .Pq Event CAH , Umask 08H
953 Then number of computational SSE2 scalar double precision instructions
955 .It Li SIMD_COMP_INST_RETIRED.SCALAR_SINGLE
956 .Pq Event CAH , Umask 02H
957 Then number of computational SSE2 scalar single precision instructions
959 .It Li SIMD_INSTR_RETIRED
960 .Pq Event CEH , Umask 00H
961 The number of retired SIMD instructions that use MMX registers.
962 .It Li SIMD_INST_RETIRED.ANY
963 .Pq Event C7H , Umask 1FH
964 The number of streaming SIMD instructions retired.
965 .It Li SIMD_INST_RETIRED.PACKED_DOUBLE
966 .Pq Event C7H , Umask 04H
967 The number of SSE2 packed double precision instructions retired.
968 .It Li SIMD_INST_RETIRED.PACKED_SINGLE
969 .Pq Event C7H , Umask 01H
970 The number of SSE packed single precision instructions retired.
971 .It Li SIMD_INST_RETIRED.SCALAR_DOUBLE
972 .Pq Event C7H , Umask 08H
973 The number of SSE2 scalar double precision instructions retired.
974 .It Li SIMD_INST_RETIRED.SCALAR_SINGLE
975 .Pq Event C7H , Umask 02H
976 The number of SSE scalar single precision instructions retired.
977 .It Li SIMD_INST_RETIRED.VECTOR
978 .Pq Event C7H , Umask 10H
979 The number of SSE2 vector instructions retired.
980 .It Li SIMD_SAT_INSTR_RETIRED
981 .Pq Event CFH , Umask 00H
982 The number of saturated arithmetic SIMD instructions retired.
983 .It Li SIMD_SAT_UOP_EXEC
984 .Pq Event B1H , Umask 00H
985 The number of SIMD saturated arithmetic micro-ops executed.
986 .It Li SIMD_UOPS_EXEC
987 .Pq Event B0H , Umask 00H
988 The number of SIMD micro-ops executed.
989 .It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC
990 .Pq Event B3H , Umask 20H
991 The number of SIMD packed arithmetic micro-ops executed.
992 .It Li SIMD_UOP_TYPE_EXEC.LOGICAL
993 .Pq Event B3H , Umask 10H
994 The number of SIMD packed logical micro-ops executed.
995 .It Li SIMD_UOP_TYPE_EXEC.MUL
996 .Pq Event B3H , Umask 01H
997 The number of SIMD packed multiply micro-ops executed.
998 .It Li SIMD_UOP_TYPE_EXEC.PACK
999 .Pq Event B3H , Umask 04H
1000 The number of SIMD pack micro-ops executed.
1001 .It Li SIMD_UOP_TYPE_EXEC.SHIFT
1002 .Pq Event B3H , Umask 02H
1003 The number of SIMD packed shift micro-ops executed.
1004 .It Li SIMD_UOP_TYPE_EXEC.UNPACK
1005 .Pq Event B3H , Umask 08H
1006 The number of SIMD unpack micro-ops executed.
1007 .It Li SNOOP_STALL_DRV Xo
1008 .Op ,agent= Ns Ar agent
1009 .Op ,core= Ns Ar core
1012 The number of times the bus stalled for snoops.
1013 .It Li SSE_PRE_EXEC.L1
1014 .Pq Event 07H , Umask 01H
1017 instructions executed.
1018 .It Li SSE_PRE_EXEC.L2
1019 .Pq Event 07H , Umask 02H
1022 instructions executed.
1023 .It Li SSE_PRE_EXEC.NTA
1024 .Pq Event 07H , Umask 00H
1027 instructions executed.
1028 .It Li SSE_PRE_EXEC.STORES
1029 .Pq Event 07H , Umask 03H
1030 The number of times SSE non-temporal store instructions were executed.
1031 .It Li SSE_PRE_MISS.L1
1032 .Pq Event 4BH , Umask 01H
1033 The number of times the
1035 instruction executed and missed all cache levels.
1036 .It Li SSE_PRE_MISS.L2
1037 .Pq Event 4BH , Umask 02H
1038 The number of times the
1040 instruction executed and missed all cache levels.
1041 .It Li SSE_PRE_MISS.NTA
1042 .Pq Event 4BH , Umask 00H
1043 The number of times the
1045 instruction executed and missed all cache levels.
1046 .It Li STORE_BLOCK.ORDER
1047 .Pq Event 04H , Umask 02H
1048 The number of cycles while a store was waiting for another store to be
1050 .It Li STORE_BLOCK.SNOOP
1051 .Pq Event 04H , Umask 08H
1052 The number of cycles while a store was blocked due to a conflict with
1053 an internal or external snoop.
1055 .Pq Event 3BH , Umask C0H
1056 The number of thermal trips.
1057 .It Li UOPS_RETIRED.LD_IND_BR
1058 .Pq Event C2H , Umask 01H
1059 The number of micro-ops retired that fused a load with another
1061 .It Li UOPS_RETIRED.STD_STA
1062 .Pq Event C2H , Umask 02H
1063 The number of store address calculations that fused into one micro-op.
1064 .It Li UOPS_RETIRED.MACRO_FUSION
1065 .Pq Event C2H , Umask 04H
1066 The number of times retired instruction pairs were fused into one
1068 .It Li UOPS_RETIRED.FUSED
1069 .Pq Event C2H , Umask 07H
1070 The number of fused micro-ops retired.
1071 .It Li UOPS_RETIRED.NON_FUSED
1072 .Pq Event C2H , Umask 8H
1073 The number of non-fused micro-ops retired.
1074 .It Li UOPS_RETIRED.ANY
1075 .Pq Event C2H , Umask 0FH
1076 The number of micro-ops retired.
1077 .It Li X87_OPS_RETIRED.ANY
1078 .Pq Event C1H , Umask FEH
1079 The number of floating point computational instructions retired.
1080 .It Li X87_OPS_RETIRED.FXCH
1081 .Pq Event C1H , Umask 01H
1084 instructions retired.
1086 .Ss Event Name Aliases
1087 The following table shows the mapping between the PMC-independent
1088 aliases supported by
1090 and the underlying hardware events used.
1091 .Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class"
1092 .It Em Alias Ta Em Event Ta Em PMC Class
1093 .It Li branches Ta Li BR_INST_RETIRED.ANY Ta Li PMC_CLASS_IAP
1094 .It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP
1095 .It Li ic-misses Ta Li L1I_MISSES Ta Li PMC_CLASS_IAP
1096 .It Li instructions Ta Li INST_RETIRED.ANY_P Ta Li PMC_CLASS_IAF
1097 .It Li interrupts Ta Li HW_INT_RCV Ta Li PMC_CLASS_IAP
1098 .It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF
1118 library first appeared in
1123 library was written by
1124 .An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .