rtl/filter.v

   1 module filter(input clock,
   2               input in,
   3               output reg out,  // out a filtered version of in
   4               output reg strobe); // true for one cycle synchronous with a change
   5
   6    parameter freq = 25_000_000; // 25MHz
   7    parameter limit =    50_000; // 50kHz
   8    parameter dur = freq / limit;
   9
  10    parameter N = 14; // INV: 2**N > dur;
  11
  12    reg [N:0] countdown;
  13
  14    // Filter out any meta stability
  15    reg       in_, in__;
  16
  17    always @(posedge clock) begin
  18       strobe <= 0;
  19       in_ <= in;
  20       in__ <= in_;
  21       if (in__ == out)
  22         countdown <= dur - 1;
  23         // Note, we depend on countdown[N] being reset here.
  24       else if (~countdown[N])
  25         countdown <= countdown - 1;
  26       else begin
  27          out <= ~out;
  28          strobe <= 1;
  29       end
  30    end
  31 endmodule