rtl/Icarus/icarus_toplevel.v

   1 `timescale 1ns/10ps
   2
   3 module icarus_toplevel();
   4    reg         clk25MHz = 1;
   5
   6    wire [22:0] fse_a;        // Mainboard common bus address
   7    wire [31:0] fse_d;        // Mainboard common bus data
   8    wire        flash_cs_n;   // Flash ROM CS#
   9    wire        enet_aen;     // Ethernet Access Enable
  10    wire        sram_cs_n;    // SRAM CS#
  11    wire [3:0]  sram_be_n;    // SRAM byte enables
  12    wire        sram_oe_n;    // SRAM OE#
  13    wire        sram_we_n;    // SRAM WE#
  14
  15    always #5 clk25MHz <= ~clk25MHz;
  16
  17    idt71v416s10 u35(fse_d[15: 0], fse_a[19:2], sram_we_n, sram_oe_n, sram_cs_n,
  18                     sram_be_n[0], sram_be_n[1]); // Yep, strange order...
  19    idt71v416s10 u36(fse_d[31:16], fse_a[19:2], sram_we_n, sram_oe_n, sram_cs_n,
  20                     sram_be_n[2], sram_be_n[3]);
  21
  22    system tommix_system_inst
  23                 ( .clk25MHz(clk25MHz)
  24           ,.reset(0)
  25           ,.fse_a(fse_a)            // Mainboard common bus address
  26           ,.fse_d(fse_d)            // Mainboard common bus data
  27           ,.flash_cs_n(flash_cs_n)  // Flash ROM CS#
  28           ,.enet_aen(enet_aen)      // Ethernet Access Enable
  29           ,.sram_cs_n(sram_cs_n)    // SRAM CS#
  30           ,.sram_be_n(sram_be_n)    // SRAM byte enables
  31           ,.sram_oe_n(sram_oe_n)    // SRAM OE#
  32           ,.sram_we_n(sram_we_n)    // SRAM WE#
  33           );
  34
  35
  36
  37    reg [31:0]  i, v;
  38    reg [31:0]  preload[0:262143];
  39    initial begin
  40       $readmemh("initialsram.data", preload);
  41       for (i = 0; i <= 262143; i = i + 1) begin
  42          v = preload[i];
  43          u36.mem2[i] = v[31:24];
  44          u36.mem1[i] = v[23:16];
  45          u35.mem2[i] = v[15: 8];
  46          u35.mem1[i] = v[ 7: 0];
  47       end
  48    end
  49 endmodule // main