initial
[fpgammix.git] / rtl / rs232.v
blob1f378d4e91a755a6b6b512581d08ee0fde0e84ba
1 `timescale 1ns/10ps
2 module rs232(input wire clk,
3 input wire rst,
5 // Master connections
6 input wire `REQ rs232_req,
7 output wire `RES rs232_res,
9 input wire rs232in_attention,
10 input wire [7:0] rs232in_data,
12 input wire rs232out_busy,
13 output wire rs232out_w,
14 output wire [7:0] rs232out_d);
16 parameter debug = 1;
18 reg [31:0] tsc = 0; // A free running counter....
19 reg [ 7:0] rs232in_cnt = 0;
21 wire [31:0] addr = rs232_req`A;
22 reg [31:0] rd_data = 0;
23 assign rs232_res`RD = rd_data;
24 assign rs232_res`HOLD = 0;
26 always @(posedge clk)
27 if (rst) begin
28 rd_data <= 0;
29 tsc <= 0;
30 rs232in_cnt <= 0;
31 end else begin
32 rd_data <= 0;
33 tsc <= tsc + 1;
34 if (rs232in_attention)
35 rs232in_cnt <= rs232in_cnt + 1'h1;
37 if (rs232_req`R)
38 case (addr[3:2])
39 0: rd_data <= {31'h0,rs232out_busy};// 0
40 1: rd_data <= {24'h0,rs232in_data}; // 4
41 2: rd_data <= {24'h0,rs232in_cnt}; // 8
42 3: rd_data <= tsc; // 12
43 endcase
44 end
46 // wire rs232en = (peri_ctrl_req`A & 'hFFF0) == 'h0000;
47 assign rs232out_d = rs232_req`WD;
48 assign rs232out_w = rs232_req`W & addr[3:0] == 0;
51 always @*
52 if (debug)
53 $display("%5d RS232: rs232out_w %d rs232out_busy %d (addr %x)", $time,
54 rs232out_w, rs232out_busy,
55 addr);
57 endmodule