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[fpgammix.git] / rtl / NiosDevKit-EP1C20 / mega / regfile.v
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1 // megafunction wizard: %ALTSYNCRAM%
2 // GENERATION: STANDARD
3 // VERSION: WM1.0
4 // MODULE: altsyncram
6 // ============================================================
7 // File Name: regfile.v
8 // Megafunction Name(s):
9 // altsyncram
10 // ============================================================
11 // ************************************************************
12 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
13 //
14 // 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition
15 // ************************************************************
18 //Copyright (C) 1991-2006 Altera Corporation
19 //Your use of Altera Corporation's design tools, logic functions
20 //and other software and tools, and its AMPP partner logic
21 //functions, and any output files any of the foregoing
22 //(including device programming or simulation files), and any
23 //associated documentation or information are expressly subject
24 //to the terms and conditions of the Altera Program License
25 //Subscription Agreement, Altera MegaCore Function License
26 //Agreement, or other applicable license agreement, including,
27 //without limitation, that your use is for the sole purpose of
28 //programming logic devices manufactured by Altera and sold by
29 //Altera or its authorized distributors. Please refer to the
30 //applicable agreement for further details.
33 // synopsys translate_off
34 `timescale 1 ps / 1 ps
35 // synopsys translate_on
36 module regfile (
37 clock,
38 data,
39 rdaddress,
40 rden,
41 wraddress,
42 wren,
43 q);
45 input clock;
46 input [63:0] data;
47 input [8:0] rdaddress;
48 input rden;
49 input [8:0] wraddress;
50 input wren;
51 output [63:0] q;
53 wire [63:0] sub_wire0;
54 wire [63:0] q = sub_wire0[63:0];
56 altsyncram altsyncram_component (
57 .wren_a (wren),
58 .clock0 (clock),
59 .address_a (wraddress),
60 .address_b (rdaddress),
61 .rden_b (rden),
62 .data_a (data),
63 .q_b (sub_wire0),
64 .aclr0 (1'b0),
65 .aclr1 (1'b0),
66 .addressstall_a (1'b0),
67 .addressstall_b (1'b0),
68 .byteena_a (1'b1),
69 .byteena_b (1'b1),
70 .clock1 (1'b1),
71 .clocken0 (1'b1),
72 .clocken1 (1'b1),
73 .data_b ({64{1'b1}}),
74 .q_a (),
75 .wren_b (1'b0));
76 defparam
77 altsyncram_component.address_aclr_a = "NONE",
78 altsyncram_component.address_aclr_b = "NONE",
79 altsyncram_component.address_reg_b = "CLOCK0",
80 altsyncram_component.indata_aclr_a = "NONE",
81 altsyncram_component.intended_device_family = "Cyclone",
82 altsyncram_component.lpm_type = "altsyncram",
83 altsyncram_component.numwords_a = 512,
84 altsyncram_component.numwords_b = 512,
85 altsyncram_component.operation_mode = "DUAL_PORT",
86 altsyncram_component.outdata_aclr_b = "NONE",
87 altsyncram_component.outdata_reg_b = "UNREGISTERED",
88 altsyncram_component.power_up_uninitialized = "FALSE",
89 altsyncram_component.rdcontrol_aclr_b = "NONE",
90 altsyncram_component.rdcontrol_reg_b = "CLOCK0",
91 altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
92 altsyncram_component.widthad_a = 9,
93 altsyncram_component.widthad_b = 9,
94 altsyncram_component.width_a = 64,
95 altsyncram_component.width_b = 64,
96 altsyncram_component.width_byteena_a = 1,
97 altsyncram_component.wrcontrol_aclr_a = "NONE";
100 endmodule
102 // ============================================================
103 // CNX file retrieval info
104 // ============================================================
105 // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
106 // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
107 // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
108 // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
109 // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
110 // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
111 // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
112 // Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
113 // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
114 // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
115 // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
116 // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
117 // Retrieval info: PRIVATE: CLRdata NUMERIC "0"
118 // Retrieval info: PRIVATE: CLRq NUMERIC "0"
119 // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
120 // Retrieval info: PRIVATE: CLRrren NUMERIC "0"
121 // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
122 // Retrieval info: PRIVATE: CLRwren NUMERIC "0"
123 // Retrieval info: PRIVATE: Clock NUMERIC "0"
124 // Retrieval info: PRIVATE: Clock_A NUMERIC "0"
125 // Retrieval info: PRIVATE: Clock_B NUMERIC "0"
126 // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
127 // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
128 // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
129 // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
130 // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
131 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
132 // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
133 // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
134 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
135 // Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
136 // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
137 // Retrieval info: PRIVATE: MIFfilename STRING ""
138 // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
139 // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
140 // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
141 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
142 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
143 // Retrieval info: PRIVATE: REGdata NUMERIC "1"
144 // Retrieval info: PRIVATE: REGq NUMERIC "0"
145 // Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
146 // Retrieval info: PRIVATE: REGrren NUMERIC "1"
147 // Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
148 // Retrieval info: PRIVATE: REGwren NUMERIC "1"
149 // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
150 // Retrieval info: PRIVATE: VarWidth NUMERIC "0"
151 // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
152 // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
153 // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
154 // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
155 // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
156 // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
157 // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
158 // Retrieval info: PRIVATE: enable NUMERIC "0"
159 // Retrieval info: PRIVATE: rden NUMERIC "1"
160 // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
161 // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
162 // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
163 // Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
164 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
165 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
166 // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
167 // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
168 // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
169 // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
170 // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
171 // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
172 // Retrieval info: CONSTANT: RDCONTROL_ACLR_B STRING "NONE"
173 // Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
174 // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
175 // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
176 // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
177 // Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
178 // Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
179 // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
180 // Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
181 // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
182 // Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
183 // Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
184 // Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL rdaddress[8..0]
185 // Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC rden
186 // Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL wraddress[8..0]
187 // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
188 // Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
189 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
190 // Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
191 // Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
192 // Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
193 // Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
194 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
195 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
196 // Retrieval info: GEN_FILE: TYPE_NORMAL regfile.v TRUE
197 // Retrieval info: GEN_FILE: TYPE_NORMAL regfile.inc FALSE
198 // Retrieval info: GEN_FILE: TYPE_NORMAL regfile.cmp FALSE
199 // Retrieval info: GEN_FILE: TYPE_NORMAL regfile.bsf FALSE
200 // Retrieval info: GEN_FILE: TYPE_NORMAL regfile_inst.v TRUE
201 // Retrieval info: GEN_FILE: TYPE_NORMAL regfile_bb.v FALSE
202 // Retrieval info: GEN_FILE: TYPE_NORMAL regfile_waveforms.html FALSE
203 // Retrieval info: GEN_FILE: TYPE_NORMAL regfile_wave*.jpg FALSE