rtl/Icarus/datamem.v

   1 // -----------------------------------------------------------------------
   2 //
   3 //   Copyright 2004 Tommy Thorn - All Rights Reserved
   4 //
   5 //   This program is free software; you can redistribute it and/or modify
   6 //   it under the terms of the GNU General Public License as published by
   7 //   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
   8 //   Bostom MA 02111-1307, USA; either version 2 of the License, or
   9 //   (at your option) any later version; incorporated herein by reference.
  10 //
  11 // -----------------------------------------------------------------------
  12
  13 `timescale 1ns/10ps
  14
  15 module datamem(input  wire        clock,
  16                input  wire [ 7:0] rdaddress,
  17                output wire [63:0] q,
  18                input  wire [ 7:0] wraddress,
  19                input  wire [ 7:0] byteena_a,
  20                input  wire        wren,
  21                input  wire [63:0] data);
  22
  23    reg [ 7:0] addr_delayed;
  24    reg [ 7:0] ram0[(1<<8) - 1:0],
  25               ram1[(1<<8) - 1:0],
  26               ram2[(1<<8) - 1:0],
  27               ram3[(1<<8) - 1:0],
  28               ram4[(1<<8) - 1:0],
  29               ram5[(1<<8) - 1:0],
  30               ram6[(1<<8) - 1:0],
  31               ram7[(1<<8) - 1:0];
  32
  33    assign q =
  34    {ram7[addr_delayed],ram6[addr_delayed],ram5[addr_delayed],ram4[addr_delayed],
  35     ram3[addr_delayed],ram2[addr_delayed],ram1[addr_delayed],ram0[addr_delayed]};
  36
  37
  38    always @(posedge clock) begin
  39      addr_delayed <= rdaddress;
  40      if (wren) begin
  41        if (byteena_a[7]) ram7[wraddress] <= data[63:56];
  42        if (byteena_a[6]) ram6[wraddress] <= data[55:48];
  43        if (byteena_a[5]) ram5[wraddress] <= data[47:40];
  44        if (byteena_a[4]) ram4[wraddress] <= data[39:32];
  45        if (byteena_a[3]) ram3[wraddress] <= data[31:24];
  46        if (byteena_a[2]) ram2[wraddress] <= data[23:16];
  47        if (byteena_a[1]) ram1[wraddress] <= data[15: 8];
  48        if (byteena_a[0]) ram0[wraddress] <= data[ 7: 0];
  49      end
  50    end
  51
  52    reg [8:0] i;
  53    initial
  54      for (i = 0; i < 256; i = i + 1) begin
  55         ram0[i] <= 0;
  56         ram1[i] <= 0;
  57         ram2[i] <= 0;
  58         ram3[i] <= 0;
  59         ram4[i] <= 0;
  60         ram5[i] <= 0;
  61         ram6[i] <= 0;
  62         ram7[i] <= 0;
  63      end
  64 endmodule