arch/mips/jmr3927/rbhma3100/setup.c

   1 /***********************************************************************
   2  *
   3  * Copyright 2001 MontaVista Software Inc.
   4  * Author: MontaVista Software, Inc.
   5  *              ahennessy@mvista.com
   6  *
   7  * Based on arch/mips/ddb5xxx/ddb5477/setup.c
   8  *
   9  *     Setup file for JMR3927.
  10  *
  11  * Copyright (C) 2000-2001 Toshiba Corporation
  12  *
  13  *  This program is free software; you can redistribute  it and/or modify it
  14  *  under  the terms of  the GNU General  Public License as published by the
  15  *  Free Software Foundation;  either version 2 of the  License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  19  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  21  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  24  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  25  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  26  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the  GNU General Public License along
  30  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  *
  33  ***********************************************************************
  34  */
  35
  36 #include <linux/config.h>
  37 #include <linux/init.h>
  38 #include <linux/kernel.h>
  39 #include <linux/kdev_t.h>
  40 #include <linux/types.h>
  41 #include <linux/sched.h>
  42 #include <linux/pci.h>
  43 #include <linux/ide.h>
  44 #include <linux/ioport.h>
  45 #include <linux/param.h>        /* for HZ */
  46 #include <linux/delay.h>
  47 #include <linux/pm.h>
  48 #ifdef CONFIG_SERIAL_TXX9
  49 #include <linux/tty.h>
  50 #include <linux/serial.h>
  51 #include <linux/serial_core.h>
  52 #endif
  53
  54 #include <asm/addrspace.h>
  55 #include <asm/time.h>
  56 #include <asm/bcache.h>
  57 #include <asm/irq.h>
  58 #include <asm/reboot.h>
  59 #include <asm/gdb-stub.h>
  60 #include <asm/jmr3927/jmr3927.h>
  61 #include <asm/mipsregs.h>
  62 #include <asm/traps.h>
  63
  64 extern void puts(unsigned char *cp);
  65
  66 /* Tick Timer divider */
  67 #define JMR3927_TIMER_CCD       0       /* 1/2 */
  68 #define JMR3927_TIMER_CLK       (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
  69
  70 unsigned char led_state = 0xf;
  71
  72 struct {
  73     struct resource ram0;
  74     struct resource ram1;
  75     struct resource pcimem;
  76     struct resource iob;
  77     struct resource ioc;
  78     struct resource pciio;
  79     struct resource jmy1394;
  80     struct resource rom1;
  81     struct resource rom0;
  82     struct resource sio0;
  83     struct resource sio1;
  84 } jmr3927_resources = {
  85     { "RAM0",           0,         0x01FFFFFF,  IORESOURCE_MEM },
  86     { "RAM1",          0x02000000, 0x03FFFFFF,  IORESOURCE_MEM },
  87     { "PCIMEM",        0x08000000, 0x07FFFFFF,  IORESOURCE_MEM },
  88     { "IOB",           0x10000000, 0x13FFFFFF                  },
  89     { "IOC",           0x14000000, 0x14FFFFFF                  },
  90     { "PCIIO",         0x15000000, 0x15FFFFFF                  },
  91     { "JMY1394",       0x1D000000, 0x1D3FFFFF                  },
  92     { "ROM1",          0x1E000000, 0x1E3FFFFF                  },
  93     { "ROM0",          0x1FC00000, 0x1FFFFFFF                  },
  94     { "SIO0",          0xFFFEF300, 0xFFFEF3FF                  },
  95     { "SIO1",          0xFFFEF400, 0xFFFEF4FF                  },
  96 };
  97
  98 /* don't enable - see errata */
  99 int jmr3927_ccfg_toeon = 0;
 100
 101 static inline void do_reset(void)
 102 {
 103 #ifdef CONFIG_TC35815
 104         extern void tc35815_killall(void);
 105         tc35815_killall();
 106 #endif
 107 #if 1   /* Resetting PCI bus */
 108         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 109         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
 110         (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);       /* flush WB */
 111         mdelay(1);
 112         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 113 #endif
 114         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
 115 }
 116
 117 static void jmr3927_machine_restart(char *command)
 118 {
 119         local_irq_disable();
 120         puts("Rebooting...");
 121         do_reset();
 122 }
 123
 124 static void jmr3927_machine_halt(void)
 125 {
 126         puts("JMR-TX3927 halted.\n");
 127         while (1);
 128 }
 129
 130 static void jmr3927_machine_power_off(void)
 131 {
 132         puts("JMR-TX3927 halted. Please turn off the power.\n");
 133         while (1);
 134 }
 135
 136 #define USE_RTC_DS1742
 137 #ifdef USE_RTC_DS1742
 138 extern void rtc_ds1742_init(unsigned long base);
 139 #endif
 140 static void __init jmr3927_time_init(void)
 141 {
 142 #ifdef USE_RTC_DS1742
 143         if (jmr3927_have_nvram()) {
 144                 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
 145         }
 146 #endif
 147 }
 148
 149 unsigned long jmr3927_do_gettimeoffset(void);
 150 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
 151
 152 static void __init jmr3927_timer_setup(struct irqaction *irq)
 153 {
 154         do_gettimeoffset = jmr3927_do_gettimeoffset;
 155
 156         jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
 157         jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
 158         jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
 159         jmr3927_tmrptr->tcr =
 160                 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
 161
 162         setup_irq(JMR3927_IRQ_TICK, irq);
 163 }
 164
 165 #define USECS_PER_JIFFY (1000000/HZ)
 166
 167 unsigned long jmr3927_do_gettimeoffset(void)
 168 {
 169        unsigned long count;
 170        unsigned long res = 0;
 171
 172        /* MUST read TRR before TISR. */
 173        count = jmr3927_tmrptr->trr;
 174
 175        if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
 176                /* timer interrupt is pending.  use Max value. */
 177                res = USECS_PER_JIFFY - 1;
 178        } else {
 179                /* convert to usec */
 180                /* res = count / (JMR3927_TIMER_CLK / 1000000); */
 181                res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
 182
 183                /*
 184                 * Due to possible jiffies inconsistencies, we need to check
 185                 * the result so that we'll get a timer that is monotonic.
 186                 */
 187                if (res >= USECS_PER_JIFFY)
 188                        res = USECS_PER_JIFFY-1;
 189        }
 190
 191        return res;
 192 }
 193
 194
 195 //#undef DO_WRITE_THROUGH
 196 #define DO_WRITE_THROUGH
 197 #define DO_ENABLE_CACHE
 198
 199 extern char * __init prom_getcmdline(void);
 200 static void jmr3927_board_init(void);
 201 extern struct resource pci_io_resource;
 202 extern struct resource pci_mem_resource;
 203
 204 void __init plat_setup(void)
 205 {
 206         char *argptr;
 207
 208         set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
 209
 210         board_time_init = jmr3927_time_init;
 211         board_timer_setup = jmr3927_timer_setup;
 212
 213         _machine_restart = jmr3927_machine_restart;
 214         _machine_halt = jmr3927_machine_halt;
 215         pm_power_off = jmr3927_machine_power_off;
 216
 217         /*
 218          * IO/MEM resources.
 219          */
 220         ioport_resource.start = pci_io_resource.start;
 221         ioport_resource.end = pci_io_resource.end;
 222         iomem_resource.start = 0;
 223         iomem_resource.end = 0xffffffff;
 224
 225         /* Reboot on panic */
 226         panic_timeout = 180;
 227
 228         {
 229                 unsigned int conf;
 230                 conf = read_c0_conf();
 231         }
 232
 233 #if 1
 234         /* cache setup */
 235         {
 236                 unsigned int conf;
 237 #ifdef DO_ENABLE_CACHE
 238                 int mips_ic_disable = 0, mips_dc_disable = 0;
 239 #else
 240                 int mips_ic_disable = 1, mips_dc_disable = 1;
 241 #endif
 242 #ifdef DO_WRITE_THROUGH
 243                 int mips_config_cwfon = 0;
 244                 int mips_config_wbon = 0;
 245 #else
 246                 int mips_config_cwfon = 1;
 247                 int mips_config_wbon = 1;
 248 #endif
 249
 250                 conf = read_c0_conf();
 251                 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
 252                 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
 253                 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
 254                 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
 255                 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
 256
 257                 write_c0_conf(conf);
 258                 write_c0_cache(0);
 259         }
 260 #endif
 261
 262         /* initialize board */
 263         jmr3927_board_init();
 264
 265         argptr = prom_getcmdline();
 266
 267         if ((argptr = strstr(argptr, "toeon")) != NULL) {
 268                         jmr3927_ccfg_toeon = 1;
 269         }
 270         argptr = prom_getcmdline();
 271         if ((argptr = strstr(argptr, "ip=")) == NULL) {
 272                 argptr = prom_getcmdline();
 273                 strcat(argptr, " ip=bootp");
 274         }
 275
 276 #ifdef CONFIG_SERIAL_TXX9
 277         {
 278                 extern int early_serial_txx9_setup(struct uart_port *port);
 279                 int i;
 280                 struct uart_port req;
 281                 for(i = 0; i < 2; i++) {
 282                         memset(&req, 0, sizeof(req));
 283                         req.line = i;
 284                         req.iotype = UPIO_MEM;
 285                         req.membase = (char *)TX3927_SIO_REG(i);
 286                         req.mapbase = TX3927_SIO_REG(i);
 287                         req.irq = i == 0 ?
 288                                 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
 289                         if (i == 0)
 290                                 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 291                         req.uartclk = JMR3927_IMCLK;
 292                         early_serial_txx9_setup(&req);
 293                 }
 294         }
 295 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 296         argptr = prom_getcmdline();
 297         if ((argptr = strstr(argptr, "console=")) == NULL) {
 298                 argptr = prom_getcmdline();
 299                 strcat(argptr, " console=ttyS1,115200");
 300         }
 301 #endif
 302 #endif
 303 }
 304
 305 static void tx3927_setup(void);
 306
 307 #ifdef CONFIG_PCI
 308 unsigned long mips_pci_io_base;
 309 unsigned long mips_pci_io_size;
 310 unsigned long mips_pci_mem_base;
 311 unsigned long mips_pci_mem_size;
 312 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 313 unsigned long mips_pci_io_pciaddr = 0;
 314 #endif
 315
 316 static void __init jmr3927_board_init(void)
 317 {
 318         char *argptr;
 319
 320 #ifdef CONFIG_PCI
 321         mips_pci_io_base = JMR3927_PCIIO;
 322         mips_pci_io_size = JMR3927_PCIIO_SIZE;
 323         mips_pci_mem_base = JMR3927_PCIMEM;
 324         mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
 325 #endif
 326
 327         tx3927_setup();
 328
 329         if (jmr3927_have_isac()) {
 330
 331 #ifdef CONFIG_FB_E1355
 332                 argptr = prom_getcmdline();
 333                 if ((argptr = strstr(argptr, "video=")) == NULL) {
 334                         argptr = prom_getcmdline();
 335                         strcat(argptr, " video=e1355fb:crt16h");
 336                 }
 337 #endif
 338
 339 #ifdef CONFIG_BLK_DEV_IDE
 340                 /* overrides PCI-IDE */
 341 #endif
 342         }
 343
 344         /* SIO0 DTR on */
 345         jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
 346
 347         jmr3927_led_set(0);
 348
 349
 350         if (jmr3927_have_isac())
 351                 jmr3927_io_led_set(0);
 352         printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
 353                jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
 354                jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
 355                jmr3927_dipsw1(), jmr3927_dipsw2(),
 356                jmr3927_dipsw3(), jmr3927_dipsw4());
 357         if (jmr3927_have_isac())
 358                 printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
 359                        jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
 360                        jmr3927_io_dipsw());
 361 }
 362
 363 void __init tx3927_setup(void)
 364 {
 365         int i;
 366
 367         /* SDRAMC are configured by PROM */
 368
 369         /* ROMC */
 370         tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
 371         tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
 372         tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
 373         tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
 374
 375         /* CCFG */
 376         /* enable Timeout BusError */
 377         if (jmr3927_ccfg_toeon)
 378                 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
 379
 380         /* clear BusErrorOnWrite flag */
 381         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
 382         /* Disable PCI snoop */
 383         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
 384
 385 #ifdef DO_WRITE_THROUGH
 386         /* Enable PCI SNOOP - with write through only */
 387         tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
 388 #endif
 389
 390         /* Pin selection */
 391         tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
 392         tx3927_ccfgptr->pcfg |=
 393                 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
 394                 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
 395
 396         printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
 397                tx3927_ccfgptr->crir,
 398                tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 399
 400         /* IRC */
 401         /* disable interrupt control */
 402         tx3927_ircptr->cer = 0;
 403         /* mask all IRC interrupts */
 404         tx3927_ircptr->imr = 0;
 405         for (i = 0; i < TX3927_NUM_IR / 2; i++) {
 406                 tx3927_ircptr->ilr[i] = 0;
 407         }
 408         /* setup IRC interrupt mode (Low Active) */
 409         for (i = 0; i < TX3927_NUM_IR / 8; i++) {
 410                 tx3927_ircptr->cr[i] = 0;
 411         }
 412
 413         /* TMR */
 414         /* disable all timers */
 415         for (i = 0; i < TX3927_NR_TMR; i++) {
 416                 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
 417                 tx3927_tmrptr(i)->tisr = 0;
 418                 tx3927_tmrptr(i)->cpra = 0xffffffff;
 419                 tx3927_tmrptr(i)->itmr = 0;
 420                 tx3927_tmrptr(i)->ccdr = 0;
 421                 tx3927_tmrptr(i)->pgmr = 0;
 422         }
 423
 424         /* DMA */
 425         tx3927_dmaptr->mcr = 0;
 426         for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
 427                 /* reset channel */
 428                 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
 429                 tx3927_dmaptr->ch[i].ccr = 0;
 430         }
 431         /* enable DMA */
 432 #ifdef __BIG_ENDIAN
 433         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
 434 #else
 435         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
 436 #endif
 437
 438 #ifdef CONFIG_PCI
 439         /* PCIC */
 440         printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
 441                tx3927_pcicptr->did, tx3927_pcicptr->vid,
 442                tx3927_pcicptr->rid);
 443         if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
 444                 printk("External\n");
 445                 /* XXX */
 446         } else {
 447                 printk("Internal\n");
 448
 449                 /* Reset PCI Bus */
 450                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 451                 udelay(100);
 452                 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
 453                                     JMR3927_IOC_RESET_ADDR);
 454                 udelay(100);
 455                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 456
 457
 458                 /* Disable External PCI Config. Access */
 459                 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
 460 #ifdef __BIG_ENDIAN
 461                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
 462                         TX3927_PCIC_LBC_TIBSE |
 463                         TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
 464 #endif
 465                 /* LB->PCI mappings */
 466                 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
 467                 tx3927_pcicptr->ilbioma = mips_pci_io_base;
 468                 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
 469                 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
 470                 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
 471                 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
 472                 /* PCI->LB mappings */
 473                 tx3927_pcicptr->iobas = 0xffffffff;
 474                 tx3927_pcicptr->ioba = 0;
 475                 tx3927_pcicptr->tlbioma = 0;
 476                 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
 477                 tx3927_pcicptr->mba = 0;
 478                 tx3927_pcicptr->tlbmma = 0;
 479 #ifndef JMR3927_INIT_INDIRECT_PCI
 480                 /* Enable Direct mapping Address Space Decoder */
 481                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
 482 #endif
 483
 484                 /* Clear All Local Bus Status */
 485                 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
 486                 /* Enable All Local Bus Interrupts */
 487                 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
 488                 /* Clear All PCI Status Error */
 489                 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
 490                 /* Enable All PCI Status Error Interrupts */
 491                 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
 492
 493                 /* PCIC Int => IRC IRQ10 */
 494                 tx3927_pcicptr->il = TX3927_IR_PCI;
 495 #if 1
 496                 /* Target Control (per errata) */
 497                 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
 498 #endif
 499
 500                 /* Enable Bus Arbiter */
 501 #if 0
 502                 tx3927_pcicptr->req_trace = 0x73737373;
 503 #endif
 504                 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
 505
 506                 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
 507                         PCI_COMMAND_MEMORY |
 508 #if 1
 509                         PCI_COMMAND_IO |
 510 #endif
 511                         PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 512         }
 513 #endif /* CONFIG_PCI */
 514
 515         /* PIO */
 516         /* PIO[15:12] connected to LEDs */
 517         tx3927_pioptr->dir = 0x0000f000;
 518         tx3927_pioptr->maskcpu = 0;
 519         tx3927_pioptr->maskext = 0;
 520         {
 521                 unsigned int conf;
 522
 523         conf = read_c0_conf();
 524                if (!(conf & TX39_CONF_ICE))
 525                        printk("TX3927 I-Cache disabled.\n");
 526                if (!(conf & TX39_CONF_DCE))
 527                        printk("TX3927 D-Cache disabled.\n");
 528                else if (!(conf & TX39_CONF_WBON))
 529                        printk("TX3927 D-Cache WriteThrough.\n");
 530                else if (!(conf & TX39_CONF_CWFON))
 531                        printk("TX3927 D-Cache WriteBack.\n");
 532                else
 533                        printk("TX3927 D-Cache WriteBack (CWF) .\n");
 534         }
 535 }