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i915: fix lock imbalance on error path...
[firewire-audio.git] / include / linux / pci.h
bloba327322a33abef0b74967f5bd0a82962d74e9ab5
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
138
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143 typedef unsigned int __bitwise pci_channel_state_t;
144
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154 };
155
156 typedef unsigned int __bitwise pcie_reset_state_t;
157
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167 };
168
169 typedef unsigned short __bitwise pci_dev_flags_t;
170 enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 };
178
179 enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182 };
183
184 typedef unsigned short __bitwise pci_bus_flags_t;
185 enum pci_bus_flags {
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
188 };
189
190 /* Based on the PCI Hotplug Spec, but some values are made up by us */
191 enum pci_bus_speed {
192 PCI_SPEED_33MHz = 0x00,
193 PCI_SPEED_66MHz = 0x01,
194 PCI_SPEED_66MHz_PCIX = 0x02,
195 PCI_SPEED_100MHz_PCIX = 0x03,
196 PCI_SPEED_133MHz_PCIX = 0x04,
197 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
198 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
199 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
200 PCI_SPEED_66MHz_PCIX_266 = 0x09,
201 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
202 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
203 AGP_UNKNOWN = 0x0c,
204 AGP_1X = 0x0d,
205 AGP_2X = 0x0e,
206 AGP_4X = 0x0f,
207 AGP_8X = 0x10,
208 PCI_SPEED_66MHz_PCIX_533 = 0x11,
209 PCI_SPEED_100MHz_PCIX_533 = 0x12,
210 PCI_SPEED_133MHz_PCIX_533 = 0x13,
211 PCIE_SPEED_2_5GT = 0x14,
212 PCIE_SPEED_5_0GT = 0x15,
213 PCIE_SPEED_8_0GT = 0x16,
214 PCI_SPEED_UNKNOWN = 0xff,
215 };
216
217 struct pci_cap_saved_state {
218 struct hlist_node next;
219 char cap_nr;
220 u32 data[0];
221 };
222
223 struct pcie_link_state;
224 struct pci_vpd;
225 struct pci_sriov;
226 struct pci_ats;
227
228 /*
229 * The pci_dev structure is used to describe PCI devices.
230 */
231 struct pci_dev {
232 struct list_head bus_list; /* node in per-bus list */
233 struct pci_bus *bus; /* bus this device is on */
234 struct pci_bus *subordinate; /* bus this device bridges to */
235
236 void *sysdata; /* hook for sys-specific extension */
237 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
238 struct pci_slot *slot; /* Physical slot this device is in */
239
240 unsigned int devfn; /* encoded device & function index */
241 unsigned short vendor;
242 unsigned short device;
243 unsigned short subsystem_vendor;
244 unsigned short subsystem_device;
245 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
246 u8 revision; /* PCI revision, low byte of class word */
247 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
248 u8 pcie_cap; /* PCI-E capability offset */
249 u8 pcie_type; /* PCI-E device/port type */
250 u8 rom_base_reg; /* which config register controls the ROM */
251 u8 pin; /* which interrupt pin this device uses */
252
253 struct pci_driver *driver; /* which driver has allocated this device */
254 u64 dma_mask; /* Mask of the bits of bus address this
255 device implements. Normally this is
256 0xffffffff. You only need to change
257 this if your device has broken DMA
258 or supports 64-bit transfers. */
259
260 struct device_dma_parameters dma_parms;
261
262 pci_power_t current_state; /* Current operating state. In ACPI-speak,
263 this is D0-D3, D0 being fully functional,
264 and D3 being off. */
265 int pm_cap; /* PM capability offset in the
266 configuration space */
267 unsigned int pme_support:5; /* Bitmask of states from which PME#
268 can be generated */
269 unsigned int pme_interrupt:1;
270 unsigned int d1_support:1; /* Low power state D1 is supported */
271 unsigned int d2_support:1; /* Low power state D2 is supported */
272 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
273 unsigned int wakeup_prepared:1;
274 unsigned int d3_delay; /* D3->D0 transition time in ms */
275
276 #ifdef CONFIG_PCIEASPM
277 struct pcie_link_state *link_state; /* ASPM link state. */
278 #endif
279
280 pci_channel_state_t error_state; /* current connectivity state */
281 struct device dev; /* Generic device interface */
282
283 int cfg_size; /* Size of configuration space */
284
285 /*
286 * Instead of touching interrupt line and base address registers
287 * directly, use the values stored here. They might be different!
288 */
289 unsigned int irq;
290 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
291
292 /* These fields are used by common fixups */
293 unsigned int transparent:1; /* Transparent PCI bridge */
294 unsigned int multifunction:1;/* Part of multi-function device */
295 /* keep track of device state */
296 unsigned int is_added:1;
297 unsigned int is_busmaster:1; /* device is busmaster */
298 unsigned int no_msi:1; /* device may not use msi */
299 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
300 unsigned int broken_parity_status:1; /* Device generates false positive parity */
301 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
302 unsigned int msi_enabled:1;
303 unsigned int msix_enabled:1;
304 unsigned int ari_enabled:1; /* ARI forwarding */
305 unsigned int is_managed:1;
306 unsigned int is_pcie:1; /* Obsolete. Will be removed.
307 Use pci_is_pcie() instead */
308 unsigned int needs_freset:1; /* Dev requires fundamental reset */
309 unsigned int state_saved:1;
310 unsigned int is_physfn:1;
311 unsigned int is_virtfn:1;
312 unsigned int reset_fn:1;
313 unsigned int is_hotplug_bridge:1;
314 unsigned int aer_firmware_first:1;
315 pci_dev_flags_t dev_flags;
316 atomic_t enable_cnt; /* pci_enable_device has been called */
317
318 u32 saved_config_space[16]; /* config space saved at suspend time */
319 struct hlist_head saved_cap_space;
320 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
321 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
322 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
323 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
324 #ifdef CONFIG_PCI_MSI
325 struct list_head msi_list;
326 #endif
327 struct pci_vpd *vpd;
328 #ifdef CONFIG_PCI_IOV
329 union {
330 struct pci_sriov *sriov; /* SR-IOV capability related */
331 struct pci_dev *physfn; /* the PF this VF is associated with */
332 };
333 struct pci_ats *ats; /* Address Translation Service */
334 #endif
335 };
336
337 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
338 {
339 #ifdef CONFIG_PCI_IOV
340 if (dev->is_virtfn)
341 dev = dev->physfn;
342 #endif
343
344 return dev;
345 }
346
347 extern struct pci_dev *alloc_pci_dev(void);
348
349 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
350 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
351 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
352
353 static inline int pci_channel_offline(struct pci_dev *pdev)
354 {
355 return (pdev->error_state != pci_channel_io_normal);
356 }
357
358 static inline struct pci_cap_saved_state *pci_find_saved_cap(
359 struct pci_dev *pci_dev, char cap)
360 {
361 struct pci_cap_saved_state *tmp;
362 struct hlist_node *pos;
363
364 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
365 if (tmp->cap_nr == cap)
366 return tmp;
367 }
368 return NULL;
369 }
370
371 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
372 struct pci_cap_saved_state *new_cap)
373 {
374 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
375 }
376
377 /*
378 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
379 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
380 * buses below host bridges or subtractive decode bridges) go in the list.
381 * Use pci_bus_for_each_resource() to iterate through all the resources.
382 */
383
384 /*
385 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
386 * and there's no way to program the bridge with the details of the window.
387 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
388 * decode bit set, because they are explicit and can be programmed with _SRS.
389 */
390 #define PCI_SUBTRACTIVE_DECODE 0x1
391
392 struct pci_bus_resource {
393 struct list_head list;
394 struct resource *res;
395 unsigned int flags;
396 };
397
398 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
399
400 struct pci_bus {
401 struct list_head node; /* node in list of buses */
402 struct pci_bus *parent; /* parent bus this bridge is on */
403 struct list_head children; /* list of child buses */
404 struct list_head devices; /* list of devices on this bus */
405 struct pci_dev *self; /* bridge device as seen by parent */
406 struct list_head slots; /* list of slots on this bus */
407 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
408 struct list_head resources; /* address space routed to this bus */
409
410 struct pci_ops *ops; /* configuration access functions */
411 void *sysdata; /* hook for sys-specific extension */
412 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
413
414 unsigned char number; /* bus number */
415 unsigned char primary; /* number of primary bridge */
416 unsigned char secondary; /* number of secondary bridge */
417 unsigned char subordinate; /* max number of subordinate buses */
418 unsigned char max_bus_speed; /* enum pci_bus_speed */
419 unsigned char cur_bus_speed; /* enum pci_bus_speed */
420
421 char name[48];
422
423 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
424 pci_bus_flags_t bus_flags; /* Inherited by child busses */
425 struct device *bridge;
426 struct device dev;
427 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
428 struct bin_attribute *legacy_mem; /* legacy mem */
429 unsigned int is_added:1;
430 };
431
432 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
433 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
434
435 /*
436 * Returns true if the pci bus is root (behind host-pci bridge),
437 * false otherwise
438 */
439 static inline bool pci_is_root_bus(struct pci_bus *pbus)
440 {
441 return !(pbus->parent);
442 }
443
444 #ifdef CONFIG_PCI_MSI
445 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
446 {
447 return pci_dev->msi_enabled || pci_dev->msix_enabled;
448 }
449 #else
450 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
451 #endif
452
453 /*
454 * Error values that may be returned by PCI functions.
455 */
456 #define PCIBIOS_SUCCESSFUL 0x00
457 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
458 #define PCIBIOS_BAD_VENDOR_ID 0x83
459 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
460 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
461 #define PCIBIOS_SET_FAILED 0x88
462 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
463
464 /* Low-level architecture-dependent routines */
465
466 struct pci_ops {
467 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
468 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
469 };
470
471 /*
472 * ACPI needs to be able to access PCI config space before we've done a
473 * PCI bus scan and created pci_bus structures.
474 */
475 extern int raw_pci_read(unsigned int domain, unsigned int bus,
476 unsigned int devfn, int reg, int len, u32 *val);
477 extern int raw_pci_write(unsigned int domain, unsigned int bus,
478 unsigned int devfn, int reg, int len, u32 val);
479
480 struct pci_bus_region {
481 resource_size_t start;
482 resource_size_t end;
483 };
484
485 struct pci_dynids {
486 spinlock_t lock; /* protects list, index */
487 struct list_head list; /* for IDs added at runtime */
488 };
489
490 /* ---------------------------------------------------------------- */
491 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
492 * a set of callbacks in struct pci_error_handlers, then that device driver
493 * will be notified of PCI bus errors, and will be driven to recovery
494 * when an error occurs.
495 */
496
497 typedef unsigned int __bitwise pci_ers_result_t;
498
499 enum pci_ers_result {
500 /* no result/none/not supported in device driver */
501 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
502
503 /* Device driver can recover without slot reset */
504 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
505
506 /* Device driver wants slot to be reset. */
507 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
508
509 /* Device has completely failed, is unrecoverable */
510 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
511
512 /* Device driver is fully recovered and operational */
513 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
514 };
515
516 /* PCI bus error event callbacks */
517 struct pci_error_handlers {
518 /* PCI bus error detected on this device */
519 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
520 enum pci_channel_state error);
521
522 /* MMIO has been re-enabled, but not DMA */
523 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
524
525 /* PCI Express link has been reset */
526 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
527
528 /* PCI slot has been reset */
529 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
530
531 /* Device driver may resume normal operations */
532 void (*resume)(struct pci_dev *dev);
533 };
534
535 /* ---------------------------------------------------------------- */
536
537 struct module;
538 struct pci_driver {
539 struct list_head node;
540 char *name;
541 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
542 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
543 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
544 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
545 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
546 int (*resume_early) (struct pci_dev *dev);
547 int (*resume) (struct pci_dev *dev); /* Device woken up */
548 void (*shutdown) (struct pci_dev *dev);
549 struct pci_error_handlers *err_handler;
550 struct device_driver driver;
551 struct pci_dynids dynids;
552 };
553
554 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
555
556 /**
557 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
558 * @_table: device table name
559 *
560 * This macro is used to create a struct pci_device_id array (a device table)
561 * in a generic manner.
562 */
563 #define DEFINE_PCI_DEVICE_TABLE(_table) \
564 const struct pci_device_id _table[] __devinitconst
565
566 /**
567 * PCI_DEVICE - macro used to describe a specific pci device
568 * @vend: the 16 bit PCI Vendor ID
569 * @dev: the 16 bit PCI Device ID
570 *
571 * This macro is used to create a struct pci_device_id that matches a
572 * specific device. The subvendor and subdevice fields will be set to
573 * PCI_ANY_ID.
574 */
575 #define PCI_DEVICE(vend,dev) \
576 .vendor = (vend), .device = (dev), \
577 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
578
579 /**
580 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
581 * @dev_class: the class, subclass, prog-if triple for this device
582 * @dev_class_mask: the class mask for this device
583 *
584 * This macro is used to create a struct pci_device_id that matches a
585 * specific PCI class. The vendor, device, subvendor, and subdevice
586 * fields will be set to PCI_ANY_ID.
587 */
588 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
589 .class = (dev_class), .class_mask = (dev_class_mask), \
590 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
591 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
592
593 /**
594 * PCI_VDEVICE - macro used to describe a specific pci device in short form
595 * @vendor: the vendor name
596 * @device: the 16 bit PCI Device ID
597 *
598 * This macro is used to create a struct pci_device_id that matches a
599 * specific PCI device. The subvendor, and subdevice fields will be set
600 * to PCI_ANY_ID. The macro allows the next field to follow as the device
601 * private data.
602 */
603
604 #define PCI_VDEVICE(vendor, device) \
605 PCI_VENDOR_ID_##vendor, (device), \
606 PCI_ANY_ID, PCI_ANY_ID, 0, 0
607
608 /* these external functions are only available when PCI support is enabled */
609 #ifdef CONFIG_PCI
610
611 extern struct bus_type pci_bus_type;
612
613 /* Do NOT directly access these two variables, unless you are arch specific pci
614 * code, or pci core code. */
615 extern struct list_head pci_root_buses; /* list of all known PCI buses */
616 /* Some device drivers need know if pci is initiated */
617 extern int no_pci_devices(void);
618
619 void pcibios_fixup_bus(struct pci_bus *);
620 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
621 char *pcibios_setup(char *str);
622
623 /* Used only when drivers/pci/setup.c is used */
624 resource_size_t pcibios_align_resource(void *, const struct resource *,
625 resource_size_t,
626 resource_size_t);
627 void pcibios_update_irq(struct pci_dev *, int irq);
628
629 /* Weak but can be overriden by arch */
630 void pci_fixup_cardbus(struct pci_bus *);
631
632 /* Generic PCI functions used internally */
633
634 extern struct pci_bus *pci_find_bus(int domain, int busnr);
635 void pci_bus_add_devices(const struct pci_bus *bus);
636 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
637 struct pci_ops *ops, void *sysdata);
638 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
639 void *sysdata)
640 {
641 struct pci_bus *root_bus;
642 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
643 if (root_bus)
644 pci_bus_add_devices(root_bus);
645 return root_bus;
646 }
647 struct pci_bus *pci_create_bus(struct device *parent, int bus,
648 struct pci_ops *ops, void *sysdata);
649 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
650 int busnr);
651 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
652 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
653 const char *name,
654 struct hotplug_slot *hotplug);
655 void pci_destroy_slot(struct pci_slot *slot);
656 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
657 int pci_scan_slot(struct pci_bus *bus, int devfn);
658 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
659 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
660 unsigned int pci_scan_child_bus(struct pci_bus *bus);
661 int __must_check pci_bus_add_device(struct pci_dev *dev);
662 void pci_read_bridge_bases(struct pci_bus *child);
663 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
664 struct resource *res);
665 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
666 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
667 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
668 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
669 extern void pci_dev_put(struct pci_dev *dev);
670 extern void pci_remove_bus(struct pci_bus *b);
671 extern void pci_remove_bus_device(struct pci_dev *dev);
672 extern void pci_stop_bus_device(struct pci_dev *dev);
673 void pci_setup_cardbus(struct pci_bus *bus);
674 extern void pci_sort_breadthfirst(void);
675 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
676 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
677 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
678
679 /* Generic PCI functions exported to card drivers */
680
681 enum pci_lost_interrupt_reason {
682 PCI_LOST_IRQ_NO_INFORMATION = 0,
683 PCI_LOST_IRQ_DISABLE_MSI,
684 PCI_LOST_IRQ_DISABLE_MSIX,
685 PCI_LOST_IRQ_DISABLE_ACPI,
686 };
687 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
688 int pci_find_capability(struct pci_dev *dev, int cap);
689 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
690 int pci_find_ext_capability(struct pci_dev *dev, int cap);
691 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
692 int cap);
693 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
694 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
695 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
696
697 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
698 struct pci_dev *from);
699 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
700 unsigned int ss_vendor, unsigned int ss_device,
701 struct pci_dev *from);
702 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
703 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
704 unsigned int devfn);
705 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
706 unsigned int devfn)
707 {
708 return pci_get_domain_bus_and_slot(0, bus, devfn);
709 }
710 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
711 int pci_dev_present(const struct pci_device_id *ids);
712
713 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
714 int where, u8 *val);
715 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
716 int where, u16 *val);
717 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
718 int where, u32 *val);
719 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
720 int where, u8 val);
721 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
722 int where, u16 val);
723 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
724 int where, u32 val);
725 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
726
727 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
728 {
729 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
730 }
731 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
732 {
733 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
734 }
735 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
736 u32 *val)
737 {
738 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
739 }
740 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
741 {
742 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
743 }
744 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
745 {
746 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
747 }
748 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
749 u32 val)
750 {
751 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
752 }
753
754 int __must_check pci_enable_device(struct pci_dev *dev);
755 int __must_check pci_enable_device_io(struct pci_dev *dev);
756 int __must_check pci_enable_device_mem(struct pci_dev *dev);
757 int __must_check pci_reenable_device(struct pci_dev *);
758 int __must_check pcim_enable_device(struct pci_dev *pdev);
759 void pcim_pin_device(struct pci_dev *pdev);
760
761 static inline int pci_is_enabled(struct pci_dev *pdev)
762 {
763 return (atomic_read(&pdev->enable_cnt) > 0);
764 }
765
766 static inline int pci_is_managed(struct pci_dev *pdev)
767 {
768 return pdev->is_managed;
769 }
770
771 void pci_disable_device(struct pci_dev *dev);
772 void pci_set_master(struct pci_dev *dev);
773 void pci_clear_master(struct pci_dev *dev);
774 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
775 int pci_set_cacheline_size(struct pci_dev *dev);
776 #define HAVE_PCI_SET_MWI
777 int __must_check pci_set_mwi(struct pci_dev *dev);
778 int pci_try_set_mwi(struct pci_dev *dev);
779 void pci_clear_mwi(struct pci_dev *dev);
780 void pci_intx(struct pci_dev *dev, int enable);
781 void pci_msi_off(struct pci_dev *dev);
782 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
783 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
784 int pcix_get_max_mmrbc(struct pci_dev *dev);
785 int pcix_get_mmrbc(struct pci_dev *dev);
786 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
787 int pcie_get_readrq(struct pci_dev *dev);
788 int pcie_set_readrq(struct pci_dev *dev, int rq);
789 int __pci_reset_function(struct pci_dev *dev);
790 int pci_reset_function(struct pci_dev *dev);
791 void pci_update_resource(struct pci_dev *dev, int resno);
792 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
793 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
794
795 /* ROM control related routines */
796 int pci_enable_rom(struct pci_dev *pdev);
797 void pci_disable_rom(struct pci_dev *pdev);
798 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
799 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
800 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
801
802 /* Power management related routines */
803 int pci_save_state(struct pci_dev *dev);
804 int pci_restore_state(struct pci_dev *dev);
805 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
806 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
807 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
808 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
809 void pci_pme_active(struct pci_dev *dev, bool enable);
810 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
811 bool runtime, bool enable);
812 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
813 pci_power_t pci_target_state(struct pci_dev *dev);
814 int pci_prepare_to_sleep(struct pci_dev *dev);
815 int pci_back_from_sleep(struct pci_dev *dev);
816 bool pci_dev_run_wake(struct pci_dev *dev);
817
818 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
819 bool enable)
820 {
821 return __pci_enable_wake(dev, state, false, enable);
822 }
823
824 /* For use by arch with custom probe code */
825 void set_pcie_port_type(struct pci_dev *pdev);
826 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
827
828 /* Functions for PCI Hotplug drivers to use */
829 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
830 #ifdef CONFIG_HOTPLUG
831 unsigned int pci_rescan_bus(struct pci_bus *bus);
832 #endif
833
834 /* Vital product data routines */
835 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
836 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
837 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
838
839 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
840 void pci_bus_assign_resources(const struct pci_bus *bus);
841 void pci_bus_size_bridges(struct pci_bus *bus);
842 int pci_claim_resource(struct pci_dev *, int);
843 void pci_assign_unassigned_resources(void);
844 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
845 void pdev_enable_device(struct pci_dev *);
846 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
847 int pci_enable_resources(struct pci_dev *, int mask);
848 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
849 int (*)(struct pci_dev *, u8, u8));
850 #define HAVE_PCI_REQ_REGIONS 2
851 int __must_check pci_request_regions(struct pci_dev *, const char *);
852 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
853 void pci_release_regions(struct pci_dev *);
854 int __must_check pci_request_region(struct pci_dev *, int, const char *);
855 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
856 void pci_release_region(struct pci_dev *, int);
857 int pci_request_selected_regions(struct pci_dev *, int, const char *);
858 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
859 void pci_release_selected_regions(struct pci_dev *, int);
860
861 /* drivers/pci/bus.c */
862 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
863 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
864 void pci_bus_remove_resources(struct pci_bus *bus);
865
866 #define pci_bus_for_each_resource(bus, res, i) \
867 for (i = 0; \
868 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
869 i++)
870
871 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
872 struct resource *res, resource_size_t size,
873 resource_size_t align, resource_size_t min,
874 unsigned int type_mask,
875 resource_size_t (*alignf)(void *,
876 const struct resource *,
877 resource_size_t,
878 resource_size_t),
879 void *alignf_data);
880 void pci_enable_bridges(struct pci_bus *bus);
881
882 /* Proper probing supporting hot-pluggable devices */
883 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
884 const char *mod_name);
885
886 /*
887 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
888 */
889 #define pci_register_driver(driver) \
890 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
891
892 void pci_unregister_driver(struct pci_driver *dev);
893 void pci_remove_behind_bridge(struct pci_dev *dev);
894 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
895 int pci_add_dynid(struct pci_driver *drv,
896 unsigned int vendor, unsigned int device,
897 unsigned int subvendor, unsigned int subdevice,
898 unsigned int class, unsigned int class_mask,
899 unsigned long driver_data);
900 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
901 struct pci_dev *dev);
902 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
903 int pass);
904
905 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
906 void *userdata);
907 int pci_cfg_space_size_ext(struct pci_dev *dev);
908 int pci_cfg_space_size(struct pci_dev *dev);
909 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
910
911 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
912 unsigned int command_bits, bool change_bridge);
913 /* kmem_cache style wrapper around pci_alloc_consistent() */
914
915 #include <linux/pci-dma.h>
916 #include <linux/dmapool.h>
917
918 #define pci_pool dma_pool
919 #define pci_pool_create(name, pdev, size, align, allocation) \
920 dma_pool_create(name, &pdev->dev, size, align, allocation)
921 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
922 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
923 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
924
925 enum pci_dma_burst_strategy {
926 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
927 strategy_parameter is N/A */
928 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
929 byte boundaries */
930 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
931 strategy_parameter byte boundaries */
932 };
933
934 struct msix_entry {
935 u32 vector; /* kernel uses to write allocated vector */
936 u16 entry; /* driver uses to specify entry, OS writes */
937 };
938
939
940 #ifndef CONFIG_PCI_MSI
941 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
942 {
943 return -1;
944 }
945
946 static inline void pci_msi_shutdown(struct pci_dev *dev)
947 { }
948 static inline void pci_disable_msi(struct pci_dev *dev)
949 { }
950
951 static inline int pci_msix_table_size(struct pci_dev *dev)
952 {
953 return 0;
954 }
955 static inline int pci_enable_msix(struct pci_dev *dev,
956 struct msix_entry *entries, int nvec)
957 {
958 return -1;
959 }
960
961 static inline void pci_msix_shutdown(struct pci_dev *dev)
962 { }
963 static inline void pci_disable_msix(struct pci_dev *dev)
964 { }
965
966 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
967 { }
968
969 static inline void pci_restore_msi_state(struct pci_dev *dev)
970 { }
971 static inline int pci_msi_enabled(void)
972 {
973 return 0;
974 }
975 #else
976 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
977 extern void pci_msi_shutdown(struct pci_dev *dev);
978 extern void pci_disable_msi(struct pci_dev *dev);
979 extern int pci_msix_table_size(struct pci_dev *dev);
980 extern int pci_enable_msix(struct pci_dev *dev,
981 struct msix_entry *entries, int nvec);
982 extern void pci_msix_shutdown(struct pci_dev *dev);
983 extern void pci_disable_msix(struct pci_dev *dev);
984 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
985 extern void pci_restore_msi_state(struct pci_dev *dev);
986 extern int pci_msi_enabled(void);
987 #endif
988
989 #ifndef CONFIG_PCIEASPM
990 static inline int pcie_aspm_enabled(void)
991 {
992 return 0;
993 }
994 #else
995 extern int pcie_aspm_enabled(void);
996 #endif
997
998 #ifndef CONFIG_PCIE_ECRC
999 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1000 {
1001 return;
1002 }
1003 static inline void pcie_ecrc_get_policy(char *str) {};
1004 #else
1005 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1006 extern void pcie_ecrc_get_policy(char *str);
1007 #endif
1008
1009 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1010
1011 #ifdef CONFIG_HT_IRQ
1012 /* The functions a driver should call */
1013 int ht_create_irq(struct pci_dev *dev, int idx);
1014 void ht_destroy_irq(unsigned int irq);
1015 #endif /* CONFIG_HT_IRQ */
1016
1017 extern void pci_block_user_cfg_access(struct pci_dev *dev);
1018 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
1019
1020 /*
1021 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1022 * a PCI domain is defined to be a set of PCI busses which share
1023 * configuration space.
1024 */
1025 #ifdef CONFIG_PCI_DOMAINS
1026 extern int pci_domains_supported;
1027 #else
1028 enum { pci_domains_supported = 0 };
1029 static inline int pci_domain_nr(struct pci_bus *bus)
1030 {
1031 return 0;
1032 }
1033
1034 static inline int pci_proc_domain(struct pci_bus *bus)
1035 {
1036 return 0;
1037 }
1038 #endif /* CONFIG_PCI_DOMAINS */
1039
1040 /* some architectures require additional setup to direct VGA traffic */
1041 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1042 unsigned int command_bits, bool change_bridge);
1043 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1044
1045 #else /* CONFIG_PCI is not enabled */
1046
1047 /*
1048 * If the system does not have PCI, clearly these return errors. Define
1049 * these as simple inline functions to avoid hair in drivers.
1050 */
1051
1052 #define _PCI_NOP(o, s, t) \
1053 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1054 int where, t val) \
1055 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1056
1057 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1058 _PCI_NOP(o, word, u16 x) \
1059 _PCI_NOP(o, dword, u32 x)
1060 _PCI_NOP_ALL(read, *)
1061 _PCI_NOP_ALL(write,)
1062
1063 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1064 unsigned int device,
1065 struct pci_dev *from)
1066 {
1067 return NULL;
1068 }
1069
1070 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1071 unsigned int device,
1072 unsigned int ss_vendor,
1073 unsigned int ss_device,
1074 struct pci_dev *from)
1075 {
1076 return NULL;
1077 }
1078
1079 static inline struct pci_dev *pci_get_class(unsigned int class,
1080 struct pci_dev *from)
1081 {
1082 return NULL;
1083 }
1084
1085 #define pci_dev_present(ids) (0)
1086 #define no_pci_devices() (1)
1087 #define pci_dev_put(dev) do { } while (0)
1088
1089 static inline void pci_set_master(struct pci_dev *dev)
1090 { }
1091
1092 static inline int pci_enable_device(struct pci_dev *dev)
1093 {
1094 return -EIO;
1095 }
1096
1097 static inline void pci_disable_device(struct pci_dev *dev)
1098 { }
1099
1100 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1101 {
1102 return -EIO;
1103 }
1104
1105 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1106 {
1107 return -EIO;
1108 }
1109
1110 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1111 unsigned int size)
1112 {
1113 return -EIO;
1114 }
1115
1116 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1117 unsigned long mask)
1118 {
1119 return -EIO;
1120 }
1121
1122 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1123 {
1124 return -EBUSY;
1125 }
1126
1127 static inline int __pci_register_driver(struct pci_driver *drv,
1128 struct module *owner)
1129 {
1130 return 0;
1131 }
1132
1133 static inline int pci_register_driver(struct pci_driver *drv)
1134 {
1135 return 0;
1136 }
1137
1138 static inline void pci_unregister_driver(struct pci_driver *drv)
1139 { }
1140
1141 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1142 {
1143 return 0;
1144 }
1145
1146 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1147 int cap)
1148 {
1149 return 0;
1150 }
1151
1152 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1153 {
1154 return 0;
1155 }
1156
1157 /* Power management related routines */
1158 static inline int pci_save_state(struct pci_dev *dev)
1159 {
1160 return 0;
1161 }
1162
1163 static inline int pci_restore_state(struct pci_dev *dev)
1164 {
1165 return 0;
1166 }
1167
1168 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1169 {
1170 return 0;
1171 }
1172
1173 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1174 pm_message_t state)
1175 {
1176 return PCI_D0;
1177 }
1178
1179 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1180 int enable)
1181 {
1182 return 0;
1183 }
1184
1185 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1186 {
1187 return -EIO;
1188 }
1189
1190 static inline void pci_release_regions(struct pci_dev *dev)
1191 { }
1192
1193 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1194
1195 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1196 { }
1197
1198 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1199 { }
1200
1201 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1202 { return NULL; }
1203
1204 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1205 unsigned int devfn)
1206 { return NULL; }
1207
1208 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1209 unsigned int devfn)
1210 { return NULL; }
1211
1212 #define dev_is_pci(d) (false)
1213 #define dev_is_pf(d) (false)
1214 #define dev_num_vf(d) (0)
1215 #endif /* CONFIG_PCI */
1216
1217 /* Include architecture-dependent settings and functions */
1218
1219 #include <asm/pci.h>
1220
1221 #ifndef PCIBIOS_MAX_MEM_32
1222 #define PCIBIOS_MAX_MEM_32 (-1)
1223 #endif
1224
1225 /* these helpers provide future and backwards compatibility
1226 * for accessing popular PCI BAR info */
1227 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1228 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1229 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1230 #define pci_resource_len(dev,bar) \
1231 ((pci_resource_start((dev), (bar)) == 0 && \
1232 pci_resource_end((dev), (bar)) == \
1233 pci_resource_start((dev), (bar))) ? 0 : \
1234 \
1235 (pci_resource_end((dev), (bar)) - \
1236 pci_resource_start((dev), (bar)) + 1))
1237
1238 /* Similar to the helpers above, these manipulate per-pci_dev
1239 * driver-specific data. They are really just a wrapper around
1240 * the generic device structure functions of these calls.
1241 */
1242 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1243 {
1244 return dev_get_drvdata(&pdev->dev);
1245 }
1246
1247 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1248 {
1249 dev_set_drvdata(&pdev->dev, data);
1250 }
1251
1252 /* If you want to know what to call your pci_dev, ask this function.
1253 * Again, it's a wrapper around the generic device.
1254 */
1255 static inline const char *pci_name(const struct pci_dev *pdev)
1256 {
1257 return dev_name(&pdev->dev);
1258 }
1259
1260
1261 /* Some archs don't want to expose struct resource to userland as-is
1262 * in sysfs and /proc
1263 */
1264 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1265 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1266 const struct resource *rsrc, resource_size_t *start,
1267 resource_size_t *end)
1268 {
1269 *start = rsrc->start;
1270 *end = rsrc->end;
1271 }
1272 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1273
1274
1275 /*
1276 * The world is not perfect and supplies us with broken PCI devices.
1277 * For at least a part of these bugs we need a work-around, so both
1278 * generic (drivers/pci/quirks.c) and per-architecture code can define
1279 * fixup hooks to be called for particular buggy devices.
1280 */
1281
1282 struct pci_fixup {
1283 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1284 void (*hook)(struct pci_dev *dev);
1285 };
1286
1287 enum pci_fixup_pass {
1288 pci_fixup_early, /* Before probing BARs */
1289 pci_fixup_header, /* After reading configuration header */
1290 pci_fixup_final, /* Final phase of device fixups */
1291 pci_fixup_enable, /* pci_enable_device() time */
1292 pci_fixup_resume, /* pci_device_resume() */
1293 pci_fixup_suspend, /* pci_device_suspend */
1294 pci_fixup_resume_early, /* pci_device_resume_early() */
1295 };
1296
1297 /* Anonymous variables would be nice... */
1298 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1299 static const struct pci_fixup __pci_fixup_##name __used \
1300 __attribute__((__section__(#section))) = { vendor, device, hook };
1301 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1302 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1303 vendor##device##hook, vendor, device, hook)
1304 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1305 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1306 vendor##device##hook, vendor, device, hook)
1307 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1308 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1309 vendor##device##hook, vendor, device, hook)
1310 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1311 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1312 vendor##device##hook, vendor, device, hook)
1313 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1314 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1315 resume##vendor##device##hook, vendor, device, hook)
1316 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1317 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1318 resume_early##vendor##device##hook, vendor, device, hook)
1319 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1320 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1321 suspend##vendor##device##hook, vendor, device, hook)
1322
1323 #ifdef CONFIG_PCI_QUIRKS
1324 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1325 #else
1326 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1327 struct pci_dev *dev) {}
1328 #endif
1329
1330 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1331 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1332 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1333 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1334 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1335 const char *name);
1336 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1337
1338 extern int pci_pci_problems;
1339 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1340 #define PCIPCI_TRITON 2
1341 #define PCIPCI_NATOMA 4
1342 #define PCIPCI_VIAETBF 8
1343 #define PCIPCI_VSFX 16
1344 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1345 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1346
1347 extern unsigned long pci_cardbus_io_size;
1348 extern unsigned long pci_cardbus_mem_size;
1349 extern u8 __devinitdata pci_dfl_cache_line_size;
1350 extern u8 pci_cache_line_size;
1351
1352 extern unsigned long pci_hotplug_io_size;
1353 extern unsigned long pci_hotplug_mem_size;
1354
1355 int pcibios_add_platform_entries(struct pci_dev *dev);
1356 void pcibios_disable_device(struct pci_dev *dev);
1357 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1358 enum pcie_reset_state state);
1359
1360 #ifdef CONFIG_PCI_MMCONFIG
1361 extern void __init pci_mmcfg_early_init(void);
1362 extern void __init pci_mmcfg_late_init(void);
1363 #else
1364 static inline void pci_mmcfg_early_init(void) { }
1365 static inline void pci_mmcfg_late_init(void) { }
1366 #endif
1367
1368 int pci_ext_cfg_avail(struct pci_dev *dev);
1369
1370 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1371
1372 #ifdef CONFIG_PCI_IOV
1373 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1374 extern void pci_disable_sriov(struct pci_dev *dev);
1375 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1376 extern int pci_num_vf(struct pci_dev *dev);
1377 #else
1378 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1379 {
1380 return -ENODEV;
1381 }
1382 static inline void pci_disable_sriov(struct pci_dev *dev)
1383 {
1384 }
1385 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1386 {
1387 return IRQ_NONE;
1388 }
1389 static inline int pci_num_vf(struct pci_dev *dev)
1390 {
1391 return 0;
1392 }
1393 #endif
1394
1395 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1396 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1397 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1398 #endif
1399
1400 /**
1401 * pci_pcie_cap - get the saved PCIe capability offset
1402 * @dev: PCI device
1403 *
1404 * PCIe capability offset is calculated at PCI device initialization
1405 * time and saved in the data structure. This function returns saved
1406 * PCIe capability offset. Using this instead of pci_find_capability()
1407 * reduces unnecessary search in the PCI configuration space. If you
1408 * need to calculate PCIe capability offset from raw device for some
1409 * reasons, please use pci_find_capability() instead.
1410 */
1411 static inline int pci_pcie_cap(struct pci_dev *dev)
1412 {
1413 return dev->pcie_cap;
1414 }
1415
1416 /**
1417 * pci_is_pcie - check if the PCI device is PCI Express capable
1418 * @dev: PCI device
1419 *
1420 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1421 */
1422 static inline bool pci_is_pcie(struct pci_dev *dev)
1423 {
1424 return !!pci_pcie_cap(dev);
1425 }
1426
1427 void pci_request_acs(void);
1428
1429
1430 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1431 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1432
1433 /* Large Resource Data Type Tag Item Names */
1434 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1435 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1436 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1437
1438 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1439 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1440 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1441
1442 /* Small Resource Data Type Tag Item Names */
1443 #define PCI_VPD_STIN_END 0x78 /* End */
1444
1445 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1446
1447 #define PCI_VPD_SRDT_TIN_MASK 0x78
1448 #define PCI_VPD_SRDT_LEN_MASK 0x07
1449
1450 #define PCI_VPD_LRDT_TAG_SIZE 3
1451 #define PCI_VPD_SRDT_TAG_SIZE 1
1452
1453 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1454
1455 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1456 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1457 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1458
1459 /**
1460 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1461 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1462 *
1463 * Returns the extracted Large Resource Data Type length.
1464 */
1465 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1466 {
1467 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1468 }
1469
1470 /**
1471 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1472 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1473 *
1474 * Returns the extracted Small Resource Data Type length.
1475 */
1476 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1477 {
1478 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1479 }
1480
1481 /**
1482 * pci_vpd_info_field_size - Extracts the information field length
1483 * @lrdt: Pointer to the beginning of an information field header
1484 *
1485 * Returns the extracted information field length.
1486 */
1487 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1488 {
1489 return info_field[2];
1490 }
1491
1492 /**
1493 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1494 * @buf: Pointer to buffered vpd data
1495 * @off: The offset into the buffer at which to begin the search
1496 * @len: The length of the vpd buffer
1497 * @rdt: The Resource Data Type to search for
1498 *
1499 * Returns the index where the Resource Data Type was found or
1500 * -ENOENT otherwise.
1501 */
1502 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1503
1504 /**
1505 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1506 * @buf: Pointer to buffered vpd data
1507 * @off: The offset into the buffer at which to begin the search
1508 * @len: The length of the buffer area, relative to off, in which to search
1509 * @kw: The keyword to search for
1510 *
1511 * Returns the index where the information field keyword was found or
1512 * -ENOENT otherwise.
1513 */
1514 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1515 unsigned int len, const char *kw);
1516
1517 #endif /* __KERNEL__ */
1518 #endif /* LINUX_PCI_H */
AMDTP streaming driver for the Linux FireWire stack (Juju)