1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
4 #include <asm/asm-compat.h>
6 #define PPC_FEATURE_32 0x80000000
7 #define PPC_FEATURE_64 0x40000000
8 #define PPC_FEATURE_601_INSTR 0x20000000
9 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10 #define PPC_FEATURE_HAS_FPU 0x08000000
11 #define PPC_FEATURE_HAS_MMU 0x04000000
12 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
13 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14 #define PPC_FEATURE_HAS_SPE 0x00800000
15 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16 #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
17 #define PPC_FEATURE_NO_TB 0x00100000
18 #define PPC_FEATURE_POWER4 0x00080000
19 #define PPC_FEATURE_POWER5 0x00040000
20 #define PPC_FEATURE_POWER5_PLUS 0x00020000
21 #define PPC_FEATURE_CELL 0x00010000
22 #define PPC_FEATURE_BOOKE 0x00008000
23 #define PPC_FEATURE_SMT 0x00004000
24 #define PPC_FEATURE_ICACHE_SNOOP 0x00002000
25 #define PPC_FEATURE_ARCH_2_05 0x00001000
26 #define PPC_FEATURE_PA6T 0x00000800
27 #define PPC_FEATURE_HAS_DFP 0x00000400
28 #define PPC_FEATURE_POWER6_EXT 0x00000200
30 #define PPC_FEATURE_TRUE_LE 0x00000002
31 #define PPC_FEATURE_PPC_LE 0x00000001
36 /* This structure can grow, it's real size is used by head.S code
37 * via the mkdefs mechanism.
41 typedef void (*cpu_setup_t
)(unsigned long offset
, struct cpu_spec
* spec
);
42 typedef void (*cpu_restore_t
)(void);
44 enum powerpc_oprofile_type
{
45 PPC_OPROFILE_INVALID
= 0,
46 PPC_OPROFILE_RS64
= 1,
47 PPC_OPROFILE_POWER4
= 2,
49 PPC_OPROFILE_BOOKE
= 4,
50 PPC_OPROFILE_CELL
= 5,
51 PPC_OPROFILE_PA6T
= 6,
54 enum powerpc_pmc_type
{
60 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
62 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
63 unsigned int pvr_mask
;
64 unsigned int pvr_value
;
67 unsigned long cpu_features
; /* Kernel features */
68 unsigned int cpu_user_features
; /* Userland features */
70 /* cache line sizes */
71 unsigned int icache_bsize
;
72 unsigned int dcache_bsize
;
74 /* number of performance monitor counters */
75 unsigned int num_pmcs
;
76 enum powerpc_pmc_type pmc_type
;
78 /* this is called to initialize various CPU bits like L1 cache,
79 * BHT, SPD, etc... from head.S before branching to identify_machine
81 cpu_setup_t cpu_setup
;
82 /* Used to restore cpu setup on secondary processors and at resume */
83 cpu_restore_t cpu_restore
;
85 /* Used by oprofile userspace to select the right counters */
86 char *oprofile_cpu_type
;
88 /* Processor specific oprofile operations */
89 enum powerpc_oprofile_type oprofile_type
;
91 /* Bit locations inside the mmcra change */
92 unsigned long oprofile_mmcra_sihv
;
93 unsigned long oprofile_mmcra_sipr
;
95 /* Bits to clear during an oprofile exception */
96 unsigned long oprofile_mmcra_clear
;
98 /* Name of processor class, for the ELF AT_PLATFORM entry */
102 extern struct cpu_spec
*cur_cpu_spec
;
104 extern unsigned int __start___ftr_fixup
, __stop___ftr_fixup
;
106 extern struct cpu_spec
*identify_cpu(unsigned long offset
, unsigned int pvr
);
107 extern void do_feature_fixups(unsigned long value
, void *fixup_start
,
110 #endif /* __ASSEMBLY__ */
112 /* CPU kernel features */
114 /* Retain the 32b definitions all use bottom half of word */
115 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
116 #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
117 #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
118 #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
119 #define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
120 #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
121 #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
122 #define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
123 #define CPU_FTR_601 ASM_CONST(0x0000000000000100)
124 #define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
125 #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
126 #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
127 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
128 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
129 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
130 #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
131 #define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
132 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
133 #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
134 #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
135 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
136 #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
137 #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
138 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
139 #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
140 #define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
143 * Add the 64-bit processor unique features in the top half of the word;
144 * on 32-bit, make the names available but defined to be 0.
147 #define LONG_ASM_CONST(x) ASM_CONST(x)
149 #define LONG_ASM_CONST(x) 0
152 #define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
153 #define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
154 #define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
155 #define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
156 #define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
157 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
158 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
159 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
160 #define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
161 #define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
162 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
163 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
164 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
165 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
166 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
167 #define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
168 #define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
172 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
173 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
174 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
176 /* We only set the altivec features if the kernel was compiled with altivec
179 #ifdef CONFIG_ALTIVEC
180 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
181 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
183 #define CPU_FTR_ALTIVEC_COMP 0
184 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
187 /* We only set the spe features if the kernel was compiled with spe
191 #define CPU_FTR_SPE_COMP CPU_FTR_SPE
192 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
193 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
194 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
196 #define CPU_FTR_SPE_COMP 0
197 #define PPC_FEATURE_HAS_SPE_COMP 0
198 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
199 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
202 /* We need to mark all pages as being coherent if we're SMP or we have a
203 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
204 * require it for PCI "streaming/prefetch" to work properly.
206 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
207 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
208 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
210 #define CPU_FTR_COMMON 0
213 /* The powersave features NAP & DOZE seems to confuse BDI when
214 debugging. So if a BDI is used, disable theses
216 #ifndef CONFIG_BDI_SWITCH
217 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
218 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
220 #define CPU_FTR_MAYBE_CAN_DOZE 0
221 #define CPU_FTR_MAYBE_CAN_NAP 0
224 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
225 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
226 !defined(CONFIG_BOOKE))
228 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
229 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
230 #define CPU_FTRS_603 (CPU_FTR_COMMON | \
231 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
232 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
233 #define CPU_FTRS_604 (CPU_FTR_COMMON | \
234 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
236 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
237 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
238 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
239 #define CPU_FTRS_740 (CPU_FTR_COMMON | \
240 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
241 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
243 #define CPU_FTRS_750 (CPU_FTR_COMMON | \
244 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
245 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
247 #define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
248 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
249 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
250 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
251 CPU_FTR_HAS_HIGH_BATS)
252 #define CPU_FTRS_750GX (CPU_FTRS_750FX)
253 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
254 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
255 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
256 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
257 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \
258 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
259 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
260 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
261 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
262 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
263 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
264 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
265 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
267 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
268 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
269 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
270 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
271 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
273 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
274 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
275 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
276 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
278 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
279 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
280 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
281 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
283 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
284 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
285 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
286 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
287 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \
289 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
290 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
291 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
292 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
293 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
295 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
296 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
297 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
298 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
299 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \
301 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
302 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
303 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
304 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
305 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \
307 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
308 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
309 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
310 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
311 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \
313 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
314 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
315 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
317 #define CPU_FTRS_82XX (CPU_FTR_COMMON | \
318 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
319 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
320 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
321 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
322 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
324 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
325 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
326 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
327 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \
328 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
329 #define CPU_FTRS_8XX (CPU_FTR_USE_TB)
330 #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
331 #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
332 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
333 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
334 CPU_FTR_UNIFIED_ID_CACHE)
335 #define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
336 CPU_FTR_NODSISRALIGN)
337 #define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
338 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
339 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
342 #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
343 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
344 #define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
345 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
346 CPU_FTR_MMCRA | CPU_FTR_CTRL)
347 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
348 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
350 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
351 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
352 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
353 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
354 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
355 CPU_FTR_MMCRA | CPU_FTR_SMT | \
356 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
358 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
359 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
360 CPU_FTR_MMCRA | CPU_FTR_SMT | \
361 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
362 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
364 #define CPU_FTRS_CELL (CPU_FTR_USE_TB | \
365 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
366 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
367 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
368 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
369 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
370 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
371 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
372 #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
373 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
376 #define CPU_FTRS_POSSIBLE \
377 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
378 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
379 CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_1T_SEGMENT)
384 CPU_FTRS_PPC601
| CPU_FTRS_603
| CPU_FTRS_604
| CPU_FTRS_740_NOTAU
|
385 CPU_FTRS_740
| CPU_FTRS_750
| CPU_FTRS_750FX1
|
386 CPU_FTRS_750FX2
| CPU_FTRS_750FX
| CPU_FTRS_750GX
|
387 CPU_FTRS_7400_NOTAU
| CPU_FTRS_7400
| CPU_FTRS_7450_20
|
388 CPU_FTRS_7450_21
| CPU_FTRS_7450_23
| CPU_FTRS_7455_1
|
389 CPU_FTRS_7455_20
| CPU_FTRS_7455
| CPU_FTRS_7447_10
|
390 CPU_FTRS_7447
| CPU_FTRS_7447A
| CPU_FTRS_82XX
|
391 CPU_FTRS_G2_LE
| CPU_FTRS_E300
| CPU_FTRS_E300C2
|
394 CPU_FTRS_GENERIC_32
|
409 CPU_FTRS_E500
| CPU_FTRS_E500_2
|
413 #endif /* __powerpc64__ */
416 #define CPU_FTRS_ALWAYS \
417 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
418 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
419 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
424 CPU_FTRS_PPC601
& CPU_FTRS_603
& CPU_FTRS_604
& CPU_FTRS_740_NOTAU
&
425 CPU_FTRS_740
& CPU_FTRS_750
& CPU_FTRS_750FX1
&
426 CPU_FTRS_750FX2
& CPU_FTRS_750FX
& CPU_FTRS_750GX
&
427 CPU_FTRS_7400_NOTAU
& CPU_FTRS_7400
& CPU_FTRS_7450_20
&
428 CPU_FTRS_7450_21
& CPU_FTRS_7450_23
& CPU_FTRS_7455_1
&
429 CPU_FTRS_7455_20
& CPU_FTRS_7455
& CPU_FTRS_7447_10
&
430 CPU_FTRS_7447
& CPU_FTRS_7447A
& CPU_FTRS_82XX
&
431 CPU_FTRS_G2_LE
& CPU_FTRS_E300
& CPU_FTRS_E300C2
&
434 CPU_FTRS_GENERIC_32
&
449 CPU_FTRS_E500
& CPU_FTRS_E500_2
&
453 #endif /* __powerpc64__ */
455 static inline int cpu_has_feature(unsigned long feature
)
457 return (CPU_FTRS_ALWAYS
& feature
) ||
459 & cur_cpu_spec
->cpu_features
463 #endif /* !__ASSEMBLY__ */
467 #define BEGIN_FTR_SECTION_NESTED(label) label:
468 #define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97)
469 #define END_FTR_SECTION_NESTED(msk, val, label) \
470 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
471 #define END_FTR_SECTION(msk, val) \
472 END_FTR_SECTION_NESTED(msk, val, 97)
474 #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
475 #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
476 #endif /* __ASSEMBLY__ */
478 #endif /* __KERNEL__ */
479 #endif /* __ASM_POWERPC_CPUTABLE_H */