2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through platform_device. Structures which
29 * define the configuration needed by the board are defined in a
30 * board structure in arch/ppc/platforms (though I do not
31 * discount the possibility that other architectures could one
34 * The Gianfar Ethernet Controller uses a ring of buffer
35 * descriptors. The beginning is indicated by a register
36 * pointing to the physical address of the start of the ring.
37 * The end is determined by a "wrap" bit being set in the
38 * last descriptor of the ring.
40 * When a packet is received, the RXF bit in the
41 * IEVENT register is set, triggering an interrupt when the
42 * corresponding bit in the IMASK register is also set (if
43 * interrupt coalescing is active, then the interrupt may not
44 * happen immediately, but will wait until either a set number
45 * of frames or amount of time have passed). In NAPI, the
46 * interrupt handler will signal there is work to be done, and
47 * exit. Without NAPI, the packet(s) will be handled
48 * immediately. Both methods will start at the last known empty
49 * descriptor, and process every subsequent descriptor until there
50 * are none left with data (NAPI will stop after a set number of
51 * packets to give time to other tasks, but will eventually
52 * process all the packets). The data arrives inside a
53 * pre-allocated skb, and so after the skb is passed up to the
54 * stack, a new skb must be allocated, and the address field in
55 * the buffer descriptor must be updated to indicate this new
58 * When the kernel requests that a packet be transmitted, the
59 * driver starts where it left off last time, and points the
60 * descriptor at the buffer which was passed in. The driver
61 * then informs the DMA engine that there are packets ready to
62 * be transmitted. Once the controller is finished transmitting
63 * the packet, an interrupt may be triggered (under the same
64 * conditions as for reception, but depending on the TXF bit).
65 * The driver then cleans up the buffer.
68 #include <linux/kernel.h>
69 #include <linux/string.h>
70 #include <linux/errno.h>
71 #include <linux/unistd.h>
72 #include <linux/slab.h>
73 #include <linux/interrupt.h>
74 #include <linux/init.h>
75 #include <linux/delay.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_vlan.h>
80 #include <linux/spinlock.h>
82 #include <linux/platform_device.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
90 #include <asm/uaccess.h>
91 #include <linux/module.h>
92 #include <linux/dma-mapping.h>
93 #include <linux/crc32.h>
94 #include <linux/mii.h>
95 #include <linux/phy.h>
98 #include "gianfar_mii.h"
100 #define TX_TIMEOUT (1*HZ)
101 #undef BRIEF_GFAR_ERRORS
102 #undef VERBOSE_GFAR_ERRORS
104 #ifdef CONFIG_GFAR_NAPI
105 #define RECEIVE(x) netif_receive_skb(x)
107 #define RECEIVE(x) netif_rx(x)
110 const char gfar_driver_name
[] = "Gianfar Ethernet";
111 const char gfar_driver_version
[] = "1.3";
113 static int gfar_enet_open(struct net_device
*dev
);
114 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
115 static void gfar_timeout(struct net_device
*dev
);
116 static int gfar_close(struct net_device
*dev
);
117 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
118 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
119 struct sk_buff
*skb
);
120 static int gfar_set_mac_address(struct net_device
*dev
);
121 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
122 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
123 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
124 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
125 static void adjust_link(struct net_device
*dev
);
126 static void init_registers(struct net_device
*dev
);
127 static int init_phy(struct net_device
*dev
);
128 static int gfar_probe(struct platform_device
*pdev
);
129 static int gfar_remove(struct platform_device
*pdev
);
130 static void free_skb_resources(struct gfar_private
*priv
);
131 static void gfar_set_multi(struct net_device
*dev
);
132 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
133 static void gfar_configure_serdes(struct net_device
*dev
);
134 #ifdef CONFIG_GFAR_NAPI
135 static int gfar_poll(struct napi_struct
*napi
, int budget
);
137 #ifdef CONFIG_NET_POLL_CONTROLLER
138 static void gfar_netpoll(struct net_device
*dev
);
140 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
141 static int gfar_clean_tx_ring(struct net_device
*dev
);
142 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
, int length
);
143 static void gfar_vlan_rx_register(struct net_device
*netdev
,
144 struct vlan_group
*grp
);
145 void gfar_halt(struct net_device
*dev
);
146 void gfar_start(struct net_device
*dev
);
147 static void gfar_clear_exact_match(struct net_device
*dev
);
148 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
150 extern const struct ethtool_ops gfar_ethtool_ops
;
152 MODULE_AUTHOR("Freescale Semiconductor, Inc");
153 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
154 MODULE_LICENSE("GPL");
156 /* Returns 1 if incoming frames use an FCB */
157 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
159 return (priv
->vlan_enable
|| priv
->rx_csum_enable
);
162 /* Set up the ethernet device structure, private data,
163 * and anything else we need before we start */
164 static int gfar_probe(struct platform_device
*pdev
)
167 struct net_device
*dev
= NULL
;
168 struct gfar_private
*priv
= NULL
;
169 struct gianfar_platform_data
*einfo
;
172 DECLARE_MAC_BUF(mac
);
174 einfo
= (struct gianfar_platform_data
*) pdev
->dev
.platform_data
;
177 printk(KERN_ERR
"gfar %d: Missing additional data!\n",
183 /* Create an ethernet device instance */
184 dev
= alloc_etherdev(sizeof (*priv
));
189 priv
= netdev_priv(dev
);
192 /* Set the info in the priv to the current info */
195 /* fill out IRQ fields */
196 if (einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
197 priv
->interruptTransmit
= platform_get_irq_byname(pdev
, "tx");
198 priv
->interruptReceive
= platform_get_irq_byname(pdev
, "rx");
199 priv
->interruptError
= platform_get_irq_byname(pdev
, "error");
200 if (priv
->interruptTransmit
< 0 || priv
->interruptReceive
< 0 || priv
->interruptError
< 0)
203 priv
->interruptTransmit
= platform_get_irq(pdev
, 0);
204 if (priv
->interruptTransmit
< 0)
208 /* get a pointer to the register memory */
209 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
210 priv
->regs
= ioremap(r
->start
, sizeof (struct gfar
));
212 if (NULL
== priv
->regs
) {
217 spin_lock_init(&priv
->txlock
);
218 spin_lock_init(&priv
->rxlock
);
220 platform_set_drvdata(pdev
, dev
);
222 /* Stop the DMA engine now, in case it was running before */
223 /* (The firmware could have used it, and left it running). */
224 /* To do this, we write Graceful Receive Stop and Graceful */
225 /* Transmit Stop, and then wait until the corresponding bits */
226 /* in IEVENT indicate the stops have completed. */
227 tempval
= gfar_read(&priv
->regs
->dmactrl
);
228 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
229 gfar_write(&priv
->regs
->dmactrl
, tempval
);
231 tempval
= gfar_read(&priv
->regs
->dmactrl
);
232 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
233 gfar_write(&priv
->regs
->dmactrl
, tempval
);
235 while (!(gfar_read(&priv
->regs
->ievent
) & (IEVENT_GRSC
| IEVENT_GTSC
)))
238 /* Reset MAC layer */
239 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
241 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
242 gfar_write(&priv
->regs
->maccfg1
, tempval
);
244 /* Initialize MACCFG2. */
245 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
247 /* Initialize ECNTRL */
248 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
250 /* Copy the station address into the dev structure, */
251 memcpy(dev
->dev_addr
, einfo
->mac_addr
, MAC_ADDR_LEN
);
253 /* Set the dev->base_addr to the gfar reg region */
254 dev
->base_addr
= (unsigned long) (priv
->regs
);
256 SET_NETDEV_DEV(dev
, &pdev
->dev
);
258 /* Fill in the dev structure */
259 dev
->open
= gfar_enet_open
;
260 dev
->hard_start_xmit
= gfar_start_xmit
;
261 dev
->tx_timeout
= gfar_timeout
;
262 dev
->watchdog_timeo
= TX_TIMEOUT
;
263 #ifdef CONFIG_GFAR_NAPI
264 netif_napi_add(dev
, &priv
->napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
266 #ifdef CONFIG_NET_POLL_CONTROLLER
267 dev
->poll_controller
= gfar_netpoll
;
269 dev
->stop
= gfar_close
;
270 dev
->change_mtu
= gfar_change_mtu
;
272 dev
->set_multicast_list
= gfar_set_multi
;
274 dev
->ethtool_ops
= &gfar_ethtool_ops
;
276 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
277 priv
->rx_csum_enable
= 1;
278 dev
->features
|= NETIF_F_IP_CSUM
;
280 priv
->rx_csum_enable
= 0;
284 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
285 dev
->vlan_rx_register
= gfar_vlan_rx_register
;
287 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
289 priv
->vlan_enable
= 1;
292 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
293 priv
->extended_hash
= 1;
294 priv
->hash_width
= 9;
296 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
297 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
298 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
299 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
300 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
301 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
302 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
303 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
304 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
305 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
306 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
307 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
308 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
309 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
310 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
311 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
314 priv
->extended_hash
= 0;
315 priv
->hash_width
= 8;
317 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
318 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
319 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
320 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
321 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
322 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
323 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
324 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
327 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
328 priv
->padding
= DEFAULT_PADDING
;
332 if (dev
->features
& NETIF_F_IP_CSUM
)
333 dev
->hard_header_len
+= GMAC_FCB_LEN
;
335 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
336 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
337 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
339 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
340 priv
->txcount
= DEFAULT_TXCOUNT
;
341 priv
->txtime
= DEFAULT_TXTIME
;
342 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
343 priv
->rxcount
= DEFAULT_RXCOUNT
;
344 priv
->rxtime
= DEFAULT_RXTIME
;
346 /* Enable most messages by default */
347 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
349 err
= register_netdev(dev
);
352 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
357 /* Create all the sysfs files */
358 gfar_init_sysfs(dev
);
360 /* Print out the device info */
361 printk(KERN_INFO DEVICE_NAME
"%s\n",
362 dev
->name
, print_mac(mac
, dev
->dev_addr
));
364 /* Even more device info helps when determining which kernel */
365 /* provided which set of benchmarks. */
366 #ifdef CONFIG_GFAR_NAPI
367 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
369 printk(KERN_INFO
"%s: Running with NAPI disabled\n", dev
->name
);
371 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
372 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
383 static int gfar_remove(struct platform_device
*pdev
)
385 struct net_device
*dev
= platform_get_drvdata(pdev
);
386 struct gfar_private
*priv
= netdev_priv(dev
);
388 platform_set_drvdata(pdev
, NULL
);
397 /* Reads the controller's registers to determine what interface
398 * connects it to the PHY.
400 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
402 struct gfar_private
*priv
= netdev_priv(dev
);
403 u32 ecntrl
= gfar_read(&priv
->regs
->ecntrl
);
405 if (ecntrl
& ECNTRL_SGMII_MODE
)
406 return PHY_INTERFACE_MODE_SGMII
;
408 if (ecntrl
& ECNTRL_TBI_MODE
) {
409 if (ecntrl
& ECNTRL_REDUCED_MODE
)
410 return PHY_INTERFACE_MODE_RTBI
;
412 return PHY_INTERFACE_MODE_TBI
;
415 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
416 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
417 return PHY_INTERFACE_MODE_RMII
;
419 phy_interface_t interface
= priv
->einfo
->interface
;
422 * This isn't autodetected right now, so it must
423 * be set by the device tree or platform code.
425 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
426 return PHY_INTERFACE_MODE_RGMII_ID
;
428 return PHY_INTERFACE_MODE_RGMII
;
432 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
433 return PHY_INTERFACE_MODE_GMII
;
435 return PHY_INTERFACE_MODE_MII
;
439 /* Initializes driver's PHY state, and attaches to the PHY.
440 * Returns 0 on success.
442 static int init_phy(struct net_device
*dev
)
444 struct gfar_private
*priv
= netdev_priv(dev
);
445 uint gigabit_support
=
446 priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
447 SUPPORTED_1000baseT_Full
: 0;
448 struct phy_device
*phydev
;
449 char phy_id
[BUS_ID_SIZE
];
450 phy_interface_t interface
;
454 priv
->oldduplex
= -1;
456 snprintf(phy_id
, BUS_ID_SIZE
, PHY_ID_FMT
, priv
->einfo
->bus_id
, priv
->einfo
->phy_id
);
458 interface
= gfar_get_interface(dev
);
460 phydev
= phy_connect(dev
, phy_id
, &adjust_link
, 0, interface
);
462 if (interface
== PHY_INTERFACE_MODE_SGMII
)
463 gfar_configure_serdes(dev
);
465 if (IS_ERR(phydev
)) {
466 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
467 return PTR_ERR(phydev
);
470 /* Remove any features not supported by the controller */
471 phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
472 phydev
->advertising
= phydev
->supported
;
474 priv
->phydev
= phydev
;
480 * Initialize TBI PHY interface for communicating with the
481 * SERDES lynx PHY on the chip. We communicate with this PHY
482 * through the MDIO bus on each controller, treating it as a
483 * "normal" PHY at the address found in the TBIPA register. We assume
484 * that the TBIPA register is valid. Either the MDIO bus code will set
485 * it to a value that doesn't conflict with other PHYs on the bus, or the
486 * value doesn't matter, as there are no other PHYs on the bus.
488 static void gfar_configure_serdes(struct net_device
*dev
)
490 struct gfar_private
*priv
= netdev_priv(dev
);
491 struct gfar_mii __iomem
*regs
=
492 (void __iomem
*)&priv
->regs
->gfar_mii_regs
;
493 int tbipa
= gfar_read(&priv
->regs
->tbipa
);
495 /* Single clk mode, mii mode off(for serdes communication) */
496 gfar_local_mdio_write(regs
, tbipa
, MII_TBICON
, TBICON_CLK_SELECT
);
498 gfar_local_mdio_write(regs
, tbipa
, MII_ADVERTISE
,
499 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
500 ADVERTISE_1000XPSE_ASYM
);
502 gfar_local_mdio_write(regs
, tbipa
, MII_BMCR
, BMCR_ANENABLE
|
503 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
506 static void init_registers(struct net_device
*dev
)
508 struct gfar_private
*priv
= netdev_priv(dev
);
511 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
513 /* Initialize IMASK */
514 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
516 /* Init hash registers to zero */
517 gfar_write(&priv
->regs
->igaddr0
, 0);
518 gfar_write(&priv
->regs
->igaddr1
, 0);
519 gfar_write(&priv
->regs
->igaddr2
, 0);
520 gfar_write(&priv
->regs
->igaddr3
, 0);
521 gfar_write(&priv
->regs
->igaddr4
, 0);
522 gfar_write(&priv
->regs
->igaddr5
, 0);
523 gfar_write(&priv
->regs
->igaddr6
, 0);
524 gfar_write(&priv
->regs
->igaddr7
, 0);
526 gfar_write(&priv
->regs
->gaddr0
, 0);
527 gfar_write(&priv
->regs
->gaddr1
, 0);
528 gfar_write(&priv
->regs
->gaddr2
, 0);
529 gfar_write(&priv
->regs
->gaddr3
, 0);
530 gfar_write(&priv
->regs
->gaddr4
, 0);
531 gfar_write(&priv
->regs
->gaddr5
, 0);
532 gfar_write(&priv
->regs
->gaddr6
, 0);
533 gfar_write(&priv
->regs
->gaddr7
, 0);
535 /* Zero out the rmon mib registers if it has them */
536 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
537 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
539 /* Mask off the CAM interrupts */
540 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
541 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
544 /* Initialize the max receive buffer length */
545 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
547 /* Initialize the Minimum Frame Length Register */
548 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
552 /* Halt the receive and transmit queues */
553 void gfar_halt(struct net_device
*dev
)
555 struct gfar_private
*priv
= netdev_priv(dev
);
556 struct gfar __iomem
*regs
= priv
->regs
;
559 /* Mask all interrupts */
560 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
562 /* Clear all interrupts */
563 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
565 /* Stop the DMA, and wait for it to stop */
566 tempval
= gfar_read(&priv
->regs
->dmactrl
);
567 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
568 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
569 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
570 gfar_write(&priv
->regs
->dmactrl
, tempval
);
572 while (!(gfar_read(&priv
->regs
->ievent
) &
573 (IEVENT_GRSC
| IEVENT_GTSC
)))
577 /* Disable Rx and Tx */
578 tempval
= gfar_read(®s
->maccfg1
);
579 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
580 gfar_write(®s
->maccfg1
, tempval
);
583 void stop_gfar(struct net_device
*dev
)
585 struct gfar_private
*priv
= netdev_priv(dev
);
586 struct gfar __iomem
*regs
= priv
->regs
;
589 phy_stop(priv
->phydev
);
592 spin_lock_irqsave(&priv
->txlock
, flags
);
593 spin_lock(&priv
->rxlock
);
597 spin_unlock(&priv
->rxlock
);
598 spin_unlock_irqrestore(&priv
->txlock
, flags
);
601 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
602 free_irq(priv
->interruptError
, dev
);
603 free_irq(priv
->interruptTransmit
, dev
);
604 free_irq(priv
->interruptReceive
, dev
);
606 free_irq(priv
->interruptTransmit
, dev
);
609 free_skb_resources(priv
);
611 dma_free_coherent(&dev
->dev
,
612 sizeof(struct txbd8
)*priv
->tx_ring_size
613 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
615 gfar_read(®s
->tbase0
));
618 /* If there are any tx skbs or rx skbs still around, free them.
619 * Then free tx_skbuff and rx_skbuff */
620 static void free_skb_resources(struct gfar_private
*priv
)
626 /* Go through all the buffer descriptors and free their data buffers */
627 txbdp
= priv
->tx_bd_base
;
629 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
631 if (priv
->tx_skbuff
[i
]) {
632 dma_unmap_single(&priv
->dev
->dev
, txbdp
->bufPtr
,
635 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
636 priv
->tx_skbuff
[i
] = NULL
;
640 kfree(priv
->tx_skbuff
);
642 rxbdp
= priv
->rx_bd_base
;
644 /* rx_skbuff is not guaranteed to be allocated, so only
645 * free it and its contents if it is allocated */
646 if(priv
->rx_skbuff
!= NULL
) {
647 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
648 if (priv
->rx_skbuff
[i
]) {
649 dma_unmap_single(&priv
->dev
->dev
, rxbdp
->bufPtr
,
650 priv
->rx_buffer_size
,
653 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
654 priv
->rx_skbuff
[i
] = NULL
;
664 kfree(priv
->rx_skbuff
);
668 void gfar_start(struct net_device
*dev
)
670 struct gfar_private
*priv
= netdev_priv(dev
);
671 struct gfar __iomem
*regs
= priv
->regs
;
674 /* Enable Rx and Tx in MACCFG1 */
675 tempval
= gfar_read(®s
->maccfg1
);
676 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
677 gfar_write(®s
->maccfg1
, tempval
);
679 /* Initialize DMACTRL to have WWR and WOP */
680 tempval
= gfar_read(&priv
->regs
->dmactrl
);
681 tempval
|= DMACTRL_INIT_SETTINGS
;
682 gfar_write(&priv
->regs
->dmactrl
, tempval
);
684 /* Make sure we aren't stopped */
685 tempval
= gfar_read(&priv
->regs
->dmactrl
);
686 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
687 gfar_write(&priv
->regs
->dmactrl
, tempval
);
689 /* Clear THLT/RHLT, so that the DMA starts polling now */
690 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
691 gfar_write(®s
->rstat
, RSTAT_CLEAR_RHALT
);
693 /* Unmask the interrupts we look for */
694 gfar_write(®s
->imask
, IMASK_DEFAULT
);
697 /* Bring the controller up and running */
698 int startup_gfar(struct net_device
*dev
)
705 struct gfar_private
*priv
= netdev_priv(dev
);
706 struct gfar __iomem
*regs
= priv
->regs
;
711 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
713 /* Allocate memory for the buffer descriptors */
714 vaddr
= (unsigned long) dma_alloc_coherent(&dev
->dev
,
715 sizeof (struct txbd8
) * priv
->tx_ring_size
+
716 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
720 if (netif_msg_ifup(priv
))
721 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
726 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
728 /* enet DMA only understands physical addresses */
729 gfar_write(®s
->tbase0
, addr
);
731 /* Start the rx descriptor ring where the tx ring leaves off */
732 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
733 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
734 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
735 gfar_write(®s
->rbase0
, addr
);
737 /* Setup the skbuff rings */
739 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
740 priv
->tx_ring_size
, GFP_KERNEL
);
742 if (NULL
== priv
->tx_skbuff
) {
743 if (netif_msg_ifup(priv
))
744 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
750 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
751 priv
->tx_skbuff
[i
] = NULL
;
754 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
755 priv
->rx_ring_size
, GFP_KERNEL
);
757 if (NULL
== priv
->rx_skbuff
) {
758 if (netif_msg_ifup(priv
))
759 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
765 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
766 priv
->rx_skbuff
[i
] = NULL
;
768 /* Initialize some variables in our dev structure */
769 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
770 priv
->cur_rx
= priv
->rx_bd_base
;
771 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
774 /* Initialize Transmit Descriptor Ring */
775 txbdp
= priv
->tx_bd_base
;
776 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
783 /* Set the last descriptor in the ring to indicate wrap */
785 txbdp
->status
|= TXBD_WRAP
;
787 rxbdp
= priv
->rx_bd_base
;
788 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
791 skb
= gfar_new_skb(dev
);
794 printk(KERN_ERR
"%s: Can't allocate RX buffers\n",
797 goto err_rxalloc_fail
;
800 priv
->rx_skbuff
[i
] = skb
;
802 gfar_new_rxbdp(dev
, rxbdp
, skb
);
807 /* Set the last descriptor in the ring to wrap */
809 rxbdp
->status
|= RXBD_WRAP
;
811 /* If the device has multiple interrupts, register for
812 * them. Otherwise, only register for the one */
813 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
814 /* Install our interrupt handlers for Error,
815 * Transmit, and Receive */
816 if (request_irq(priv
->interruptError
, gfar_error
,
817 0, "enet_error", dev
) < 0) {
818 if (netif_msg_intr(priv
))
819 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
820 dev
->name
, priv
->interruptError
);
826 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
827 0, "enet_tx", dev
) < 0) {
828 if (netif_msg_intr(priv
))
829 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
830 dev
->name
, priv
->interruptTransmit
);
837 if (request_irq(priv
->interruptReceive
, gfar_receive
,
838 0, "enet_rx", dev
) < 0) {
839 if (netif_msg_intr(priv
))
840 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
841 dev
->name
, priv
->interruptReceive
);
847 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
848 0, "gfar_interrupt", dev
) < 0) {
849 if (netif_msg_intr(priv
))
850 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
851 dev
->name
, priv
->interruptError
);
858 phy_start(priv
->phydev
);
860 /* Configure the coalescing support */
861 if (priv
->txcoalescing
)
862 gfar_write(®s
->txic
,
863 mk_ic_value(priv
->txcount
, priv
->txtime
));
865 gfar_write(®s
->txic
, 0);
867 if (priv
->rxcoalescing
)
868 gfar_write(®s
->rxic
,
869 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
871 gfar_write(®s
->rxic
, 0);
873 if (priv
->rx_csum_enable
)
874 rctrl
|= RCTRL_CHECKSUMMING
;
876 if (priv
->extended_hash
) {
877 rctrl
|= RCTRL_EXTHASH
;
879 gfar_clear_exact_match(dev
);
883 if (priv
->vlan_enable
)
887 rctrl
&= ~RCTRL_PAL_MASK
;
888 rctrl
|= RCTRL_PADDING(priv
->padding
);
891 /* Init rctrl based on our settings */
892 gfar_write(&priv
->regs
->rctrl
, rctrl
);
894 if (dev
->features
& NETIF_F_IP_CSUM
)
895 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
897 /* Set the extraction length and index */
898 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
899 ATTRELI_EI(priv
->rx_stash_index
);
901 gfar_write(&priv
->regs
->attreli
, attrs
);
903 /* Start with defaults, and add stashing or locking
904 * depending on the approprate variables */
905 attrs
= ATTR_INIT_SETTINGS
;
907 if (priv
->bd_stash_en
)
908 attrs
|= ATTR_BDSTASH
;
910 if (priv
->rx_stash_size
!= 0)
911 attrs
|= ATTR_BUFSTASH
;
913 gfar_write(&priv
->regs
->attr
, attrs
);
915 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
916 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
917 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
919 /* Start the controller */
925 free_irq(priv
->interruptTransmit
, dev
);
927 free_irq(priv
->interruptError
, dev
);
931 free_skb_resources(priv
);
933 dma_free_coherent(&dev
->dev
,
934 sizeof(struct txbd8
)*priv
->tx_ring_size
935 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
937 gfar_read(®s
->tbase0
));
942 /* Called when something needs to use the ethernet device */
943 /* Returns 0 for success. */
944 static int gfar_enet_open(struct net_device
*dev
)
946 #ifdef CONFIG_GFAR_NAPI
947 struct gfar_private
*priv
= netdev_priv(dev
);
951 #ifdef CONFIG_GFAR_NAPI
952 napi_enable(&priv
->napi
);
955 /* Initialize a bunch of registers */
958 gfar_set_mac_address(dev
);
963 #ifdef CONFIG_GFAR_NAPI
964 napi_disable(&priv
->napi
);
969 err
= startup_gfar(dev
);
971 #ifdef CONFIG_GFAR_NAPI
972 napi_disable(&priv
->napi
);
977 netif_start_queue(dev
);
982 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
, struct txbd8
*bdp
)
984 struct txfcb
*fcb
= (struct txfcb
*)skb_push (skb
, GMAC_FCB_LEN
);
986 memset(fcb
, 0, GMAC_FCB_LEN
);
991 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
995 /* If we're here, it's a IP packet with a TCP or UDP
996 * payload. We set it to checksum, using a pseudo-header
999 flags
= TXFCB_DEFAULT
;
1001 /* Tell the controller what the protocol is */
1002 /* And provide the already calculated phcs */
1003 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
1005 fcb
->phcs
= udp_hdr(skb
)->check
;
1007 fcb
->phcs
= tcp_hdr(skb
)->check
;
1009 /* l3os is the distance between the start of the
1010 * frame (skb->data) and the start of the IP hdr.
1011 * l4os is the distance between the start of the
1012 * l3 hdr and the l4 hdr */
1013 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
1014 fcb
->l4os
= skb_network_header_len(skb
);
1019 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1021 fcb
->flags
|= TXFCB_VLN
;
1022 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1025 /* This is called by the kernel when a frame is ready for transmission. */
1026 /* It is pointed to by the dev->hard_start_xmit function pointer */
1027 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1029 struct gfar_private
*priv
= netdev_priv(dev
);
1030 struct txfcb
*fcb
= NULL
;
1031 struct txbd8
*txbdp
;
1033 unsigned long flags
;
1035 /* Update transmit stats */
1036 dev
->stats
.tx_bytes
+= skb
->len
;
1039 spin_lock_irqsave(&priv
->txlock
, flags
);
1041 /* Point at the first free tx descriptor */
1042 txbdp
= priv
->cur_tx
;
1044 /* Clear all but the WRAP status flags */
1045 status
= txbdp
->status
& TXBD_WRAP
;
1047 /* Set up checksumming */
1048 if (likely((dev
->features
& NETIF_F_IP_CSUM
)
1049 && (CHECKSUM_PARTIAL
== skb
->ip_summed
))) {
1050 fcb
= gfar_add_fcb(skb
, txbdp
);
1052 gfar_tx_checksum(skb
, fcb
);
1055 if (priv
->vlan_enable
&&
1056 unlikely(priv
->vlgrp
&& vlan_tx_tag_present(skb
))) {
1057 if (unlikely(NULL
== fcb
)) {
1058 fcb
= gfar_add_fcb(skb
, txbdp
);
1062 gfar_tx_vlan(skb
, fcb
);
1065 /* Set buffer length and pointer */
1066 txbdp
->length
= skb
->len
;
1067 txbdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1068 skb
->len
, DMA_TO_DEVICE
);
1070 /* Save the skb pointer so we can free it later */
1071 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
1073 /* Update the current skb pointer (wrapping if this was the last) */
1075 (priv
->skb_curtx
+ 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1077 /* Flag the BD as interrupt-causing */
1078 status
|= TXBD_INTERRUPT
;
1080 /* Flag the BD as ready to go, last in frame, and */
1081 /* in need of CRC */
1082 status
|= (TXBD_READY
| TXBD_LAST
| TXBD_CRC
);
1084 dev
->trans_start
= jiffies
;
1086 /* The powerpc-specific eieio() is used, as wmb() has too strong
1087 * semantics (it requires synchronization between cacheable and
1088 * uncacheable mappings, which eieio doesn't provide and which we
1089 * don't need), thus requiring a more expensive sync instruction. At
1090 * some point, the set of architecture-independent barrier functions
1091 * should be expanded to include weaker barriers.
1095 txbdp
->status
= status
;
1097 /* If this was the last BD in the ring, the next one */
1098 /* is at the beginning of the ring */
1099 if (txbdp
->status
& TXBD_WRAP
)
1100 txbdp
= priv
->tx_bd_base
;
1104 /* If the next BD still needs to be cleaned up, then the bds
1105 are full. We need to tell the kernel to stop sending us stuff. */
1106 if (txbdp
== priv
->dirty_tx
) {
1107 netif_stop_queue(dev
);
1109 dev
->stats
.tx_fifo_errors
++;
1112 /* Update the current txbd to the next one */
1113 priv
->cur_tx
= txbdp
;
1115 /* Tell the DMA to go go go */
1116 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1119 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1124 /* Stops the kernel queue, and halts the controller */
1125 static int gfar_close(struct net_device
*dev
)
1127 struct gfar_private
*priv
= netdev_priv(dev
);
1129 #ifdef CONFIG_GFAR_NAPI
1130 napi_disable(&priv
->napi
);
1135 /* Disconnect from the PHY */
1136 phy_disconnect(priv
->phydev
);
1137 priv
->phydev
= NULL
;
1139 netif_stop_queue(dev
);
1144 /* Changes the mac address if the controller is not running. */
1145 static int gfar_set_mac_address(struct net_device
*dev
)
1147 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1153 /* Enables and disables VLAN insertion/extraction */
1154 static void gfar_vlan_rx_register(struct net_device
*dev
,
1155 struct vlan_group
*grp
)
1157 struct gfar_private
*priv
= netdev_priv(dev
);
1158 unsigned long flags
;
1161 spin_lock_irqsave(&priv
->rxlock
, flags
);
1166 /* Enable VLAN tag insertion */
1167 tempval
= gfar_read(&priv
->regs
->tctrl
);
1168 tempval
|= TCTRL_VLINS
;
1170 gfar_write(&priv
->regs
->tctrl
, tempval
);
1172 /* Enable VLAN tag extraction */
1173 tempval
= gfar_read(&priv
->regs
->rctrl
);
1174 tempval
|= RCTRL_VLEX
;
1175 gfar_write(&priv
->regs
->rctrl
, tempval
);
1177 /* Disable VLAN tag insertion */
1178 tempval
= gfar_read(&priv
->regs
->tctrl
);
1179 tempval
&= ~TCTRL_VLINS
;
1180 gfar_write(&priv
->regs
->tctrl
, tempval
);
1182 /* Disable VLAN tag extraction */
1183 tempval
= gfar_read(&priv
->regs
->rctrl
);
1184 tempval
&= ~RCTRL_VLEX
;
1185 gfar_write(&priv
->regs
->rctrl
, tempval
);
1188 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1191 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1193 int tempsize
, tempval
;
1194 struct gfar_private
*priv
= netdev_priv(dev
);
1195 int oldsize
= priv
->rx_buffer_size
;
1196 int frame_size
= new_mtu
+ ETH_HLEN
;
1198 if (priv
->vlan_enable
)
1199 frame_size
+= VLAN_HLEN
;
1201 if (gfar_uses_fcb(priv
))
1202 frame_size
+= GMAC_FCB_LEN
;
1204 frame_size
+= priv
->padding
;
1206 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1207 if (netif_msg_drv(priv
))
1208 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1214 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1215 INCREMENTAL_BUFFER_SIZE
;
1217 /* Only stop and start the controller if it isn't already
1218 * stopped, and we changed something */
1219 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1222 priv
->rx_buffer_size
= tempsize
;
1226 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1227 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1229 /* If the mtu is larger than the max size for standard
1230 * ethernet frames (ie, a jumbo frame), then set maccfg2
1231 * to allow huge frames, and to check the length */
1232 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1234 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1235 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1237 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1239 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1241 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1247 /* gfar_timeout gets called when a packet has not been
1248 * transmitted after a set amount of time.
1249 * For now, assume that clearing out all the structures, and
1250 * starting over will fix the problem. */
1251 static void gfar_timeout(struct net_device
*dev
)
1253 dev
->stats
.tx_errors
++;
1255 if (dev
->flags
& IFF_UP
) {
1260 netif_schedule(dev
);
1263 /* Interrupt Handler for Transmit complete */
1264 static int gfar_clean_tx_ring(struct net_device
*dev
)
1267 struct gfar_private
*priv
= netdev_priv(dev
);
1270 bdp
= priv
->dirty_tx
;
1271 while ((bdp
->status
& TXBD_READY
) == 0) {
1272 /* If dirty_tx and cur_tx are the same, then either the */
1273 /* ring is empty or full now (it could only be full in the beginning, */
1274 /* obviously). If it is empty, we are done. */
1275 if ((bdp
== priv
->cur_tx
) && (netif_queue_stopped(dev
) == 0))
1280 /* Deferred means some collisions occurred during transmit, */
1281 /* but we eventually sent the packet. */
1282 if (bdp
->status
& TXBD_DEF
)
1283 dev
->stats
.collisions
++;
1285 /* Free the sk buffer associated with this TxBD */
1286 dev_kfree_skb_irq(priv
->tx_skbuff
[priv
->skb_dirtytx
]);
1288 priv
->tx_skbuff
[priv
->skb_dirtytx
] = NULL
;
1290 (priv
->skb_dirtytx
+
1291 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1293 /* Clean BD length for empty detection */
1296 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1297 if (bdp
->status
& TXBD_WRAP
)
1298 bdp
= priv
->tx_bd_base
;
1302 /* Move dirty_tx to be the next bd */
1303 priv
->dirty_tx
= bdp
;
1305 /* We freed a buffer, so now we can restart transmission */
1306 if (netif_queue_stopped(dev
))
1307 netif_wake_queue(dev
);
1308 } /* while ((bdp->status & TXBD_READY) == 0) */
1310 dev
->stats
.tx_packets
+= howmany
;
1315 /* Interrupt Handler for Transmit complete */
1316 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
)
1318 struct net_device
*dev
= (struct net_device
*) dev_id
;
1319 struct gfar_private
*priv
= netdev_priv(dev
);
1322 gfar_write(&priv
->regs
->ievent
, IEVENT_TX_MASK
);
1325 spin_lock(&priv
->txlock
);
1327 gfar_clean_tx_ring(dev
);
1329 /* If we are coalescing the interrupts, reset the timer */
1330 /* Otherwise, clear it */
1331 if (likely(priv
->txcoalescing
)) {
1332 gfar_write(&priv
->regs
->txic
, 0);
1333 gfar_write(&priv
->regs
->txic
,
1334 mk_ic_value(priv
->txcount
, priv
->txtime
));
1337 spin_unlock(&priv
->txlock
);
1342 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
1343 struct sk_buff
*skb
)
1345 struct gfar_private
*priv
= netdev_priv(dev
);
1346 u32
* status_len
= (u32
*)bdp
;
1349 bdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1350 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1352 flags
= RXBD_EMPTY
| RXBD_INTERRUPT
;
1354 if (bdp
== priv
->rx_bd_base
+ priv
->rx_ring_size
- 1)
1359 *status_len
= (u32
)flags
<< 16;
1363 struct sk_buff
* gfar_new_skb(struct net_device
*dev
)
1365 unsigned int alignamount
;
1366 struct gfar_private
*priv
= netdev_priv(dev
);
1367 struct sk_buff
*skb
= NULL
;
1369 /* We have to allocate the skb, so keep trying till we succeed */
1370 skb
= netdev_alloc_skb(dev
, priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1375 alignamount
= RXBUF_ALIGNMENT
-
1376 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1378 /* We need the data buffer to be aligned properly. We will reserve
1379 * as many bytes as needed to align the data properly
1381 skb_reserve(skb
, alignamount
);
1386 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
1388 struct gfar_private
*priv
= netdev_priv(dev
);
1389 struct net_device_stats
*stats
= &dev
->stats
;
1390 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1392 /* If the packet was truncated, none of the other errors
1394 if (status
& RXBD_TRUNCATED
) {
1395 stats
->rx_length_errors
++;
1401 /* Count the errors, if there were any */
1402 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1403 stats
->rx_length_errors
++;
1405 if (status
& RXBD_LARGE
)
1410 if (status
& RXBD_NONOCTET
) {
1411 stats
->rx_frame_errors
++;
1412 estats
->rx_nonoctet
++;
1414 if (status
& RXBD_CRCERR
) {
1415 estats
->rx_crcerr
++;
1416 stats
->rx_crc_errors
++;
1418 if (status
& RXBD_OVERRUN
) {
1419 estats
->rx_overrun
++;
1420 stats
->rx_crc_errors
++;
1424 irqreturn_t
gfar_receive(int irq
, void *dev_id
)
1426 struct net_device
*dev
= (struct net_device
*) dev_id
;
1427 struct gfar_private
*priv
= netdev_priv(dev
);
1428 #ifdef CONFIG_GFAR_NAPI
1431 unsigned long flags
;
1435 #ifdef CONFIG_GFAR_NAPI
1436 /* Clear IEVENT, so interrupts aren't called again
1437 * because of the packets that have already arrived */
1438 gfar_write(&priv
->regs
->ievent
, IEVENT_RTX_MASK
);
1440 if (netif_rx_schedule_prep(dev
, &priv
->napi
)) {
1441 tempval
= gfar_read(&priv
->regs
->imask
);
1442 tempval
&= IMASK_RTX_DISABLED
;
1443 gfar_write(&priv
->regs
->imask
, tempval
);
1445 __netif_rx_schedule(dev
, &priv
->napi
);
1447 if (netif_msg_rx_err(priv
))
1448 printk(KERN_DEBUG
"%s: receive called twice (%x)[%x]\n",
1449 dev
->name
, gfar_read(&priv
->regs
->ievent
),
1450 gfar_read(&priv
->regs
->imask
));
1453 /* Clear IEVENT, so rx interrupt isn't called again
1454 * because of this interrupt */
1455 gfar_write(&priv
->regs
->ievent
, IEVENT_RX_MASK
);
1457 spin_lock_irqsave(&priv
->rxlock
, flags
);
1458 gfar_clean_rx_ring(dev
, priv
->rx_ring_size
);
1460 /* If we are coalescing interrupts, update the timer */
1461 /* Otherwise, clear it */
1462 if (likely(priv
->rxcoalescing
)) {
1463 gfar_write(&priv
->regs
->rxic
, 0);
1464 gfar_write(&priv
->regs
->rxic
,
1465 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1468 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1474 static inline int gfar_rx_vlan(struct sk_buff
*skb
,
1475 struct vlan_group
*vlgrp
, unsigned short vlctl
)
1477 #ifdef CONFIG_GFAR_NAPI
1478 return vlan_hwaccel_receive_skb(skb
, vlgrp
, vlctl
);
1480 return vlan_hwaccel_rx(skb
, vlgrp
, vlctl
);
1484 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1486 /* If valid headers were found, and valid sums
1487 * were verified, then we tell the kernel that no
1488 * checksumming is necessary. Otherwise, it is */
1489 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1490 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1492 skb
->ip_summed
= CHECKSUM_NONE
;
1496 static inline struct rxfcb
*gfar_get_fcb(struct sk_buff
*skb
)
1498 struct rxfcb
*fcb
= (struct rxfcb
*)skb
->data
;
1500 /* Remove the FCB from the skb */
1501 skb_pull(skb
, GMAC_FCB_LEN
);
1506 /* gfar_process_frame() -- handle one incoming packet if skb
1508 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1511 struct gfar_private
*priv
= netdev_priv(dev
);
1512 struct rxfcb
*fcb
= NULL
;
1515 if (netif_msg_rx_err(priv
))
1516 printk(KERN_WARNING
"%s: Missing skb!!.\n", dev
->name
);
1517 dev
->stats
.rx_dropped
++;
1518 priv
->extra_stats
.rx_skbmissing
++;
1522 /* Prep the skb for the packet */
1523 skb_put(skb
, length
);
1525 /* Grab the FCB if there is one */
1526 if (gfar_uses_fcb(priv
))
1527 fcb
= gfar_get_fcb(skb
);
1529 /* Remove the padded bytes, if there are any */
1531 skb_pull(skb
, priv
->padding
);
1533 if (priv
->rx_csum_enable
)
1534 gfar_rx_checksum(skb
, fcb
);
1536 /* Tell the skb what kind of packet this is */
1537 skb
->protocol
= eth_type_trans(skb
, dev
);
1539 /* Send the packet up the stack */
1540 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
)))
1541 ret
= gfar_rx_vlan(skb
, priv
->vlgrp
, fcb
->vlctl
);
1545 if (NET_RX_DROP
== ret
)
1546 priv
->extra_stats
.kernel_dropped
++;
1552 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1553 * until the budget/quota has been reached. Returns the number
1556 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1559 struct sk_buff
*skb
;
1562 struct gfar_private
*priv
= netdev_priv(dev
);
1564 /* Get the first full descriptor */
1567 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1568 struct sk_buff
*newskb
;
1571 /* Add another skb for the future */
1572 newskb
= gfar_new_skb(dev
);
1574 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1576 /* We drop the frame if we failed to allocate a new buffer */
1577 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
1578 bdp
->status
& RXBD_ERR
)) {
1579 count_errors(bdp
->status
, dev
);
1581 if (unlikely(!newskb
))
1585 dma_unmap_single(&priv
->dev
->dev
,
1587 priv
->rx_buffer_size
,
1590 dev_kfree_skb_any(skb
);
1593 /* Increment the number of packets */
1594 dev
->stats
.rx_packets
++;
1597 /* Remove the FCS from the packet length */
1598 pkt_len
= bdp
->length
- 4;
1600 gfar_process_frame(dev
, skb
, pkt_len
);
1602 dev
->stats
.rx_bytes
+= pkt_len
;
1605 dev
->last_rx
= jiffies
;
1607 priv
->rx_skbuff
[priv
->skb_currx
] = newskb
;
1609 /* Setup the new bdp */
1610 gfar_new_rxbdp(dev
, bdp
, newskb
);
1612 /* Update to the next pointer */
1613 if (bdp
->status
& RXBD_WRAP
)
1614 bdp
= priv
->rx_bd_base
;
1618 /* update to point at the next skb */
1620 (priv
->skb_currx
+ 1) &
1621 RX_RING_MOD_MASK(priv
->rx_ring_size
);
1624 /* Update the current rxbd pointer to be the next one */
1630 #ifdef CONFIG_GFAR_NAPI
1631 static int gfar_poll(struct napi_struct
*napi
, int budget
)
1633 struct gfar_private
*priv
= container_of(napi
, struct gfar_private
, napi
);
1634 struct net_device
*dev
= priv
->dev
;
1636 unsigned long flags
;
1638 /* If we fail to get the lock, don't bother with the TX BDs */
1639 if (spin_trylock_irqsave(&priv
->txlock
, flags
)) {
1640 gfar_clean_tx_ring(dev
);
1641 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1644 howmany
= gfar_clean_rx_ring(dev
, budget
);
1646 if (howmany
< budget
) {
1647 netif_rx_complete(dev
, napi
);
1649 /* Clear the halt bit in RSTAT */
1650 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1652 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1654 /* If we are coalescing interrupts, update the timer */
1655 /* Otherwise, clear it */
1656 if (likely(priv
->rxcoalescing
)) {
1657 gfar_write(&priv
->regs
->rxic
, 0);
1658 gfar_write(&priv
->regs
->rxic
,
1659 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1667 #ifdef CONFIG_NET_POLL_CONTROLLER
1669 * Polling 'interrupt' - used by things like netconsole to send skbs
1670 * without having to re-enable interrupts. It's not called while
1671 * the interrupt routine is executing.
1673 static void gfar_netpoll(struct net_device
*dev
)
1675 struct gfar_private
*priv
= netdev_priv(dev
);
1677 /* If the device has multiple interrupts, run tx/rx */
1678 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1679 disable_irq(priv
->interruptTransmit
);
1680 disable_irq(priv
->interruptReceive
);
1681 disable_irq(priv
->interruptError
);
1682 gfar_interrupt(priv
->interruptTransmit
, dev
);
1683 enable_irq(priv
->interruptError
);
1684 enable_irq(priv
->interruptReceive
);
1685 enable_irq(priv
->interruptTransmit
);
1687 disable_irq(priv
->interruptTransmit
);
1688 gfar_interrupt(priv
->interruptTransmit
, dev
);
1689 enable_irq(priv
->interruptTransmit
);
1694 /* The interrupt handler for devices with one interrupt */
1695 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
)
1697 struct net_device
*dev
= dev_id
;
1698 struct gfar_private
*priv
= netdev_priv(dev
);
1700 /* Save ievent for future reference */
1701 u32 events
= gfar_read(&priv
->regs
->ievent
);
1703 /* Check for reception */
1704 if (events
& IEVENT_RX_MASK
)
1705 gfar_receive(irq
, dev_id
);
1707 /* Check for transmit completion */
1708 if (events
& IEVENT_TX_MASK
)
1709 gfar_transmit(irq
, dev_id
);
1711 /* Check for errors */
1712 if (events
& IEVENT_ERR_MASK
)
1713 gfar_error(irq
, dev_id
);
1718 /* Called every time the controller might need to be made
1719 * aware of new link state. The PHY code conveys this
1720 * information through variables in the phydev structure, and this
1721 * function converts those variables into the appropriate
1722 * register values, and can bring down the device if needed.
1724 static void adjust_link(struct net_device
*dev
)
1726 struct gfar_private
*priv
= netdev_priv(dev
);
1727 struct gfar __iomem
*regs
= priv
->regs
;
1728 unsigned long flags
;
1729 struct phy_device
*phydev
= priv
->phydev
;
1732 spin_lock_irqsave(&priv
->txlock
, flags
);
1734 u32 tempval
= gfar_read(®s
->maccfg2
);
1735 u32 ecntrl
= gfar_read(®s
->ecntrl
);
1737 /* Now we make sure that we can be in full duplex mode.
1738 * If not, we operate in half-duplex mode. */
1739 if (phydev
->duplex
!= priv
->oldduplex
) {
1741 if (!(phydev
->duplex
))
1742 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
1744 tempval
|= MACCFG2_FULL_DUPLEX
;
1746 priv
->oldduplex
= phydev
->duplex
;
1749 if (phydev
->speed
!= priv
->oldspeed
) {
1751 switch (phydev
->speed
) {
1754 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
1759 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
1761 /* Reduced mode distinguishes
1762 * between 10 and 100 */
1763 if (phydev
->speed
== SPEED_100
)
1764 ecntrl
|= ECNTRL_R100
;
1766 ecntrl
&= ~(ECNTRL_R100
);
1769 if (netif_msg_link(priv
))
1771 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1772 dev
->name
, phydev
->speed
);
1776 priv
->oldspeed
= phydev
->speed
;
1779 gfar_write(®s
->maccfg2
, tempval
);
1780 gfar_write(®s
->ecntrl
, ecntrl
);
1782 if (!priv
->oldlink
) {
1785 netif_schedule(dev
);
1787 } else if (priv
->oldlink
) {
1791 priv
->oldduplex
= -1;
1794 if (new_state
&& netif_msg_link(priv
))
1795 phy_print_status(phydev
);
1797 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1800 /* Update the hash table based on the current list of multicast
1801 * addresses we subscribe to. Also, change the promiscuity of
1802 * the device based on the flags (this function is called
1803 * whenever dev->flags is changed */
1804 static void gfar_set_multi(struct net_device
*dev
)
1806 struct dev_mc_list
*mc_ptr
;
1807 struct gfar_private
*priv
= netdev_priv(dev
);
1808 struct gfar __iomem
*regs
= priv
->regs
;
1811 if(dev
->flags
& IFF_PROMISC
) {
1812 /* Set RCTRL to PROM */
1813 tempval
= gfar_read(®s
->rctrl
);
1814 tempval
|= RCTRL_PROM
;
1815 gfar_write(®s
->rctrl
, tempval
);
1817 /* Set RCTRL to not PROM */
1818 tempval
= gfar_read(®s
->rctrl
);
1819 tempval
&= ~(RCTRL_PROM
);
1820 gfar_write(®s
->rctrl
, tempval
);
1823 if(dev
->flags
& IFF_ALLMULTI
) {
1824 /* Set the hash to rx all multicast frames */
1825 gfar_write(®s
->igaddr0
, 0xffffffff);
1826 gfar_write(®s
->igaddr1
, 0xffffffff);
1827 gfar_write(®s
->igaddr2
, 0xffffffff);
1828 gfar_write(®s
->igaddr3
, 0xffffffff);
1829 gfar_write(®s
->igaddr4
, 0xffffffff);
1830 gfar_write(®s
->igaddr5
, 0xffffffff);
1831 gfar_write(®s
->igaddr6
, 0xffffffff);
1832 gfar_write(®s
->igaddr7
, 0xffffffff);
1833 gfar_write(®s
->gaddr0
, 0xffffffff);
1834 gfar_write(®s
->gaddr1
, 0xffffffff);
1835 gfar_write(®s
->gaddr2
, 0xffffffff);
1836 gfar_write(®s
->gaddr3
, 0xffffffff);
1837 gfar_write(®s
->gaddr4
, 0xffffffff);
1838 gfar_write(®s
->gaddr5
, 0xffffffff);
1839 gfar_write(®s
->gaddr6
, 0xffffffff);
1840 gfar_write(®s
->gaddr7
, 0xffffffff);
1845 /* zero out the hash */
1846 gfar_write(®s
->igaddr0
, 0x0);
1847 gfar_write(®s
->igaddr1
, 0x0);
1848 gfar_write(®s
->igaddr2
, 0x0);
1849 gfar_write(®s
->igaddr3
, 0x0);
1850 gfar_write(®s
->igaddr4
, 0x0);
1851 gfar_write(®s
->igaddr5
, 0x0);
1852 gfar_write(®s
->igaddr6
, 0x0);
1853 gfar_write(®s
->igaddr7
, 0x0);
1854 gfar_write(®s
->gaddr0
, 0x0);
1855 gfar_write(®s
->gaddr1
, 0x0);
1856 gfar_write(®s
->gaddr2
, 0x0);
1857 gfar_write(®s
->gaddr3
, 0x0);
1858 gfar_write(®s
->gaddr4
, 0x0);
1859 gfar_write(®s
->gaddr5
, 0x0);
1860 gfar_write(®s
->gaddr6
, 0x0);
1861 gfar_write(®s
->gaddr7
, 0x0);
1863 /* If we have extended hash tables, we need to
1864 * clear the exact match registers to prepare for
1866 if (priv
->extended_hash
) {
1867 em_num
= GFAR_EM_NUM
+ 1;
1868 gfar_clear_exact_match(dev
);
1875 if(dev
->mc_count
== 0)
1878 /* Parse the list, and set the appropriate bits */
1879 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
1881 gfar_set_mac_for_addr(dev
, idx
,
1885 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
1893 /* Clears each of the exact match registers to zero, so they
1894 * don't interfere with normal reception */
1895 static void gfar_clear_exact_match(struct net_device
*dev
)
1898 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
1900 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
1901 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
1904 /* Set the appropriate hash bit for the given addr */
1905 /* The algorithm works like so:
1906 * 1) Take the Destination Address (ie the multicast address), and
1907 * do a CRC on it (little endian), and reverse the bits of the
1909 * 2) Use the 8 most significant bits as a hash into a 256-entry
1910 * table. The table is controlled through 8 32-bit registers:
1911 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1912 * gaddr7. This means that the 3 most significant bits in the
1913 * hash index which gaddr register to use, and the 5 other bits
1914 * indicate which bit (assuming an IBM numbering scheme, which
1915 * for PowerPC (tm) is usually the case) in the register holds
1917 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
1920 struct gfar_private
*priv
= netdev_priv(dev
);
1921 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
1922 int width
= priv
->hash_width
;
1923 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
1924 u8 whichreg
= result
>> (32 - width
+ 5);
1925 u32 value
= (1 << (31-whichbit
));
1927 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
1929 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
1935 /* There are multiple MAC Address register pairs on some controllers
1936 * This function sets the numth pair to a given address
1938 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
1940 struct gfar_private
*priv
= netdev_priv(dev
);
1942 char tmpbuf
[MAC_ADDR_LEN
];
1944 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
1948 /* Now copy it into the mac registers backwards, cuz */
1949 /* little endian is silly */
1950 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
1951 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
1953 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
1955 tempval
= *((u32
*) (tmpbuf
+ 4));
1957 gfar_write(macptr
+1, tempval
);
1960 /* GFAR error interrupt handler */
1961 static irqreturn_t
gfar_error(int irq
, void *dev_id
)
1963 struct net_device
*dev
= dev_id
;
1964 struct gfar_private
*priv
= netdev_priv(dev
);
1966 /* Save ievent for future reference */
1967 u32 events
= gfar_read(&priv
->regs
->ievent
);
1970 gfar_write(&priv
->regs
->ievent
, IEVENT_ERR_MASK
);
1973 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
1974 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1975 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
1977 /* Update the error counters */
1978 if (events
& IEVENT_TXE
) {
1979 dev
->stats
.tx_errors
++;
1981 if (events
& IEVENT_LC
)
1982 dev
->stats
.tx_window_errors
++;
1983 if (events
& IEVENT_CRL
)
1984 dev
->stats
.tx_aborted_errors
++;
1985 if (events
& IEVENT_XFUN
) {
1986 if (netif_msg_tx_err(priv
))
1987 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
1988 "packet dropped.\n", dev
->name
);
1989 dev
->stats
.tx_dropped
++;
1990 priv
->extra_stats
.tx_underrun
++;
1992 /* Reactivate the Tx Queues */
1993 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1995 if (netif_msg_tx_err(priv
))
1996 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
1998 if (events
& IEVENT_BSY
) {
1999 dev
->stats
.rx_errors
++;
2000 priv
->extra_stats
.rx_bsy
++;
2002 gfar_receive(irq
, dev_id
);
2004 #ifndef CONFIG_GFAR_NAPI
2005 /* Clear the halt bit in RSTAT */
2006 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
2009 if (netif_msg_rx_err(priv
))
2010 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
2011 dev
->name
, gfar_read(&priv
->regs
->rstat
));
2013 if (events
& IEVENT_BABR
) {
2014 dev
->stats
.rx_errors
++;
2015 priv
->extra_stats
.rx_babr
++;
2017 if (netif_msg_rx_err(priv
))
2018 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
2020 if (events
& IEVENT_EBERR
) {
2021 priv
->extra_stats
.eberr
++;
2022 if (netif_msg_rx_err(priv
))
2023 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
2025 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
2026 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
2028 if (events
& IEVENT_BABT
) {
2029 priv
->extra_stats
.tx_babt
++;
2030 if (netif_msg_tx_err(priv
))
2031 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
2036 /* work with hotplug and coldplug */
2037 MODULE_ALIAS("platform:fsl-gianfar");
2039 /* Structure for a device driver */
2040 static struct platform_driver gfar_driver
= {
2041 .probe
= gfar_probe
,
2042 .remove
= gfar_remove
,
2044 .name
= "fsl-gianfar",
2045 .owner
= THIS_MODULE
,
2049 static int __init
gfar_init(void)
2051 int err
= gfar_mdio_init();
2056 err
= platform_driver_register(&gfar_driver
);
2064 static void __exit
gfar_exit(void)
2066 platform_driver_unregister(&gfar_driver
);
2070 module_init(gfar_init
);
2071 module_exit(gfar_exit
);