[POWERPC] Fix 32-bit mm operations when not using BATs
[firewire-audio.git] / drivers / ata / sata_uli.c
blobd659ace80f4f6c985f6da071a61b9d42ff93b8a5
1 /*
2 * sata_uli.c - ULi Electronics SATA
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20 * libata documentation is available via 'make {ps|pdf}docs',
21 * as Documentation/DocBook/libata.*
23 * Hardware documentation available under NDA.
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/blkdev.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/device.h>
35 #include <scsi/scsi_host.h>
36 #include <linux/libata.h>
38 #define DRV_NAME "sata_uli"
39 #define DRV_VERSION "1.1"
41 enum {
42 uli_5289 = 0,
43 uli_5287 = 1,
44 uli_5281 = 2,
46 uli_max_ports = 4,
48 /* PCI configuration registers */
49 ULI5287_BASE = 0x90, /* sata0 phy SCR registers */
50 ULI5287_OFFS = 0x10, /* offset from sata0->sata1 phy regs */
51 ULI5281_BASE = 0x60, /* sata0 phy SCR registers */
52 ULI5281_OFFS = 0x60, /* offset from sata0->sata1 phy regs */
55 struct uli_priv {
56 unsigned int scr_cfg_addr[uli_max_ports];
59 static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
60 static u32 uli_scr_read (struct ata_port *ap, unsigned int sc_reg);
61 static void uli_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
63 static const struct pci_device_id uli_pci_tbl[] = {
64 { PCI_VDEVICE(AL, 0x5289), uli_5289 },
65 { PCI_VDEVICE(AL, 0x5287), uli_5287 },
66 { PCI_VDEVICE(AL, 0x5281), uli_5281 },
68 { } /* terminate list */
71 static struct pci_driver uli_pci_driver = {
72 .name = DRV_NAME,
73 .id_table = uli_pci_tbl,
74 .probe = uli_init_one,
75 .remove = ata_pci_remove_one,
78 static struct scsi_host_template uli_sht = {
79 .module = THIS_MODULE,
80 .name = DRV_NAME,
81 .ioctl = ata_scsi_ioctl,
82 .queuecommand = ata_scsi_queuecmd,
83 .can_queue = ATA_DEF_QUEUE,
84 .this_id = ATA_SHT_THIS_ID,
85 .sg_tablesize = LIBATA_MAX_PRD,
86 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
87 .emulated = ATA_SHT_EMULATED,
88 .use_clustering = ATA_SHT_USE_CLUSTERING,
89 .proc_name = DRV_NAME,
90 .dma_boundary = ATA_DMA_BOUNDARY,
91 .slave_configure = ata_scsi_slave_config,
92 .slave_destroy = ata_scsi_slave_destroy,
93 .bios_param = ata_std_bios_param,
96 static const struct ata_port_operations uli_ops = {
97 .port_disable = ata_port_disable,
99 .tf_load = ata_tf_load,
100 .tf_read = ata_tf_read,
101 .check_status = ata_check_status,
102 .exec_command = ata_exec_command,
103 .dev_select = ata_std_dev_select,
105 .bmdma_setup = ata_bmdma_setup,
106 .bmdma_start = ata_bmdma_start,
107 .bmdma_stop = ata_bmdma_stop,
108 .bmdma_status = ata_bmdma_status,
109 .qc_prep = ata_qc_prep,
110 .qc_issue = ata_qc_issue_prot,
111 .data_xfer = ata_data_xfer,
113 .freeze = ata_bmdma_freeze,
114 .thaw = ata_bmdma_thaw,
115 .error_handler = ata_bmdma_error_handler,
116 .post_internal_cmd = ata_bmdma_post_internal_cmd,
118 .irq_handler = ata_interrupt,
119 .irq_clear = ata_bmdma_irq_clear,
120 .irq_on = ata_irq_on,
121 .irq_ack = ata_irq_ack,
123 .scr_read = uli_scr_read,
124 .scr_write = uli_scr_write,
126 .port_start = ata_port_start,
129 static struct ata_port_info uli_port_info = {
130 .sht = &uli_sht,
131 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
132 ATA_FLAG_IGN_SIMPLEX,
133 .pio_mask = 0x1f, /* pio0-4 */
134 .udma_mask = 0x7f, /* udma0-6 */
135 .port_ops = &uli_ops,
139 MODULE_AUTHOR("Peer Chen");
140 MODULE_DESCRIPTION("low-level driver for ULi Electronics SATA controller");
141 MODULE_LICENSE("GPL");
142 MODULE_DEVICE_TABLE(pci, uli_pci_tbl);
143 MODULE_VERSION(DRV_VERSION);
145 static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
147 struct uli_priv *hpriv = ap->host->private_data;
148 return hpriv->scr_cfg_addr[ap->port_no] + (4 * sc_reg);
151 static u32 uli_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
153 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
154 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
155 u32 val;
157 pci_read_config_dword(pdev, cfg_addr, &val);
158 return val;
161 static void uli_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
163 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
164 unsigned int cfg_addr = get_scr_cfg_addr(ap, scr);
166 pci_write_config_dword(pdev, cfg_addr, val);
169 static u32 uli_scr_read (struct ata_port *ap, unsigned int sc_reg)
171 if (sc_reg > SCR_CONTROL)
172 return 0xffffffffU;
174 return uli_scr_cfg_read(ap, sc_reg);
177 static void uli_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
179 if (sc_reg > SCR_CONTROL) //SCR_CONTROL=2, SCR_ERROR=1, SCR_STATUS=0
180 return;
182 uli_scr_cfg_write(ap, sc_reg, val);
185 static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
187 static int printed_version;
188 struct ata_probe_ent *probe_ent;
189 struct ata_port_info *ppi[2];
190 int rc;
191 unsigned int board_idx = (unsigned int) ent->driver_data;
192 struct uli_priv *hpriv;
193 void __iomem * const *iomap;
195 if (!printed_version++)
196 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
198 rc = pcim_enable_device(pdev);
199 if (rc)
200 return rc;
202 rc = pci_request_regions(pdev, DRV_NAME);
203 if (rc) {
204 pcim_pin_device(pdev);
205 return rc;
208 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
209 if (rc)
210 return rc;
211 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
212 if (rc)
213 return rc;
215 ppi[0] = ppi[1] = &uli_port_info;
216 probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
217 if (!probe_ent)
218 return -ENOMEM;
220 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
221 if (!hpriv)
222 return -ENOMEM;
224 probe_ent->private_data = hpriv;
226 iomap = pcim_iomap_table(pdev);
228 switch (board_idx) {
229 case uli_5287:
230 hpriv->scr_cfg_addr[0] = ULI5287_BASE;
231 hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS;
232 probe_ent->n_ports = 4;
234 probe_ent->port[2].cmd_addr = iomap[0] + 8;
235 probe_ent->port[2].altstatus_addr =
236 probe_ent->port[2].ctl_addr = (void __iomem *)
237 ((unsigned long)iomap[1] | ATA_PCI_CTL_OFS) + 4;
238 probe_ent->port[2].bmdma_addr = iomap[4] + 16;
239 hpriv->scr_cfg_addr[2] = ULI5287_BASE + ULI5287_OFFS*4;
241 probe_ent->port[3].cmd_addr = iomap[2] + 8;
242 probe_ent->port[3].altstatus_addr =
243 probe_ent->port[3].ctl_addr = (void __iomem *)
244 ((unsigned long)iomap[3] | ATA_PCI_CTL_OFS) + 4;
245 probe_ent->port[3].bmdma_addr = iomap[4] + 24;
246 hpriv->scr_cfg_addr[3] = ULI5287_BASE + ULI5287_OFFS*5;
248 ata_std_ports(&probe_ent->port[2]);
249 ata_std_ports(&probe_ent->port[3]);
250 break;
252 case uli_5289:
253 hpriv->scr_cfg_addr[0] = ULI5287_BASE;
254 hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS;
255 break;
257 case uli_5281:
258 hpriv->scr_cfg_addr[0] = ULI5281_BASE;
259 hpriv->scr_cfg_addr[1] = ULI5281_BASE + ULI5281_OFFS;
260 break;
262 default:
263 BUG();
264 break;
267 pci_set_master(pdev);
268 pci_intx(pdev, 1);
270 if (!ata_device_add(probe_ent))
271 return -ENODEV;
273 devm_kfree(&pdev->dev, probe_ent);
274 return 0;
277 static int __init uli_init(void)
279 return pci_register_driver(&uli_pci_driver);
282 static void __exit uli_exit(void)
284 pci_unregister_driver(&uli_pci_driver);
288 module_init(uli_init);
289 module_exit(uli_exit);