2 * Copyright (C) 2004 IBM Corporation
5 * Leendert van Doorn <leendert@watson.ibm.com>
6 * Dave Safford <safford@watson.ibm.com>
7 * Reiner Sailer <sailer@watson.ibm.com>
8 * Kylene Hall <kjhall@us.ibm.com>
10 * Maintained by: <tpmdd_devel@lists.sourceforge.net>
12 * Device driver for TCG/TCPA TPM (trusted platform module).
13 * Specifications at www.trustedcomputinggroup.org
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation, version 2 of the
24 /* National definitions */
27 TPM_NSC_BASE0_HI
= 0x60,
28 TPM_NSC_BASE0_LO
= 0x61,
29 TPM_NSC_BASE1_HI
= 0x62,
30 TPM_NSC_BASE1_LO
= 0x63
43 enum tpm_nsc_status_loc
{
51 NSC_STATUS_OBF
= 0x01, /* output buffer full */
52 NSC_STATUS_IBF
= 0x02, /* input buffer full */
53 NSC_STATUS_F0
= 0x04, /* F0 */
54 NSC_STATUS_A2
= 0x08, /* A2 */
55 NSC_STATUS_RDY
= 0x10, /* ready to receive command */
56 NSC_STATUS_IBR
= 0x20 /* ready to receive data */
60 enum tpm_nsc_cmd_mode
{
61 NSC_COMMAND_NORMAL
= 0x01, /* normal mode */
62 NSC_COMMAND_EOC
= 0x03,
63 NSC_COMMAND_CANCEL
= 0x22
66 * Wait for a certain status to appear
68 static int wait_for_stat(struct tpm_chip
*chip
, u8 mask
, u8 val
, u8
* data
)
72 /* status immediately available check */
73 *data
= inb(chip
->vendor
->base
+ NSC_STATUS
);
74 if ((*data
& mask
) == val
)
78 stop
= jiffies
+ 10 * HZ
;
81 *data
= inb(chip
->vendor
->base
+ 1);
82 if ((*data
& mask
) == val
)
85 while (time_before(jiffies
, stop
));
90 static int nsc_wait_for_ready(struct tpm_chip
*chip
)
95 /* status immediately available check */
96 status
= inb(chip
->vendor
->base
+ NSC_STATUS
);
97 if (status
& NSC_STATUS_OBF
)
98 status
= inb(chip
->vendor
->base
+ NSC_DATA
);
99 if (status
& NSC_STATUS_RDY
)
102 /* wait for status */
103 stop
= jiffies
+ 100;
106 status
= inb(chip
->vendor
->base
+ NSC_STATUS
);
107 if (status
& NSC_STATUS_OBF
)
108 status
= inb(chip
->vendor
->base
+ NSC_DATA
);
109 if (status
& NSC_STATUS_RDY
)
112 while (time_before(jiffies
, stop
));
114 dev_info(chip
->dev
, "wait for ready failed\n");
119 static int tpm_nsc_recv(struct tpm_chip
*chip
, u8
* buf
, size_t count
)
129 if (wait_for_stat(chip
, NSC_STATUS_F0
, NSC_STATUS_F0
, &data
) < 0) {
130 dev_err(chip
->dev
, "F0 timeout\n");
134 inb(chip
->vendor
->base
+ NSC_DATA
)) != NSC_COMMAND_NORMAL
) {
135 dev_err(chip
->dev
, "not in normal mode (0x%x)\n",
140 /* read the whole packet */
141 for (p
= buffer
; p
< &buffer
[count
]; p
++) {
143 (chip
, NSC_STATUS_OBF
, NSC_STATUS_OBF
, &data
) < 0) {
145 "OBF timeout (while reading data)\n");
148 if (data
& NSC_STATUS_F0
)
150 *p
= inb(chip
->vendor
->base
+ NSC_DATA
);
153 if ((data
& NSC_STATUS_F0
) == 0 &&
154 (wait_for_stat(chip
, NSC_STATUS_F0
, NSC_STATUS_F0
, &data
) < 0)) {
155 dev_err(chip
->dev
, "F0 not set\n");
158 if ((data
= inb(chip
->vendor
->base
+ NSC_DATA
)) != NSC_COMMAND_EOC
) {
160 "expected end of command(0x%x)\n", data
);
164 native_size
= (__force __be32
*) (buf
+ 2);
165 size
= be32_to_cpu(*native_size
);
173 static int tpm_nsc_send(struct tpm_chip
*chip
, u8
* buf
, size_t count
)
179 * If we hit the chip with back to back commands it locks up
180 * and never set IBF. Hitting it with this "hammer" seems to
181 * fix it. Not sure why this is needed, we followed the flow
182 * chart in the manual to the letter.
184 outb(NSC_COMMAND_CANCEL
, chip
->vendor
->base
+ NSC_COMMAND
);
186 if (nsc_wait_for_ready(chip
) != 0)
189 if (wait_for_stat(chip
, NSC_STATUS_IBF
, 0, &data
) < 0) {
190 dev_err(chip
->dev
, "IBF timeout\n");
194 outb(NSC_COMMAND_NORMAL
, chip
->vendor
->base
+ NSC_COMMAND
);
195 if (wait_for_stat(chip
, NSC_STATUS_IBR
, NSC_STATUS_IBR
, &data
) < 0) {
196 dev_err(chip
->dev
, "IBR timeout\n");
200 for (i
= 0; i
< count
; i
++) {
201 if (wait_for_stat(chip
, NSC_STATUS_IBF
, 0, &data
) < 0) {
203 "IBF timeout (while writing data)\n");
206 outb(buf
[i
], chip
->vendor
->base
+ NSC_DATA
);
209 if (wait_for_stat(chip
, NSC_STATUS_IBF
, 0, &data
) < 0) {
210 dev_err(chip
->dev
, "IBF timeout\n");
213 outb(NSC_COMMAND_EOC
, chip
->vendor
->base
+ NSC_COMMAND
);
218 static void tpm_nsc_cancel(struct tpm_chip
*chip
)
220 outb(NSC_COMMAND_CANCEL
, chip
->vendor
->base
+ NSC_COMMAND
);
223 static u8
tpm_nsc_status(struct tpm_chip
*chip
)
225 return inb(chip
->vendor
->base
+ NSC_STATUS
);
228 static struct file_operations nsc_ops
= {
229 .owner
= THIS_MODULE
,
234 .release
= tpm_release
,
237 static DEVICE_ATTR(pubek
, S_IRUGO
, tpm_show_pubek
, NULL
);
238 static DEVICE_ATTR(pcrs
, S_IRUGO
, tpm_show_pcrs
, NULL
);
239 static DEVICE_ATTR(caps
, S_IRUGO
, tpm_show_caps
, NULL
);
240 static DEVICE_ATTR(cancel
, S_IWUSR
|S_IWGRP
, NULL
, tpm_store_cancel
);
242 static struct attribute
* nsc_attrs
[] = {
243 &dev_attr_pubek
.attr
,
246 &dev_attr_cancel
.attr
,
250 static struct attribute_group nsc_attr_grp
= { .attrs
= nsc_attrs
};
252 static struct tpm_vendor_specific tpm_nsc
= {
253 .recv
= tpm_nsc_recv
,
254 .send
= tpm_nsc_send
,
255 .cancel
= tpm_nsc_cancel
,
256 .status
= tpm_nsc_status
,
257 .req_complete_mask
= NSC_STATUS_OBF
,
258 .req_complete_val
= NSC_STATUS_OBF
,
259 .req_canceled
= NSC_STATUS_RDY
,
260 .attr_group
= &nsc_attr_grp
,
261 .miscdev
= { .fops
= &nsc_ops
, },
264 static int __devinit
tpm_nsc_init(struct pci_dev
*pci_dev
,
265 const struct pci_device_id
*pci_id
)
269 int nscAddrBase
= TPM_ADDR
;
272 if (pci_enable_device(pci_dev
))
275 /* select PM channel 1 */
276 tpm_write_index(nscAddrBase
,NSC_LDN_INDEX
, 0x12);
278 /* verify that it is a National part (SID) */
279 if (tpm_read_index(TPM_ADDR
, NSC_SID_INDEX
) != 0xEF) {
280 nscAddrBase
= (tpm_read_index(TPM_SUPERIO_ADDR
, 0x2C)<<8)|
281 (tpm_read_index(TPM_SUPERIO_ADDR
, 0x2B)&0xFE);
282 if (tpm_read_index(nscAddrBase
, NSC_SID_INDEX
) != 0xF6) {
288 hi
= tpm_read_index(nscAddrBase
, TPM_NSC_BASE0_HI
);
289 lo
= tpm_read_index(nscAddrBase
, TPM_NSC_BASE0_LO
);
290 tpm_nsc
.base
= (hi
<<8) | lo
;
292 dev_dbg(&pci_dev
->dev
, "NSC TPM detected\n");
293 dev_dbg(&pci_dev
->dev
,
294 "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
295 tpm_read_index(nscAddrBase
,0x07), tpm_read_index(nscAddrBase
,0x20),
296 tpm_read_index(nscAddrBase
,0x27));
297 dev_dbg(&pci_dev
->dev
,
298 "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
299 tpm_read_index(nscAddrBase
,0x21), tpm_read_index(nscAddrBase
,0x25),
300 tpm_read_index(nscAddrBase
,0x26), tpm_read_index(nscAddrBase
,0x28));
301 dev_dbg(&pci_dev
->dev
, "NSC IO Base0 0x%x\n",
302 (tpm_read_index(nscAddrBase
,0x60) << 8) | tpm_read_index(nscAddrBase
,0x61));
303 dev_dbg(&pci_dev
->dev
, "NSC IO Base1 0x%x\n",
304 (tpm_read_index(nscAddrBase
,0x62) << 8) | tpm_read_index(nscAddrBase
,0x63));
305 dev_dbg(&pci_dev
->dev
, "NSC Interrupt number and wakeup 0x%x\n",
306 tpm_read_index(nscAddrBase
,0x70));
307 dev_dbg(&pci_dev
->dev
, "NSC IRQ type select 0x%x\n",
308 tpm_read_index(nscAddrBase
,0x71));
309 dev_dbg(&pci_dev
->dev
,
310 "NSC DMA channel select0 0x%x, select1 0x%x\n",
311 tpm_read_index(nscAddrBase
,0x74), tpm_read_index(nscAddrBase
,0x75));
312 dev_dbg(&pci_dev
->dev
,
314 "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
315 tpm_read_index(nscAddrBase
,0xF0), tpm_read_index(nscAddrBase
,0xF1),
316 tpm_read_index(nscAddrBase
,0xF2), tpm_read_index(nscAddrBase
,0xF3),
317 tpm_read_index(nscAddrBase
,0xF4), tpm_read_index(nscAddrBase
,0xF5),
318 tpm_read_index(nscAddrBase
,0xF6), tpm_read_index(nscAddrBase
,0xF7),
319 tpm_read_index(nscAddrBase
,0xF8), tpm_read_index(nscAddrBase
,0xF9));
321 dev_info(&pci_dev
->dev
,
322 "NSC TPM revision %d\n",
323 tpm_read_index(nscAddrBase
, 0x27) & 0x1F);
325 /* enable the DPM module */
326 tpm_write_index(nscAddrBase
, NSC_LDC_INDEX
, 0x01);
328 if ((rc
= tpm_register_hardware(&pci_dev
->dev
, &tpm_nsc
)) < 0)
334 pci_disable_device(pci_dev
);
338 static void __devexit
tpm_nsc_remove(struct pci_dev
*pci_dev
)
340 struct tpm_chip
*chip
= pci_get_drvdata(pci_dev
);
343 tpm_remove_hardware(chip
->dev
);
346 static struct pci_device_id tpm_pci_tbl
[] __devinitdata
= {
347 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
)},
348 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
)},
349 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
)},
350 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
)},
351 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
)},
352 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_0
)},
353 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
)},
354 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
)},
355 {PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_LPC
)},
359 MODULE_DEVICE_TABLE(pci
, tpm_pci_tbl
);
361 static struct pci_driver nsc_pci_driver
= {
363 .id_table
= tpm_pci_tbl
,
364 .probe
= tpm_nsc_init
,
365 .remove
= __devexit_p(tpm_nsc_remove
),
366 .suspend
= tpm_pm_suspend
,
367 .resume
= tpm_pm_resume
,
370 static int __init
init_nsc(void)
372 return pci_register_driver(&nsc_pci_driver
);
375 static void __exit
cleanup_nsc(void)
377 pci_unregister_driver(&nsc_pci_driver
);
380 module_init(init_nsc
);
381 module_exit(cleanup_nsc
);
383 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
384 MODULE_DESCRIPTION("TPM Driver");
385 MODULE_VERSION("2.0");
386 MODULE_LICENSE("GPL");