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[PATCH] sata_promise: Support FastTrak TX4300/TX4310
[firewire-audio.git] / drivers / scsi / sata_promise.c
blob84cb3940ad8821a2f96aa861c131353472b7f72d
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include <asm/io.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.04"
50
51
52 enum {
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE = 0x41, /* TBG mode */
56 PDC_FLASH_CTL = 0x44, /* Flash control register */
57 PDC_PCI_CTL = 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
62 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
63
64 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
65 (1<<8) | (1<<9) | (1<<10),
66
67 board_2037x = 0, /* FastTrak S150 TX2plus */
68 board_20319 = 1, /* FastTrak S150 TX4 */
69 board_20619 = 2, /* FastTrak TX4000 */
70 board_20771 = 3, /* FastTrak TX2300 */
71 board_2057x = 4, /* SATAII150 Tx2plus */
72 board_40518 = 5, /* SATAII150 Tx4 */
73
74 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
75
76 PDC_RESET = (1 << 11), /* HDMA reset */
77
78 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
79 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI,
80 };
81
82
83 struct pdc_port_priv {
84 u8 *pkt;
85 dma_addr_t pkt_dma;
86 };
87
88 struct pdc_host_priv {
89 int hotplug_offset;
90 };
91
92 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
93 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
94 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
95 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
96 static void pdc_eng_timeout(struct ata_port *ap);
97 static int pdc_port_start(struct ata_port *ap);
98 static void pdc_port_stop(struct ata_port *ap);
99 static void pdc_pata_phy_reset(struct ata_port *ap);
100 static void pdc_sata_phy_reset(struct ata_port *ap);
101 static void pdc_qc_prep(struct ata_queued_cmd *qc);
102 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
103 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
104 static void pdc_irq_clear(struct ata_port *ap);
105 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
106 static void pdc_host_stop(struct ata_host_set *host_set);
107
108
109 static struct scsi_host_template pdc_ata_sht = {
110 .module = THIS_MODULE,
111 .name = DRV_NAME,
112 .ioctl = ata_scsi_ioctl,
113 .queuecommand = ata_scsi_queuecmd,
114 .eh_timed_out = ata_scsi_timed_out,
115 .eh_strategy_handler = ata_scsi_error,
116 .can_queue = ATA_DEF_QUEUE,
117 .this_id = ATA_SHT_THIS_ID,
118 .sg_tablesize = LIBATA_MAX_PRD,
119 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
120 .emulated = ATA_SHT_EMULATED,
121 .use_clustering = ATA_SHT_USE_CLUSTERING,
122 .proc_name = DRV_NAME,
123 .dma_boundary = ATA_DMA_BOUNDARY,
124 .slave_configure = ata_scsi_slave_config,
125 .bios_param = ata_std_bios_param,
126 };
127
128 static const struct ata_port_operations pdc_sata_ops = {
129 .port_disable = ata_port_disable,
130 .tf_load = pdc_tf_load_mmio,
131 .tf_read = ata_tf_read,
132 .check_status = ata_check_status,
133 .exec_command = pdc_exec_command_mmio,
134 .dev_select = ata_std_dev_select,
135
136 .phy_reset = pdc_sata_phy_reset,
137
138 .qc_prep = pdc_qc_prep,
139 .qc_issue = pdc_qc_issue_prot,
140 .eng_timeout = pdc_eng_timeout,
141 .irq_handler = pdc_interrupt,
142 .irq_clear = pdc_irq_clear,
143
144 .scr_read = pdc_sata_scr_read,
145 .scr_write = pdc_sata_scr_write,
146 .port_start = pdc_port_start,
147 .port_stop = pdc_port_stop,
148 .host_stop = pdc_host_stop,
149 };
150
151 static const struct ata_port_operations pdc_pata_ops = {
152 .port_disable = ata_port_disable,
153 .tf_load = pdc_tf_load_mmio,
154 .tf_read = ata_tf_read,
155 .check_status = ata_check_status,
156 .exec_command = pdc_exec_command_mmio,
157 .dev_select = ata_std_dev_select,
158
159 .phy_reset = pdc_pata_phy_reset,
160
161 .qc_prep = pdc_qc_prep,
162 .qc_issue = pdc_qc_issue_prot,
163 .eng_timeout = pdc_eng_timeout,
164 .irq_handler = pdc_interrupt,
165 .irq_clear = pdc_irq_clear,
166
167 .port_start = pdc_port_start,
168 .port_stop = pdc_port_stop,
169 .host_stop = pdc_host_stop,
170 };
171
172 static const struct ata_port_info pdc_port_info[] = {
173 /* board_2037x */
174 {
175 .sht = &pdc_ata_sht,
176 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
177 .pio_mask = 0x1f, /* pio0-4 */
178 .mwdma_mask = 0x07, /* mwdma0-2 */
179 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
180 .port_ops = &pdc_sata_ops,
181 },
182
183 /* board_20319 */
184 {
185 .sht = &pdc_ata_sht,
186 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
187 .pio_mask = 0x1f, /* pio0-4 */
188 .mwdma_mask = 0x07, /* mwdma0-2 */
189 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
190 .port_ops = &pdc_sata_ops,
191 },
192
193 /* board_20619 */
194 {
195 .sht = &pdc_ata_sht,
196 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
197 .pio_mask = 0x1f, /* pio0-4 */
198 .mwdma_mask = 0x07, /* mwdma0-2 */
199 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
200 .port_ops = &pdc_pata_ops,
201 },
202
203 /* board_20771 */
204 {
205 .sht = &pdc_ata_sht,
206 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
207 .pio_mask = 0x1f, /* pio0-4 */
208 .mwdma_mask = 0x07, /* mwdma0-2 */
209 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
210 .port_ops = &pdc_sata_ops,
211 },
212
213 /* board_2057x */
214 {
215 .sht = &pdc_ata_sht,
216 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
217 .pio_mask = 0x1f, /* pio0-4 */
218 .mwdma_mask = 0x07, /* mwdma0-2 */
219 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
220 .port_ops = &pdc_sata_ops,
221 },
222
223 /* board_40518 */
224 {
225 .sht = &pdc_ata_sht,
226 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
227 .pio_mask = 0x1f, /* pio0-4 */
228 .mwdma_mask = 0x07, /* mwdma0-2 */
229 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
230 .port_ops = &pdc_sata_ops,
231 },
232 };
233
234 static const struct pci_device_id pdc_ata_pci_tbl[] = {
235 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
236 board_2037x },
237 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
238 board_2037x },
239 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
240 board_2037x },
241 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
242 board_2037x },
243 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
244 board_2037x },
245 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
246 board_2037x },
247 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
248 board_2057x },
249 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
250 board_2057x },
251 { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
252 board_2037x },
253
254 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
255 board_20319 },
256 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
257 board_20319 },
258 { PCI_VENDOR_ID_PROMISE, 0x3515, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
259 board_20319 },
260 { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_20319 },
262 { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_20319 },
264 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_40518 },
266
267 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 board_20619 },
269
270 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_20771 },
272 { } /* terminate list */
273 };
274
275
276 static struct pci_driver pdc_ata_pci_driver = {
277 .name = DRV_NAME,
278 .id_table = pdc_ata_pci_tbl,
279 .probe = pdc_ata_init_one,
280 .remove = ata_pci_remove_one,
281 };
282
283
284 static int pdc_port_start(struct ata_port *ap)
285 {
286 struct device *dev = ap->host_set->dev;
287 struct pdc_port_priv *pp;
288 int rc;
289
290 rc = ata_port_start(ap);
291 if (rc)
292 return rc;
293
294 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
295 if (!pp) {
296 rc = -ENOMEM;
297 goto err_out;
298 }
299
300 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
301 if (!pp->pkt) {
302 rc = -ENOMEM;
303 goto err_out_kfree;
304 }
305
306 ap->private_data = pp;
307
308 return 0;
309
310 err_out_kfree:
311 kfree(pp);
312 err_out:
313 ata_port_stop(ap);
314 return rc;
315 }
316
317
318 static void pdc_port_stop(struct ata_port *ap)
319 {
320 struct device *dev = ap->host_set->dev;
321 struct pdc_port_priv *pp = ap->private_data;
322
323 ap->private_data = NULL;
324 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
325 kfree(pp);
326 ata_port_stop(ap);
327 }
328
329
330 static void pdc_host_stop(struct ata_host_set *host_set)
331 {
332 struct pdc_host_priv *hp = host_set->private_data;
333
334 ata_pci_host_stop(host_set);
335
336 kfree(hp);
337 }
338
339
340 static void pdc_reset_port(struct ata_port *ap)
341 {
342 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
343 unsigned int i;
344 u32 tmp;
345
346 for (i = 11; i > 0; i--) {
347 tmp = readl(mmio);
348 if (tmp & PDC_RESET)
349 break;
350
351 udelay(100);
352
353 tmp |= PDC_RESET;
354 writel(tmp, mmio);
355 }
356
357 tmp &= ~PDC_RESET;
358 writel(tmp, mmio);
359 readl(mmio); /* flush */
360 }
361
362 static void pdc_sata_phy_reset(struct ata_port *ap)
363 {
364 pdc_reset_port(ap);
365 sata_phy_reset(ap);
366 }
367
368 static void pdc_pata_phy_reset(struct ata_port *ap)
369 {
370 /* FIXME: add cable detect. Don't assume 40-pin cable */
371 ap->cbl = ATA_CBL_PATA40;
372 ap->udma_mask &= ATA_UDMA_MASK_40C;
373
374 pdc_reset_port(ap);
375 ata_port_probe(ap);
376 ata_bus_reset(ap);
377 }
378
379 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
380 {
381 if (sc_reg > SCR_CONTROL)
382 return 0xffffffffU;
383 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
384 }
385
386
387 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
388 u32 val)
389 {
390 if (sc_reg > SCR_CONTROL)
391 return;
392 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
393 }
394
395 static void pdc_qc_prep(struct ata_queued_cmd *qc)
396 {
397 struct pdc_port_priv *pp = qc->ap->private_data;
398 unsigned int i;
399
400 VPRINTK("ENTER\n");
401
402 switch (qc->tf.protocol) {
403 case ATA_PROT_DMA:
404 ata_qc_prep(qc);
405 /* fall through */
406
407 case ATA_PROT_NODATA:
408 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
409 qc->dev->devno, pp->pkt);
410
411 if (qc->tf.flags & ATA_TFLAG_LBA48)
412 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
413 else
414 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
415
416 pdc_pkt_footer(&qc->tf, pp->pkt, i);
417 break;
418
419 default:
420 break;
421 }
422 }
423
424 static void pdc_eng_timeout(struct ata_port *ap)
425 {
426 struct ata_host_set *host_set = ap->host_set;
427 u8 drv_stat;
428 struct ata_queued_cmd *qc;
429 unsigned long flags;
430
431 DPRINTK("ENTER\n");
432
433 spin_lock_irqsave(&host_set->lock, flags);
434
435 qc = ata_qc_from_tag(ap, ap->active_tag);
436
437 switch (qc->tf.protocol) {
438 case ATA_PROT_DMA:
439 case ATA_PROT_NODATA:
440 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
441 drv_stat = ata_wait_idle(ap);
442 qc->err_mask |= __ac_err_mask(drv_stat);
443 break;
444
445 default:
446 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
447
448 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
449 ap->id, qc->tf.command, drv_stat);
450
451 qc->err_mask |= ac_err_mask(drv_stat);
452 break;
453 }
454
455 spin_unlock_irqrestore(&host_set->lock, flags);
456 ata_eh_qc_complete(qc);
457 DPRINTK("EXIT\n");
458 }
459
460 static inline unsigned int pdc_host_intr( struct ata_port *ap,
461 struct ata_queued_cmd *qc)
462 {
463 unsigned int handled = 0;
464 u32 tmp;
465 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
466
467 tmp = readl(mmio);
468 if (tmp & PDC_ERR_MASK) {
469 qc->err_mask |= AC_ERR_DEV;
470 pdc_reset_port(ap);
471 }
472
473 switch (qc->tf.protocol) {
474 case ATA_PROT_DMA:
475 case ATA_PROT_NODATA:
476 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
477 ata_qc_complete(qc);
478 handled = 1;
479 break;
480
481 default:
482 ap->stats.idle_irq++;
483 break;
484 }
485
486 return handled;
487 }
488
489 static void pdc_irq_clear(struct ata_port *ap)
490 {
491 struct ata_host_set *host_set = ap->host_set;
492 void __iomem *mmio = host_set->mmio_base;
493
494 readl(mmio + PDC_INT_SEQMASK);
495 }
496
497 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
498 {
499 struct ata_host_set *host_set = dev_instance;
500 struct ata_port *ap;
501 u32 mask = 0;
502 unsigned int i, tmp;
503 unsigned int handled = 0;
504 void __iomem *mmio_base;
505
506 VPRINTK("ENTER\n");
507
508 if (!host_set || !host_set->mmio_base) {
509 VPRINTK("QUICK EXIT\n");
510 return IRQ_NONE;
511 }
512
513 mmio_base = host_set->mmio_base;
514
515 /* reading should also clear interrupts */
516 mask = readl(mmio_base + PDC_INT_SEQMASK);
517
518 if (mask == 0xffffffff) {
519 VPRINTK("QUICK EXIT 2\n");
520 return IRQ_NONE;
521 }
522
523 spin_lock(&host_set->lock);
524
525 mask &= 0xffff; /* only 16 tags possible */
526 if (!mask) {
527 VPRINTK("QUICK EXIT 3\n");
528 goto done_irq;
529 }
530
531 writel(mask, mmio_base + PDC_INT_SEQMASK);
532
533 for (i = 0; i < host_set->n_ports; i++) {
534 VPRINTK("port %u\n", i);
535 ap = host_set->ports[i];
536 tmp = mask & (1 << (i + 1));
537 if (tmp && ap &&
538 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
539 struct ata_queued_cmd *qc;
540
541 qc = ata_qc_from_tag(ap, ap->active_tag);
542 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
543 handled += pdc_host_intr(ap, qc);
544 }
545 }
546
547 VPRINTK("EXIT\n");
548
549 done_irq:
550 spin_unlock(&host_set->lock);
551 return IRQ_RETVAL(handled);
552 }
553
554 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
555 {
556 struct ata_port *ap = qc->ap;
557 struct pdc_port_priv *pp = ap->private_data;
558 unsigned int port_no = ap->port_no;
559 u8 seq = (u8) (port_no + 1);
560
561 VPRINTK("ENTER, ap %p\n", ap);
562
563 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
564 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
565
566 pp->pkt[2] = seq;
567 wmb(); /* flush PRD, pkt writes */
568 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
569 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
570 }
571
572 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
573 {
574 switch (qc->tf.protocol) {
575 case ATA_PROT_DMA:
576 case ATA_PROT_NODATA:
577 pdc_packet_start(qc);
578 return 0;
579
580 case ATA_PROT_ATAPI_DMA:
581 BUG();
582 break;
583
584 default:
585 break;
586 }
587
588 return ata_qc_issue_prot(qc);
589 }
590
591 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
592 {
593 WARN_ON (tf->protocol == ATA_PROT_DMA ||
594 tf->protocol == ATA_PROT_NODATA);
595 ata_tf_load(ap, tf);
596 }
597
598
599 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
600 {
601 WARN_ON (tf->protocol == ATA_PROT_DMA ||
602 tf->protocol == ATA_PROT_NODATA);
603 ata_exec_command(ap, tf);
604 }
605
606
607 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
608 {
609 port->cmd_addr = base;
610 port->data_addr = base;
611 port->feature_addr =
612 port->error_addr = base + 0x4;
613 port->nsect_addr = base + 0x8;
614 port->lbal_addr = base + 0xc;
615 port->lbam_addr = base + 0x10;
616 port->lbah_addr = base + 0x14;
617 port->device_addr = base + 0x18;
618 port->command_addr =
619 port->status_addr = base + 0x1c;
620 port->altstatus_addr =
621 port->ctl_addr = base + 0x38;
622 }
623
624
625 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
626 {
627 void __iomem *mmio = pe->mmio_base;
628 struct pdc_host_priv *hp = pe->private_data;
629 int hotplug_offset = hp->hotplug_offset;
630 u32 tmp;
631
632 /*
633 * Except for the hotplug stuff, this is voodoo from the
634 * Promise driver. Label this entire section
635 * "TODO: figure out why we do this"
636 */
637
638 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
639 tmp = readl(mmio + PDC_FLASH_CTL);
640 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
641 writel(tmp, mmio + PDC_FLASH_CTL);
642
643 /* clear plug/unplug flags for all ports */
644 tmp = readl(mmio + hotplug_offset);
645 writel(tmp | 0xff, mmio + hotplug_offset);
646
647 /* mask plug/unplug ints */
648 tmp = readl(mmio + hotplug_offset);
649 writel(tmp | 0xff0000, mmio + hotplug_offset);
650
651 /* reduce TBG clock to 133 Mhz. */
652 tmp = readl(mmio + PDC_TBG_MODE);
653 tmp &= ~0x30000; /* clear bit 17, 16*/
654 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
655 writel(tmp, mmio + PDC_TBG_MODE);
656
657 readl(mmio + PDC_TBG_MODE); /* flush */
658 msleep(10);
659
660 /* adjust slew rate control register. */
661 tmp = readl(mmio + PDC_SLEW_CTL);
662 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
663 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
664 writel(tmp, mmio + PDC_SLEW_CTL);
665 }
666
667 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
668 {
669 static int printed_version;
670 struct ata_probe_ent *probe_ent = NULL;
671 struct pdc_host_priv *hp;
672 unsigned long base;
673 void __iomem *mmio_base;
674 unsigned int board_idx = (unsigned int) ent->driver_data;
675 int pci_dev_busy = 0;
676 int rc;
677
678 if (!printed_version++)
679 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
680
681 /*
682 * If this driver happens to only be useful on Apple's K2, then
683 * we should check that here as it has a normal Serverworks ID
684 */
685 rc = pci_enable_device(pdev);
686 if (rc)
687 return rc;
688
689 rc = pci_request_regions(pdev, DRV_NAME);
690 if (rc) {
691 pci_dev_busy = 1;
692 goto err_out;
693 }
694
695 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
696 if (rc)
697 goto err_out_regions;
698 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
699 if (rc)
700 goto err_out_regions;
701
702 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
703 if (probe_ent == NULL) {
704 rc = -ENOMEM;
705 goto err_out_regions;
706 }
707
708 probe_ent->dev = pci_dev_to_dev(pdev);
709 INIT_LIST_HEAD(&probe_ent->node);
710
711 mmio_base = pci_iomap(pdev, 3, 0);
712 if (mmio_base == NULL) {
713 rc = -ENOMEM;
714 goto err_out_free_ent;
715 }
716 base = (unsigned long) mmio_base;
717
718 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
719 if (hp == NULL) {
720 rc = -ENOMEM;
721 goto err_out_free_ent;
722 }
723
724 /* Set default hotplug offset */
725 hp->hotplug_offset = PDC_SATA_PLUG_CSR;
726 probe_ent->private_data = hp;
727
728 probe_ent->sht = pdc_port_info[board_idx].sht;
729 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
730 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
731 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
732 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
733 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
734
735 probe_ent->irq = pdev->irq;
736 probe_ent->irq_flags = SA_SHIRQ;
737 probe_ent->mmio_base = mmio_base;
738
739 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
740 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
741
742 probe_ent->port[0].scr_addr = base + 0x400;
743 probe_ent->port[1].scr_addr = base + 0x500;
744
745 /* notice 4-port boards */
746 switch (board_idx) {
747 case board_40518:
748 /* Override hotplug offset for SATAII150 */
749 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
750 /* Fall through */
751 case board_20319:
752 probe_ent->n_ports = 4;
753
754 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
755 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
756
757 probe_ent->port[2].scr_addr = base + 0x600;
758 probe_ent->port[3].scr_addr = base + 0x700;
759 break;
760 case board_2057x:
761 /* Override hotplug offset for SATAII150 */
762 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
763 /* Fall through */
764 case board_2037x:
765 probe_ent->n_ports = 2;
766 break;
767 case board_20771:
768 probe_ent->n_ports = 2;
769 break;
770 case board_20619:
771 probe_ent->n_ports = 4;
772
773 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
774 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
775
776 probe_ent->port[2].scr_addr = base + 0x600;
777 probe_ent->port[3].scr_addr = base + 0x700;
778 break;
779 default:
780 BUG();
781 break;
782 }
783
784 pci_set_master(pdev);
785
786 /* initialize adapter */
787 pdc_host_init(board_idx, probe_ent);
788
789 /* FIXME: Need any other frees than hp? */
790 if (!ata_device_add(probe_ent))
791 kfree(hp);
792
793 kfree(probe_ent);
794
795 return 0;
796
797 err_out_free_ent:
798 kfree(probe_ent);
799 err_out_regions:
800 pci_release_regions(pdev);
801 err_out:
802 if (!pci_dev_busy)
803 pci_disable_device(pdev);
804 return rc;
805 }
806
807
808 static int __init pdc_ata_init(void)
809 {
810 return pci_module_init(&pdc_ata_pci_driver);
811 }
812
813
814 static void __exit pdc_ata_exit(void)
815 {
816 pci_unregister_driver(&pdc_ata_pci_driver);
817 }
818
819
820 MODULE_AUTHOR("Jeff Garzik");
821 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
822 MODULE_LICENSE("GPL");
823 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
824 MODULE_VERSION(DRV_VERSION);
825
826 module_init(pdc_ata_init);
827 module_exit(pdc_ata_exit);
AMDTP streaming driver for the Linux FireWire stack (Juju)