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ASoC: Unconditionally enable WM8994 AIF1ADC TDM mode
[firewire-audio.git] / sound / soc / codecs / wm8994.c
bloba87046a96f2abb01df5bde6d23bc24c29c3bfa3a
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30
31 #include <linux/mfd/wm8994/core.h>
32 #include <linux/mfd/wm8994/registers.h>
33 #include <linux/mfd/wm8994/pdata.h>
34 #include <linux/mfd/wm8994/gpio.h>
35
36 #include "wm8994.h"
37 #include "wm_hubs.h"
38
39 static struct snd_soc_codec *wm8994_codec;
40 struct snd_soc_codec_device soc_codec_dev_wm8994;
41
42 struct fll_config {
43 int src;
44 int in;
45 int out;
46 };
47
48 #define WM8994_NUM_DRC 3
49 #define WM8994_NUM_EQ 3
50
51 static int wm8994_drc_base[] = {
52 WM8994_AIF1_DRC1_1,
53 WM8994_AIF1_DRC2_1,
54 WM8994_AIF2_DRC_1,
55 };
56
57 static int wm8994_retune_mobile_base[] = {
58 WM8994_AIF1_DAC1_EQ_GAINS_1,
59 WM8994_AIF1_DAC2_EQ_GAINS_1,
60 WM8994_AIF2_EQ_GAINS_1,
61 };
62
63 #define WM8994_REG_CACHE_SIZE 0x621
64
65 struct wm8994_micdet {
66 struct snd_soc_jack *jack;
67 int det;
68 int shrt;
69 };
70
71 /* codec private data */
72 struct wm8994_priv {
73 struct wm_hubs_data hubs;
74 struct snd_soc_codec codec;
75 u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
76 int sysclk[2];
77 int sysclk_rate[2];
78 int mclk[2];
79 int aifclk[2];
80 struct fll_config fll[2], fll_suspend[2];
81
82 int dac_rates[2];
83 int lrclk_shared[2];
84
85 /* Platform dependant DRC configuration */
86 const char **drc_texts;
87 int drc_cfg[WM8994_NUM_DRC];
88 struct soc_enum drc_enum;
89
90 /* Platform dependant ReTune mobile configuration */
91 int num_retune_mobile_texts;
92 const char **retune_mobile_texts;
93 int retune_mobile_cfg[WM8994_NUM_EQ];
94 struct soc_enum retune_mobile_enum;
95
96 struct wm8994_micdet micdet[2];
97
98 struct wm8994_pdata *pdata;
99 };
100
101 static struct {
102 unsigned short readable; /* Mask of readable bits */
103 unsigned short writable; /* Mask of writable bits */
104 unsigned short vol; /* Mask of volatile bits */
105 } access_masks[] = {
106 { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Software Reset */
107 { 0x3B37, 0x3B37, 0x0000 }, /* R1 - Power Management (1) */
108 { 0x6BF0, 0x6BF0, 0x0000 }, /* R2 - Power Management (2) */
109 { 0x3FF0, 0x3FF0, 0x0000 }, /* R3 - Power Management (3) */
110 { 0x3F3F, 0x3F3F, 0x0000 }, /* R4 - Power Management (4) */
111 { 0x3F0F, 0x3F0F, 0x0000 }, /* R5 - Power Management (5) */
112 { 0x003F, 0x003F, 0x0000 }, /* R6 - Power Management (6) */
113 { 0x0000, 0x0000, 0x0000 }, /* R7 */
114 { 0x0000, 0x0000, 0x0000 }, /* R8 */
115 { 0x0000, 0x0000, 0x0000 }, /* R9 */
116 { 0x0000, 0x0000, 0x0000 }, /* R10 */
117 { 0x0000, 0x0000, 0x0000 }, /* R11 */
118 { 0x0000, 0x0000, 0x0000 }, /* R12 */
119 { 0x0000, 0x0000, 0x0000 }, /* R13 */
120 { 0x0000, 0x0000, 0x0000 }, /* R14 */
121 { 0x0000, 0x0000, 0x0000 }, /* R15 */
122 { 0x0000, 0x0000, 0x0000 }, /* R16 */
123 { 0x0000, 0x0000, 0x0000 }, /* R17 */
124 { 0x0000, 0x0000, 0x0000 }, /* R18 */
125 { 0x0000, 0x0000, 0x0000 }, /* R19 */
126 { 0x0000, 0x0000, 0x0000 }, /* R20 */
127 { 0x01C0, 0x01C0, 0x0000 }, /* R21 - Input Mixer (1) */
128 { 0x0000, 0x0000, 0x0000 }, /* R22 */
129 { 0x0000, 0x0000, 0x0000 }, /* R23 */
130 { 0x00DF, 0x01DF, 0x0000 }, /* R24 - Left Line Input 1&2 Volume */
131 { 0x00DF, 0x01DF, 0x0000 }, /* R25 - Left Line Input 3&4 Volume */
132 { 0x00DF, 0x01DF, 0x0000 }, /* R26 - Right Line Input 1&2 Volume */
133 { 0x00DF, 0x01DF, 0x0000 }, /* R27 - Right Line Input 3&4 Volume */
134 { 0x00FF, 0x01FF, 0x0000 }, /* R28 - Left Output Volume */
135 { 0x00FF, 0x01FF, 0x0000 }, /* R29 - Right Output Volume */
136 { 0x0077, 0x0077, 0x0000 }, /* R30 - Line Outputs Volume */
137 { 0x0030, 0x0030, 0x0000 }, /* R31 - HPOUT2 Volume */
138 { 0x00FF, 0x01FF, 0x0000 }, /* R32 - Left OPGA Volume */
139 { 0x00FF, 0x01FF, 0x0000 }, /* R33 - Right OPGA Volume */
140 { 0x007F, 0x007F, 0x0000 }, /* R34 - SPKMIXL Attenuation */
141 { 0x017F, 0x017F, 0x0000 }, /* R35 - SPKMIXR Attenuation */
142 { 0x003F, 0x003F, 0x0000 }, /* R36 - SPKOUT Mixers */
143 { 0x003F, 0x003F, 0x0000 }, /* R37 - ClassD */
144 { 0x00FF, 0x01FF, 0x0000 }, /* R38 - Speaker Volume Left */
145 { 0x00FF, 0x01FF, 0x0000 }, /* R39 - Speaker Volume Right */
146 { 0x00FF, 0x00FF, 0x0000 }, /* R40 - Input Mixer (2) */
147 { 0x01B7, 0x01B7, 0x0000 }, /* R41 - Input Mixer (3) */
148 { 0x01B7, 0x01B7, 0x0000 }, /* R42 - Input Mixer (4) */
149 { 0x01C7, 0x01C7, 0x0000 }, /* R43 - Input Mixer (5) */
150 { 0x01C7, 0x01C7, 0x0000 }, /* R44 - Input Mixer (6) */
151 { 0x01FF, 0x01FF, 0x0000 }, /* R45 - Output Mixer (1) */
152 { 0x01FF, 0x01FF, 0x0000 }, /* R46 - Output Mixer (2) */
153 { 0x0FFF, 0x0FFF, 0x0000 }, /* R47 - Output Mixer (3) */
154 { 0x0FFF, 0x0FFF, 0x0000 }, /* R48 - Output Mixer (4) */
155 { 0x0FFF, 0x0FFF, 0x0000 }, /* R49 - Output Mixer (5) */
156 { 0x0FFF, 0x0FFF, 0x0000 }, /* R50 - Output Mixer (6) */
157 { 0x0038, 0x0038, 0x0000 }, /* R51 - HPOUT2 Mixer */
158 { 0x0077, 0x0077, 0x0000 }, /* R52 - Line Mixer (1) */
159 { 0x0077, 0x0077, 0x0000 }, /* R53 - Line Mixer (2) */
160 { 0x03FF, 0x03FF, 0x0000 }, /* R54 - Speaker Mixer */
161 { 0x00C1, 0x00C1, 0x0000 }, /* R55 - Additional Control */
162 { 0x00F0, 0x00F0, 0x0000 }, /* R56 - AntiPOP (1) */
163 { 0x01EF, 0x01EF, 0x0000 }, /* R57 - AntiPOP (2) */
164 { 0x00FF, 0x00FF, 0x0000 }, /* R58 - MICBIAS */
165 { 0x000F, 0x000F, 0x0000 }, /* R59 - LDO 1 */
166 { 0x0007, 0x0007, 0x0000 }, /* R60 - LDO 2 */
167 { 0x0000, 0x0000, 0x0000 }, /* R61 */
168 { 0x0000, 0x0000, 0x0000 }, /* R62 */
169 { 0x0000, 0x0000, 0x0000 }, /* R63 */
170 { 0x0000, 0x0000, 0x0000 }, /* R64 */
171 { 0x0000, 0x0000, 0x0000 }, /* R65 */
172 { 0x0000, 0x0000, 0x0000 }, /* R66 */
173 { 0x0000, 0x0000, 0x0000 }, /* R67 */
174 { 0x0000, 0x0000, 0x0000 }, /* R68 */
175 { 0x0000, 0x0000, 0x0000 }, /* R69 */
176 { 0x0000, 0x0000, 0x0000 }, /* R70 */
177 { 0x0000, 0x0000, 0x0000 }, /* R71 */
178 { 0x0000, 0x0000, 0x0000 }, /* R72 */
179 { 0x0000, 0x0000, 0x0000 }, /* R73 */
180 { 0x0000, 0x0000, 0x0000 }, /* R74 */
181 { 0x0000, 0x0000, 0x0000 }, /* R75 */
182 { 0x8000, 0x8000, 0x0000 }, /* R76 - Charge Pump (1) */
183 { 0x0000, 0x0000, 0x0000 }, /* R77 */
184 { 0x0000, 0x0000, 0x0000 }, /* R78 */
185 { 0x0000, 0x0000, 0x0000 }, /* R79 */
186 { 0x0000, 0x0000, 0x0000 }, /* R80 */
187 { 0x0301, 0x0301, 0x0000 }, /* R81 - Class W (1) */
188 { 0x0000, 0x0000, 0x0000 }, /* R82 */
189 { 0x0000, 0x0000, 0x0000 }, /* R83 */
190 { 0x333F, 0x333F, 0x0000 }, /* R84 - DC Servo (1) */
191 { 0x0FEF, 0x0FEF, 0x0000 }, /* R85 - DC Servo (2) */
192 { 0x0000, 0x0000, 0x0000 }, /* R86 */
193 { 0xFFFF, 0xFFFF, 0x0000 }, /* R87 - DC Servo (4) */
194 { 0x0333, 0x0000, 0x0000 }, /* R88 - DC Servo Readback */
195 { 0x0000, 0x0000, 0x0000 }, /* R89 */
196 { 0x0000, 0x0000, 0x0000 }, /* R90 */
197 { 0x0000, 0x0000, 0x0000 }, /* R91 */
198 { 0x0000, 0x0000, 0x0000 }, /* R92 */
199 { 0x0000, 0x0000, 0x0000 }, /* R93 */
200 { 0x0000, 0x0000, 0x0000 }, /* R94 */
201 { 0x0000, 0x0000, 0x0000 }, /* R95 */
202 { 0x00EE, 0x00EE, 0x0000 }, /* R96 - Analogue HP (1) */
203 { 0x0000, 0x0000, 0x0000 }, /* R97 */
204 { 0x0000, 0x0000, 0x0000 }, /* R98 */
205 { 0x0000, 0x0000, 0x0000 }, /* R99 */
206 { 0x0000, 0x0000, 0x0000 }, /* R100 */
207 { 0x0000, 0x0000, 0x0000 }, /* R101 */
208 { 0x0000, 0x0000, 0x0000 }, /* R102 */
209 { 0x0000, 0x0000, 0x0000 }, /* R103 */
210 { 0x0000, 0x0000, 0x0000 }, /* R104 */
211 { 0x0000, 0x0000, 0x0000 }, /* R105 */
212 { 0x0000, 0x0000, 0x0000 }, /* R106 */
213 { 0x0000, 0x0000, 0x0000 }, /* R107 */
214 { 0x0000, 0x0000, 0x0000 }, /* R108 */
215 { 0x0000, 0x0000, 0x0000 }, /* R109 */
216 { 0x0000, 0x0000, 0x0000 }, /* R110 */
217 { 0x0000, 0x0000, 0x0000 }, /* R111 */
218 { 0x0000, 0x0000, 0x0000 }, /* R112 */
219 { 0x0000, 0x0000, 0x0000 }, /* R113 */
220 { 0x0000, 0x0000, 0x0000 }, /* R114 */
221 { 0x0000, 0x0000, 0x0000 }, /* R115 */
222 { 0x0000, 0x0000, 0x0000 }, /* R116 */
223 { 0x0000, 0x0000, 0x0000 }, /* R117 */
224 { 0x0000, 0x0000, 0x0000 }, /* R118 */
225 { 0x0000, 0x0000, 0x0000 }, /* R119 */
226 { 0x0000, 0x0000, 0x0000 }, /* R120 */
227 { 0x0000, 0x0000, 0x0000 }, /* R121 */
228 { 0x0000, 0x0000, 0x0000 }, /* R122 */
229 { 0x0000, 0x0000, 0x0000 }, /* R123 */
230 { 0x0000, 0x0000, 0x0000 }, /* R124 */
231 { 0x0000, 0x0000, 0x0000 }, /* R125 */
232 { 0x0000, 0x0000, 0x0000 }, /* R126 */
233 { 0x0000, 0x0000, 0x0000 }, /* R127 */
234 { 0x0000, 0x0000, 0x0000 }, /* R128 */
235 { 0x0000, 0x0000, 0x0000 }, /* R129 */
236 { 0x0000, 0x0000, 0x0000 }, /* R130 */
237 { 0x0000, 0x0000, 0x0000 }, /* R131 */
238 { 0x0000, 0x0000, 0x0000 }, /* R132 */
239 { 0x0000, 0x0000, 0x0000 }, /* R133 */
240 { 0x0000, 0x0000, 0x0000 }, /* R134 */
241 { 0x0000, 0x0000, 0x0000 }, /* R135 */
242 { 0x0000, 0x0000, 0x0000 }, /* R136 */
243 { 0x0000, 0x0000, 0x0000 }, /* R137 */
244 { 0x0000, 0x0000, 0x0000 }, /* R138 */
245 { 0x0000, 0x0000, 0x0000 }, /* R139 */
246 { 0x0000, 0x0000, 0x0000 }, /* R140 */
247 { 0x0000, 0x0000, 0x0000 }, /* R141 */
248 { 0x0000, 0x0000, 0x0000 }, /* R142 */
249 { 0x0000, 0x0000, 0x0000 }, /* R143 */
250 { 0x0000, 0x0000, 0x0000 }, /* R144 */
251 { 0x0000, 0x0000, 0x0000 }, /* R145 */
252 { 0x0000, 0x0000, 0x0000 }, /* R146 */
253 { 0x0000, 0x0000, 0x0000 }, /* R147 */
254 { 0x0000, 0x0000, 0x0000 }, /* R148 */
255 { 0x0000, 0x0000, 0x0000 }, /* R149 */
256 { 0x0000, 0x0000, 0x0000 }, /* R150 */
257 { 0x0000, 0x0000, 0x0000 }, /* R151 */
258 { 0x0000, 0x0000, 0x0000 }, /* R152 */
259 { 0x0000, 0x0000, 0x0000 }, /* R153 */
260 { 0x0000, 0x0000, 0x0000 }, /* R154 */
261 { 0x0000, 0x0000, 0x0000 }, /* R155 */
262 { 0x0000, 0x0000, 0x0000 }, /* R156 */
263 { 0x0000, 0x0000, 0x0000 }, /* R157 */
264 { 0x0000, 0x0000, 0x0000 }, /* R158 */
265 { 0x0000, 0x0000, 0x0000 }, /* R159 */
266 { 0x0000, 0x0000, 0x0000 }, /* R160 */
267 { 0x0000, 0x0000, 0x0000 }, /* R161 */
268 { 0x0000, 0x0000, 0x0000 }, /* R162 */
269 { 0x0000, 0x0000, 0x0000 }, /* R163 */
270 { 0x0000, 0x0000, 0x0000 }, /* R164 */
271 { 0x0000, 0x0000, 0x0000 }, /* R165 */
272 { 0x0000, 0x0000, 0x0000 }, /* R166 */
273 { 0x0000, 0x0000, 0x0000 }, /* R167 */
274 { 0x0000, 0x0000, 0x0000 }, /* R168 */
275 { 0x0000, 0x0000, 0x0000 }, /* R169 */
276 { 0x0000, 0x0000, 0x0000 }, /* R170 */
277 { 0x0000, 0x0000, 0x0000 }, /* R171 */
278 { 0x0000, 0x0000, 0x0000 }, /* R172 */
279 { 0x0000, 0x0000, 0x0000 }, /* R173 */
280 { 0x0000, 0x0000, 0x0000 }, /* R174 */
281 { 0x0000, 0x0000, 0x0000 }, /* R175 */
282 { 0x0000, 0x0000, 0x0000 }, /* R176 */
283 { 0x0000, 0x0000, 0x0000 }, /* R177 */
284 { 0x0000, 0x0000, 0x0000 }, /* R178 */
285 { 0x0000, 0x0000, 0x0000 }, /* R179 */
286 { 0x0000, 0x0000, 0x0000 }, /* R180 */
287 { 0x0000, 0x0000, 0x0000 }, /* R181 */
288 { 0x0000, 0x0000, 0x0000 }, /* R182 */
289 { 0x0000, 0x0000, 0x0000 }, /* R183 */
290 { 0x0000, 0x0000, 0x0000 }, /* R184 */
291 { 0x0000, 0x0000, 0x0000 }, /* R185 */
292 { 0x0000, 0x0000, 0x0000 }, /* R186 */
293 { 0x0000, 0x0000, 0x0000 }, /* R187 */
294 { 0x0000, 0x0000, 0x0000 }, /* R188 */
295 { 0x0000, 0x0000, 0x0000 }, /* R189 */
296 { 0x0000, 0x0000, 0x0000 }, /* R190 */
297 { 0x0000, 0x0000, 0x0000 }, /* R191 */
298 { 0x0000, 0x0000, 0x0000 }, /* R192 */
299 { 0x0000, 0x0000, 0x0000 }, /* R193 */
300 { 0x0000, 0x0000, 0x0000 }, /* R194 */
301 { 0x0000, 0x0000, 0x0000 }, /* R195 */
302 { 0x0000, 0x0000, 0x0000 }, /* R196 */
303 { 0x0000, 0x0000, 0x0000 }, /* R197 */
304 { 0x0000, 0x0000, 0x0000 }, /* R198 */
305 { 0x0000, 0x0000, 0x0000 }, /* R199 */
306 { 0x0000, 0x0000, 0x0000 }, /* R200 */
307 { 0x0000, 0x0000, 0x0000 }, /* R201 */
308 { 0x0000, 0x0000, 0x0000 }, /* R202 */
309 { 0x0000, 0x0000, 0x0000 }, /* R203 */
310 { 0x0000, 0x0000, 0x0000 }, /* R204 */
311 { 0x0000, 0x0000, 0x0000 }, /* R205 */
312 { 0x0000, 0x0000, 0x0000 }, /* R206 */
313 { 0x0000, 0x0000, 0x0000 }, /* R207 */
314 { 0x0000, 0x0000, 0x0000 }, /* R208 */
315 { 0x0000, 0x0000, 0x0000 }, /* R209 */
316 { 0x0000, 0x0000, 0x0000 }, /* R210 */
317 { 0x0000, 0x0000, 0x0000 }, /* R211 */
318 { 0x0000, 0x0000, 0x0000 }, /* R212 */
319 { 0x0000, 0x0000, 0x0000 }, /* R213 */
320 { 0x0000, 0x0000, 0x0000 }, /* R214 */
321 { 0x0000, 0x0000, 0x0000 }, /* R215 */
322 { 0x0000, 0x0000, 0x0000 }, /* R216 */
323 { 0x0000, 0x0000, 0x0000 }, /* R217 */
324 { 0x0000, 0x0000, 0x0000 }, /* R218 */
325 { 0x0000, 0x0000, 0x0000 }, /* R219 */
326 { 0x0000, 0x0000, 0x0000 }, /* R220 */
327 { 0x0000, 0x0000, 0x0000 }, /* R221 */
328 { 0x0000, 0x0000, 0x0000 }, /* R222 */
329 { 0x0000, 0x0000, 0x0000 }, /* R223 */
330 { 0x0000, 0x0000, 0x0000 }, /* R224 */
331 { 0x0000, 0x0000, 0x0000 }, /* R225 */
332 { 0x0000, 0x0000, 0x0000 }, /* R226 */
333 { 0x0000, 0x0000, 0x0000 }, /* R227 */
334 { 0x0000, 0x0000, 0x0000 }, /* R228 */
335 { 0x0000, 0x0000, 0x0000 }, /* R229 */
336 { 0x0000, 0x0000, 0x0000 }, /* R230 */
337 { 0x0000, 0x0000, 0x0000 }, /* R231 */
338 { 0x0000, 0x0000, 0x0000 }, /* R232 */
339 { 0x0000, 0x0000, 0x0000 }, /* R233 */
340 { 0x0000, 0x0000, 0x0000 }, /* R234 */
341 { 0x0000, 0x0000, 0x0000 }, /* R235 */
342 { 0x0000, 0x0000, 0x0000 }, /* R236 */
343 { 0x0000, 0x0000, 0x0000 }, /* R237 */
344 { 0x0000, 0x0000, 0x0000 }, /* R238 */
345 { 0x0000, 0x0000, 0x0000 }, /* R239 */
346 { 0x0000, 0x0000, 0x0000 }, /* R240 */
347 { 0x0000, 0x0000, 0x0000 }, /* R241 */
348 { 0x0000, 0x0000, 0x0000 }, /* R242 */
349 { 0x0000, 0x0000, 0x0000 }, /* R243 */
350 { 0x0000, 0x0000, 0x0000 }, /* R244 */
351 { 0x0000, 0x0000, 0x0000 }, /* R245 */
352 { 0x0000, 0x0000, 0x0000 }, /* R246 */
353 { 0x0000, 0x0000, 0x0000 }, /* R247 */
354 { 0x0000, 0x0000, 0x0000 }, /* R248 */
355 { 0x0000, 0x0000, 0x0000 }, /* R249 */
356 { 0x0000, 0x0000, 0x0000 }, /* R250 */
357 { 0x0000, 0x0000, 0x0000 }, /* R251 */
358 { 0x0000, 0x0000, 0x0000 }, /* R252 */
359 { 0x0000, 0x0000, 0x0000 }, /* R253 */
360 { 0x0000, 0x0000, 0x0000 }, /* R254 */
361 { 0x0000, 0x0000, 0x0000 }, /* R255 */
362 { 0x000F, 0x0000, 0x0000 }, /* R256 - Chip Revision */
363 { 0x0074, 0x0074, 0x0000 }, /* R257 - Control Interface */
364 { 0x0000, 0x0000, 0x0000 }, /* R258 */
365 { 0x0000, 0x0000, 0x0000 }, /* R259 */
366 { 0x0000, 0x0000, 0x0000 }, /* R260 */
367 { 0x0000, 0x0000, 0x0000 }, /* R261 */
368 { 0x0000, 0x0000, 0x0000 }, /* R262 */
369 { 0x0000, 0x0000, 0x0000 }, /* R263 */
370 { 0x0000, 0x0000, 0x0000 }, /* R264 */
371 { 0x0000, 0x0000, 0x0000 }, /* R265 */
372 { 0x0000, 0x0000, 0x0000 }, /* R266 */
373 { 0x0000, 0x0000, 0x0000 }, /* R267 */
374 { 0x0000, 0x0000, 0x0000 }, /* R268 */
375 { 0x0000, 0x0000, 0x0000 }, /* R269 */
376 { 0x0000, 0x0000, 0x0000 }, /* R270 */
377 { 0x0000, 0x0000, 0x0000 }, /* R271 */
378 { 0x807F, 0x837F, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */
379 { 0x017F, 0x0000, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
380 { 0x0000, 0x0000, 0x0000 }, /* R274 */
381 { 0x0000, 0x0000, 0x0000 }, /* R275 */
382 { 0x0000, 0x0000, 0x0000 }, /* R276 */
383 { 0x0000, 0x0000, 0x0000 }, /* R277 */
384 { 0x0000, 0x0000, 0x0000 }, /* R278 */
385 { 0x0000, 0x0000, 0x0000 }, /* R279 */
386 { 0x0000, 0x0000, 0x0000 }, /* R280 */
387 { 0x0000, 0x0000, 0x0000 }, /* R281 */
388 { 0x0000, 0x0000, 0x0000 }, /* R282 */
389 { 0x0000, 0x0000, 0x0000 }, /* R283 */
390 { 0x0000, 0x0000, 0x0000 }, /* R284 */
391 { 0x0000, 0x0000, 0x0000 }, /* R285 */
392 { 0x0000, 0x0000, 0x0000 }, /* R286 */
393 { 0x0000, 0x0000, 0x0000 }, /* R287 */
394 { 0x0000, 0x0000, 0x0000 }, /* R288 */
395 { 0x0000, 0x0000, 0x0000 }, /* R289 */
396 { 0x0000, 0x0000, 0x0000 }, /* R290 */
397 { 0x0000, 0x0000, 0x0000 }, /* R291 */
398 { 0x0000, 0x0000, 0x0000 }, /* R292 */
399 { 0x0000, 0x0000, 0x0000 }, /* R293 */
400 { 0x0000, 0x0000, 0x0000 }, /* R294 */
401 { 0x0000, 0x0000, 0x0000 }, /* R295 */
402 { 0x0000, 0x0000, 0x0000 }, /* R296 */
403 { 0x0000, 0x0000, 0x0000 }, /* R297 */
404 { 0x0000, 0x0000, 0x0000 }, /* R298 */
405 { 0x0000, 0x0000, 0x0000 }, /* R299 */
406 { 0x0000, 0x0000, 0x0000 }, /* R300 */
407 { 0x0000, 0x0000, 0x0000 }, /* R301 */
408 { 0x0000, 0x0000, 0x0000 }, /* R302 */
409 { 0x0000, 0x0000, 0x0000 }, /* R303 */
410 { 0x0000, 0x0000, 0x0000 }, /* R304 */
411 { 0x0000, 0x0000, 0x0000 }, /* R305 */
412 { 0x0000, 0x0000, 0x0000 }, /* R306 */
413 { 0x0000, 0x0000, 0x0000 }, /* R307 */
414 { 0x0000, 0x0000, 0x0000 }, /* R308 */
415 { 0x0000, 0x0000, 0x0000 }, /* R309 */
416 { 0x0000, 0x0000, 0x0000 }, /* R310 */
417 { 0x0000, 0x0000, 0x0000 }, /* R311 */
418 { 0x0000, 0x0000, 0x0000 }, /* R312 */
419 { 0x0000, 0x0000, 0x0000 }, /* R313 */
420 { 0x0000, 0x0000, 0x0000 }, /* R314 */
421 { 0x0000, 0x0000, 0x0000 }, /* R315 */
422 { 0x0000, 0x0000, 0x0000 }, /* R316 */
423 { 0x0000, 0x0000, 0x0000 }, /* R317 */
424 { 0x0000, 0x0000, 0x0000 }, /* R318 */
425 { 0x0000, 0x0000, 0x0000 }, /* R319 */
426 { 0x0000, 0x0000, 0x0000 }, /* R320 */
427 { 0x0000, 0x0000, 0x0000 }, /* R321 */
428 { 0x0000, 0x0000, 0x0000 }, /* R322 */
429 { 0x0000, 0x0000, 0x0000 }, /* R323 */
430 { 0x0000, 0x0000, 0x0000 }, /* R324 */
431 { 0x0000, 0x0000, 0x0000 }, /* R325 */
432 { 0x0000, 0x0000, 0x0000 }, /* R326 */
433 { 0x0000, 0x0000, 0x0000 }, /* R327 */
434 { 0x0000, 0x0000, 0x0000 }, /* R328 */
435 { 0x0000, 0x0000, 0x0000 }, /* R329 */
436 { 0x0000, 0x0000, 0x0000 }, /* R330 */
437 { 0x0000, 0x0000, 0x0000 }, /* R331 */
438 { 0x0000, 0x0000, 0x0000 }, /* R332 */
439 { 0x0000, 0x0000, 0x0000 }, /* R333 */
440 { 0x0000, 0x0000, 0x0000 }, /* R334 */
441 { 0x0000, 0x0000, 0x0000 }, /* R335 */
442 { 0x0000, 0x0000, 0x0000 }, /* R336 */
443 { 0x0000, 0x0000, 0x0000 }, /* R337 */
444 { 0x0000, 0x0000, 0x0000 }, /* R338 */
445 { 0x0000, 0x0000, 0x0000 }, /* R339 */
446 { 0x0000, 0x0000, 0x0000 }, /* R340 */
447 { 0x0000, 0x0000, 0x0000 }, /* R341 */
448 { 0x0000, 0x0000, 0x0000 }, /* R342 */
449 { 0x0000, 0x0000, 0x0000 }, /* R343 */
450 { 0x0000, 0x0000, 0x0000 }, /* R344 */
451 { 0x0000, 0x0000, 0x0000 }, /* R345 */
452 { 0x0000, 0x0000, 0x0000 }, /* R346 */
453 { 0x0000, 0x0000, 0x0000 }, /* R347 */
454 { 0x0000, 0x0000, 0x0000 }, /* R348 */
455 { 0x0000, 0x0000, 0x0000 }, /* R349 */
456 { 0x0000, 0x0000, 0x0000 }, /* R350 */
457 { 0x0000, 0x0000, 0x0000 }, /* R351 */
458 { 0x0000, 0x0000, 0x0000 }, /* R352 */
459 { 0x0000, 0x0000, 0x0000 }, /* R353 */
460 { 0x0000, 0x0000, 0x0000 }, /* R354 */
461 { 0x0000, 0x0000, 0x0000 }, /* R355 */
462 { 0x0000, 0x0000, 0x0000 }, /* R356 */
463 { 0x0000, 0x0000, 0x0000 }, /* R357 */
464 { 0x0000, 0x0000, 0x0000 }, /* R358 */
465 { 0x0000, 0x0000, 0x0000 }, /* R359 */
466 { 0x0000, 0x0000, 0x0000 }, /* R360 */
467 { 0x0000, 0x0000, 0x0000 }, /* R361 */
468 { 0x0000, 0x0000, 0x0000 }, /* R362 */
469 { 0x0000, 0x0000, 0x0000 }, /* R363 */
470 { 0x0000, 0x0000, 0x0000 }, /* R364 */
471 { 0x0000, 0x0000, 0x0000 }, /* R365 */
472 { 0x0000, 0x0000, 0x0000 }, /* R366 */
473 { 0x0000, 0x0000, 0x0000 }, /* R367 */
474 { 0x0000, 0x0000, 0x0000 }, /* R368 */
475 { 0x0000, 0x0000, 0x0000 }, /* R369 */
476 { 0x0000, 0x0000, 0x0000 }, /* R370 */
477 { 0x0000, 0x0000, 0x0000 }, /* R371 */
478 { 0x0000, 0x0000, 0x0000 }, /* R372 */
479 { 0x0000, 0x0000, 0x0000 }, /* R373 */
480 { 0x0000, 0x0000, 0x0000 }, /* R374 */
481 { 0x0000, 0x0000, 0x0000 }, /* R375 */
482 { 0x0000, 0x0000, 0x0000 }, /* R376 */
483 { 0x0000, 0x0000, 0x0000 }, /* R377 */
484 { 0x0000, 0x0000, 0x0000 }, /* R378 */
485 { 0x0000, 0x0000, 0x0000 }, /* R379 */
486 { 0x0000, 0x0000, 0x0000 }, /* R380 */
487 { 0x0000, 0x0000, 0x0000 }, /* R381 */
488 { 0x0000, 0x0000, 0x0000 }, /* R382 */
489 { 0x0000, 0x0000, 0x0000 }, /* R383 */
490 { 0x0000, 0x0000, 0x0000 }, /* R384 */
491 { 0x0000, 0x0000, 0x0000 }, /* R385 */
492 { 0x0000, 0x0000, 0x0000 }, /* R386 */
493 { 0x0000, 0x0000, 0x0000 }, /* R387 */
494 { 0x0000, 0x0000, 0x0000 }, /* R388 */
495 { 0x0000, 0x0000, 0x0000 }, /* R389 */
496 { 0x0000, 0x0000, 0x0000 }, /* R390 */
497 { 0x0000, 0x0000, 0x0000 }, /* R391 */
498 { 0x0000, 0x0000, 0x0000 }, /* R392 */
499 { 0x0000, 0x0000, 0x0000 }, /* R393 */
500 { 0x0000, 0x0000, 0x0000 }, /* R394 */
501 { 0x0000, 0x0000, 0x0000 }, /* R395 */
502 { 0x0000, 0x0000, 0x0000 }, /* R396 */
503 { 0x0000, 0x0000, 0x0000 }, /* R397 */
504 { 0x0000, 0x0000, 0x0000 }, /* R398 */
505 { 0x0000, 0x0000, 0x0000 }, /* R399 */
506 { 0x0000, 0x0000, 0x0000 }, /* R400 */
507 { 0x0000, 0x0000, 0x0000 }, /* R401 */
508 { 0x0000, 0x0000, 0x0000 }, /* R402 */
509 { 0x0000, 0x0000, 0x0000 }, /* R403 */
510 { 0x0000, 0x0000, 0x0000 }, /* R404 */
511 { 0x0000, 0x0000, 0x0000 }, /* R405 */
512 { 0x0000, 0x0000, 0x0000 }, /* R406 */
513 { 0x0000, 0x0000, 0x0000 }, /* R407 */
514 { 0x0000, 0x0000, 0x0000 }, /* R408 */
515 { 0x0000, 0x0000, 0x0000 }, /* R409 */
516 { 0x0000, 0x0000, 0x0000 }, /* R410 */
517 { 0x0000, 0x0000, 0x0000 }, /* R411 */
518 { 0x0000, 0x0000, 0x0000 }, /* R412 */
519 { 0x0000, 0x0000, 0x0000 }, /* R413 */
520 { 0x0000, 0x0000, 0x0000 }, /* R414 */
521 { 0x0000, 0x0000, 0x0000 }, /* R415 */
522 { 0x0000, 0x0000, 0x0000 }, /* R416 */
523 { 0x0000, 0x0000, 0x0000 }, /* R417 */
524 { 0x0000, 0x0000, 0x0000 }, /* R418 */
525 { 0x0000, 0x0000, 0x0000 }, /* R419 */
526 { 0x0000, 0x0000, 0x0000 }, /* R420 */
527 { 0x0000, 0x0000, 0x0000 }, /* R421 */
528 { 0x0000, 0x0000, 0x0000 }, /* R422 */
529 { 0x0000, 0x0000, 0x0000 }, /* R423 */
530 { 0x0000, 0x0000, 0x0000 }, /* R424 */
531 { 0x0000, 0x0000, 0x0000 }, /* R425 */
532 { 0x0000, 0x0000, 0x0000 }, /* R426 */
533 { 0x0000, 0x0000, 0x0000 }, /* R427 */
534 { 0x0000, 0x0000, 0x0000 }, /* R428 */
535 { 0x0000, 0x0000, 0x0000 }, /* R429 */
536 { 0x0000, 0x0000, 0x0000 }, /* R430 */
537 { 0x0000, 0x0000, 0x0000 }, /* R431 */
538 { 0x0000, 0x0000, 0x0000 }, /* R432 */
539 { 0x0000, 0x0000, 0x0000 }, /* R433 */
540 { 0x0000, 0x0000, 0x0000 }, /* R434 */
541 { 0x0000, 0x0000, 0x0000 }, /* R435 */
542 { 0x0000, 0x0000, 0x0000 }, /* R436 */
543 { 0x0000, 0x0000, 0x0000 }, /* R437 */
544 { 0x0000, 0x0000, 0x0000 }, /* R438 */
545 { 0x0000, 0x0000, 0x0000 }, /* R439 */
546 { 0x0000, 0x0000, 0x0000 }, /* R440 */
547 { 0x0000, 0x0000, 0x0000 }, /* R441 */
548 { 0x0000, 0x0000, 0x0000 }, /* R442 */
549 { 0x0000, 0x0000, 0x0000 }, /* R443 */
550 { 0x0000, 0x0000, 0x0000 }, /* R444 */
551 { 0x0000, 0x0000, 0x0000 }, /* R445 */
552 { 0x0000, 0x0000, 0x0000 }, /* R446 */
553 { 0x0000, 0x0000, 0x0000 }, /* R447 */
554 { 0x0000, 0x0000, 0x0000 }, /* R448 */
555 { 0x0000, 0x0000, 0x0000 }, /* R449 */
556 { 0x0000, 0x0000, 0x0000 }, /* R450 */
557 { 0x0000, 0x0000, 0x0000 }, /* R451 */
558 { 0x0000, 0x0000, 0x0000 }, /* R452 */
559 { 0x0000, 0x0000, 0x0000 }, /* R453 */
560 { 0x0000, 0x0000, 0x0000 }, /* R454 */
561 { 0x0000, 0x0000, 0x0000 }, /* R455 */
562 { 0x0000, 0x0000, 0x0000 }, /* R456 */
563 { 0x0000, 0x0000, 0x0000 }, /* R457 */
564 { 0x0000, 0x0000, 0x0000 }, /* R458 */
565 { 0x0000, 0x0000, 0x0000 }, /* R459 */
566 { 0x0000, 0x0000, 0x0000 }, /* R460 */
567 { 0x0000, 0x0000, 0x0000 }, /* R461 */
568 { 0x0000, 0x0000, 0x0000 }, /* R462 */
569 { 0x0000, 0x0000, 0x0000 }, /* R463 */
570 { 0x0000, 0x0000, 0x0000 }, /* R464 */
571 { 0x0000, 0x0000, 0x0000 }, /* R465 */
572 { 0x0000, 0x0000, 0x0000 }, /* R466 */
573 { 0x0000, 0x0000, 0x0000 }, /* R467 */
574 { 0x0000, 0x0000, 0x0000 }, /* R468 */
575 { 0x0000, 0x0000, 0x0000 }, /* R469 */
576 { 0x0000, 0x0000, 0x0000 }, /* R470 */
577 { 0x0000, 0x0000, 0x0000 }, /* R471 */
578 { 0x0000, 0x0000, 0x0000 }, /* R472 */
579 { 0x0000, 0x0000, 0x0000 }, /* R473 */
580 { 0x0000, 0x0000, 0x0000 }, /* R474 */
581 { 0x0000, 0x0000, 0x0000 }, /* R475 */
582 { 0x0000, 0x0000, 0x0000 }, /* R476 */
583 { 0x0000, 0x0000, 0x0000 }, /* R477 */
584 { 0x0000, 0x0000, 0x0000 }, /* R478 */
585 { 0x0000, 0x0000, 0x0000 }, /* R479 */
586 { 0x0000, 0x0000, 0x0000 }, /* R480 */
587 { 0x0000, 0x0000, 0x0000 }, /* R481 */
588 { 0x0000, 0x0000, 0x0000 }, /* R482 */
589 { 0x0000, 0x0000, 0x0000 }, /* R483 */
590 { 0x0000, 0x0000, 0x0000 }, /* R484 */
591 { 0x0000, 0x0000, 0x0000 }, /* R485 */
592 { 0x0000, 0x0000, 0x0000 }, /* R486 */
593 { 0x0000, 0x0000, 0x0000 }, /* R487 */
594 { 0x0000, 0x0000, 0x0000 }, /* R488 */
595 { 0x0000, 0x0000, 0x0000 }, /* R489 */
596 { 0x0000, 0x0000, 0x0000 }, /* R490 */
597 { 0x0000, 0x0000, 0x0000 }, /* R491 */
598 { 0x0000, 0x0000, 0x0000 }, /* R492 */
599 { 0x0000, 0x0000, 0x0000 }, /* R493 */
600 { 0x0000, 0x0000, 0x0000 }, /* R494 */
601 { 0x0000, 0x0000, 0x0000 }, /* R495 */
602 { 0x0000, 0x0000, 0x0000 }, /* R496 */
603 { 0x0000, 0x0000, 0x0000 }, /* R497 */
604 { 0x0000, 0x0000, 0x0000 }, /* R498 */
605 { 0x0000, 0x0000, 0x0000 }, /* R499 */
606 { 0x0000, 0x0000, 0x0000 }, /* R500 */
607 { 0x0000, 0x0000, 0x0000 }, /* R501 */
608 { 0x0000, 0x0000, 0x0000 }, /* R502 */
609 { 0x0000, 0x0000, 0x0000 }, /* R503 */
610 { 0x0000, 0x0000, 0x0000 }, /* R504 */
611 { 0x0000, 0x0000, 0x0000 }, /* R505 */
612 { 0x0000, 0x0000, 0x0000 }, /* R506 */
613 { 0x0000, 0x0000, 0x0000 }, /* R507 */
614 { 0x0000, 0x0000, 0x0000 }, /* R508 */
615 { 0x0000, 0x0000, 0x0000 }, /* R509 */
616 { 0x0000, 0x0000, 0x0000 }, /* R510 */
617 { 0x0000, 0x0000, 0x0000 }, /* R511 */
618 { 0x001F, 0x001F, 0x0000 }, /* R512 - AIF1 Clocking (1) */
619 { 0x003F, 0x003F, 0x0000 }, /* R513 - AIF1 Clocking (2) */
620 { 0x0000, 0x0000, 0x0000 }, /* R514 */
621 { 0x0000, 0x0000, 0x0000 }, /* R515 */
622 { 0x001F, 0x001F, 0x0000 }, /* R516 - AIF2 Clocking (1) */
623 { 0x003F, 0x003F, 0x0000 }, /* R517 - AIF2 Clocking (2) */
624 { 0x0000, 0x0000, 0x0000 }, /* R518 */
625 { 0x0000, 0x0000, 0x0000 }, /* R519 */
626 { 0x001F, 0x001F, 0x0000 }, /* R520 - Clocking (1) */
627 { 0x0777, 0x0777, 0x0000 }, /* R521 - Clocking (2) */
628 { 0x0000, 0x0000, 0x0000 }, /* R522 */
629 { 0x0000, 0x0000, 0x0000 }, /* R523 */
630 { 0x0000, 0x0000, 0x0000 }, /* R524 */
631 { 0x0000, 0x0000, 0x0000 }, /* R525 */
632 { 0x0000, 0x0000, 0x0000 }, /* R526 */
633 { 0x0000, 0x0000, 0x0000 }, /* R527 */
634 { 0x00FF, 0x00FF, 0x0000 }, /* R528 - AIF1 Rate */
635 { 0x00FF, 0x00FF, 0x0000 }, /* R529 - AIF2 Rate */
636 { 0x000F, 0x0000, 0x0000 }, /* R530 - Rate Status */
637 { 0x0000, 0x0000, 0x0000 }, /* R531 */
638 { 0x0000, 0x0000, 0x0000 }, /* R532 */
639 { 0x0000, 0x0000, 0x0000 }, /* R533 */
640 { 0x0000, 0x0000, 0x0000 }, /* R534 */
641 { 0x0000, 0x0000, 0x0000 }, /* R535 */
642 { 0x0000, 0x0000, 0x0000 }, /* R536 */
643 { 0x0000, 0x0000, 0x0000 }, /* R537 */
644 { 0x0000, 0x0000, 0x0000 }, /* R538 */
645 { 0x0000, 0x0000, 0x0000 }, /* R539 */
646 { 0x0000, 0x0000, 0x0000 }, /* R540 */
647 { 0x0000, 0x0000, 0x0000 }, /* R541 */
648 { 0x0000, 0x0000, 0x0000 }, /* R542 */
649 { 0x0000, 0x0000, 0x0000 }, /* R543 */
650 { 0x0007, 0x0007, 0x0000 }, /* R544 - FLL1 Control (1) */
651 { 0x3F77, 0x3F77, 0x0000 }, /* R545 - FLL1 Control (2) */
652 { 0xFFFF, 0xFFFF, 0x0000 }, /* R546 - FLL1 Control (3) */
653 { 0x7FEF, 0x7FEF, 0x0000 }, /* R547 - FLL1 Control (4) */
654 { 0x1FDB, 0x1FDB, 0x0000 }, /* R548 - FLL1 Control (5) */
655 { 0x0000, 0x0000, 0x0000 }, /* R549 */
656 { 0x0000, 0x0000, 0x0000 }, /* R550 */
657 { 0x0000, 0x0000, 0x0000 }, /* R551 */
658 { 0x0000, 0x0000, 0x0000 }, /* R552 */
659 { 0x0000, 0x0000, 0x0000 }, /* R553 */
660 { 0x0000, 0x0000, 0x0000 }, /* R554 */
661 { 0x0000, 0x0000, 0x0000 }, /* R555 */
662 { 0x0000, 0x0000, 0x0000 }, /* R556 */
663 { 0x0000, 0x0000, 0x0000 }, /* R557 */
664 { 0x0000, 0x0000, 0x0000 }, /* R558 */
665 { 0x0000, 0x0000, 0x0000 }, /* R559 */
666 { 0x0000, 0x0000, 0x0000 }, /* R560 */
667 { 0x0000, 0x0000, 0x0000 }, /* R561 */
668 { 0x0000, 0x0000, 0x0000 }, /* R562 */
669 { 0x0000, 0x0000, 0x0000 }, /* R563 */
670 { 0x0000, 0x0000, 0x0000 }, /* R564 */
671 { 0x0000, 0x0000, 0x0000 }, /* R565 */
672 { 0x0000, 0x0000, 0x0000 }, /* R566 */
673 { 0x0000, 0x0000, 0x0000 }, /* R567 */
674 { 0x0000, 0x0000, 0x0000 }, /* R568 */
675 { 0x0000, 0x0000, 0x0000 }, /* R569 */
676 { 0x0000, 0x0000, 0x0000 }, /* R570 */
677 { 0x0000, 0x0000, 0x0000 }, /* R571 */
678 { 0x0000, 0x0000, 0x0000 }, /* R572 */
679 { 0x0000, 0x0000, 0x0000 }, /* R573 */
680 { 0x0000, 0x0000, 0x0000 }, /* R574 */
681 { 0x0000, 0x0000, 0x0000 }, /* R575 */
682 { 0x0007, 0x0007, 0x0000 }, /* R576 - FLL2 Control (1) */
683 { 0x3F77, 0x3F77, 0x0000 }, /* R577 - FLL2 Control (2) */
684 { 0xFFFF, 0xFFFF, 0x0000 }, /* R578 - FLL2 Control (3) */
685 { 0x7FEF, 0x7FEF, 0x0000 }, /* R579 - FLL2 Control (4) */
686 { 0x1FDB, 0x1FDB, 0x0000 }, /* R580 - FLL2 Control (5) */
687 { 0x0000, 0x0000, 0x0000 }, /* R581 */
688 { 0x0000, 0x0000, 0x0000 }, /* R582 */
689 { 0x0000, 0x0000, 0x0000 }, /* R583 */
690 { 0x0000, 0x0000, 0x0000 }, /* R584 */
691 { 0x0000, 0x0000, 0x0000 }, /* R585 */
692 { 0x0000, 0x0000, 0x0000 }, /* R586 */
693 { 0x0000, 0x0000, 0x0000 }, /* R587 */
694 { 0x0000, 0x0000, 0x0000 }, /* R588 */
695 { 0x0000, 0x0000, 0x0000 }, /* R589 */
696 { 0x0000, 0x0000, 0x0000 }, /* R590 */
697 { 0x0000, 0x0000, 0x0000 }, /* R591 */
698 { 0x0000, 0x0000, 0x0000 }, /* R592 */
699 { 0x0000, 0x0000, 0x0000 }, /* R593 */
700 { 0x0000, 0x0000, 0x0000 }, /* R594 */
701 { 0x0000, 0x0000, 0x0000 }, /* R595 */
702 { 0x0000, 0x0000, 0x0000 }, /* R596 */
703 { 0x0000, 0x0000, 0x0000 }, /* R597 */
704 { 0x0000, 0x0000, 0x0000 }, /* R598 */
705 { 0x0000, 0x0000, 0x0000 }, /* R599 */
706 { 0x0000, 0x0000, 0x0000 }, /* R600 */
707 { 0x0000, 0x0000, 0x0000 }, /* R601 */
708 { 0x0000, 0x0000, 0x0000 }, /* R602 */
709 { 0x0000, 0x0000, 0x0000 }, /* R603 */
710 { 0x0000, 0x0000, 0x0000 }, /* R604 */
711 { 0x0000, 0x0000, 0x0000 }, /* R605 */
712 { 0x0000, 0x0000, 0x0000 }, /* R606 */
713 { 0x0000, 0x0000, 0x0000 }, /* R607 */
714 { 0x0000, 0x0000, 0x0000 }, /* R608 */
715 { 0x0000, 0x0000, 0x0000 }, /* R609 */
716 { 0x0000, 0x0000, 0x0000 }, /* R610 */
717 { 0x0000, 0x0000, 0x0000 }, /* R611 */
718 { 0x0000, 0x0000, 0x0000 }, /* R612 */
719 { 0x0000, 0x0000, 0x0000 }, /* R613 */
720 { 0x0000, 0x0000, 0x0000 }, /* R614 */
721 { 0x0000, 0x0000, 0x0000 }, /* R615 */
722 { 0x0000, 0x0000, 0x0000 }, /* R616 */
723 { 0x0000, 0x0000, 0x0000 }, /* R617 */
724 { 0x0000, 0x0000, 0x0000 }, /* R618 */
725 { 0x0000, 0x0000, 0x0000 }, /* R619 */
726 { 0x0000, 0x0000, 0x0000 }, /* R620 */
727 { 0x0000, 0x0000, 0x0000 }, /* R621 */
728 { 0x0000, 0x0000, 0x0000 }, /* R622 */
729 { 0x0000, 0x0000, 0x0000 }, /* R623 */
730 { 0x0000, 0x0000, 0x0000 }, /* R624 */
731 { 0x0000, 0x0000, 0x0000 }, /* R625 */
732 { 0x0000, 0x0000, 0x0000 }, /* R626 */
733 { 0x0000, 0x0000, 0x0000 }, /* R627 */
734 { 0x0000, 0x0000, 0x0000 }, /* R628 */
735 { 0x0000, 0x0000, 0x0000 }, /* R629 */
736 { 0x0000, 0x0000, 0x0000 }, /* R630 */
737 { 0x0000, 0x0000, 0x0000 }, /* R631 */
738 { 0x0000, 0x0000, 0x0000 }, /* R632 */
739 { 0x0000, 0x0000, 0x0000 }, /* R633 */
740 { 0x0000, 0x0000, 0x0000 }, /* R634 */
741 { 0x0000, 0x0000, 0x0000 }, /* R635 */
742 { 0x0000, 0x0000, 0x0000 }, /* R636 */
743 { 0x0000, 0x0000, 0x0000 }, /* R637 */
744 { 0x0000, 0x0000, 0x0000 }, /* R638 */
745 { 0x0000, 0x0000, 0x0000 }, /* R639 */
746 { 0x0000, 0x0000, 0x0000 }, /* R640 */
747 { 0x0000, 0x0000, 0x0000 }, /* R641 */
748 { 0x0000, 0x0000, 0x0000 }, /* R642 */
749 { 0x0000, 0x0000, 0x0000 }, /* R643 */
750 { 0x0000, 0x0000, 0x0000 }, /* R644 */
751 { 0x0000, 0x0000, 0x0000 }, /* R645 */
752 { 0x0000, 0x0000, 0x0000 }, /* R646 */
753 { 0x0000, 0x0000, 0x0000 }, /* R647 */
754 { 0x0000, 0x0000, 0x0000 }, /* R648 */
755 { 0x0000, 0x0000, 0x0000 }, /* R649 */
756 { 0x0000, 0x0000, 0x0000 }, /* R650 */
757 { 0x0000, 0x0000, 0x0000 }, /* R651 */
758 { 0x0000, 0x0000, 0x0000 }, /* R652 */
759 { 0x0000, 0x0000, 0x0000 }, /* R653 */
760 { 0x0000, 0x0000, 0x0000 }, /* R654 */
761 { 0x0000, 0x0000, 0x0000 }, /* R655 */
762 { 0x0000, 0x0000, 0x0000 }, /* R656 */
763 { 0x0000, 0x0000, 0x0000 }, /* R657 */
764 { 0x0000, 0x0000, 0x0000 }, /* R658 */
765 { 0x0000, 0x0000, 0x0000 }, /* R659 */
766 { 0x0000, 0x0000, 0x0000 }, /* R660 */
767 { 0x0000, 0x0000, 0x0000 }, /* R661 */
768 { 0x0000, 0x0000, 0x0000 }, /* R662 */
769 { 0x0000, 0x0000, 0x0000 }, /* R663 */
770 { 0x0000, 0x0000, 0x0000 }, /* R664 */
771 { 0x0000, 0x0000, 0x0000 }, /* R665 */
772 { 0x0000, 0x0000, 0x0000 }, /* R666 */
773 { 0x0000, 0x0000, 0x0000 }, /* R667 */
774 { 0x0000, 0x0000, 0x0000 }, /* R668 */
775 { 0x0000, 0x0000, 0x0000 }, /* R669 */
776 { 0x0000, 0x0000, 0x0000 }, /* R670 */
777 { 0x0000, 0x0000, 0x0000 }, /* R671 */
778 { 0x0000, 0x0000, 0x0000 }, /* R672 */
779 { 0x0000, 0x0000, 0x0000 }, /* R673 */
780 { 0x0000, 0x0000, 0x0000 }, /* R674 */
781 { 0x0000, 0x0000, 0x0000 }, /* R675 */
782 { 0x0000, 0x0000, 0x0000 }, /* R676 */
783 { 0x0000, 0x0000, 0x0000 }, /* R677 */
784 { 0x0000, 0x0000, 0x0000 }, /* R678 */
785 { 0x0000, 0x0000, 0x0000 }, /* R679 */
786 { 0x0000, 0x0000, 0x0000 }, /* R680 */
787 { 0x0000, 0x0000, 0x0000 }, /* R681 */
788 { 0x0000, 0x0000, 0x0000 }, /* R682 */
789 { 0x0000, 0x0000, 0x0000 }, /* R683 */
790 { 0x0000, 0x0000, 0x0000 }, /* R684 */
791 { 0x0000, 0x0000, 0x0000 }, /* R685 */
792 { 0x0000, 0x0000, 0x0000 }, /* R686 */
793 { 0x0000, 0x0000, 0x0000 }, /* R687 */
794 { 0x0000, 0x0000, 0x0000 }, /* R688 */
795 { 0x0000, 0x0000, 0x0000 }, /* R689 */
796 { 0x0000, 0x0000, 0x0000 }, /* R690 */
797 { 0x0000, 0x0000, 0x0000 }, /* R691 */
798 { 0x0000, 0x0000, 0x0000 }, /* R692 */
799 { 0x0000, 0x0000, 0x0000 }, /* R693 */
800 { 0x0000, 0x0000, 0x0000 }, /* R694 */
801 { 0x0000, 0x0000, 0x0000 }, /* R695 */
802 { 0x0000, 0x0000, 0x0000 }, /* R696 */
803 { 0x0000, 0x0000, 0x0000 }, /* R697 */
804 { 0x0000, 0x0000, 0x0000 }, /* R698 */
805 { 0x0000, 0x0000, 0x0000 }, /* R699 */
806 { 0x0000, 0x0000, 0x0000 }, /* R700 */
807 { 0x0000, 0x0000, 0x0000 }, /* R701 */
808 { 0x0000, 0x0000, 0x0000 }, /* R702 */
809 { 0x0000, 0x0000, 0x0000 }, /* R703 */
810 { 0x0000, 0x0000, 0x0000 }, /* R704 */
811 { 0x0000, 0x0000, 0x0000 }, /* R705 */
812 { 0x0000, 0x0000, 0x0000 }, /* R706 */
813 { 0x0000, 0x0000, 0x0000 }, /* R707 */
814 { 0x0000, 0x0000, 0x0000 }, /* R708 */
815 { 0x0000, 0x0000, 0x0000 }, /* R709 */
816 { 0x0000, 0x0000, 0x0000 }, /* R710 */
817 { 0x0000, 0x0000, 0x0000 }, /* R711 */
818 { 0x0000, 0x0000, 0x0000 }, /* R712 */
819 { 0x0000, 0x0000, 0x0000 }, /* R713 */
820 { 0x0000, 0x0000, 0x0000 }, /* R714 */
821 { 0x0000, 0x0000, 0x0000 }, /* R715 */
822 { 0x0000, 0x0000, 0x0000 }, /* R716 */
823 { 0x0000, 0x0000, 0x0000 }, /* R717 */
824 { 0x0000, 0x0000, 0x0000 }, /* R718 */
825 { 0x0000, 0x0000, 0x0000 }, /* R719 */
826 { 0x0000, 0x0000, 0x0000 }, /* R720 */
827 { 0x0000, 0x0000, 0x0000 }, /* R721 */
828 { 0x0000, 0x0000, 0x0000 }, /* R722 */
829 { 0x0000, 0x0000, 0x0000 }, /* R723 */
830 { 0x0000, 0x0000, 0x0000 }, /* R724 */
831 { 0x0000, 0x0000, 0x0000 }, /* R725 */
832 { 0x0000, 0x0000, 0x0000 }, /* R726 */
833 { 0x0000, 0x0000, 0x0000 }, /* R727 */
834 { 0x0000, 0x0000, 0x0000 }, /* R728 */
835 { 0x0000, 0x0000, 0x0000 }, /* R729 */
836 { 0x0000, 0x0000, 0x0000 }, /* R730 */
837 { 0x0000, 0x0000, 0x0000 }, /* R731 */
838 { 0x0000, 0x0000, 0x0000 }, /* R732 */
839 { 0x0000, 0x0000, 0x0000 }, /* R733 */
840 { 0x0000, 0x0000, 0x0000 }, /* R734 */
841 { 0x0000, 0x0000, 0x0000 }, /* R735 */
842 { 0x0000, 0x0000, 0x0000 }, /* R736 */
843 { 0x0000, 0x0000, 0x0000 }, /* R737 */
844 { 0x0000, 0x0000, 0x0000 }, /* R738 */
845 { 0x0000, 0x0000, 0x0000 }, /* R739 */
846 { 0x0000, 0x0000, 0x0000 }, /* R740 */
847 { 0x0000, 0x0000, 0x0000 }, /* R741 */
848 { 0x0000, 0x0000, 0x0000 }, /* R742 */
849 { 0x0000, 0x0000, 0x0000 }, /* R743 */
850 { 0x0000, 0x0000, 0x0000 }, /* R744 */
851 { 0x0000, 0x0000, 0x0000 }, /* R745 */
852 { 0x0000, 0x0000, 0x0000 }, /* R746 */
853 { 0x0000, 0x0000, 0x0000 }, /* R747 */
854 { 0x0000, 0x0000, 0x0000 }, /* R748 */
855 { 0x0000, 0x0000, 0x0000 }, /* R749 */
856 { 0x0000, 0x0000, 0x0000 }, /* R750 */
857 { 0x0000, 0x0000, 0x0000 }, /* R751 */
858 { 0x0000, 0x0000, 0x0000 }, /* R752 */
859 { 0x0000, 0x0000, 0x0000 }, /* R753 */
860 { 0x0000, 0x0000, 0x0000 }, /* R754 */
861 { 0x0000, 0x0000, 0x0000 }, /* R755 */
862 { 0x0000, 0x0000, 0x0000 }, /* R756 */
863 { 0x0000, 0x0000, 0x0000 }, /* R757 */
864 { 0x0000, 0x0000, 0x0000 }, /* R758 */
865 { 0x0000, 0x0000, 0x0000 }, /* R759 */
866 { 0x0000, 0x0000, 0x0000 }, /* R760 */
867 { 0x0000, 0x0000, 0x0000 }, /* R761 */
868 { 0x0000, 0x0000, 0x0000 }, /* R762 */
869 { 0x0000, 0x0000, 0x0000 }, /* R763 */
870 { 0x0000, 0x0000, 0x0000 }, /* R764 */
871 { 0x0000, 0x0000, 0x0000 }, /* R765 */
872 { 0x0000, 0x0000, 0x0000 }, /* R766 */
873 { 0x0000, 0x0000, 0x0000 }, /* R767 */
874 { 0xE1F8, 0xE1F8, 0x0000 }, /* R768 - AIF1 Control (1) */
875 { 0xCD1F, 0xCD1F, 0x0000 }, /* R769 - AIF1 Control (2) */
876 { 0xF000, 0xF000, 0x0000 }, /* R770 - AIF1 Master/Slave */
877 { 0x01F0, 0x01F0, 0x0000 }, /* R771 - AIF1 BCLK */
878 { 0x0FFF, 0x0FFF, 0x0000 }, /* R772 - AIF1ADC LRCLK */
879 { 0x0FFF, 0x0FFF, 0x0000 }, /* R773 - AIF1DAC LRCLK */
880 { 0x0003, 0x0003, 0x0000 }, /* R774 - AIF1DAC Data */
881 { 0x0003, 0x0003, 0x0000 }, /* R775 - AIF1ADC Data */
882 { 0x0000, 0x0000, 0x0000 }, /* R776 */
883 { 0x0000, 0x0000, 0x0000 }, /* R777 */
884 { 0x0000, 0x0000, 0x0000 }, /* R778 */
885 { 0x0000, 0x0000, 0x0000 }, /* R779 */
886 { 0x0000, 0x0000, 0x0000 }, /* R780 */
887 { 0x0000, 0x0000, 0x0000 }, /* R781 */
888 { 0x0000, 0x0000, 0x0000 }, /* R782 */
889 { 0x0000, 0x0000, 0x0000 }, /* R783 */
890 { 0xF1F8, 0xF1F8, 0x0000 }, /* R784 - AIF2 Control (1) */
891 { 0xFD1F, 0xFD1F, 0x0000 }, /* R785 - AIF2 Control (2) */
892 { 0xF000, 0xF000, 0x0000 }, /* R786 - AIF2 Master/Slave */
893 { 0x01F0, 0x01F0, 0x0000 }, /* R787 - AIF2 BCLK */
894 { 0x0FFF, 0x0FFF, 0x0000 }, /* R788 - AIF2ADC LRCLK */
895 { 0x0FFF, 0x0FFF, 0x0000 }, /* R789 - AIF2DAC LRCLK */
896 { 0x0003, 0x0003, 0x0000 }, /* R790 - AIF2DAC Data */
897 { 0x0003, 0x0003, 0x0000 }, /* R791 - AIF2ADC Data */
898 { 0x0000, 0x0000, 0x0000 }, /* R792 */
899 { 0x0000, 0x0000, 0x0000 }, /* R793 */
900 { 0x0000, 0x0000, 0x0000 }, /* R794 */
901 { 0x0000, 0x0000, 0x0000 }, /* R795 */
902 { 0x0000, 0x0000, 0x0000 }, /* R796 */
903 { 0x0000, 0x0000, 0x0000 }, /* R797 */
904 { 0x0000, 0x0000, 0x0000 }, /* R798 */
905 { 0x0000, 0x0000, 0x0000 }, /* R799 */
906 { 0x0000, 0x0000, 0x0000 }, /* R800 */
907 { 0x0000, 0x0000, 0x0000 }, /* R801 */
908 { 0x0000, 0x0000, 0x0000 }, /* R802 */
909 { 0x0000, 0x0000, 0x0000 }, /* R803 */
910 { 0x0000, 0x0000, 0x0000 }, /* R804 */
911 { 0x0000, 0x0000, 0x0000 }, /* R805 */
912 { 0x0000, 0x0000, 0x0000 }, /* R806 */
913 { 0x0000, 0x0000, 0x0000 }, /* R807 */
914 { 0x0000, 0x0000, 0x0000 }, /* R808 */
915 { 0x0000, 0x0000, 0x0000 }, /* R809 */
916 { 0x0000, 0x0000, 0x0000 }, /* R810 */
917 { 0x0000, 0x0000, 0x0000 }, /* R811 */
918 { 0x0000, 0x0000, 0x0000 }, /* R812 */
919 { 0x0000, 0x0000, 0x0000 }, /* R813 */
920 { 0x0000, 0x0000, 0x0000 }, /* R814 */
921 { 0x0000, 0x0000, 0x0000 }, /* R815 */
922 { 0x0000, 0x0000, 0x0000 }, /* R816 */
923 { 0x0000, 0x0000, 0x0000 }, /* R817 */
924 { 0x0000, 0x0000, 0x0000 }, /* R818 */
925 { 0x0000, 0x0000, 0x0000 }, /* R819 */
926 { 0x0000, 0x0000, 0x0000 }, /* R820 */
927 { 0x0000, 0x0000, 0x0000 }, /* R821 */
928 { 0x0000, 0x0000, 0x0000 }, /* R822 */
929 { 0x0000, 0x0000, 0x0000 }, /* R823 */
930 { 0x0000, 0x0000, 0x0000 }, /* R824 */
931 { 0x0000, 0x0000, 0x0000 }, /* R825 */
932 { 0x0000, 0x0000, 0x0000 }, /* R826 */
933 { 0x0000, 0x0000, 0x0000 }, /* R827 */
934 { 0x0000, 0x0000, 0x0000 }, /* R828 */
935 { 0x0000, 0x0000, 0x0000 }, /* R829 */
936 { 0x0000, 0x0000, 0x0000 }, /* R830 */
937 { 0x0000, 0x0000, 0x0000 }, /* R831 */
938 { 0x0000, 0x0000, 0x0000 }, /* R832 */
939 { 0x0000, 0x0000, 0x0000 }, /* R833 */
940 { 0x0000, 0x0000, 0x0000 }, /* R834 */
941 { 0x0000, 0x0000, 0x0000 }, /* R835 */
942 { 0x0000, 0x0000, 0x0000 }, /* R836 */
943 { 0x0000, 0x0000, 0x0000 }, /* R837 */
944 { 0x0000, 0x0000, 0x0000 }, /* R838 */
945 { 0x0000, 0x0000, 0x0000 }, /* R839 */
946 { 0x0000, 0x0000, 0x0000 }, /* R840 */
947 { 0x0000, 0x0000, 0x0000 }, /* R841 */
948 { 0x0000, 0x0000, 0x0000 }, /* R842 */
949 { 0x0000, 0x0000, 0x0000 }, /* R843 */
950 { 0x0000, 0x0000, 0x0000 }, /* R844 */
951 { 0x0000, 0x0000, 0x0000 }, /* R845 */
952 { 0x0000, 0x0000, 0x0000 }, /* R846 */
953 { 0x0000, 0x0000, 0x0000 }, /* R847 */
954 { 0x0000, 0x0000, 0x0000 }, /* R848 */
955 { 0x0000, 0x0000, 0x0000 }, /* R849 */
956 { 0x0000, 0x0000, 0x0000 }, /* R850 */
957 { 0x0000, 0x0000, 0x0000 }, /* R851 */
958 { 0x0000, 0x0000, 0x0000 }, /* R852 */
959 { 0x0000, 0x0000, 0x0000 }, /* R853 */
960 { 0x0000, 0x0000, 0x0000 }, /* R854 */
961 { 0x0000, 0x0000, 0x0000 }, /* R855 */
962 { 0x0000, 0x0000, 0x0000 }, /* R856 */
963 { 0x0000, 0x0000, 0x0000 }, /* R857 */
964 { 0x0000, 0x0000, 0x0000 }, /* R858 */
965 { 0x0000, 0x0000, 0x0000 }, /* R859 */
966 { 0x0000, 0x0000, 0x0000 }, /* R860 */
967 { 0x0000, 0x0000, 0x0000 }, /* R861 */
968 { 0x0000, 0x0000, 0x0000 }, /* R862 */
969 { 0x0000, 0x0000, 0x0000 }, /* R863 */
970 { 0x0000, 0x0000, 0x0000 }, /* R864 */
971 { 0x0000, 0x0000, 0x0000 }, /* R865 */
972 { 0x0000, 0x0000, 0x0000 }, /* R866 */
973 { 0x0000, 0x0000, 0x0000 }, /* R867 */
974 { 0x0000, 0x0000, 0x0000 }, /* R868 */
975 { 0x0000, 0x0000, 0x0000 }, /* R869 */
976 { 0x0000, 0x0000, 0x0000 }, /* R870 */
977 { 0x0000, 0x0000, 0x0000 }, /* R871 */
978 { 0x0000, 0x0000, 0x0000 }, /* R872 */
979 { 0x0000, 0x0000, 0x0000 }, /* R873 */
980 { 0x0000, 0x0000, 0x0000 }, /* R874 */
981 { 0x0000, 0x0000, 0x0000 }, /* R875 */
982 { 0x0000, 0x0000, 0x0000 }, /* R876 */
983 { 0x0000, 0x0000, 0x0000 }, /* R877 */
984 { 0x0000, 0x0000, 0x0000 }, /* R878 */
985 { 0x0000, 0x0000, 0x0000 }, /* R879 */
986 { 0x0000, 0x0000, 0x0000 }, /* R880 */
987 { 0x0000, 0x0000, 0x0000 }, /* R881 */
988 { 0x0000, 0x0000, 0x0000 }, /* R882 */
989 { 0x0000, 0x0000, 0x0000 }, /* R883 */
990 { 0x0000, 0x0000, 0x0000 }, /* R884 */
991 { 0x0000, 0x0000, 0x0000 }, /* R885 */
992 { 0x0000, 0x0000, 0x0000 }, /* R886 */
993 { 0x0000, 0x0000, 0x0000 }, /* R887 */
994 { 0x0000, 0x0000, 0x0000 }, /* R888 */
995 { 0x0000, 0x0000, 0x0000 }, /* R889 */
996 { 0x0000, 0x0000, 0x0000 }, /* R890 */
997 { 0x0000, 0x0000, 0x0000 }, /* R891 */
998 { 0x0000, 0x0000, 0x0000 }, /* R892 */
999 { 0x0000, 0x0000, 0x0000 }, /* R893 */
1000 { 0x0000, 0x0000, 0x0000 }, /* R894 */
1001 { 0x0000, 0x0000, 0x0000 }, /* R895 */
1002 { 0x0000, 0x0000, 0x0000 }, /* R896 */
1003 { 0x0000, 0x0000, 0x0000 }, /* R897 */
1004 { 0x0000, 0x0000, 0x0000 }, /* R898 */
1005 { 0x0000, 0x0000, 0x0000 }, /* R899 */
1006 { 0x0000, 0x0000, 0x0000 }, /* R900 */
1007 { 0x0000, 0x0000, 0x0000 }, /* R901 */
1008 { 0x0000, 0x0000, 0x0000 }, /* R902 */
1009 { 0x0000, 0x0000, 0x0000 }, /* R903 */
1010 { 0x0000, 0x0000, 0x0000 }, /* R904 */
1011 { 0x0000, 0x0000, 0x0000 }, /* R905 */
1012 { 0x0000, 0x0000, 0x0000 }, /* R906 */
1013 { 0x0000, 0x0000, 0x0000 }, /* R907 */
1014 { 0x0000, 0x0000, 0x0000 }, /* R908 */
1015 { 0x0000, 0x0000, 0x0000 }, /* R909 */
1016 { 0x0000, 0x0000, 0x0000 }, /* R910 */
1017 { 0x0000, 0x0000, 0x0000 }, /* R911 */
1018 { 0x0000, 0x0000, 0x0000 }, /* R912 */
1019 { 0x0000, 0x0000, 0x0000 }, /* R913 */
1020 { 0x0000, 0x0000, 0x0000 }, /* R914 */
1021 { 0x0000, 0x0000, 0x0000 }, /* R915 */
1022 { 0x0000, 0x0000, 0x0000 }, /* R916 */
1023 { 0x0000, 0x0000, 0x0000 }, /* R917 */
1024 { 0x0000, 0x0000, 0x0000 }, /* R918 */
1025 { 0x0000, 0x0000, 0x0000 }, /* R919 */
1026 { 0x0000, 0x0000, 0x0000 }, /* R920 */
1027 { 0x0000, 0x0000, 0x0000 }, /* R921 */
1028 { 0x0000, 0x0000, 0x0000 }, /* R922 */
1029 { 0x0000, 0x0000, 0x0000 }, /* R923 */
1030 { 0x0000, 0x0000, 0x0000 }, /* R924 */
1031 { 0x0000, 0x0000, 0x0000 }, /* R925 */
1032 { 0x0000, 0x0000, 0x0000 }, /* R926 */
1033 { 0x0000, 0x0000, 0x0000 }, /* R927 */
1034 { 0x0000, 0x0000, 0x0000 }, /* R928 */
1035 { 0x0000, 0x0000, 0x0000 }, /* R929 */
1036 { 0x0000, 0x0000, 0x0000 }, /* R930 */
1037 { 0x0000, 0x0000, 0x0000 }, /* R931 */
1038 { 0x0000, 0x0000, 0x0000 }, /* R932 */
1039 { 0x0000, 0x0000, 0x0000 }, /* R933 */
1040 { 0x0000, 0x0000, 0x0000 }, /* R934 */
1041 { 0x0000, 0x0000, 0x0000 }, /* R935 */
1042 { 0x0000, 0x0000, 0x0000 }, /* R936 */
1043 { 0x0000, 0x0000, 0x0000 }, /* R937 */
1044 { 0x0000, 0x0000, 0x0000 }, /* R938 */
1045 { 0x0000, 0x0000, 0x0000 }, /* R939 */
1046 { 0x0000, 0x0000, 0x0000 }, /* R940 */
1047 { 0x0000, 0x0000, 0x0000 }, /* R941 */
1048 { 0x0000, 0x0000, 0x0000 }, /* R942 */
1049 { 0x0000, 0x0000, 0x0000 }, /* R943 */
1050 { 0x0000, 0x0000, 0x0000 }, /* R944 */
1051 { 0x0000, 0x0000, 0x0000 }, /* R945 */
1052 { 0x0000, 0x0000, 0x0000 }, /* R946 */
1053 { 0x0000, 0x0000, 0x0000 }, /* R947 */
1054 { 0x0000, 0x0000, 0x0000 }, /* R948 */
1055 { 0x0000, 0x0000, 0x0000 }, /* R949 */
1056 { 0x0000, 0x0000, 0x0000 }, /* R950 */
1057 { 0x0000, 0x0000, 0x0000 }, /* R951 */
1058 { 0x0000, 0x0000, 0x0000 }, /* R952 */
1059 { 0x0000, 0x0000, 0x0000 }, /* R953 */
1060 { 0x0000, 0x0000, 0x0000 }, /* R954 */
1061 { 0x0000, 0x0000, 0x0000 }, /* R955 */
1062 { 0x0000, 0x0000, 0x0000 }, /* R956 */
1063 { 0x0000, 0x0000, 0x0000 }, /* R957 */
1064 { 0x0000, 0x0000, 0x0000 }, /* R958 */
1065 { 0x0000, 0x0000, 0x0000 }, /* R959 */
1066 { 0x0000, 0x0000, 0x0000 }, /* R960 */
1067 { 0x0000, 0x0000, 0x0000 }, /* R961 */
1068 { 0x0000, 0x0000, 0x0000 }, /* R962 */
1069 { 0x0000, 0x0000, 0x0000 }, /* R963 */
1070 { 0x0000, 0x0000, 0x0000 }, /* R964 */
1071 { 0x0000, 0x0000, 0x0000 }, /* R965 */
1072 { 0x0000, 0x0000, 0x0000 }, /* R966 */
1073 { 0x0000, 0x0000, 0x0000 }, /* R967 */
1074 { 0x0000, 0x0000, 0x0000 }, /* R968 */
1075 { 0x0000, 0x0000, 0x0000 }, /* R969 */
1076 { 0x0000, 0x0000, 0x0000 }, /* R970 */
1077 { 0x0000, 0x0000, 0x0000 }, /* R971 */
1078 { 0x0000, 0x0000, 0x0000 }, /* R972 */
1079 { 0x0000, 0x0000, 0x0000 }, /* R973 */
1080 { 0x0000, 0x0000, 0x0000 }, /* R974 */
1081 { 0x0000, 0x0000, 0x0000 }, /* R975 */
1082 { 0x0000, 0x0000, 0x0000 }, /* R976 */
1083 { 0x0000, 0x0000, 0x0000 }, /* R977 */
1084 { 0x0000, 0x0000, 0x0000 }, /* R978 */
1085 { 0x0000, 0x0000, 0x0000 }, /* R979 */
1086 { 0x0000, 0x0000, 0x0000 }, /* R980 */
1087 { 0x0000, 0x0000, 0x0000 }, /* R981 */
1088 { 0x0000, 0x0000, 0x0000 }, /* R982 */
1089 { 0x0000, 0x0000, 0x0000 }, /* R983 */
1090 { 0x0000, 0x0000, 0x0000 }, /* R984 */
1091 { 0x0000, 0x0000, 0x0000 }, /* R985 */
1092 { 0x0000, 0x0000, 0x0000 }, /* R986 */
1093 { 0x0000, 0x0000, 0x0000 }, /* R987 */
1094 { 0x0000, 0x0000, 0x0000 }, /* R988 */
1095 { 0x0000, 0x0000, 0x0000 }, /* R989 */
1096 { 0x0000, 0x0000, 0x0000 }, /* R990 */
1097 { 0x0000, 0x0000, 0x0000 }, /* R991 */
1098 { 0x0000, 0x0000, 0x0000 }, /* R992 */
1099 { 0x0000, 0x0000, 0x0000 }, /* R993 */
1100 { 0x0000, 0x0000, 0x0000 }, /* R994 */
1101 { 0x0000, 0x0000, 0x0000 }, /* R995 */
1102 { 0x0000, 0x0000, 0x0000 }, /* R996 */
1103 { 0x0000, 0x0000, 0x0000 }, /* R997 */
1104 { 0x0000, 0x0000, 0x0000 }, /* R998 */
1105 { 0x0000, 0x0000, 0x0000 }, /* R999 */
1106 { 0x0000, 0x0000, 0x0000 }, /* R1000 */
1107 { 0x0000, 0x0000, 0x0000 }, /* R1001 */
1108 { 0x0000, 0x0000, 0x0000 }, /* R1002 */
1109 { 0x0000, 0x0000, 0x0000 }, /* R1003 */
1110 { 0x0000, 0x0000, 0x0000 }, /* R1004 */
1111 { 0x0000, 0x0000, 0x0000 }, /* R1005 */
1112 { 0x0000, 0x0000, 0x0000 }, /* R1006 */
1113 { 0x0000, 0x0000, 0x0000 }, /* R1007 */
1114 { 0x0000, 0x0000, 0x0000 }, /* R1008 */
1115 { 0x0000, 0x0000, 0x0000 }, /* R1009 */
1116 { 0x0000, 0x0000, 0x0000 }, /* R1010 */
1117 { 0x0000, 0x0000, 0x0000 }, /* R1011 */
1118 { 0x0000, 0x0000, 0x0000 }, /* R1012 */
1119 { 0x0000, 0x0000, 0x0000 }, /* R1013 */
1120 { 0x0000, 0x0000, 0x0000 }, /* R1014 */
1121 { 0x0000, 0x0000, 0x0000 }, /* R1015 */
1122 { 0x0000, 0x0000, 0x0000 }, /* R1016 */
1123 { 0x0000, 0x0000, 0x0000 }, /* R1017 */
1124 { 0x0000, 0x0000, 0x0000 }, /* R1018 */
1125 { 0x0000, 0x0000, 0x0000 }, /* R1019 */
1126 { 0x0000, 0x0000, 0x0000 }, /* R1020 */
1127 { 0x0000, 0x0000, 0x0000 }, /* R1021 */
1128 { 0x0000, 0x0000, 0x0000 }, /* R1022 */
1129 { 0x0000, 0x0000, 0x0000 }, /* R1023 */
1130 { 0x00FF, 0x01FF, 0x0000 }, /* R1024 - AIF1 ADC1 Left Volume */
1131 { 0x00FF, 0x01FF, 0x0000 }, /* R1025 - AIF1 ADC1 Right Volume */
1132 { 0x00FF, 0x01FF, 0x0000 }, /* R1026 - AIF1 DAC1 Left Volume */
1133 { 0x00FF, 0x01FF, 0x0000 }, /* R1027 - AIF1 DAC1 Right Volume */
1134 { 0x00FF, 0x01FF, 0x0000 }, /* R1028 - AIF1 ADC2 Left Volume */
1135 { 0x00FF, 0x01FF, 0x0000 }, /* R1029 - AIF1 ADC2 Right Volume */
1136 { 0x00FF, 0x01FF, 0x0000 }, /* R1030 - AIF1 DAC2 Left Volume */
1137 { 0x00FF, 0x01FF, 0x0000 }, /* R1031 - AIF1 DAC2 Right Volume */
1138 { 0x0000, 0x0000, 0x0000 }, /* R1032 */
1139 { 0x0000, 0x0000, 0x0000 }, /* R1033 */
1140 { 0x0000, 0x0000, 0x0000 }, /* R1034 */
1141 { 0x0000, 0x0000, 0x0000 }, /* R1035 */
1142 { 0x0000, 0x0000, 0x0000 }, /* R1036 */
1143 { 0x0000, 0x0000, 0x0000 }, /* R1037 */
1144 { 0x0000, 0x0000, 0x0000 }, /* R1038 */
1145 { 0x0000, 0x0000, 0x0000 }, /* R1039 */
1146 { 0xF800, 0xF800, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */
1147 { 0x7800, 0x7800, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */
1148 { 0x0000, 0x0000, 0x0000 }, /* R1042 */
1149 { 0x0000, 0x0000, 0x0000 }, /* R1043 */
1150 { 0x0000, 0x0000, 0x0000 }, /* R1044 */
1151 { 0x0000, 0x0000, 0x0000 }, /* R1045 */
1152 { 0x0000, 0x0000, 0x0000 }, /* R1046 */
1153 { 0x0000, 0x0000, 0x0000 }, /* R1047 */
1154 { 0x0000, 0x0000, 0x0000 }, /* R1048 */
1155 { 0x0000, 0x0000, 0x0000 }, /* R1049 */
1156 { 0x0000, 0x0000, 0x0000 }, /* R1050 */
1157 { 0x0000, 0x0000, 0x0000 }, /* R1051 */
1158 { 0x0000, 0x0000, 0x0000 }, /* R1052 */
1159 { 0x0000, 0x0000, 0x0000 }, /* R1053 */
1160 { 0x0000, 0x0000, 0x0000 }, /* R1054 */
1161 { 0x0000, 0x0000, 0x0000 }, /* R1055 */
1162 { 0x02B6, 0x02B6, 0x0000 }, /* R1056 - AIF1 DAC1 Filters (1) */
1163 { 0x3F00, 0x3F00, 0x0000 }, /* R1057 - AIF1 DAC1 Filters (2) */
1164 { 0x02B6, 0x02B6, 0x0000 }, /* R1058 - AIF1 DAC2 Filters (1) */
1165 { 0x3F00, 0x3F00, 0x0000 }, /* R1059 - AIF1 DAC2 Filters (2) */
1166 { 0x0000, 0x0000, 0x0000 }, /* R1060 */
1167 { 0x0000, 0x0000, 0x0000 }, /* R1061 */
1168 { 0x0000, 0x0000, 0x0000 }, /* R1062 */
1169 { 0x0000, 0x0000, 0x0000 }, /* R1063 */
1170 { 0x0000, 0x0000, 0x0000 }, /* R1064 */
1171 { 0x0000, 0x0000, 0x0000 }, /* R1065 */
1172 { 0x0000, 0x0000, 0x0000 }, /* R1066 */
1173 { 0x0000, 0x0000, 0x0000 }, /* R1067 */
1174 { 0x0000, 0x0000, 0x0000 }, /* R1068 */
1175 { 0x0000, 0x0000, 0x0000 }, /* R1069 */
1176 { 0x0000, 0x0000, 0x0000 }, /* R1070 */
1177 { 0x0000, 0x0000, 0x0000 }, /* R1071 */
1178 { 0x0000, 0x0000, 0x0000 }, /* R1072 */
1179 { 0x0000, 0x0000, 0x0000 }, /* R1073 */
1180 { 0x0000, 0x0000, 0x0000 }, /* R1074 */
1181 { 0x0000, 0x0000, 0x0000 }, /* R1075 */
1182 { 0x0000, 0x0000, 0x0000 }, /* R1076 */
1183 { 0x0000, 0x0000, 0x0000 }, /* R1077 */
1184 { 0x0000, 0x0000, 0x0000 }, /* R1078 */
1185 { 0x0000, 0x0000, 0x0000 }, /* R1079 */
1186 { 0x0000, 0x0000, 0x0000 }, /* R1080 */
1187 { 0x0000, 0x0000, 0x0000 }, /* R1081 */
1188 { 0x0000, 0x0000, 0x0000 }, /* R1082 */
1189 { 0x0000, 0x0000, 0x0000 }, /* R1083 */
1190 { 0x0000, 0x0000, 0x0000 }, /* R1084 */
1191 { 0x0000, 0x0000, 0x0000 }, /* R1085 */
1192 { 0x0000, 0x0000, 0x0000 }, /* R1086 */
1193 { 0x0000, 0x0000, 0x0000 }, /* R1087 */
1194 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1088 - AIF1 DRC1 (1) */
1195 { 0x1FFF, 0x1FFF, 0x0000 }, /* R1089 - AIF1 DRC1 (2) */
1196 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */
1197 { 0x07FF, 0x07FF, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */
1198 { 0x03FF, 0x03FF, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */
1199 { 0x0000, 0x0000, 0x0000 }, /* R1093 */
1200 { 0x0000, 0x0000, 0x0000 }, /* R1094 */
1201 { 0x0000, 0x0000, 0x0000 }, /* R1095 */
1202 { 0x0000, 0x0000, 0x0000 }, /* R1096 */
1203 { 0x0000, 0x0000, 0x0000 }, /* R1097 */
1204 { 0x0000, 0x0000, 0x0000 }, /* R1098 */
1205 { 0x0000, 0x0000, 0x0000 }, /* R1099 */
1206 { 0x0000, 0x0000, 0x0000 }, /* R1100 */
1207 { 0x0000, 0x0000, 0x0000 }, /* R1101 */
1208 { 0x0000, 0x0000, 0x0000 }, /* R1102 */
1209 { 0x0000, 0x0000, 0x0000 }, /* R1103 */
1210 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1104 - AIF1 DRC2 (1) */
1211 { 0x1FFF, 0x1FFF, 0x0000 }, /* R1105 - AIF1 DRC2 (2) */
1212 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */
1213 { 0x07FF, 0x07FF, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */
1214 { 0x03FF, 0x03FF, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */
1215 { 0x0000, 0x0000, 0x0000 }, /* R1109 */
1216 { 0x0000, 0x0000, 0x0000 }, /* R1110 */
1217 { 0x0000, 0x0000, 0x0000 }, /* R1111 */
1218 { 0x0000, 0x0000, 0x0000 }, /* R1112 */
1219 { 0x0000, 0x0000, 0x0000 }, /* R1113 */
1220 { 0x0000, 0x0000, 0x0000 }, /* R1114 */
1221 { 0x0000, 0x0000, 0x0000 }, /* R1115 */
1222 { 0x0000, 0x0000, 0x0000 }, /* R1116 */
1223 { 0x0000, 0x0000, 0x0000 }, /* R1117 */
1224 { 0x0000, 0x0000, 0x0000 }, /* R1118 */
1225 { 0x0000, 0x0000, 0x0000 }, /* R1119 */
1226 { 0x0000, 0x0000, 0x0000 }, /* R1120 */
1227 { 0x0000, 0x0000, 0x0000 }, /* R1121 */
1228 { 0x0000, 0x0000, 0x0000 }, /* R1122 */
1229 { 0x0000, 0x0000, 0x0000 }, /* R1123 */
1230 { 0x0000, 0x0000, 0x0000 }, /* R1124 */
1231 { 0x0000, 0x0000, 0x0000 }, /* R1125 */
1232 { 0x0000, 0x0000, 0x0000 }, /* R1126 */
1233 { 0x0000, 0x0000, 0x0000 }, /* R1127 */
1234 { 0x0000, 0x0000, 0x0000 }, /* R1128 */
1235 { 0x0000, 0x0000, 0x0000 }, /* R1129 */
1236 { 0x0000, 0x0000, 0x0000 }, /* R1130 */
1237 { 0x0000, 0x0000, 0x0000 }, /* R1131 */
1238 { 0x0000, 0x0000, 0x0000 }, /* R1132 */
1239 { 0x0000, 0x0000, 0x0000 }, /* R1133 */
1240 { 0x0000, 0x0000, 0x0000 }, /* R1134 */
1241 { 0x0000, 0x0000, 0x0000 }, /* R1135 */
1242 { 0x0000, 0x0000, 0x0000 }, /* R1136 */
1243 { 0x0000, 0x0000, 0x0000 }, /* R1137 */
1244 { 0x0000, 0x0000, 0x0000 }, /* R1138 */
1245 { 0x0000, 0x0000, 0x0000 }, /* R1139 */
1246 { 0x0000, 0x0000, 0x0000 }, /* R1140 */
1247 { 0x0000, 0x0000, 0x0000 }, /* R1141 */
1248 { 0x0000, 0x0000, 0x0000 }, /* R1142 */
1249 { 0x0000, 0x0000, 0x0000 }, /* R1143 */
1250 { 0x0000, 0x0000, 0x0000 }, /* R1144 */
1251 { 0x0000, 0x0000, 0x0000 }, /* R1145 */
1252 { 0x0000, 0x0000, 0x0000 }, /* R1146 */
1253 { 0x0000, 0x0000, 0x0000 }, /* R1147 */
1254 { 0x0000, 0x0000, 0x0000 }, /* R1148 */
1255 { 0x0000, 0x0000, 0x0000 }, /* R1149 */
1256 { 0x0000, 0x0000, 0x0000 }, /* R1150 */
1257 { 0x0000, 0x0000, 0x0000 }, /* R1151 */
1258 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
1259 { 0xFFC0, 0xFFC0, 0x0000 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
1260 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
1261 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
1262 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
1263 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
1264 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
1265 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
1266 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
1267 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
1268 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
1269 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
1270 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
1271 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
1272 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
1273 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
1274 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
1275 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
1276 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
1277 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
1278 { 0x0000, 0x0000, 0x0000 }, /* R1172 */
1279 { 0x0000, 0x0000, 0x0000 }, /* R1173 */
1280 { 0x0000, 0x0000, 0x0000 }, /* R1174 */
1281 { 0x0000, 0x0000, 0x0000 }, /* R1175 */
1282 { 0x0000, 0x0000, 0x0000 }, /* R1176 */
1283 { 0x0000, 0x0000, 0x0000 }, /* R1177 */
1284 { 0x0000, 0x0000, 0x0000 }, /* R1178 */
1285 { 0x0000, 0x0000, 0x0000 }, /* R1179 */
1286 { 0x0000, 0x0000, 0x0000 }, /* R1180 */
1287 { 0x0000, 0x0000, 0x0000 }, /* R1181 */
1288 { 0x0000, 0x0000, 0x0000 }, /* R1182 */
1289 { 0x0000, 0x0000, 0x0000 }, /* R1183 */
1290 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
1291 { 0xFFC0, 0xFFC0, 0x0000 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
1292 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
1293 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
1294 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
1295 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
1296 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
1297 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
1298 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
1299 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
1300 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
1301 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
1302 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
1303 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
1304 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
1305 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
1306 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
1307 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
1308 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
1309 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
1310 { 0x0000, 0x0000, 0x0000 }, /* R1204 */
1311 { 0x0000, 0x0000, 0x0000 }, /* R1205 */
1312 { 0x0000, 0x0000, 0x0000 }, /* R1206 */
1313 { 0x0000, 0x0000, 0x0000 }, /* R1207 */
1314 { 0x0000, 0x0000, 0x0000 }, /* R1208 */
1315 { 0x0000, 0x0000, 0x0000 }, /* R1209 */
1316 { 0x0000, 0x0000, 0x0000 }, /* R1210 */
1317 { 0x0000, 0x0000, 0x0000 }, /* R1211 */
1318 { 0x0000, 0x0000, 0x0000 }, /* R1212 */
1319 { 0x0000, 0x0000, 0x0000 }, /* R1213 */
1320 { 0x0000, 0x0000, 0x0000 }, /* R1214 */
1321 { 0x0000, 0x0000, 0x0000 }, /* R1215 */
1322 { 0x0000, 0x0000, 0x0000 }, /* R1216 */
1323 { 0x0000, 0x0000, 0x0000 }, /* R1217 */
1324 { 0x0000, 0x0000, 0x0000 }, /* R1218 */
1325 { 0x0000, 0x0000, 0x0000 }, /* R1219 */
1326 { 0x0000, 0x0000, 0x0000 }, /* R1220 */
1327 { 0x0000, 0x0000, 0x0000 }, /* R1221 */
1328 { 0x0000, 0x0000, 0x0000 }, /* R1222 */
1329 { 0x0000, 0x0000, 0x0000 }, /* R1223 */
1330 { 0x0000, 0x0000, 0x0000 }, /* R1224 */
1331 { 0x0000, 0x0000, 0x0000 }, /* R1225 */
1332 { 0x0000, 0x0000, 0x0000 }, /* R1226 */
1333 { 0x0000, 0x0000, 0x0000 }, /* R1227 */
1334 { 0x0000, 0x0000, 0x0000 }, /* R1228 */
1335 { 0x0000, 0x0000, 0x0000 }, /* R1229 */
1336 { 0x0000, 0x0000, 0x0000 }, /* R1230 */
1337 { 0x0000, 0x0000, 0x0000 }, /* R1231 */
1338 { 0x0000, 0x0000, 0x0000 }, /* R1232 */
1339 { 0x0000, 0x0000, 0x0000 }, /* R1233 */
1340 { 0x0000, 0x0000, 0x0000 }, /* R1234 */
1341 { 0x0000, 0x0000, 0x0000 }, /* R1235 */
1342 { 0x0000, 0x0000, 0x0000 }, /* R1236 */
1343 { 0x0000, 0x0000, 0x0000 }, /* R1237 */
1344 { 0x0000, 0x0000, 0x0000 }, /* R1238 */
1345 { 0x0000, 0x0000, 0x0000 }, /* R1239 */
1346 { 0x0000, 0x0000, 0x0000 }, /* R1240 */
1347 { 0x0000, 0x0000, 0x0000 }, /* R1241 */
1348 { 0x0000, 0x0000, 0x0000 }, /* R1242 */
1349 { 0x0000, 0x0000, 0x0000 }, /* R1243 */
1350 { 0x0000, 0x0000, 0x0000 }, /* R1244 */
1351 { 0x0000, 0x0000, 0x0000 }, /* R1245 */
1352 { 0x0000, 0x0000, 0x0000 }, /* R1246 */
1353 { 0x0000, 0x0000, 0x0000 }, /* R1247 */
1354 { 0x0000, 0x0000, 0x0000 }, /* R1248 */
1355 { 0x0000, 0x0000, 0x0000 }, /* R1249 */
1356 { 0x0000, 0x0000, 0x0000 }, /* R1250 */
1357 { 0x0000, 0x0000, 0x0000 }, /* R1251 */
1358 { 0x0000, 0x0000, 0x0000 }, /* R1252 */
1359 { 0x0000, 0x0000, 0x0000 }, /* R1253 */
1360 { 0x0000, 0x0000, 0x0000 }, /* R1254 */
1361 { 0x0000, 0x0000, 0x0000 }, /* R1255 */
1362 { 0x0000, 0x0000, 0x0000 }, /* R1256 */
1363 { 0x0000, 0x0000, 0x0000 }, /* R1257 */
1364 { 0x0000, 0x0000, 0x0000 }, /* R1258 */
1365 { 0x0000, 0x0000, 0x0000 }, /* R1259 */
1366 { 0x0000, 0x0000, 0x0000 }, /* R1260 */
1367 { 0x0000, 0x0000, 0x0000 }, /* R1261 */
1368 { 0x0000, 0x0000, 0x0000 }, /* R1262 */
1369 { 0x0000, 0x0000, 0x0000 }, /* R1263 */
1370 { 0x0000, 0x0000, 0x0000 }, /* R1264 */
1371 { 0x0000, 0x0000, 0x0000 }, /* R1265 */
1372 { 0x0000, 0x0000, 0x0000 }, /* R1266 */
1373 { 0x0000, 0x0000, 0x0000 }, /* R1267 */
1374 { 0x0000, 0x0000, 0x0000 }, /* R1268 */
1375 { 0x0000, 0x0000, 0x0000 }, /* R1269 */
1376 { 0x0000, 0x0000, 0x0000 }, /* R1270 */
1377 { 0x0000, 0x0000, 0x0000 }, /* R1271 */
1378 { 0x0000, 0x0000, 0x0000 }, /* R1272 */
1379 { 0x0000, 0x0000, 0x0000 }, /* R1273 */
1380 { 0x0000, 0x0000, 0x0000 }, /* R1274 */
1381 { 0x0000, 0x0000, 0x0000 }, /* R1275 */
1382 { 0x0000, 0x0000, 0x0000 }, /* R1276 */
1383 { 0x0000, 0x0000, 0x0000 }, /* R1277 */
1384 { 0x0000, 0x0000, 0x0000 }, /* R1278 */
1385 { 0x0000, 0x0000, 0x0000 }, /* R1279 */
1386 { 0x00FF, 0x01FF, 0x0000 }, /* R1280 - AIF2 ADC Left Volume */
1387 { 0x00FF, 0x01FF, 0x0000 }, /* R1281 - AIF2 ADC Right Volume */
1388 { 0x00FF, 0x01FF, 0x0000 }, /* R1282 - AIF2 DAC Left Volume */
1389 { 0x00FF, 0x01FF, 0x0000 }, /* R1283 - AIF2 DAC Right Volume */
1390 { 0x0000, 0x0000, 0x0000 }, /* R1284 */
1391 { 0x0000, 0x0000, 0x0000 }, /* R1285 */
1392 { 0x0000, 0x0000, 0x0000 }, /* R1286 */
1393 { 0x0000, 0x0000, 0x0000 }, /* R1287 */
1394 { 0x0000, 0x0000, 0x0000 }, /* R1288 */
1395 { 0x0000, 0x0000, 0x0000 }, /* R1289 */
1396 { 0x0000, 0x0000, 0x0000 }, /* R1290 */
1397 { 0x0000, 0x0000, 0x0000 }, /* R1291 */
1398 { 0x0000, 0x0000, 0x0000 }, /* R1292 */
1399 { 0x0000, 0x0000, 0x0000 }, /* R1293 */
1400 { 0x0000, 0x0000, 0x0000 }, /* R1294 */
1401 { 0x0000, 0x0000, 0x0000 }, /* R1295 */
1402 { 0xF800, 0xF800, 0x0000 }, /* R1296 - AIF2 ADC Filters */
1403 { 0x0000, 0x0000, 0x0000 }, /* R1297 */
1404 { 0x0000, 0x0000, 0x0000 }, /* R1298 */
1405 { 0x0000, 0x0000, 0x0000 }, /* R1299 */
1406 { 0x0000, 0x0000, 0x0000 }, /* R1300 */
1407 { 0x0000, 0x0000, 0x0000 }, /* R1301 */
1408 { 0x0000, 0x0000, 0x0000 }, /* R1302 */
1409 { 0x0000, 0x0000, 0x0000 }, /* R1303 */
1410 { 0x0000, 0x0000, 0x0000 }, /* R1304 */
1411 { 0x0000, 0x0000, 0x0000 }, /* R1305 */
1412 { 0x0000, 0x0000, 0x0000 }, /* R1306 */
1413 { 0x0000, 0x0000, 0x0000 }, /* R1307 */
1414 { 0x0000, 0x0000, 0x0000 }, /* R1308 */
1415 { 0x0000, 0x0000, 0x0000 }, /* R1309 */
1416 { 0x0000, 0x0000, 0x0000 }, /* R1310 */
1417 { 0x0000, 0x0000, 0x0000 }, /* R1311 */
1418 { 0x02B6, 0x02B6, 0x0000 }, /* R1312 - AIF2 DAC Filters (1) */
1419 { 0x3F00, 0x3F00, 0x0000 }, /* R1313 - AIF2 DAC Filters (2) */
1420 { 0x0000, 0x0000, 0x0000 }, /* R1314 */
1421 { 0x0000, 0x0000, 0x0000 }, /* R1315 */
1422 { 0x0000, 0x0000, 0x0000 }, /* R1316 */
1423 { 0x0000, 0x0000, 0x0000 }, /* R1317 */
1424 { 0x0000, 0x0000, 0x0000 }, /* R1318 */
1425 { 0x0000, 0x0000, 0x0000 }, /* R1319 */
1426 { 0x0000, 0x0000, 0x0000 }, /* R1320 */
1427 { 0x0000, 0x0000, 0x0000 }, /* R1321 */
1428 { 0x0000, 0x0000, 0x0000 }, /* R1322 */
1429 { 0x0000, 0x0000, 0x0000 }, /* R1323 */
1430 { 0x0000, 0x0000, 0x0000 }, /* R1324 */
1431 { 0x0000, 0x0000, 0x0000 }, /* R1325 */
1432 { 0x0000, 0x0000, 0x0000 }, /* R1326 */
1433 { 0x0000, 0x0000, 0x0000 }, /* R1327 */
1434 { 0x0000, 0x0000, 0x0000 }, /* R1328 */
1435 { 0x0000, 0x0000, 0x0000 }, /* R1329 */
1436 { 0x0000, 0x0000, 0x0000 }, /* R1330 */
1437 { 0x0000, 0x0000, 0x0000 }, /* R1331 */
1438 { 0x0000, 0x0000, 0x0000 }, /* R1332 */
1439 { 0x0000, 0x0000, 0x0000 }, /* R1333 */
1440 { 0x0000, 0x0000, 0x0000 }, /* R1334 */
1441 { 0x0000, 0x0000, 0x0000 }, /* R1335 */
1442 { 0x0000, 0x0000, 0x0000 }, /* R1336 */
1443 { 0x0000, 0x0000, 0x0000 }, /* R1337 */
1444 { 0x0000, 0x0000, 0x0000 }, /* R1338 */
1445 { 0x0000, 0x0000, 0x0000 }, /* R1339 */
1446 { 0x0000, 0x0000, 0x0000 }, /* R1340 */
1447 { 0x0000, 0x0000, 0x0000 }, /* R1341 */
1448 { 0x0000, 0x0000, 0x0000 }, /* R1342 */
1449 { 0x0000, 0x0000, 0x0000 }, /* R1343 */
1450 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1344 - AIF2 DRC (1) */
1451 { 0x1FFF, 0x1FFF, 0x0000 }, /* R1345 - AIF2 DRC (2) */
1452 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1346 - AIF2 DRC (3) */
1453 { 0x07FF, 0x07FF, 0x0000 }, /* R1347 - AIF2 DRC (4) */
1454 { 0x03FF, 0x03FF, 0x0000 }, /* R1348 - AIF2 DRC (5) */
1455 { 0x0000, 0x0000, 0x0000 }, /* R1349 */
1456 { 0x0000, 0x0000, 0x0000 }, /* R1350 */
1457 { 0x0000, 0x0000, 0x0000 }, /* R1351 */
1458 { 0x0000, 0x0000, 0x0000 }, /* R1352 */
1459 { 0x0000, 0x0000, 0x0000 }, /* R1353 */
1460 { 0x0000, 0x0000, 0x0000 }, /* R1354 */
1461 { 0x0000, 0x0000, 0x0000 }, /* R1355 */
1462 { 0x0000, 0x0000, 0x0000 }, /* R1356 */
1463 { 0x0000, 0x0000, 0x0000 }, /* R1357 */
1464 { 0x0000, 0x0000, 0x0000 }, /* R1358 */
1465 { 0x0000, 0x0000, 0x0000 }, /* R1359 */
1466 { 0x0000, 0x0000, 0x0000 }, /* R1360 */
1467 { 0x0000, 0x0000, 0x0000 }, /* R1361 */
1468 { 0x0000, 0x0000, 0x0000 }, /* R1362 */
1469 { 0x0000, 0x0000, 0x0000 }, /* R1363 */
1470 { 0x0000, 0x0000, 0x0000 }, /* R1364 */
1471 { 0x0000, 0x0000, 0x0000 }, /* R1365 */
1472 { 0x0000, 0x0000, 0x0000 }, /* R1366 */
1473 { 0x0000, 0x0000, 0x0000 }, /* R1367 */
1474 { 0x0000, 0x0000, 0x0000 }, /* R1368 */
1475 { 0x0000, 0x0000, 0x0000 }, /* R1369 */
1476 { 0x0000, 0x0000, 0x0000 }, /* R1370 */
1477 { 0x0000, 0x0000, 0x0000 }, /* R1371 */
1478 { 0x0000, 0x0000, 0x0000 }, /* R1372 */
1479 { 0x0000, 0x0000, 0x0000 }, /* R1373 */
1480 { 0x0000, 0x0000, 0x0000 }, /* R1374 */
1481 { 0x0000, 0x0000, 0x0000 }, /* R1375 */
1482 { 0x0000, 0x0000, 0x0000 }, /* R1376 */
1483 { 0x0000, 0x0000, 0x0000 }, /* R1377 */
1484 { 0x0000, 0x0000, 0x0000 }, /* R1378 */
1485 { 0x0000, 0x0000, 0x0000 }, /* R1379 */
1486 { 0x0000, 0x0000, 0x0000 }, /* R1380 */
1487 { 0x0000, 0x0000, 0x0000 }, /* R1381 */
1488 { 0x0000, 0x0000, 0x0000 }, /* R1382 */
1489 { 0x0000, 0x0000, 0x0000 }, /* R1383 */
1490 { 0x0000, 0x0000, 0x0000 }, /* R1384 */
1491 { 0x0000, 0x0000, 0x0000 }, /* R1385 */
1492 { 0x0000, 0x0000, 0x0000 }, /* R1386 */
1493 { 0x0000, 0x0000, 0x0000 }, /* R1387 */
1494 { 0x0000, 0x0000, 0x0000 }, /* R1388 */
1495 { 0x0000, 0x0000, 0x0000 }, /* R1389 */
1496 { 0x0000, 0x0000, 0x0000 }, /* R1390 */
1497 { 0x0000, 0x0000, 0x0000 }, /* R1391 */
1498 { 0x0000, 0x0000, 0x0000 }, /* R1392 */
1499 { 0x0000, 0x0000, 0x0000 }, /* R1393 */
1500 { 0x0000, 0x0000, 0x0000 }, /* R1394 */
1501 { 0x0000, 0x0000, 0x0000 }, /* R1395 */
1502 { 0x0000, 0x0000, 0x0000 }, /* R1396 */
1503 { 0x0000, 0x0000, 0x0000 }, /* R1397 */
1504 { 0x0000, 0x0000, 0x0000 }, /* R1398 */
1505 { 0x0000, 0x0000, 0x0000 }, /* R1399 */
1506 { 0x0000, 0x0000, 0x0000 }, /* R1400 */
1507 { 0x0000, 0x0000, 0x0000 }, /* R1401 */
1508 { 0x0000, 0x0000, 0x0000 }, /* R1402 */
1509 { 0x0000, 0x0000, 0x0000 }, /* R1403 */
1510 { 0x0000, 0x0000, 0x0000 }, /* R1404 */
1511 { 0x0000, 0x0000, 0x0000 }, /* R1405 */
1512 { 0x0000, 0x0000, 0x0000 }, /* R1406 */
1513 { 0x0000, 0x0000, 0x0000 }, /* R1407 */
1514 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1408 - AIF2 EQ Gains (1) */
1515 { 0xFFC0, 0xFFC0, 0x0000 }, /* R1409 - AIF2 EQ Gains (2) */
1516 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1410 - AIF2 EQ Band 1 A */
1517 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1411 - AIF2 EQ Band 1 B */
1518 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1412 - AIF2 EQ Band 1 PG */
1519 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1413 - AIF2 EQ Band 2 A */
1520 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1414 - AIF2 EQ Band 2 B */
1521 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1415 - AIF2 EQ Band 2 C */
1522 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1416 - AIF2 EQ Band 2 PG */
1523 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1417 - AIF2 EQ Band 3 A */
1524 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1418 - AIF2 EQ Band 3 B */
1525 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1419 - AIF2 EQ Band 3 C */
1526 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1420 - AIF2 EQ Band 3 PG */
1527 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1421 - AIF2 EQ Band 4 A */
1528 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1422 - AIF2 EQ Band 4 B */
1529 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1423 - AIF2 EQ Band 4 C */
1530 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1424 - AIF2 EQ Band 4 PG */
1531 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1425 - AIF2 EQ Band 5 A */
1532 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1426 - AIF2 EQ Band 5 B */
1533 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1427 - AIF2 EQ Band 5 PG */
1534 { 0x0000, 0x0000, 0x0000 }, /* R1428 */
1535 { 0x0000, 0x0000, 0x0000 }, /* R1429 */
1536 { 0x0000, 0x0000, 0x0000 }, /* R1430 */
1537 { 0x0000, 0x0000, 0x0000 }, /* R1431 */
1538 { 0x0000, 0x0000, 0x0000 }, /* R1432 */
1539 { 0x0000, 0x0000, 0x0000 }, /* R1433 */
1540 { 0x0000, 0x0000, 0x0000 }, /* R1434 */
1541 { 0x0000, 0x0000, 0x0000 }, /* R1435 */
1542 { 0x0000, 0x0000, 0x0000 }, /* R1436 */
1543 { 0x0000, 0x0000, 0x0000 }, /* R1437 */
1544 { 0x0000, 0x0000, 0x0000 }, /* R1438 */
1545 { 0x0000, 0x0000, 0x0000 }, /* R1439 */
1546 { 0x0000, 0x0000, 0x0000 }, /* R1440 */
1547 { 0x0000, 0x0000, 0x0000 }, /* R1441 */
1548 { 0x0000, 0x0000, 0x0000 }, /* R1442 */
1549 { 0x0000, 0x0000, 0x0000 }, /* R1443 */
1550 { 0x0000, 0x0000, 0x0000 }, /* R1444 */
1551 { 0x0000, 0x0000, 0x0000 }, /* R1445 */
1552 { 0x0000, 0x0000, 0x0000 }, /* R1446 */
1553 { 0x0000, 0x0000, 0x0000 }, /* R1447 */
1554 { 0x0000, 0x0000, 0x0000 }, /* R1448 */
1555 { 0x0000, 0x0000, 0x0000 }, /* R1449 */
1556 { 0x0000, 0x0000, 0x0000 }, /* R1450 */
1557 { 0x0000, 0x0000, 0x0000 }, /* R1451 */
1558 { 0x0000, 0x0000, 0x0000 }, /* R1452 */
1559 { 0x0000, 0x0000, 0x0000 }, /* R1453 */
1560 { 0x0000, 0x0000, 0x0000 }, /* R1454 */
1561 { 0x0000, 0x0000, 0x0000 }, /* R1455 */
1562 { 0x0000, 0x0000, 0x0000 }, /* R1456 */
1563 { 0x0000, 0x0000, 0x0000 }, /* R1457 */
1564 { 0x0000, 0x0000, 0x0000 }, /* R1458 */
1565 { 0x0000, 0x0000, 0x0000 }, /* R1459 */
1566 { 0x0000, 0x0000, 0x0000 }, /* R1460 */
1567 { 0x0000, 0x0000, 0x0000 }, /* R1461 */
1568 { 0x0000, 0x0000, 0x0000 }, /* R1462 */
1569 { 0x0000, 0x0000, 0x0000 }, /* R1463 */
1570 { 0x0000, 0x0000, 0x0000 }, /* R1464 */
1571 { 0x0000, 0x0000, 0x0000 }, /* R1465 */
1572 { 0x0000, 0x0000, 0x0000 }, /* R1466 */
1573 { 0x0000, 0x0000, 0x0000 }, /* R1467 */
1574 { 0x0000, 0x0000, 0x0000 }, /* R1468 */
1575 { 0x0000, 0x0000, 0x0000 }, /* R1469 */
1576 { 0x0000, 0x0000, 0x0000 }, /* R1470 */
1577 { 0x0000, 0x0000, 0x0000 }, /* R1471 */
1578 { 0x0000, 0x0000, 0x0000 }, /* R1472 */
1579 { 0x0000, 0x0000, 0x0000 }, /* R1473 */
1580 { 0x0000, 0x0000, 0x0000 }, /* R1474 */
1581 { 0x0000, 0x0000, 0x0000 }, /* R1475 */
1582 { 0x0000, 0x0000, 0x0000 }, /* R1476 */
1583 { 0x0000, 0x0000, 0x0000 }, /* R1477 */
1584 { 0x0000, 0x0000, 0x0000 }, /* R1478 */
1585 { 0x0000, 0x0000, 0x0000 }, /* R1479 */
1586 { 0x0000, 0x0000, 0x0000 }, /* R1480 */
1587 { 0x0000, 0x0000, 0x0000 }, /* R1481 */
1588 { 0x0000, 0x0000, 0x0000 }, /* R1482 */
1589 { 0x0000, 0x0000, 0x0000 }, /* R1483 */
1590 { 0x0000, 0x0000, 0x0000 }, /* R1484 */
1591 { 0x0000, 0x0000, 0x0000 }, /* R1485 */
1592 { 0x0000, 0x0000, 0x0000 }, /* R1486 */
1593 { 0x0000, 0x0000, 0x0000 }, /* R1487 */
1594 { 0x0000, 0x0000, 0x0000 }, /* R1488 */
1595 { 0x0000, 0x0000, 0x0000 }, /* R1489 */
1596 { 0x0000, 0x0000, 0x0000 }, /* R1490 */
1597 { 0x0000, 0x0000, 0x0000 }, /* R1491 */
1598 { 0x0000, 0x0000, 0x0000 }, /* R1492 */
1599 { 0x0000, 0x0000, 0x0000 }, /* R1493 */
1600 { 0x0000, 0x0000, 0x0000 }, /* R1494 */
1601 { 0x0000, 0x0000, 0x0000 }, /* R1495 */
1602 { 0x0000, 0x0000, 0x0000 }, /* R1496 */
1603 { 0x0000, 0x0000, 0x0000 }, /* R1497 */
1604 { 0x0000, 0x0000, 0x0000 }, /* R1498 */
1605 { 0x0000, 0x0000, 0x0000 }, /* R1499 */
1606 { 0x0000, 0x0000, 0x0000 }, /* R1500 */
1607 { 0x0000, 0x0000, 0x0000 }, /* R1501 */
1608 { 0x0000, 0x0000, 0x0000 }, /* R1502 */
1609 { 0x0000, 0x0000, 0x0000 }, /* R1503 */
1610 { 0x0000, 0x0000, 0x0000 }, /* R1504 */
1611 { 0x0000, 0x0000, 0x0000 }, /* R1505 */
1612 { 0x0000, 0x0000, 0x0000 }, /* R1506 */
1613 { 0x0000, 0x0000, 0x0000 }, /* R1507 */
1614 { 0x0000, 0x0000, 0x0000 }, /* R1508 */
1615 { 0x0000, 0x0000, 0x0000 }, /* R1509 */
1616 { 0x0000, 0x0000, 0x0000 }, /* R1510 */
1617 { 0x0000, 0x0000, 0x0000 }, /* R1511 */
1618 { 0x0000, 0x0000, 0x0000 }, /* R1512 */
1619 { 0x0000, 0x0000, 0x0000 }, /* R1513 */
1620 { 0x0000, 0x0000, 0x0000 }, /* R1514 */
1621 { 0x0000, 0x0000, 0x0000 }, /* R1515 */
1622 { 0x0000, 0x0000, 0x0000 }, /* R1516 */
1623 { 0x0000, 0x0000, 0x0000 }, /* R1517 */
1624 { 0x0000, 0x0000, 0x0000 }, /* R1518 */
1625 { 0x0000, 0x0000, 0x0000 }, /* R1519 */
1626 { 0x0000, 0x0000, 0x0000 }, /* R1520 */
1627 { 0x0000, 0x0000, 0x0000 }, /* R1521 */
1628 { 0x0000, 0x0000, 0x0000 }, /* R1522 */
1629 { 0x0000, 0x0000, 0x0000 }, /* R1523 */
1630 { 0x0000, 0x0000, 0x0000 }, /* R1524 */
1631 { 0x0000, 0x0000, 0x0000 }, /* R1525 */
1632 { 0x0000, 0x0000, 0x0000 }, /* R1526 */
1633 { 0x0000, 0x0000, 0x0000 }, /* R1527 */
1634 { 0x0000, 0x0000, 0x0000 }, /* R1528 */
1635 { 0x0000, 0x0000, 0x0000 }, /* R1529 */
1636 { 0x0000, 0x0000, 0x0000 }, /* R1530 */
1637 { 0x0000, 0x0000, 0x0000 }, /* R1531 */
1638 { 0x0000, 0x0000, 0x0000 }, /* R1532 */
1639 { 0x0000, 0x0000, 0x0000 }, /* R1533 */
1640 { 0x0000, 0x0000, 0x0000 }, /* R1534 */
1641 { 0x0000, 0x0000, 0x0000 }, /* R1535 */
1642 { 0x01EF, 0x01EF, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */
1643 { 0x0037, 0x0037, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */
1644 { 0x0037, 0x0037, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */
1645 { 0x01EF, 0x01EF, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */
1646 { 0x0037, 0x0037, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */
1647 { 0x0037, 0x0037, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */
1648 { 0x0003, 0x0003, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
1649 { 0x0003, 0x0003, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
1650 { 0x0003, 0x0003, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
1651 { 0x0003, 0x0003, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
1652 { 0x0000, 0x0000, 0x0000 }, /* R1546 */
1653 { 0x0000, 0x0000, 0x0000 }, /* R1547 */
1654 { 0x0000, 0x0000, 0x0000 }, /* R1548 */
1655 { 0x0000, 0x0000, 0x0000 }, /* R1549 */
1656 { 0x0000, 0x0000, 0x0000 }, /* R1550 */
1657 { 0x0000, 0x0000, 0x0000 }, /* R1551 */
1658 { 0x02FF, 0x03FF, 0x0000 }, /* R1552 - DAC1 Left Volume */
1659 { 0x02FF, 0x03FF, 0x0000 }, /* R1553 - DAC1 Right Volume */
1660 { 0x02FF, 0x03FF, 0x0000 }, /* R1554 - DAC2 Left Volume */
1661 { 0x02FF, 0x03FF, 0x0000 }, /* R1555 - DAC2 Right Volume */
1662 { 0x0003, 0x0003, 0x0000 }, /* R1556 - DAC Softmute */
1663 { 0x0000, 0x0000, 0x0000 }, /* R1557 */
1664 { 0x0000, 0x0000, 0x0000 }, /* R1558 */
1665 { 0x0000, 0x0000, 0x0000 }, /* R1559 */
1666 { 0x0000, 0x0000, 0x0000 }, /* R1560 */
1667 { 0x0000, 0x0000, 0x0000 }, /* R1561 */
1668 { 0x0000, 0x0000, 0x0000 }, /* R1562 */
1669 { 0x0000, 0x0000, 0x0000 }, /* R1563 */
1670 { 0x0000, 0x0000, 0x0000 }, /* R1564 */
1671 { 0x0000, 0x0000, 0x0000 }, /* R1565 */
1672 { 0x0000, 0x0000, 0x0000 }, /* R1566 */
1673 { 0x0000, 0x0000, 0x0000 }, /* R1567 */
1674 { 0x0003, 0x0003, 0x0000 }, /* R1568 - Oversampling */
1675 { 0x03C3, 0x03C3, 0x0000 }, /* R1569 - Sidetone */
1676 };
1677
1678 static int wm8994_readable(unsigned int reg)
1679 {
1680 switch (reg) {
1681 case WM8994_GPIO_1:
1682 case WM8994_GPIO_2:
1683 case WM8994_GPIO_3:
1684 case WM8994_GPIO_4:
1685 case WM8994_GPIO_5:
1686 case WM8994_GPIO_6:
1687 case WM8994_GPIO_7:
1688 case WM8994_GPIO_8:
1689 case WM8994_GPIO_9:
1690 case WM8994_GPIO_10:
1691 case WM8994_GPIO_11:
1692 case WM8994_INTERRUPT_STATUS_1:
1693 case WM8994_INTERRUPT_STATUS_2:
1694 case WM8994_INTERRUPT_RAW_STATUS_2:
1695 return 1;
1696 default:
1697 break;
1698 }
1699
1700 if (reg >= ARRAY_SIZE(access_masks))
1701 return 0;
1702 return access_masks[reg].readable != 0;
1703 }
1704
1705 static int wm8994_volatile(unsigned int reg)
1706 {
1707 if (reg >= WM8994_REG_CACHE_SIZE)
1708 return 1;
1709
1710 switch (reg) {
1711 case WM8994_SOFTWARE_RESET:
1712 case WM8994_CHIP_REVISION:
1713 case WM8994_DC_SERVO_1:
1714 case WM8994_DC_SERVO_READBACK:
1715 case WM8994_RATE_STATUS:
1716 case WM8994_LDO_1:
1717 case WM8994_LDO_2:
1718 return 1;
1719 default:
1720 return 0;
1721 }
1722 }
1723
1724 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
1725 unsigned int value)
1726 {
1727 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1728
1729 BUG_ON(reg > WM8994_MAX_REGISTER);
1730
1731 if (!wm8994_volatile(reg))
1732 wm8994->reg_cache[reg] = value;
1733
1734 dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value);
1735
1736 return wm8994_reg_write(codec->control_data, reg, value);
1737 }
1738
1739 static unsigned int wm8994_read(struct snd_soc_codec *codec,
1740 unsigned int reg)
1741 {
1742 u16 *reg_cache = codec->reg_cache;
1743
1744 BUG_ON(reg > WM8994_MAX_REGISTER);
1745
1746 if (wm8994_volatile(reg))
1747 return wm8994_reg_read(codec->control_data, reg);
1748 else
1749 return reg_cache[reg];
1750 }
1751
1752 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
1753 {
1754 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1755 int rate;
1756 int reg1 = 0;
1757 int offset;
1758
1759 if (aif)
1760 offset = 4;
1761 else
1762 offset = 0;
1763
1764 switch (wm8994->sysclk[aif]) {
1765 case WM8994_SYSCLK_MCLK1:
1766 rate = wm8994->mclk[0];
1767 break;
1768
1769 case WM8994_SYSCLK_MCLK2:
1770 reg1 |= 0x8;
1771 rate = wm8994->mclk[1];
1772 break;
1773
1774 case WM8994_SYSCLK_FLL1:
1775 reg1 |= 0x10;
1776 rate = wm8994->fll[0].out;
1777 break;
1778
1779 case WM8994_SYSCLK_FLL2:
1780 reg1 |= 0x18;
1781 rate = wm8994->fll[1].out;
1782 break;
1783
1784 default:
1785 return -EINVAL;
1786 }
1787
1788 if (rate >= 13500000) {
1789 rate /= 2;
1790 reg1 |= WM8994_AIF1CLK_DIV;
1791
1792 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
1793 aif + 1, rate);
1794 }
1795
1796 if (rate && rate < 3000000)
1797 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
1798 aif + 1, rate);
1799
1800 wm8994->aifclk[aif] = rate;
1801
1802 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
1803 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
1804 reg1);
1805
1806 return 0;
1807 }
1808
1809 static int configure_clock(struct snd_soc_codec *codec)
1810 {
1811 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1812 int old, new;
1813
1814 /* Bring up the AIF clocks first */
1815 configure_aif_clock(codec, 0);
1816 configure_aif_clock(codec, 1);
1817
1818 /* Then switch CLK_SYS over to the higher of them; a change
1819 * can only happen as a result of a clocking change which can
1820 * only be made outside of DAPM so we can safely redo the
1821 * clocking.
1822 */
1823
1824 /* If they're equal it doesn't matter which is used */
1825 if (wm8994->aifclk[0] == wm8994->aifclk[1])
1826 return 0;
1827
1828 if (wm8994->aifclk[0] < wm8994->aifclk[1])
1829 new = WM8994_SYSCLK_SRC;
1830 else
1831 new = 0;
1832
1833 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
1834
1835 /* If there's no change then we're done. */
1836 if (old == new)
1837 return 0;
1838
1839 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
1840
1841 snd_soc_dapm_sync(codec);
1842
1843 return 0;
1844 }
1845
1846 static int check_clk_sys(struct snd_soc_dapm_widget *source,
1847 struct snd_soc_dapm_widget *sink)
1848 {
1849 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
1850 const char *clk;
1851
1852 /* Check what we're currently using for CLK_SYS */
1853 if (reg & WM8994_SYSCLK_SRC)
1854 clk = "AIF2CLK";
1855 else
1856 clk = "AIF1CLK";
1857
1858 return strcmp(source->name, clk) == 0;
1859 }
1860
1861 static const char *sidetone_hpf_text[] = {
1862 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
1863 };
1864
1865 static const struct soc_enum sidetone_hpf =
1866 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
1867
1868 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
1869 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1870 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1871 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
1872 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1873
1874 #define WM8994_DRC_SWITCH(xname, reg, shift) \
1875 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1876 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
1877 .put = wm8994_put_drc_sw, \
1878 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
1879
1880 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
1881 struct snd_ctl_elem_value *ucontrol)
1882 {
1883 struct soc_mixer_control *mc =
1884 (struct soc_mixer_control *)kcontrol->private_value;
1885 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1886 int mask, ret;
1887
1888 /* Can't enable both ADC and DAC paths simultaneously */
1889 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
1890 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
1891 WM8994_AIF1ADC1R_DRC_ENA_MASK;
1892 else
1893 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
1894
1895 ret = snd_soc_read(codec, mc->reg);
1896 if (ret < 0)
1897 return ret;
1898 if (ret & mask)
1899 return -EINVAL;
1900
1901 return snd_soc_put_volsw(kcontrol, ucontrol);
1902 }
1903
1904
1905
1906 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
1907 {
1908 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1909 struct wm8994_pdata *pdata = wm8994->pdata;
1910 int base = wm8994_drc_base[drc];
1911 int cfg = wm8994->drc_cfg[drc];
1912 int save, i;
1913
1914 /* Save any enables; the configuration should clear them. */
1915 save = snd_soc_read(codec, base);
1916 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
1917 WM8994_AIF1ADC1R_DRC_ENA;
1918
1919 for (i = 0; i < WM8994_DRC_REGS; i++)
1920 snd_soc_update_bits(codec, base + i, 0xffff,
1921 pdata->drc_cfgs[cfg].regs[i]);
1922
1923 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
1924 WM8994_AIF1ADC1L_DRC_ENA |
1925 WM8994_AIF1ADC1R_DRC_ENA, save);
1926 }
1927
1928 /* Icky as hell but saves code duplication */
1929 static int wm8994_get_drc(const char *name)
1930 {
1931 if (strcmp(name, "AIF1DRC1 Mode") == 0)
1932 return 0;
1933 if (strcmp(name, "AIF1DRC2 Mode") == 0)
1934 return 1;
1935 if (strcmp(name, "AIF2DRC Mode") == 0)
1936 return 2;
1937 return -EINVAL;
1938 }
1939
1940 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
1941 struct snd_ctl_elem_value *ucontrol)
1942 {
1943 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1944 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1945 struct wm8994_pdata *pdata = wm8994->pdata;
1946 int drc = wm8994_get_drc(kcontrol->id.name);
1947 int value = ucontrol->value.integer.value[0];
1948
1949 if (drc < 0)
1950 return drc;
1951
1952 if (value >= pdata->num_drc_cfgs)
1953 return -EINVAL;
1954
1955 wm8994->drc_cfg[drc] = value;
1956
1957 wm8994_set_drc(codec, drc);
1958
1959 return 0;
1960 }
1961
1962 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
1963 struct snd_ctl_elem_value *ucontrol)
1964 {
1965 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1966 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1967 int drc = wm8994_get_drc(kcontrol->id.name);
1968
1969 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
1970
1971 return 0;
1972 }
1973
1974 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
1975 {
1976 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1977 struct wm8994_pdata *pdata = wm8994->pdata;
1978 int base = wm8994_retune_mobile_base[block];
1979 int iface, best, best_val, save, i, cfg;
1980
1981 if (!pdata || !wm8994->num_retune_mobile_texts)
1982 return;
1983
1984 switch (block) {
1985 case 0:
1986 case 1:
1987 iface = 0;
1988 break;
1989 case 2:
1990 iface = 1;
1991 break;
1992 default:
1993 return;
1994 }
1995
1996 /* Find the version of the currently selected configuration
1997 * with the nearest sample rate. */
1998 cfg = wm8994->retune_mobile_cfg[block];
1999 best = 0;
2000 best_val = INT_MAX;
2001 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2002 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2003 wm8994->retune_mobile_texts[cfg]) == 0 &&
2004 abs(pdata->retune_mobile_cfgs[i].rate
2005 - wm8994->dac_rates[iface]) < best_val) {
2006 best = i;
2007 best_val = abs(pdata->retune_mobile_cfgs[i].rate
2008 - wm8994->dac_rates[iface]);
2009 }
2010 }
2011
2012 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
2013 block,
2014 pdata->retune_mobile_cfgs[best].name,
2015 pdata->retune_mobile_cfgs[best].rate,
2016 wm8994->dac_rates[iface]);
2017
2018 /* The EQ will be disabled while reconfiguring it, remember the
2019 * current configuration.
2020 */
2021 save = snd_soc_read(codec, base);
2022 save &= WM8994_AIF1DAC1_EQ_ENA;
2023
2024 for (i = 0; i < WM8994_EQ_REGS; i++)
2025 snd_soc_update_bits(codec, base + i, 0xffff,
2026 pdata->retune_mobile_cfgs[best].regs[i]);
2027
2028 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
2029 }
2030
2031 /* Icky as hell but saves code duplication */
2032 static int wm8994_get_retune_mobile_block(const char *name)
2033 {
2034 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
2035 return 0;
2036 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
2037 return 1;
2038 if (strcmp(name, "AIF2 EQ Mode") == 0)
2039 return 2;
2040 return -EINVAL;
2041 }
2042
2043 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
2044 struct snd_ctl_elem_value *ucontrol)
2045 {
2046 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2047 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2048 struct wm8994_pdata *pdata = wm8994->pdata;
2049 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
2050 int value = ucontrol->value.integer.value[0];
2051
2052 if (block < 0)
2053 return block;
2054
2055 if (value >= pdata->num_retune_mobile_cfgs)
2056 return -EINVAL;
2057
2058 wm8994->retune_mobile_cfg[block] = value;
2059
2060 wm8994_set_retune_mobile(codec, block);
2061
2062 return 0;
2063 }
2064
2065 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
2066 struct snd_ctl_elem_value *ucontrol)
2067 {
2068 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2069 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2070 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
2071
2072 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
2073
2074 return 0;
2075 }
2076
2077 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
2078 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
2079 WM8994_AIF1_ADC1_RIGHT_VOLUME,
2080 1, 119, 0, digital_tlv),
2081 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
2082 WM8994_AIF1_ADC2_RIGHT_VOLUME,
2083 1, 119, 0, digital_tlv),
2084 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
2085 WM8994_AIF2_ADC_RIGHT_VOLUME,
2086 1, 119, 0, digital_tlv),
2087
2088 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
2089 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2090 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
2091 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2092 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
2093 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2094
2095 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
2096 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
2097
2098 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
2099 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
2100 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
2101
2102 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
2103 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
2104 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
2105
2106 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
2107 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
2108 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
2109
2110 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
2111 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
2112 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
2113
2114 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
2115 5, 12, 0, st_tlv),
2116 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
2117 0, 12, 0, st_tlv),
2118 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
2119 5, 12, 0, st_tlv),
2120 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
2121 0, 12, 0, st_tlv),
2122 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
2123 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
2124
2125 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
2126 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2127 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
2128 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
2129
2130 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
2131 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2132 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
2133 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
2134
2135 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
2136 6, 1, 1, wm_hubs_spkmix_tlv),
2137 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
2138 2, 1, 1, wm_hubs_spkmix_tlv),
2139
2140 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
2141 6, 1, 1, wm_hubs_spkmix_tlv),
2142 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
2143 2, 1, 1, wm_hubs_spkmix_tlv),
2144
2145 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
2146 10, 15, 0, wm8994_3d_tlv),
2147 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
2148 8, 1, 0),
2149 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
2150 10, 15, 0, wm8994_3d_tlv),
2151 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
2152 8, 1, 0),
2153 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
2154 10, 15, 0, wm8994_3d_tlv),
2155 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
2156 8, 1, 0),
2157 };
2158
2159 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
2160 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
2161 eq_tlv),
2162 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
2163 eq_tlv),
2164 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
2165 eq_tlv),
2166 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
2167 eq_tlv),
2168 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
2169 eq_tlv),
2170
2171 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
2172 eq_tlv),
2173 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
2174 eq_tlv),
2175 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
2176 eq_tlv),
2177 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
2178 eq_tlv),
2179 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
2180 eq_tlv),
2181
2182 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
2183 eq_tlv),
2184 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
2185 eq_tlv),
2186 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
2187 eq_tlv),
2188 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
2189 eq_tlv),
2190 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
2191 eq_tlv),
2192 };
2193
2194 static int clk_sys_event(struct snd_soc_dapm_widget *w,
2195 struct snd_kcontrol *kcontrol, int event)
2196 {
2197 struct snd_soc_codec *codec = w->codec;
2198
2199 switch (event) {
2200 case SND_SOC_DAPM_PRE_PMU:
2201 return configure_clock(codec);
2202
2203 case SND_SOC_DAPM_POST_PMD:
2204 configure_clock(codec);
2205 break;
2206 }
2207
2208 return 0;
2209 }
2210
2211 static void wm8994_update_class_w(struct snd_soc_codec *codec)
2212 {
2213 int enable = 1;
2214 int source = 0; /* GCC flow analysis can't track enable */
2215 int reg, reg_r;
2216
2217 /* Only support direct DAC->headphone paths */
2218 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
2219 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
2220 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
2221 enable = 0;
2222 }
2223
2224 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
2225 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
2226 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
2227 enable = 0;
2228 }
2229
2230 /* We also need the same setting for L/R and only one path */
2231 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
2232 switch (reg) {
2233 case WM8994_AIF2DACL_TO_DAC1L:
2234 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
2235 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
2236 break;
2237 case WM8994_AIF1DAC2L_TO_DAC1L:
2238 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
2239 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
2240 break;
2241 case WM8994_AIF1DAC1L_TO_DAC1L:
2242 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
2243 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
2244 break;
2245 default:
2246 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
2247 enable = 0;
2248 break;
2249 }
2250
2251 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
2252 if (reg_r != reg) {
2253 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
2254 enable = 0;
2255 }
2256
2257 if (enable) {
2258 dev_dbg(codec->dev, "Class W enabled\n");
2259 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
2260 WM8994_CP_DYN_PWR |
2261 WM8994_CP_DYN_SRC_SEL_MASK,
2262 source | WM8994_CP_DYN_PWR);
2263
2264 } else {
2265 dev_dbg(codec->dev, "Class W disabled\n");
2266 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
2267 WM8994_CP_DYN_PWR, 0);
2268 }
2269 }
2270
2271 static const char *hp_mux_text[] = {
2272 "Mixer",
2273 "DAC",
2274 };
2275
2276 #define WM8994_HP_ENUM(xname, xenum) \
2277 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2278 .info = snd_soc_info_enum_double, \
2279 .get = snd_soc_dapm_get_enum_double, \
2280 .put = wm8994_put_hp_enum, \
2281 .private_value = (unsigned long)&xenum }
2282
2283 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
2284 struct snd_ctl_elem_value *ucontrol)
2285 {
2286 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
2287 struct snd_soc_codec *codec = w->codec;
2288 int ret;
2289
2290 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
2291
2292 wm8994_update_class_w(codec);
2293
2294 return ret;
2295 }
2296
2297 static const struct soc_enum hpl_enum =
2298 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
2299
2300 static const struct snd_kcontrol_new hpl_mux =
2301 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
2302
2303 static const struct soc_enum hpr_enum =
2304 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
2305
2306 static const struct snd_kcontrol_new hpr_mux =
2307 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
2308
2309 static const char *adc_mux_text[] = {
2310 "ADC",
2311 "DMIC",
2312 };
2313
2314 static const struct soc_enum adc_enum =
2315 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
2316
2317 static const struct snd_kcontrol_new adcl_mux =
2318 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
2319
2320 static const struct snd_kcontrol_new adcr_mux =
2321 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
2322
2323 static const struct snd_kcontrol_new left_speaker_mixer[] = {
2324 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
2325 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
2326 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
2327 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
2328 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
2329 };
2330
2331 static const struct snd_kcontrol_new right_speaker_mixer[] = {
2332 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
2333 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
2334 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
2335 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
2336 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
2337 };
2338
2339 /* Debugging; dump chip status after DAPM transitions */
2340 static int post_ev(struct snd_soc_dapm_widget *w,
2341 struct snd_kcontrol *kcontrol, int event)
2342 {
2343 struct snd_soc_codec *codec = w->codec;
2344 dev_dbg(codec->dev, "SRC status: %x\n",
2345 snd_soc_read(codec,
2346 WM8994_RATE_STATUS));
2347 return 0;
2348 }
2349
2350 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
2351 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
2352 1, 1, 0),
2353 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
2354 0, 1, 0),
2355 };
2356
2357 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
2358 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
2359 1, 1, 0),
2360 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
2361 0, 1, 0),
2362 };
2363
2364 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
2365 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
2366 1, 1, 0),
2367 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
2368 0, 1, 0),
2369 };
2370
2371 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
2372 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
2373 1, 1, 0),
2374 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
2375 0, 1, 0),
2376 };
2377
2378 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
2379 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
2380 5, 1, 0),
2381 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
2382 4, 1, 0),
2383 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
2384 2, 1, 0),
2385 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
2386 1, 1, 0),
2387 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
2388 0, 1, 0),
2389 };
2390
2391 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
2392 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
2393 5, 1, 0),
2394 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
2395 4, 1, 0),
2396 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
2397 2, 1, 0),
2398 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
2399 1, 1, 0),
2400 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
2401 0, 1, 0),
2402 };
2403
2404 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
2405 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2406 .info = snd_soc_info_volsw, \
2407 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
2408 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
2409
2410 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
2411 struct snd_ctl_elem_value *ucontrol)
2412 {
2413 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
2414 struct snd_soc_codec *codec = w->codec;
2415 int ret;
2416
2417 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
2418
2419 wm8994_update_class_w(codec);
2420
2421 return ret;
2422 }
2423
2424 static const struct snd_kcontrol_new dac1l_mix[] = {
2425 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
2426 5, 1, 0),
2427 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
2428 4, 1, 0),
2429 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
2430 2, 1, 0),
2431 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
2432 1, 1, 0),
2433 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
2434 0, 1, 0),
2435 };
2436
2437 static const struct snd_kcontrol_new dac1r_mix[] = {
2438 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
2439 5, 1, 0),
2440 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
2441 4, 1, 0),
2442 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
2443 2, 1, 0),
2444 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
2445 1, 1, 0),
2446 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
2447 0, 1, 0),
2448 };
2449
2450 static const char *sidetone_text[] = {
2451 "ADC/DMIC1", "DMIC2",
2452 };
2453
2454 static const struct soc_enum sidetone1_enum =
2455 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
2456
2457 static const struct snd_kcontrol_new sidetone1_mux =
2458 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
2459
2460 static const struct soc_enum sidetone2_enum =
2461 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
2462
2463 static const struct snd_kcontrol_new sidetone2_mux =
2464 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
2465
2466 static const char *aif1dac_text[] = {
2467 "AIF1DACDAT", "AIF3DACDAT",
2468 };
2469
2470 static const struct soc_enum aif1dac_enum =
2471 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
2472
2473 static const struct snd_kcontrol_new aif1dac_mux =
2474 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
2475
2476 static const char *aif2dac_text[] = {
2477 "AIF2DACDAT", "AIF3DACDAT",
2478 };
2479
2480 static const struct soc_enum aif2dac_enum =
2481 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
2482
2483 static const struct snd_kcontrol_new aif2dac_mux =
2484 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
2485
2486 static const char *aif2adc_text[] = {
2487 "AIF2ADCDAT", "AIF3DACDAT",
2488 };
2489
2490 static const struct soc_enum aif2adc_enum =
2491 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
2492
2493 static const struct snd_kcontrol_new aif2adc_mux =
2494 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
2495
2496 static const char *aif3adc_text[] = {
2497 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT",
2498 };
2499
2500 static const struct soc_enum aif3adc_enum =
2501 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
2502
2503 static const struct snd_kcontrol_new aif3adc_mux =
2504 SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum);
2505
2506 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
2507 SND_SOC_DAPM_INPUT("DMIC1DAT"),
2508 SND_SOC_DAPM_INPUT("DMIC2DAT"),
2509 SND_SOC_DAPM_INPUT("Clock"),
2510
2511 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
2512 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2513
2514 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
2515 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
2516 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
2517
2518 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
2519 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
2520
2521 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
2522 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
2523 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
2524 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
2525 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0,
2526 WM8994_POWER_MANAGEMENT_5, 9, 0),
2527 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0,
2528 WM8994_POWER_MANAGEMENT_5, 8, 0),
2529
2530 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
2531 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
2532 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
2533 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
2534 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0,
2535 WM8994_POWER_MANAGEMENT_5, 11, 0),
2536 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0,
2537 WM8994_POWER_MANAGEMENT_5, 10, 0),
2538
2539 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
2540 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
2541 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
2542 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
2543
2544 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
2545 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
2546 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
2547 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
2548
2549 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
2550 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
2551 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
2552 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
2553
2554 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
2555 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
2556
2557 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
2558 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
2559 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
2560 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
2561
2562 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
2563 WM8994_POWER_MANAGEMENT_4, 13, 0),
2564 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
2565 WM8994_POWER_MANAGEMENT_4, 12, 0),
2566 SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0,
2567 WM8994_POWER_MANAGEMENT_5, 13, 0),
2568 SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0,
2569 WM8994_POWER_MANAGEMENT_5, 12, 0),
2570
2571 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2572 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2573 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2574
2575 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
2576 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
2577 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
2578 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux),
2579
2580 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2581 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2582
2583 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
2584
2585 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
2586 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
2587 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
2588 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
2589
2590 /* Power is done with the muxes since the ADC power also controls the
2591 * downsampling chain, the chip will automatically manage the analogue
2592 * specific portions.
2593 */
2594 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
2595 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
2596
2597 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
2598 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
2599
2600 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
2601 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
2602 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
2603 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
2604
2605 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
2606 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
2607
2608 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
2609 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
2610 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
2611 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
2612
2613 SND_SOC_DAPM_POST("Debug log", post_ev),
2614 };
2615
2616 static const struct snd_soc_dapm_route intercon[] = {
2617
2618 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
2619 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
2620
2621 { "DSP1CLK", NULL, "CLK_SYS" },
2622 { "DSP2CLK", NULL, "CLK_SYS" },
2623 { "DSPINTCLK", NULL, "CLK_SYS" },
2624
2625 { "AIF1ADC1L", NULL, "AIF1CLK" },
2626 { "AIF1ADC1L", NULL, "DSP1CLK" },
2627 { "AIF1ADC1R", NULL, "AIF1CLK" },
2628 { "AIF1ADC1R", NULL, "DSP1CLK" },
2629 { "AIF1ADC1R", NULL, "DSPINTCLK" },
2630
2631 { "AIF1DAC1L", NULL, "AIF1CLK" },
2632 { "AIF1DAC1L", NULL, "DSP1CLK" },
2633 { "AIF1DAC1R", NULL, "AIF1CLK" },
2634 { "AIF1DAC1R", NULL, "DSP1CLK" },
2635 { "AIF1DAC1R", NULL, "DSPINTCLK" },
2636
2637 { "AIF1ADC2L", NULL, "AIF1CLK" },
2638 { "AIF1ADC2L", NULL, "DSP1CLK" },
2639 { "AIF1ADC2R", NULL, "AIF1CLK" },
2640 { "AIF1ADC2R", NULL, "DSP1CLK" },
2641 { "AIF1ADC2R", NULL, "DSPINTCLK" },
2642
2643 { "AIF1DAC2L", NULL, "AIF1CLK" },
2644 { "AIF1DAC2L", NULL, "DSP1CLK" },
2645 { "AIF1DAC2R", NULL, "AIF1CLK" },
2646 { "AIF1DAC2R", NULL, "DSP1CLK" },
2647 { "AIF1DAC2R", NULL, "DSPINTCLK" },
2648
2649 { "AIF2ADCL", NULL, "AIF2CLK" },
2650 { "AIF2ADCL", NULL, "DSP2CLK" },
2651 { "AIF2ADCR", NULL, "AIF2CLK" },
2652 { "AIF2ADCR", NULL, "DSP2CLK" },
2653 { "AIF2ADCR", NULL, "DSPINTCLK" },
2654
2655 { "AIF2DACL", NULL, "AIF2CLK" },
2656 { "AIF2DACL", NULL, "DSP2CLK" },
2657 { "AIF2DACR", NULL, "AIF2CLK" },
2658 { "AIF2DACR", NULL, "DSP2CLK" },
2659 { "AIF2DACR", NULL, "DSPINTCLK" },
2660
2661 { "DMIC1L", NULL, "DMIC1DAT" },
2662 { "DMIC1L", NULL, "CLK_SYS" },
2663 { "DMIC1R", NULL, "DMIC1DAT" },
2664 { "DMIC1R", NULL, "CLK_SYS" },
2665 { "DMIC2L", NULL, "DMIC2DAT" },
2666 { "DMIC2L", NULL, "CLK_SYS" },
2667 { "DMIC2R", NULL, "DMIC2DAT" },
2668 { "DMIC2R", NULL, "CLK_SYS" },
2669
2670 { "ADCL", NULL, "AIF1CLK" },
2671 { "ADCL", NULL, "DSP1CLK" },
2672 { "ADCL", NULL, "DSPINTCLK" },
2673
2674 { "ADCR", NULL, "AIF1CLK" },
2675 { "ADCR", NULL, "DSP1CLK" },
2676 { "ADCR", NULL, "DSPINTCLK" },
2677
2678 { "ADCL Mux", "ADC", "ADCL" },
2679 { "ADCL Mux", "DMIC", "DMIC1L" },
2680 { "ADCR Mux", "ADC", "ADCR" },
2681 { "ADCR Mux", "DMIC", "DMIC1R" },
2682
2683 { "DAC1L", NULL, "AIF1CLK" },
2684 { "DAC1L", NULL, "DSP1CLK" },
2685 { "DAC1L", NULL, "DSPINTCLK" },
2686
2687 { "DAC1R", NULL, "AIF1CLK" },
2688 { "DAC1R", NULL, "DSP1CLK" },
2689 { "DAC1R", NULL, "DSPINTCLK" },
2690
2691 { "DAC2L", NULL, "AIF2CLK" },
2692 { "DAC2L", NULL, "DSP2CLK" },
2693 { "DAC2L", NULL, "DSPINTCLK" },
2694
2695 { "DAC2R", NULL, "AIF2DACR" },
2696 { "DAC2R", NULL, "AIF2CLK" },
2697 { "DAC2R", NULL, "DSP2CLK" },
2698 { "DAC2R", NULL, "DSPINTCLK" },
2699
2700 { "TOCLK", NULL, "CLK_SYS" },
2701
2702 /* AIF1 outputs */
2703 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
2704 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
2705 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
2706
2707 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
2708 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
2709 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
2710
2711 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
2712 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
2713 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
2714
2715 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
2716 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
2717 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
2718
2719 /* Pin level routing for AIF3 */
2720 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
2721 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
2722 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
2723 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
2724
2725 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2726 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2727
2728 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
2729 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
2730 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
2731 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
2732 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
2733 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
2734 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
2735
2736 /* DAC1 inputs */
2737 { "DAC1L", NULL, "DAC1L Mixer" },
2738 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
2739 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
2740 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
2741 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
2742 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
2743
2744 { "DAC1R", NULL, "DAC1R Mixer" },
2745 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
2746 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
2747 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
2748 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
2749 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
2750
2751 /* DAC2/AIF2 outputs */
2752 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
2753 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
2754 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
2755 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
2756 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
2757 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
2758 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
2759
2760 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
2761 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
2762 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
2763 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
2764 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
2765 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
2766 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
2767
2768 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
2769
2770 /* AIF3 output */
2771 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
2772 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
2773 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
2774 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
2775 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
2776 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
2777 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
2778 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
2779
2780 /* Sidetone */
2781 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
2782 { "Left Sidetone", "DMIC2", "DMIC2L" },
2783 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
2784 { "Right Sidetone", "DMIC2", "DMIC2R" },
2785
2786 /* Output stages */
2787 { "Left Output Mixer", "DAC Switch", "DAC1L" },
2788 { "Right Output Mixer", "DAC Switch", "DAC1R" },
2789
2790 { "SPKL", "DAC1 Switch", "DAC1L" },
2791 { "SPKL", "DAC2 Switch", "DAC2L" },
2792
2793 { "SPKR", "DAC1 Switch", "DAC1R" },
2794 { "SPKR", "DAC2 Switch", "DAC2R" },
2795
2796 { "Left Headphone Mux", "DAC", "DAC1L" },
2797 { "Right Headphone Mux", "DAC", "DAC1R" },
2798 };
2799
2800 /* The size in bits of the FLL divide multiplied by 10
2801 * to allow rounding later */
2802 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2803
2804 struct fll_div {
2805 u16 outdiv;
2806 u16 n;
2807 u16 k;
2808 u16 clk_ref_div;
2809 u16 fll_fratio;
2810 };
2811
2812 static int wm8994_get_fll_config(struct fll_div *fll,
2813 int freq_in, int freq_out)
2814 {
2815 u64 Kpart;
2816 unsigned int K, Ndiv, Nmod;
2817
2818 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2819
2820 /* Scale the input frequency down to <= 13.5MHz */
2821 fll->clk_ref_div = 0;
2822 while (freq_in > 13500000) {
2823 fll->clk_ref_div++;
2824 freq_in /= 2;
2825
2826 if (fll->clk_ref_div > 3)
2827 return -EINVAL;
2828 }
2829 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2830
2831 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2832 fll->outdiv = 3;
2833 while (freq_out * (fll->outdiv + 1) < 90000000) {
2834 fll->outdiv++;
2835 if (fll->outdiv > 63)
2836 return -EINVAL;
2837 }
2838 freq_out *= fll->outdiv + 1;
2839 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2840
2841 if (freq_in > 1000000) {
2842 fll->fll_fratio = 0;
2843 } else if (freq_in > 256000) {
2844 fll->fll_fratio = 1;
2845 freq_in *= 2;
2846 } else if (freq_in > 128000) {
2847 fll->fll_fratio = 2;
2848 freq_in *= 4;
2849 } else if (freq_in > 64000) {
2850 fll->fll_fratio = 3;
2851 freq_in *= 8;
2852 } else {
2853 fll->fll_fratio = 4;
2854 freq_in *= 16;
2855 }
2856 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2857
2858 /* Now, calculate N.K */
2859 Ndiv = freq_out / freq_in;
2860
2861 fll->n = Ndiv;
2862 Nmod = freq_out % freq_in;
2863 pr_debug("Nmod=%d\n", Nmod);
2864
2865 /* Calculate fractional part - scale up so we can round. */
2866 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2867
2868 do_div(Kpart, freq_in);
2869
2870 K = Kpart & 0xFFFFFFFF;
2871
2872 if ((K % 10) >= 5)
2873 K += 5;
2874
2875 /* Move down to proper range now rounding is done */
2876 fll->k = K / 10;
2877
2878 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2879
2880 return 0;
2881 }
2882
2883 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2884 unsigned int freq_in, unsigned int freq_out)
2885 {
2886 struct snd_soc_codec *codec = dai->codec;
2887 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2888 int reg_offset, ret;
2889 struct fll_div fll;
2890 u16 reg, aif1, aif2;
2891
2892 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
2893 & WM8994_AIF1CLK_ENA;
2894
2895 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
2896 & WM8994_AIF2CLK_ENA;
2897
2898 switch (id) {
2899 case WM8994_FLL1:
2900 reg_offset = 0;
2901 id = 0;
2902 break;
2903 case WM8994_FLL2:
2904 reg_offset = 0x20;
2905 id = 1;
2906 break;
2907 default:
2908 return -EINVAL;
2909 }
2910
2911 switch (src) {
2912 case 0:
2913 /* Allow no source specification when stopping */
2914 if (freq_out)
2915 return -EINVAL;
2916 break;
2917 case WM8994_FLL_SRC_MCLK1:
2918 case WM8994_FLL_SRC_MCLK2:
2919 case WM8994_FLL_SRC_LRCLK:
2920 case WM8994_FLL_SRC_BCLK:
2921 break;
2922 default:
2923 return -EINVAL;
2924 }
2925
2926 /* Are we changing anything? */
2927 if (wm8994->fll[id].src == src &&
2928 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2929 return 0;
2930
2931 /* If we're stopping the FLL redo the old config - no
2932 * registers will actually be written but we avoid GCC flow
2933 * analysis bugs spewing warnings.
2934 */
2935 if (freq_out)
2936 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2937 else
2938 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2939 wm8994->fll[id].out);
2940 if (ret < 0)
2941 return ret;
2942
2943 /* Gate the AIF clocks while we reclock */
2944 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2945 WM8994_AIF1CLK_ENA, 0);
2946 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2947 WM8994_AIF2CLK_ENA, 0);
2948
2949 /* We always need to disable the FLL while reconfiguring */
2950 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2951 WM8994_FLL1_ENA, 0);
2952
2953 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2954 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2955 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2956 WM8994_FLL1_OUTDIV_MASK |
2957 WM8994_FLL1_FRATIO_MASK, reg);
2958
2959 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
2960
2961 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2962 WM8994_FLL1_N_MASK,
2963 fll.n << WM8994_FLL1_N_SHIFT);
2964
2965 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2966 WM8994_FLL1_REFCLK_DIV_MASK |
2967 WM8994_FLL1_REFCLK_SRC_MASK,
2968 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2969 (src - 1));
2970
2971 /* Enable (with fractional mode if required) */
2972 if (freq_out) {
2973 if (fll.k)
2974 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2975 else
2976 reg = WM8994_FLL1_ENA;
2977 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2978 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2979 reg);
2980 }
2981
2982 wm8994->fll[id].in = freq_in;
2983 wm8994->fll[id].out = freq_out;
2984 wm8994->fll[id].src = src;
2985
2986 /* Enable any gated AIF clocks */
2987 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2988 WM8994_AIF1CLK_ENA, aif1);
2989 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2990 WM8994_AIF2CLK_ENA, aif2);
2991
2992 configure_clock(codec);
2993
2994 return 0;
2995 }
2996
2997 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2998
2999 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
3000 int clk_id, unsigned int freq, int dir)
3001 {
3002 struct snd_soc_codec *codec = dai->codec;
3003 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3004 int i;
3005
3006 switch (dai->id) {
3007 case 1:
3008 case 2:
3009 break;
3010
3011 default:
3012 /* AIF3 shares clocking with AIF1/2 */
3013 return -EINVAL;
3014 }
3015
3016 switch (clk_id) {
3017 case WM8994_SYSCLK_MCLK1:
3018 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
3019 wm8994->mclk[0] = freq;
3020 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
3021 dai->id, freq);
3022 break;
3023
3024 case WM8994_SYSCLK_MCLK2:
3025 /* TODO: Set GPIO AF */
3026 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
3027 wm8994->mclk[1] = freq;
3028 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
3029 dai->id, freq);
3030 break;
3031
3032 case WM8994_SYSCLK_FLL1:
3033 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
3034 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
3035 break;
3036
3037 case WM8994_SYSCLK_FLL2:
3038 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
3039 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
3040 break;
3041
3042 case WM8994_SYSCLK_OPCLK:
3043 /* Special case - a division (times 10) is given and
3044 * no effect on main clocking.
3045 */
3046 if (freq) {
3047 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
3048 if (opclk_divs[i] == freq)
3049 break;
3050 if (i == ARRAY_SIZE(opclk_divs))
3051 return -EINVAL;
3052 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
3053 WM8994_OPCLK_DIV_MASK, i);
3054 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
3055 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
3056 } else {
3057 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
3058 WM8994_OPCLK_ENA, 0);
3059 }
3060
3061 default:
3062 return -EINVAL;
3063 }
3064
3065 configure_clock(codec);
3066
3067 return 0;
3068 }
3069
3070 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3071 enum snd_soc_bias_level level)
3072 {
3073 switch (level) {
3074 case SND_SOC_BIAS_ON:
3075 break;
3076
3077 case SND_SOC_BIAS_PREPARE:
3078 /* VMID=2x40k */
3079 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
3080 WM8994_VMID_SEL_MASK, 0x2);
3081 break;
3082
3083 case SND_SOC_BIAS_STANDBY:
3084 if (codec->bias_level == SND_SOC_BIAS_OFF) {
3085 /* Tweak DC servo configuration for improved
3086 * performance. */
3087 snd_soc_write(codec, 0x102, 0x3);
3088 snd_soc_write(codec, 0x56, 0x3);
3089 snd_soc_write(codec, 0x102, 0);
3090
3091 /* Discharge LINEOUT1 & 2 */
3092 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
3093 WM8994_LINEOUT1_DISCH |
3094 WM8994_LINEOUT2_DISCH,
3095 WM8994_LINEOUT1_DISCH |
3096 WM8994_LINEOUT2_DISCH);
3097
3098 /* Startup bias, VMID ramp & buffer */
3099 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3100 WM8994_STARTUP_BIAS_ENA |
3101 WM8994_VMID_BUF_ENA |
3102 WM8994_VMID_RAMP_MASK,
3103 WM8994_STARTUP_BIAS_ENA |
3104 WM8994_VMID_BUF_ENA |
3105 (0x11 << WM8994_VMID_RAMP_SHIFT));
3106
3107 /* Main bias enable, VMID=2x40k */
3108 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
3109 WM8994_BIAS_ENA |
3110 WM8994_VMID_SEL_MASK,
3111 WM8994_BIAS_ENA | 0x2);
3112
3113 msleep(20);
3114 }
3115
3116 /* VMID=2x500k */
3117 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
3118 WM8994_VMID_SEL_MASK, 0x4);
3119
3120 break;
3121
3122 case SND_SOC_BIAS_OFF:
3123 if (codec->bias_level == SND_SOC_BIAS_STANDBY) {
3124 /* Switch over to startup biases */
3125 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3126 WM8994_BIAS_SRC |
3127 WM8994_STARTUP_BIAS_ENA |
3128 WM8994_VMID_BUF_ENA |
3129 WM8994_VMID_RAMP_MASK,
3130 WM8994_BIAS_SRC |
3131 WM8994_STARTUP_BIAS_ENA |
3132 WM8994_VMID_BUF_ENA |
3133 (1 << WM8994_VMID_RAMP_SHIFT));
3134
3135 /* Disable main biases */
3136 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
3137 WM8994_BIAS_ENA |
3138 WM8994_VMID_SEL_MASK, 0);
3139
3140 /* Discharge line */
3141 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
3142 WM8994_LINEOUT1_DISCH |
3143 WM8994_LINEOUT2_DISCH,
3144 WM8994_LINEOUT1_DISCH |
3145 WM8994_LINEOUT2_DISCH);
3146
3147 msleep(5);
3148
3149 /* Switch off startup biases */
3150 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3151 WM8994_BIAS_SRC |
3152 WM8994_STARTUP_BIAS_ENA |
3153 WM8994_VMID_BUF_ENA |
3154 WM8994_VMID_RAMP_MASK, 0);
3155 }
3156 break;
3157 }
3158 codec->bias_level = level;
3159 return 0;
3160 }
3161
3162 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3163 {
3164 struct snd_soc_codec *codec = dai->codec;
3165 int ms_reg;
3166 int aif1_reg;
3167 int ms = 0;
3168 int aif1 = 0;
3169
3170 switch (dai->id) {
3171 case 1:
3172 ms_reg = WM8994_AIF1_MASTER_SLAVE;
3173 aif1_reg = WM8994_AIF1_CONTROL_1;
3174 break;
3175 case 2:
3176 ms_reg = WM8994_AIF2_MASTER_SLAVE;
3177 aif1_reg = WM8994_AIF2_CONTROL_1;
3178 break;
3179 default:
3180 return -EINVAL;
3181 }
3182
3183 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3184 case SND_SOC_DAIFMT_CBS_CFS:
3185 break;
3186 case SND_SOC_DAIFMT_CBM_CFM:
3187 ms = WM8994_AIF1_MSTR;
3188 break;
3189 default:
3190 return -EINVAL;
3191 }
3192
3193 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3194 case SND_SOC_DAIFMT_DSP_B:
3195 aif1 |= WM8994_AIF1_LRCLK_INV;
3196 case SND_SOC_DAIFMT_DSP_A:
3197 aif1 |= 0x18;
3198 break;
3199 case SND_SOC_DAIFMT_I2S:
3200 aif1 |= 0x10;
3201 break;
3202 case SND_SOC_DAIFMT_RIGHT_J:
3203 break;
3204 case SND_SOC_DAIFMT_LEFT_J:
3205 aif1 |= 0x8;
3206 break;
3207 default:
3208 return -EINVAL;
3209 }
3210
3211 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3212 case SND_SOC_DAIFMT_DSP_A:
3213 case SND_SOC_DAIFMT_DSP_B:
3214 /* frame inversion not valid for DSP modes */
3215 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3216 case SND_SOC_DAIFMT_NB_NF:
3217 break;
3218 case SND_SOC_DAIFMT_IB_NF:
3219 aif1 |= WM8994_AIF1_BCLK_INV;
3220 break;
3221 default:
3222 return -EINVAL;
3223 }
3224 break;
3225
3226 case SND_SOC_DAIFMT_I2S:
3227 case SND_SOC_DAIFMT_RIGHT_J:
3228 case SND_SOC_DAIFMT_LEFT_J:
3229 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3230 case SND_SOC_DAIFMT_NB_NF:
3231 break;
3232 case SND_SOC_DAIFMT_IB_IF:
3233 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
3234 break;
3235 case SND_SOC_DAIFMT_IB_NF:
3236 aif1 |= WM8994_AIF1_BCLK_INV;
3237 break;
3238 case SND_SOC_DAIFMT_NB_IF:
3239 aif1 |= WM8994_AIF1_LRCLK_INV;
3240 break;
3241 default:
3242 return -EINVAL;
3243 }
3244 break;
3245 default:
3246 return -EINVAL;
3247 }
3248
3249 snd_soc_update_bits(codec, aif1_reg,
3250 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
3251 WM8994_AIF1_FMT_MASK,
3252 aif1);
3253 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
3254 ms);
3255
3256 return 0;
3257 }
3258
3259 static struct {
3260 int val, rate;
3261 } srs[] = {
3262 { 0, 8000 },
3263 { 1, 11025 },
3264 { 2, 12000 },
3265 { 3, 16000 },
3266 { 4, 22050 },
3267 { 5, 24000 },
3268 { 6, 32000 },
3269 { 7, 44100 },
3270 { 8, 48000 },
3271 { 9, 88200 },
3272 { 10, 96000 },
3273 };
3274
3275 static int fs_ratios[] = {
3276 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
3277 };
3278
3279 static int bclk_divs[] = {
3280 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
3281 640, 880, 960, 1280, 1760, 1920
3282 };
3283
3284 static int wm8994_hw_params(struct snd_pcm_substream *substream,
3285 struct snd_pcm_hw_params *params,
3286 struct snd_soc_dai *dai)
3287 {
3288 struct snd_soc_codec *codec = dai->codec;
3289 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3290 int aif1_reg;
3291 int bclk_reg;
3292 int lrclk_reg;
3293 int rate_reg;
3294 int aif1 = 0;
3295 int bclk = 0;
3296 int lrclk = 0;
3297 int rate_val = 0;
3298 int id = dai->id - 1;
3299
3300 int i, cur_val, best_val, bclk_rate, best;
3301
3302 switch (dai->id) {
3303 case 1:
3304 aif1_reg = WM8994_AIF1_CONTROL_1;
3305 bclk_reg = WM8994_AIF1_BCLK;
3306 rate_reg = WM8994_AIF1_RATE;
3307 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
3308 wm8994->lrclk_shared[0])
3309 lrclk_reg = WM8994_AIF1DAC_LRCLK;
3310 else
3311 lrclk_reg = WM8994_AIF1ADC_LRCLK;
3312 break;
3313 case 2:
3314 aif1_reg = WM8994_AIF2_CONTROL_1;
3315 bclk_reg = WM8994_AIF2_BCLK;
3316 rate_reg = WM8994_AIF2_RATE;
3317 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
3318 wm8994->lrclk_shared[1])
3319 lrclk_reg = WM8994_AIF2DAC_LRCLK;
3320 else
3321 lrclk_reg = WM8994_AIF2ADC_LRCLK;
3322 break;
3323 default:
3324 return -EINVAL;
3325 }
3326
3327 bclk_rate = params_rate(params) * 2;
3328 switch (params_format(params)) {
3329 case SNDRV_PCM_FORMAT_S16_LE:
3330 bclk_rate *= 16;
3331 break;
3332 case SNDRV_PCM_FORMAT_S20_3LE:
3333 bclk_rate *= 20;
3334 aif1 |= 0x20;
3335 break;
3336 case SNDRV_PCM_FORMAT_S24_LE:
3337 bclk_rate *= 24;
3338 aif1 |= 0x40;
3339 break;
3340 case SNDRV_PCM_FORMAT_S32_LE:
3341 bclk_rate *= 32;
3342 aif1 |= 0x60;
3343 break;
3344 default:
3345 return -EINVAL;
3346 }
3347
3348 /* Try to find an appropriate sample rate; look for an exact match. */
3349 for (i = 0; i < ARRAY_SIZE(srs); i++)
3350 if (srs[i].rate == params_rate(params))
3351 break;
3352 if (i == ARRAY_SIZE(srs))
3353 return -EINVAL;
3354 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
3355
3356 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
3357 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
3358 dai->id, wm8994->aifclk[id], bclk_rate);
3359
3360 if (wm8994->aifclk[id] == 0) {
3361 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
3362 return -EINVAL;
3363 }
3364
3365 /* AIFCLK/fs ratio; look for a close match in either direction */
3366 best = 0;
3367 best_val = abs((fs_ratios[0] * params_rate(params))
3368 - wm8994->aifclk[id]);
3369 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
3370 cur_val = abs((fs_ratios[i] * params_rate(params))
3371 - wm8994->aifclk[id]);
3372 if (cur_val >= best_val)
3373 continue;
3374 best = i;
3375 best_val = cur_val;
3376 }
3377 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
3378 dai->id, fs_ratios[best]);
3379 rate_val |= best;
3380
3381 /* We may not get quite the right frequency if using
3382 * approximate clocks so look for the closest match that is
3383 * higher than the target (we need to ensure that there enough
3384 * BCLKs to clock out the samples).
3385 */
3386 best = 0;
3387 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
3388 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
3389 if (cur_val < 0) /* BCLK table is sorted */
3390 break;
3391 best = i;
3392 }
3393 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
3394 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
3395 bclk_divs[best], bclk_rate);
3396 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
3397
3398 lrclk = bclk_rate / params_rate(params);
3399 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
3400 lrclk, bclk_rate / lrclk);
3401
3402 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
3403 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
3404 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
3405 lrclk);
3406 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
3407 WM8994_AIF1CLK_RATE_MASK, rate_val);
3408
3409 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3410 switch (dai->id) {
3411 case 1:
3412 wm8994->dac_rates[0] = params_rate(params);
3413 wm8994_set_retune_mobile(codec, 0);
3414 wm8994_set_retune_mobile(codec, 1);
3415 break;
3416 case 2:
3417 wm8994->dac_rates[1] = params_rate(params);
3418 wm8994_set_retune_mobile(codec, 2);
3419 break;
3420 }
3421 }
3422
3423 return 0;
3424 }
3425
3426 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
3427 {
3428 struct snd_soc_codec *codec = codec_dai->codec;
3429 int mute_reg;
3430 int reg;
3431
3432 switch (codec_dai->id) {
3433 case 1:
3434 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
3435 break;
3436 case 2:
3437 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
3438 break;
3439 default:
3440 return -EINVAL;
3441 }
3442
3443 if (mute)
3444 reg = WM8994_AIF1DAC1_MUTE;
3445 else
3446 reg = 0;
3447
3448 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3449
3450 return 0;
3451 }
3452
3453 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3454 {
3455 struct snd_soc_codec *codec = codec_dai->codec;
3456 int reg, val, mask;
3457
3458 switch (codec_dai->id) {
3459 case 1:
3460 reg = WM8994_AIF1_MASTER_SLAVE;
3461 mask = WM8994_AIF1_TRI;
3462 break;
3463 case 2:
3464 reg = WM8994_AIF2_MASTER_SLAVE;
3465 mask = WM8994_AIF2_TRI;
3466 break;
3467 case 3:
3468 reg = WM8994_POWER_MANAGEMENT_6;
3469 mask = WM8994_AIF3_TRI;
3470 break;
3471 default:
3472 return -EINVAL;
3473 }
3474
3475 if (tristate)
3476 val = mask;
3477 else
3478 val = 0;
3479
3480 return snd_soc_update_bits(codec, reg, mask, reg);
3481 }
3482
3483 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3484
3485 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3486 SNDRV_PCM_FMTBIT_S24_LE)
3487
3488 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3489 .set_sysclk = wm8994_set_dai_sysclk,
3490 .set_fmt = wm8994_set_dai_fmt,
3491 .hw_params = wm8994_hw_params,
3492 .digital_mute = wm8994_aif_mute,
3493 .set_pll = wm8994_set_fll,
3494 .set_tristate = wm8994_set_tristate,
3495 };
3496
3497 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3498 .set_sysclk = wm8994_set_dai_sysclk,
3499 .set_fmt = wm8994_set_dai_fmt,
3500 .hw_params = wm8994_hw_params,
3501 .digital_mute = wm8994_aif_mute,
3502 .set_pll = wm8994_set_fll,
3503 .set_tristate = wm8994_set_tristate,
3504 };
3505
3506 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3507 .set_tristate = wm8994_set_tristate,
3508 };
3509
3510 struct snd_soc_dai wm8994_dai[] = {
3511 {
3512 .name = "WM8994 AIF1",
3513 .id = 1,
3514 .playback = {
3515 .stream_name = "AIF1 Playback",
3516 .channels_min = 2,
3517 .channels_max = 2,
3518 .rates = WM8994_RATES,
3519 .formats = WM8994_FORMATS,
3520 },
3521 .capture = {
3522 .stream_name = "AIF1 Capture",
3523 .channels_min = 2,
3524 .channels_max = 2,
3525 .rates = WM8994_RATES,
3526 .formats = WM8994_FORMATS,
3527 },
3528 .ops = &wm8994_aif1_dai_ops,
3529 },
3530 {
3531 .name = "WM8994 AIF2",
3532 .id = 2,
3533 .playback = {
3534 .stream_name = "AIF2 Playback",
3535 .channels_min = 2,
3536 .channels_max = 2,
3537 .rates = WM8994_RATES,
3538 .formats = WM8994_FORMATS,
3539 },
3540 .capture = {
3541 .stream_name = "AIF2 Capture",
3542 .channels_min = 2,
3543 .channels_max = 2,
3544 .rates = WM8994_RATES,
3545 .formats = WM8994_FORMATS,
3546 },
3547 .ops = &wm8994_aif2_dai_ops,
3548 },
3549 {
3550 .name = "WM8994 AIF3",
3551 .id = 3,
3552 .playback = {
3553 .stream_name = "AIF3 Playback",
3554 .channels_min = 2,
3555 .channels_max = 2,
3556 .rates = WM8994_RATES,
3557 .formats = WM8994_FORMATS,
3558 },
3559 .capture = {
3560 .stream_name = "AIF3 Capture",
3561 .channels_min = 2,
3562 .channels_max = 2,
3563 .rates = WM8994_RATES,
3564 .formats = WM8994_FORMATS,
3565 },
3566 .ops = &wm8994_aif3_dai_ops,
3567 }
3568 };
3569 EXPORT_SYMBOL_GPL(wm8994_dai);
3570
3571 #ifdef CONFIG_PM
3572 static int wm8994_suspend(struct platform_device *pdev, pm_message_t state)
3573 {
3574 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3575 struct snd_soc_codec *codec = socdev->card->codec;
3576 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3577 int i, ret;
3578
3579 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3580 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3581 sizeof(struct fll_config));
3582 ret = wm8994_set_fll(&codec->dai[0], i + 1, 0, 0, 0);
3583 if (ret < 0)
3584 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3585 i + 1, ret);
3586 }
3587
3588 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3589
3590 return 0;
3591 }
3592
3593 static int wm8994_resume(struct platform_device *pdev)
3594 {
3595 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3596 struct snd_soc_codec *codec = socdev->card->codec;
3597 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3598 u16 *reg_cache = codec->reg_cache;
3599 int i, ret;
3600
3601 /* Restore the registers */
3602 for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) {
3603 switch (i) {
3604 case WM8994_LDO_1:
3605 case WM8994_LDO_2:
3606 case WM8994_SOFTWARE_RESET:
3607 /* Handled by other MFD drivers */
3608 continue;
3609 default:
3610 break;
3611 }
3612
3613 if (!access_masks[i].writable)
3614 continue;
3615
3616 wm8994_reg_write(codec->control_data, i, reg_cache[i]);
3617 }
3618
3619 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3620
3621 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3622 if (!wm8994->fll_suspend[i].out)
3623 continue;
3624
3625 ret = wm8994_set_fll(&codec->dai[0], i + 1,
3626 wm8994->fll_suspend[i].src,
3627 wm8994->fll_suspend[i].in,
3628 wm8994->fll_suspend[i].out);
3629 if (ret < 0)
3630 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3631 i + 1, ret);
3632 }
3633
3634 return 0;
3635 }
3636 #else
3637 #define wm8994_suspend NULL
3638 #define wm8994_resume NULL
3639 #endif
3640
3641 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3642 {
3643 struct snd_soc_codec *codec = &wm8994->codec;
3644 struct wm8994_pdata *pdata = wm8994->pdata;
3645 struct snd_kcontrol_new controls[] = {
3646 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3647 wm8994->retune_mobile_enum,
3648 wm8994_get_retune_mobile_enum,
3649 wm8994_put_retune_mobile_enum),
3650 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3651 wm8994->retune_mobile_enum,
3652 wm8994_get_retune_mobile_enum,
3653 wm8994_put_retune_mobile_enum),
3654 SOC_ENUM_EXT("AIF2 EQ Mode",
3655 wm8994->retune_mobile_enum,
3656 wm8994_get_retune_mobile_enum,
3657 wm8994_put_retune_mobile_enum),
3658 };
3659 int ret, i, j;
3660 const char **t;
3661
3662 /* We need an array of texts for the enum API but the number
3663 * of texts is likely to be less than the number of
3664 * configurations due to the sample rate dependency of the
3665 * configurations. */
3666 wm8994->num_retune_mobile_texts = 0;
3667 wm8994->retune_mobile_texts = NULL;
3668 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3669 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3670 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3671 wm8994->retune_mobile_texts[j]) == 0)
3672 break;
3673 }
3674
3675 if (j != wm8994->num_retune_mobile_texts)
3676 continue;
3677
3678 /* Expand the array... */
3679 t = krealloc(wm8994->retune_mobile_texts,
3680 sizeof(char *) *
3681 (wm8994->num_retune_mobile_texts + 1),
3682 GFP_KERNEL);
3683 if (t == NULL)
3684 continue;
3685
3686 /* ...store the new entry... */
3687 t[wm8994->num_retune_mobile_texts] =
3688 pdata->retune_mobile_cfgs[i].name;
3689
3690 /* ...and remember the new version. */
3691 wm8994->num_retune_mobile_texts++;
3692 wm8994->retune_mobile_texts = t;
3693 }
3694
3695 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3696 wm8994->num_retune_mobile_texts);
3697
3698 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3699 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3700
3701 ret = snd_soc_add_controls(&wm8994->codec, controls,
3702 ARRAY_SIZE(controls));
3703 if (ret != 0)
3704 dev_err(wm8994->codec.dev,
3705 "Failed to add ReTune Mobile controls: %d\n", ret);
3706 }
3707
3708 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3709 {
3710 struct snd_soc_codec *codec = &wm8994->codec;
3711 struct wm8994_pdata *pdata = wm8994->pdata;
3712 int ret, i;
3713
3714 if (!pdata)
3715 return;
3716
3717 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3718 pdata->lineout2_diff,
3719 pdata->lineout1fb,
3720 pdata->lineout2fb,
3721 pdata->jd_scthr,
3722 pdata->jd_thr,
3723 pdata->micbias1_lvl,
3724 pdata->micbias2_lvl);
3725
3726 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3727
3728 if (pdata->num_drc_cfgs) {
3729 struct snd_kcontrol_new controls[] = {
3730 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3731 wm8994_get_drc_enum, wm8994_put_drc_enum),
3732 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3733 wm8994_get_drc_enum, wm8994_put_drc_enum),
3734 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3735 wm8994_get_drc_enum, wm8994_put_drc_enum),
3736 };
3737
3738 /* We need an array of texts for the enum API */
3739 wm8994->drc_texts = kmalloc(sizeof(char *)
3740 * pdata->num_drc_cfgs, GFP_KERNEL);
3741 if (!wm8994->drc_texts) {
3742 dev_err(wm8994->codec.dev,
3743 "Failed to allocate %d DRC config texts\n",
3744 pdata->num_drc_cfgs);
3745 return;
3746 }
3747
3748 for (i = 0; i < pdata->num_drc_cfgs; i++)
3749 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3750
3751 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3752 wm8994->drc_enum.texts = wm8994->drc_texts;
3753
3754 ret = snd_soc_add_controls(&wm8994->codec, controls,
3755 ARRAY_SIZE(controls));
3756 if (ret != 0)
3757 dev_err(wm8994->codec.dev,
3758 "Failed to add DRC mode controls: %d\n", ret);
3759
3760 for (i = 0; i < WM8994_NUM_DRC; i++)
3761 wm8994_set_drc(codec, i);
3762 }
3763
3764 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3765 pdata->num_retune_mobile_cfgs);
3766
3767 if (pdata->num_retune_mobile_cfgs)
3768 wm8994_handle_retune_mobile_pdata(wm8994);
3769 else
3770 snd_soc_add_controls(&wm8994->codec, wm8994_eq_controls,
3771 ARRAY_SIZE(wm8994_eq_controls));
3772 }
3773
3774 static int wm8994_probe(struct platform_device *pdev)
3775 {
3776 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3777 struct snd_soc_codec *codec;
3778 int ret = 0;
3779
3780 if (wm8994_codec == NULL) {
3781 dev_err(&pdev->dev, "Codec device not registered\n");
3782 return -ENODEV;
3783 }
3784
3785 socdev->card->codec = wm8994_codec;
3786 codec = wm8994_codec;
3787
3788 /* register pcms */
3789 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
3790 if (ret < 0) {
3791 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
3792 return ret;
3793 }
3794
3795 wm8994_handle_pdata(snd_soc_codec_get_drvdata(codec));
3796
3797 wm_hubs_add_analogue_controls(codec);
3798 snd_soc_add_controls(codec, wm8994_snd_controls,
3799 ARRAY_SIZE(wm8994_snd_controls));
3800 snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets,
3801 ARRAY_SIZE(wm8994_dapm_widgets));
3802 wm_hubs_add_analogue_routes(codec, 0, 0);
3803 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
3804
3805 return 0;
3806 }
3807
3808 static int wm8994_remove(struct platform_device *pdev)
3809 {
3810 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3811
3812 snd_soc_free_pcms(socdev);
3813 snd_soc_dapm_free(socdev);
3814
3815 return 0;
3816 }
3817
3818 struct snd_soc_codec_device soc_codec_dev_wm8994 = {
3819 .probe = wm8994_probe,
3820 .remove = wm8994_remove,
3821 .suspend = wm8994_suspend,
3822 .resume = wm8994_resume,
3823 };
3824 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
3825
3826 /**
3827 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3828 *
3829 * @codec: WM8994 codec
3830 * @jack: jack to report detection events on
3831 * @micbias: microphone bias to detect on
3832 * @det: value to report for presence detection
3833 * @shrt: value to report for short detection
3834 *
3835 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3836 * being used to bring out signals to the processor then only platform
3837 * data configuration is needed for WM8903 and processor GPIOs should
3838 * be configured using snd_soc_jack_add_gpios() instead.
3839 *
3840 * Configuration of detection levels is available via the micbias1_lvl
3841 * and micbias2_lvl platform data members.
3842 */
3843 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3844 int micbias, int det, int shrt)
3845 {
3846 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3847 struct wm8994_micdet *micdet;
3848 int reg;
3849
3850 switch (micbias) {
3851 case 1:
3852 micdet = &wm8994->micdet[0];
3853 break;
3854 case 2:
3855 micdet = &wm8994->micdet[1];
3856 break;
3857 default:
3858 return -EINVAL;
3859 }
3860
3861 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
3862 micbias, det, shrt);
3863
3864 /* Store the configuration */
3865 micdet->jack = jack;
3866 micdet->det = det;
3867 micdet->shrt = shrt;
3868
3869 /* If either of the jacks is set up then enable detection */
3870 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3871 reg = WM8994_MICD_ENA;
3872 else
3873 reg = 0;
3874
3875 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3876
3877 return 0;
3878 }
3879 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3880
3881 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3882 {
3883 struct wm8994_priv *priv = data;
3884 struct snd_soc_codec *codec = &priv->codec;
3885 int reg;
3886 int report;
3887
3888 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3889 if (reg < 0) {
3890 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3891 reg);
3892 return IRQ_HANDLED;
3893 }
3894
3895 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3896
3897 report = 0;
3898 if (reg & WM8994_MIC1_DET_STS)
3899 report |= priv->micdet[0].det;
3900 if (reg & WM8994_MIC1_SHRT_STS)
3901 report |= priv->micdet[0].shrt;
3902 snd_soc_jack_report(priv->micdet[0].jack, report,
3903 priv->micdet[0].det | priv->micdet[0].shrt);
3904
3905 report = 0;
3906 if (reg & WM8994_MIC2_DET_STS)
3907 report |= priv->micdet[1].det;
3908 if (reg & WM8994_MIC2_SHRT_STS)
3909 report |= priv->micdet[1].shrt;
3910 snd_soc_jack_report(priv->micdet[1].jack, report,
3911 priv->micdet[1].det | priv->micdet[1].shrt);
3912
3913 return IRQ_HANDLED;
3914 }
3915
3916 static int wm8994_codec_probe(struct platform_device *pdev)
3917 {
3918 int ret;
3919 struct wm8994_priv *wm8994;
3920 struct snd_soc_codec *codec;
3921 int i;
3922 u16 rev;
3923
3924 if (wm8994_codec) {
3925 dev_err(&pdev->dev, "Another WM8994 is registered\n");
3926 return -EINVAL;
3927 }
3928
3929 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3930 if (!wm8994) {
3931 dev_err(&pdev->dev, "Failed to allocate private data\n");
3932 return -ENOMEM;
3933 }
3934
3935 codec = &wm8994->codec;
3936
3937 mutex_init(&codec->mutex);
3938 INIT_LIST_HEAD(&codec->dapm_widgets);
3939 INIT_LIST_HEAD(&codec->dapm_paths);
3940
3941 snd_soc_codec_set_drvdata(codec, wm8994);
3942 codec->control_data = dev_get_drvdata(pdev->dev.parent);
3943 codec->name = "WM8994";
3944 codec->owner = THIS_MODULE;
3945 codec->read = wm8994_read;
3946 codec->write = wm8994_write;
3947 codec->readable_register = wm8994_readable;
3948 codec->bias_level = SND_SOC_BIAS_OFF;
3949 codec->set_bias_level = wm8994_set_bias_level;
3950 codec->dai = &wm8994_dai[0];
3951 codec->num_dai = 3;
3952 codec->reg_cache_size = WM8994_MAX_REGISTER;
3953 codec->reg_cache = &wm8994->reg_cache;
3954 codec->dev = &pdev->dev;
3955
3956 wm8994->pdata = pdev->dev.parent->platform_data;
3957
3958 /* Fill the cache with physical values we inherited; don't reset */
3959 ret = wm8994_bulk_read(codec->control_data, 0,
3960 ARRAY_SIZE(wm8994->reg_cache) - 1,
3961 codec->reg_cache);
3962 if (ret < 0) {
3963 dev_err(codec->dev, "Failed to fill register cache: %d\n",
3964 ret);
3965 goto err;
3966 }
3967
3968 /* Clear the cached values for unreadable/volatile registers to
3969 * avoid potential confusion.
3970 */
3971 for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++)
3972 if (wm8994_volatile(i) || !wm8994_readable(i))
3973 wm8994->reg_cache[i] = 0;
3974
3975 /* Set revision-specific configuration */
3976 rev = snd_soc_read(codec, WM8994_CHIP_REVISION);
3977 switch (rev) {
3978 case 2:
3979 case 3:
3980 wm8994->hubs.dcs_codes = -5;
3981 wm8994->hubs.hp_startup_mode = 1;
3982 wm8994->hubs.dcs_readback_mode = 1;
3983 break;
3984 default:
3985 wm8994->hubs.dcs_readback_mode = 1;
3986 break;
3987 }
3988
3989 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3990 wm8994_mic_irq, "Mic 1 detect", wm8994);
3991 if (ret != 0)
3992 dev_warn(&pdev->dev,
3993 "Failed to request Mic1 detect IRQ: %d\n", ret);
3994
3995 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3996 wm8994_mic_irq, "Mic 1 short", wm8994);
3997 if (ret != 0)
3998 dev_warn(&pdev->dev,
3999 "Failed to request Mic1 short IRQ: %d\n", ret);
4000
4001 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
4002 wm8994_mic_irq, "Mic 2 detect", wm8994);
4003 if (ret != 0)
4004 dev_warn(&pdev->dev,
4005 "Failed to request Mic2 detect IRQ: %d\n", ret);
4006
4007 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
4008 wm8994_mic_irq, "Mic 2 short", wm8994);
4009 if (ret != 0)
4010 dev_warn(&pdev->dev,
4011 "Failed to request Mic2 short IRQ: %d\n", ret);
4012
4013 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4014 * configured on init - if a system wants to do this dynamically
4015 * at runtime we can deal with that then.
4016 */
4017 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
4018 if (ret < 0) {
4019 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
4020 goto err_irq;
4021 }
4022 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4023 wm8994->lrclk_shared[0] = 1;
4024 wm8994_dai[0].symmetric_rates = 1;
4025 } else {
4026 wm8994->lrclk_shared[0] = 0;
4027 }
4028
4029 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
4030 if (ret < 0) {
4031 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
4032 goto err_irq;
4033 }
4034 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4035 wm8994->lrclk_shared[1] = 1;
4036 wm8994_dai[1].symmetric_rates = 1;
4037 } else {
4038 wm8994->lrclk_shared[1] = 0;
4039 }
4040
4041 for (i = 0; i < ARRAY_SIZE(wm8994_dai); i++)
4042 wm8994_dai[i].dev = codec->dev;
4043
4044 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
4045
4046 wm8994_codec = codec;
4047
4048 /* Latch volume updates (right only; we always do left then right). */
4049 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
4050 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
4051 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
4052 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
4053 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
4054 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
4055 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
4056 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
4057 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
4058 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
4059 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
4060 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
4061 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
4062 WM8994_DAC1_VU, WM8994_DAC1_VU);
4063 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
4064 WM8994_DAC2_VU, WM8994_DAC2_VU);
4065
4066 /* Set the low bit of the 3D stereo depth so TLV matches */
4067 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4068 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4069 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4070 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4071 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4072 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4073 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4074 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4075 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4076
4077 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
4078 * behaviour on idle TDM clock cycles. */
4079 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4080 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4081
4082 wm8994_update_class_w(codec);
4083
4084 ret = snd_soc_register_codec(codec);
4085 if (ret != 0) {
4086 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
4087 goto err_irq;
4088 }
4089
4090 ret = snd_soc_register_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai));
4091 if (ret != 0) {
4092 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
4093 goto err_codec;
4094 }
4095
4096 platform_set_drvdata(pdev, wm8994);
4097
4098 return 0;
4099
4100 err_codec:
4101 snd_soc_unregister_codec(codec);
4102 err_irq:
4103 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
4104 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
4105 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
4106 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
4107 err:
4108 kfree(wm8994);
4109 return ret;
4110 }
4111
4112 static int __devexit wm8994_codec_remove(struct platform_device *pdev)
4113 {
4114 struct wm8994_priv *wm8994 = platform_get_drvdata(pdev);
4115 struct snd_soc_codec *codec = &wm8994->codec;
4116
4117 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4118 snd_soc_unregister_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai));
4119 snd_soc_unregister_codec(&wm8994->codec);
4120 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
4121 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
4122 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
4123 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
4124 kfree(wm8994);
4125 wm8994_codec = NULL;
4126
4127 return 0;
4128 }
4129
4130 static struct platform_driver wm8994_codec_driver = {
4131 .driver = {
4132 .name = "wm8994-codec",
4133 .owner = THIS_MODULE,
4134 },
4135 .probe = wm8994_codec_probe,
4136 .remove = __devexit_p(wm8994_codec_remove),
4137 };
4138
4139 static __init int wm8994_init(void)
4140 {
4141 return platform_driver_register(&wm8994_codec_driver);
4142 }
4143 module_init(wm8994_init);
4144
4145 static __exit void wm8994_exit(void)
4146 {
4147 platform_driver_unregister(&wm8994_codec_driver);
4148 }
4149 module_exit(wm8994_exit);
4150
4151
4152 MODULE_DESCRIPTION("ASoC WM8994 driver");
4153 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4154 MODULE_LICENSE("GPL");
4155 MODULE_ALIAS("platform:wm8994-codec");
AMDTP streaming driver for the Linux FireWire stack (Juju)