1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include "net_driver.h"
25 #include "falcon_hwdefs.h"
26 #include "falcon_io.h"
30 #include "workarounds.h"
32 /* Falcon hardware control.
33 * Falcon is the internal codename for the SFC4000 controller that is
34 * present in SFE400X evaluation boards
38 * struct falcon_nic_data - Falcon NIC state
39 * @next_buffer_table: First available buffer table id
40 * @pci_dev2: The secondary PCI device if present
41 * @i2c_data: Operations and state for I2C bit-bashing algorithm
43 struct falcon_nic_data
{
44 unsigned next_buffer_table
;
45 struct pci_dev
*pci_dev2
;
46 struct i2c_algo_bit_data i2c_data
;
49 /**************************************************************************
53 **************************************************************************
56 static int disable_dma_stats
;
58 /* This is set to 16 for a good reason. In summary, if larger than
59 * 16, the descriptor cache holds more than a default socket
60 * buffer's worth of packets (for UDP we can only have at most one
61 * socket buffer's worth outstanding). This combined with the fact
62 * that we only get 1 TX event per descriptor cache means the NIC
65 #define TX_DC_ENTRIES 16
66 #define TX_DC_ENTRIES_ORDER 0
67 #define TX_DC_BASE 0x130000
69 #define RX_DC_ENTRIES 64
70 #define RX_DC_ENTRIES_ORDER 2
71 #define RX_DC_BASE 0x100000
73 /* RX FIFO XOFF watermark
75 * When the amount of the RX FIFO increases used increases past this
76 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
77 * This also has an effect on RX/TX arbitration
79 static int rx_xoff_thresh_bytes
= -1;
80 module_param(rx_xoff_thresh_bytes
, int, 0644);
81 MODULE_PARM_DESC(rx_xoff_thresh_bytes
, "RX fifo XOFF threshold");
83 /* RX FIFO XON watermark
85 * When the amount of the RX FIFO used decreases below this
86 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
87 * This also has an effect on RX/TX arbitration
89 static int rx_xon_thresh_bytes
= -1;
90 module_param(rx_xon_thresh_bytes
, int, 0644);
91 MODULE_PARM_DESC(rx_xon_thresh_bytes
, "RX fifo XON threshold");
93 /* TX descriptor ring size - min 512 max 4k */
94 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
95 #define FALCON_TXD_RING_SIZE 1024
96 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
98 /* RX descriptor ring size - min 512 max 4k */
99 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
100 #define FALCON_RXD_RING_SIZE 1024
101 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
103 /* Event queue size - max 32k */
104 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
105 #define FALCON_EVQ_SIZE 4096
106 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
108 /* Max number of internal errors. After this resets will not be performed */
109 #define FALCON_MAX_INT_ERRORS 4
111 /* Maximum period that we wait for flush events. If the flush event
112 * doesn't arrive in this period of time then we check if the queue
113 * was disabled anyway. */
114 #define FALCON_FLUSH_TIMEOUT 10 /* 10ms */
116 /**************************************************************************
120 **************************************************************************
123 /* DMA address mask */
124 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
126 /* TX DMA length mask (13-bit) */
127 #define FALCON_TX_DMA_MASK (4096 - 1)
129 /* Size and alignment of special buffers (4KB) */
130 #define FALCON_BUF_SIZE 4096
132 /* Dummy SRAM size code */
133 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
135 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
136 #define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
137 #define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
138 #define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
139 #define PCI_EXP_LNKSTA_LNK_WID 0x3f0
140 #define PCI_EXP_LNKSTA_LNK_WID_LBN 4
142 #define FALCON_IS_DUAL_FUNC(efx) \
143 (falcon_rev(efx) < FALCON_REV_B0)
145 /**************************************************************************
147 * Falcon hardware access
149 **************************************************************************/
151 /* Read the current event from the event queue */
152 static inline efx_qword_t
*falcon_event(struct efx_channel
*channel
,
155 return (((efx_qword_t
*) (channel
->eventq
.addr
)) + index
);
158 /* See if an event is present
160 * We check both the high and low dword of the event for all ones. We
161 * wrote all ones when we cleared the event, and no valid event can
162 * have all ones in either its high or low dwords. This approach is
163 * robust against reordering.
165 * Note that using a single 64-bit comparison is incorrect; even
166 * though the CPU read will be atomic, the DMA write may not be.
168 static inline int falcon_event_present(efx_qword_t
*event
)
170 return (!(EFX_DWORD_IS_ALL_ONES(event
->dword
[0]) |
171 EFX_DWORD_IS_ALL_ONES(event
->dword
[1])));
174 /**************************************************************************
176 * I2C bus - this is a bit-bashing interface using GPIO pins
177 * Note that it uses the output enables to tristate the outputs
178 * SDA is the data pin and SCL is the clock
180 **************************************************************************
182 static void falcon_setsda(void *data
, int state
)
184 struct efx_nic
*efx
= (struct efx_nic
*)data
;
187 falcon_read(efx
, ®
, GPIO_CTL_REG_KER
);
188 EFX_SET_OWORD_FIELD(reg
, GPIO3_OEN
, !state
);
189 falcon_write(efx
, ®
, GPIO_CTL_REG_KER
);
192 static void falcon_setscl(void *data
, int state
)
194 struct efx_nic
*efx
= (struct efx_nic
*)data
;
197 falcon_read(efx
, ®
, GPIO_CTL_REG_KER
);
198 EFX_SET_OWORD_FIELD(reg
, GPIO0_OEN
, !state
);
199 falcon_write(efx
, ®
, GPIO_CTL_REG_KER
);
202 static int falcon_getsda(void *data
)
204 struct efx_nic
*efx
= (struct efx_nic
*)data
;
207 falcon_read(efx
, ®
, GPIO_CTL_REG_KER
);
208 return EFX_OWORD_FIELD(reg
, GPIO3_IN
);
211 static int falcon_getscl(void *data
)
213 struct efx_nic
*efx
= (struct efx_nic
*)data
;
216 falcon_read(efx
, ®
, GPIO_CTL_REG_KER
);
217 return EFX_OWORD_FIELD(reg
, GPIO0_IN
);
220 static struct i2c_algo_bit_data falcon_i2c_bit_operations
= {
221 .setsda
= falcon_setsda
,
222 .setscl
= falcon_setscl
,
223 .getsda
= falcon_getsda
,
224 .getscl
= falcon_getscl
,
226 /* Wait up to 50 ms for slave to let us pull SCL high */
227 .timeout
= DIV_ROUND_UP(HZ
, 20),
230 /**************************************************************************
232 * Falcon special buffer handling
233 * Special buffers are used for event queues and the TX and RX
236 *************************************************************************/
239 * Initialise a Falcon special buffer
241 * This will define a buffer (previously allocated via
242 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
243 * it to be used for event queues, descriptor rings etc.
246 falcon_init_special_buffer(struct efx_nic
*efx
,
247 struct efx_special_buffer
*buffer
)
249 efx_qword_t buf_desc
;
254 EFX_BUG_ON_PARANOID(!buffer
->addr
);
256 /* Write buffer descriptors to NIC */
257 for (i
= 0; i
< buffer
->entries
; i
++) {
258 index
= buffer
->index
+ i
;
259 dma_addr
= buffer
->dma_addr
+ (i
* 4096);
260 EFX_LOG(efx
, "mapping special buffer %d at %llx\n",
261 index
, (unsigned long long)dma_addr
);
262 EFX_POPULATE_QWORD_4(buf_desc
,
263 IP_DAT_BUF_SIZE
, IP_DAT_BUF_SIZE_4K
,
265 BUF_ADR_FBUF
, (dma_addr
>> 12),
266 BUF_OWNER_ID_FBUF
, 0);
267 falcon_write_sram(efx
, &buf_desc
, index
);
273 /* Unmaps a buffer from Falcon and clears the buffer table entries */
275 falcon_fini_special_buffer(struct efx_nic
*efx
,
276 struct efx_special_buffer
*buffer
)
278 efx_oword_t buf_tbl_upd
;
279 unsigned int start
= buffer
->index
;
280 unsigned int end
= (buffer
->index
+ buffer
->entries
- 1);
282 if (!buffer
->entries
)
285 EFX_LOG(efx
, "unmapping special buffers %d-%d\n",
286 buffer
->index
, buffer
->index
+ buffer
->entries
- 1);
288 EFX_POPULATE_OWORD_4(buf_tbl_upd
,
292 BUF_CLR_START_ID
, start
);
293 falcon_write(efx
, &buf_tbl_upd
, BUF_TBL_UPD_REG_KER
);
297 * Allocate a new Falcon special buffer
299 * This allocates memory for a new buffer, clears it and allocates a
300 * new buffer ID range. It does not write into Falcon's buffer table.
302 * This call will allocate 4KB buffers, since Falcon can't use 8KB
303 * buffers for event queues and descriptor rings.
305 static int falcon_alloc_special_buffer(struct efx_nic
*efx
,
306 struct efx_special_buffer
*buffer
,
309 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
311 len
= ALIGN(len
, FALCON_BUF_SIZE
);
313 buffer
->addr
= pci_alloc_consistent(efx
->pci_dev
, len
,
318 buffer
->entries
= len
/ FALCON_BUF_SIZE
;
319 BUG_ON(buffer
->dma_addr
& (FALCON_BUF_SIZE
- 1));
321 /* All zeros is a potentially valid event so memset to 0xff */
322 memset(buffer
->addr
, 0xff, len
);
324 /* Select new buffer ID */
325 buffer
->index
= nic_data
->next_buffer_table
;
326 nic_data
->next_buffer_table
+= buffer
->entries
;
328 EFX_LOG(efx
, "allocating special buffers %d-%d at %llx+%x "
329 "(virt %p phys %lx)\n", buffer
->index
,
330 buffer
->index
+ buffer
->entries
- 1,
331 (unsigned long long)buffer
->dma_addr
, len
,
332 buffer
->addr
, virt_to_phys(buffer
->addr
));
337 static void falcon_free_special_buffer(struct efx_nic
*efx
,
338 struct efx_special_buffer
*buffer
)
343 EFX_LOG(efx
, "deallocating special buffers %d-%d at %llx+%x "
344 "(virt %p phys %lx)\n", buffer
->index
,
345 buffer
->index
+ buffer
->entries
- 1,
346 (unsigned long long)buffer
->dma_addr
, buffer
->len
,
347 buffer
->addr
, virt_to_phys(buffer
->addr
));
349 pci_free_consistent(efx
->pci_dev
, buffer
->len
, buffer
->addr
,
355 /**************************************************************************
357 * Falcon generic buffer handling
358 * These buffers are used for interrupt status and MAC stats
360 **************************************************************************/
362 static int falcon_alloc_buffer(struct efx_nic
*efx
,
363 struct efx_buffer
*buffer
, unsigned int len
)
365 buffer
->addr
= pci_alloc_consistent(efx
->pci_dev
, len
,
370 memset(buffer
->addr
, 0, len
);
374 static void falcon_free_buffer(struct efx_nic
*efx
, struct efx_buffer
*buffer
)
377 pci_free_consistent(efx
->pci_dev
, buffer
->len
,
378 buffer
->addr
, buffer
->dma_addr
);
383 /**************************************************************************
387 **************************************************************************/
389 /* Returns a pointer to the specified transmit descriptor in the TX
390 * descriptor queue belonging to the specified channel.
392 static inline efx_qword_t
*falcon_tx_desc(struct efx_tx_queue
*tx_queue
,
395 return (((efx_qword_t
*) (tx_queue
->txd
.addr
)) + index
);
398 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
399 static inline void falcon_notify_tx_desc(struct efx_tx_queue
*tx_queue
)
404 write_ptr
= tx_queue
->write_count
& FALCON_TXD_RING_MASK
;
405 EFX_POPULATE_DWORD_1(reg
, TX_DESC_WPTR_DWORD
, write_ptr
);
406 falcon_writel_page(tx_queue
->efx
, ®
,
407 TX_DESC_UPD_REG_KER_DWORD
, tx_queue
->queue
);
411 /* For each entry inserted into the software descriptor ring, create a
412 * descriptor in the hardware TX descriptor ring (in host memory), and
415 void falcon_push_buffers(struct efx_tx_queue
*tx_queue
)
418 struct efx_tx_buffer
*buffer
;
422 BUG_ON(tx_queue
->write_count
== tx_queue
->insert_count
);
425 write_ptr
= tx_queue
->write_count
& FALCON_TXD_RING_MASK
;
426 buffer
= &tx_queue
->buffer
[write_ptr
];
427 txd
= falcon_tx_desc(tx_queue
, write_ptr
);
428 ++tx_queue
->write_count
;
430 /* Create TX descriptor ring entry */
431 EFX_POPULATE_QWORD_5(*txd
,
433 TX_KER_CONT
, buffer
->continuation
,
434 TX_KER_BYTE_CNT
, buffer
->len
,
435 TX_KER_BUF_REGION
, 0,
436 TX_KER_BUF_ADR
, buffer
->dma_addr
);
437 } while (tx_queue
->write_count
!= tx_queue
->insert_count
);
439 wmb(); /* Ensure descriptors are written before they are fetched */
440 falcon_notify_tx_desc(tx_queue
);
443 /* Allocate hardware resources for a TX queue */
444 int falcon_probe_tx(struct efx_tx_queue
*tx_queue
)
446 struct efx_nic
*efx
= tx_queue
->efx
;
447 return falcon_alloc_special_buffer(efx
, &tx_queue
->txd
,
448 FALCON_TXD_RING_SIZE
*
449 sizeof(efx_qword_t
));
452 int falcon_init_tx(struct efx_tx_queue
*tx_queue
)
454 efx_oword_t tx_desc_ptr
;
455 struct efx_nic
*efx
= tx_queue
->efx
;
458 /* Pin TX descriptor ring */
459 rc
= falcon_init_special_buffer(efx
, &tx_queue
->txd
);
463 /* Push TX descriptor ring to card */
464 EFX_POPULATE_OWORD_10(tx_desc_ptr
,
468 TX_DESCQ_BUF_BASE_ID
, tx_queue
->txd
.index
,
469 TX_DESCQ_EVQ_ID
, tx_queue
->channel
->evqnum
,
470 TX_DESCQ_OWNER_ID
, 0,
471 TX_DESCQ_LABEL
, tx_queue
->queue
,
472 TX_DESCQ_SIZE
, FALCON_TXD_RING_ORDER
,
474 TX_NON_IP_DROP_DIS_B0
, 1);
476 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
477 int csum
= tx_queue
->queue
== EFX_TX_QUEUE_OFFLOAD_CSUM
;
478 EFX_SET_OWORD_FIELD(tx_desc_ptr
, TX_IP_CHKSM_DIS_B0
, !csum
);
479 EFX_SET_OWORD_FIELD(tx_desc_ptr
, TX_TCP_CHKSM_DIS_B0
, !csum
);
482 falcon_write_table(efx
, &tx_desc_ptr
, efx
->type
->txd_ptr_tbl_base
,
485 if (falcon_rev(efx
) < FALCON_REV_B0
) {
488 /* Only 128 bits in this register */
489 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT
>= 128);
491 falcon_read(efx
, ®
, TX_CHKSM_CFG_REG_KER_A1
);
492 if (tx_queue
->queue
== EFX_TX_QUEUE_OFFLOAD_CSUM
)
493 clear_bit_le(tx_queue
->queue
, (void *)®
);
495 set_bit_le(tx_queue
->queue
, (void *)®
);
496 falcon_write(efx
, ®
, TX_CHKSM_CFG_REG_KER_A1
);
502 static int falcon_flush_tx_queue(struct efx_tx_queue
*tx_queue
)
504 struct efx_nic
*efx
= tx_queue
->efx
;
505 struct efx_channel
*channel
= &efx
->channel
[0];
506 efx_oword_t tx_flush_descq
;
507 unsigned int read_ptr
, i
;
509 /* Post a flush command */
510 EFX_POPULATE_OWORD_2(tx_flush_descq
,
511 TX_FLUSH_DESCQ_CMD
, 1,
512 TX_FLUSH_DESCQ
, tx_queue
->queue
);
513 falcon_write(efx
, &tx_flush_descq
, TX_FLUSH_DESCQ_REG_KER
);
514 msleep(FALCON_FLUSH_TIMEOUT
);
516 if (EFX_WORKAROUND_7803(efx
))
519 /* Look for a flush completed event */
520 read_ptr
= channel
->eventq_read_ptr
;
521 for (i
= 0; i
< FALCON_EVQ_SIZE
; ++i
) {
522 efx_qword_t
*event
= falcon_event(channel
, read_ptr
);
523 int ev_code
, ev_sub_code
, ev_queue
;
524 if (!falcon_event_present(event
))
527 ev_code
= EFX_QWORD_FIELD(*event
, EV_CODE
);
528 ev_sub_code
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_CODE
);
529 ev_queue
= EFX_QWORD_FIELD(*event
, DRIVER_EV_TX_DESCQ_ID
);
530 if ((ev_sub_code
== TX_DESCQ_FLS_DONE_EV_DECODE
) &&
531 (ev_queue
== tx_queue
->queue
)) {
532 EFX_LOG(efx
, "tx queue %d flush command succesful\n",
537 read_ptr
= (read_ptr
+ 1) & FALCON_EVQ_MASK
;
540 if (EFX_WORKAROUND_11557(efx
)) {
544 falcon_read_table(efx
, ®
, efx
->type
->txd_ptr_tbl_base
,
546 enabled
= EFX_OWORD_FIELD(reg
, TX_DESCQ_EN
);
548 EFX_LOG(efx
, "tx queue %d disabled without a "
549 "flush event seen\n", tx_queue
->queue
);
554 EFX_ERR(efx
, "tx queue %d flush command timed out\n", tx_queue
->queue
);
558 void falcon_fini_tx(struct efx_tx_queue
*tx_queue
)
560 struct efx_nic
*efx
= tx_queue
->efx
;
561 efx_oword_t tx_desc_ptr
;
563 /* Stop the hardware using the queue */
564 if (falcon_flush_tx_queue(tx_queue
))
565 EFX_ERR(efx
, "failed to flush tx queue %d\n", tx_queue
->queue
);
567 /* Remove TX descriptor ring from card */
568 EFX_ZERO_OWORD(tx_desc_ptr
);
569 falcon_write_table(efx
, &tx_desc_ptr
, efx
->type
->txd_ptr_tbl_base
,
572 /* Unpin TX descriptor ring */
573 falcon_fini_special_buffer(efx
, &tx_queue
->txd
);
576 /* Free buffers backing TX queue */
577 void falcon_remove_tx(struct efx_tx_queue
*tx_queue
)
579 falcon_free_special_buffer(tx_queue
->efx
, &tx_queue
->txd
);
582 /**************************************************************************
586 **************************************************************************/
588 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
589 static inline efx_qword_t
*falcon_rx_desc(struct efx_rx_queue
*rx_queue
,
592 return (((efx_qword_t
*) (rx_queue
->rxd
.addr
)) + index
);
595 /* This creates an entry in the RX descriptor queue */
596 static inline void falcon_build_rx_desc(struct efx_rx_queue
*rx_queue
,
599 struct efx_rx_buffer
*rx_buf
;
602 rxd
= falcon_rx_desc(rx_queue
, index
);
603 rx_buf
= efx_rx_buffer(rx_queue
, index
);
604 EFX_POPULATE_QWORD_3(*rxd
,
607 rx_queue
->efx
->type
->rx_buffer_padding
,
608 RX_KER_BUF_REGION
, 0,
609 RX_KER_BUF_ADR
, rx_buf
->dma_addr
);
612 /* This writes to the RX_DESC_WPTR register for the specified receive
615 void falcon_notify_rx_desc(struct efx_rx_queue
*rx_queue
)
620 while (rx_queue
->notified_count
!= rx_queue
->added_count
) {
621 falcon_build_rx_desc(rx_queue
,
622 rx_queue
->notified_count
&
623 FALCON_RXD_RING_MASK
);
624 ++rx_queue
->notified_count
;
628 write_ptr
= rx_queue
->added_count
& FALCON_RXD_RING_MASK
;
629 EFX_POPULATE_DWORD_1(reg
, RX_DESC_WPTR_DWORD
, write_ptr
);
630 falcon_writel_page(rx_queue
->efx
, ®
,
631 RX_DESC_UPD_REG_KER_DWORD
, rx_queue
->queue
);
634 int falcon_probe_rx(struct efx_rx_queue
*rx_queue
)
636 struct efx_nic
*efx
= rx_queue
->efx
;
637 return falcon_alloc_special_buffer(efx
, &rx_queue
->rxd
,
638 FALCON_RXD_RING_SIZE
*
639 sizeof(efx_qword_t
));
642 int falcon_init_rx(struct efx_rx_queue
*rx_queue
)
644 efx_oword_t rx_desc_ptr
;
645 struct efx_nic
*efx
= rx_queue
->efx
;
647 int is_b0
= falcon_rev(efx
) >= FALCON_REV_B0
;
648 int iscsi_digest_en
= is_b0
;
650 EFX_LOG(efx
, "RX queue %d ring in special buffers %d-%d\n",
651 rx_queue
->queue
, rx_queue
->rxd
.index
,
652 rx_queue
->rxd
.index
+ rx_queue
->rxd
.entries
- 1);
654 /* Pin RX descriptor ring */
655 rc
= falcon_init_special_buffer(efx
, &rx_queue
->rxd
);
659 /* Push RX descriptor ring to card */
660 EFX_POPULATE_OWORD_10(rx_desc_ptr
,
661 RX_ISCSI_DDIG_EN
, iscsi_digest_en
,
662 RX_ISCSI_HDIG_EN
, iscsi_digest_en
,
663 RX_DESCQ_BUF_BASE_ID
, rx_queue
->rxd
.index
,
664 RX_DESCQ_EVQ_ID
, rx_queue
->channel
->evqnum
,
665 RX_DESCQ_OWNER_ID
, 0,
666 RX_DESCQ_LABEL
, rx_queue
->queue
,
667 RX_DESCQ_SIZE
, FALCON_RXD_RING_ORDER
,
668 RX_DESCQ_TYPE
, 0 /* kernel queue */ ,
669 /* For >=B0 this is scatter so disable */
670 RX_DESCQ_JUMBO
, !is_b0
,
672 falcon_write_table(efx
, &rx_desc_ptr
, efx
->type
->rxd_ptr_tbl_base
,
677 static int falcon_flush_rx_queue(struct efx_rx_queue
*rx_queue
)
679 struct efx_nic
*efx
= rx_queue
->efx
;
680 struct efx_channel
*channel
= &efx
->channel
[0];
681 unsigned int read_ptr
, i
;
682 efx_oword_t rx_flush_descq
;
684 /* Post a flush command */
685 EFX_POPULATE_OWORD_2(rx_flush_descq
,
686 RX_FLUSH_DESCQ_CMD
, 1,
687 RX_FLUSH_DESCQ
, rx_queue
->queue
);
688 falcon_write(efx
, &rx_flush_descq
, RX_FLUSH_DESCQ_REG_KER
);
689 msleep(FALCON_FLUSH_TIMEOUT
);
691 if (EFX_WORKAROUND_7803(efx
))
694 /* Look for a flush completed event */
695 read_ptr
= channel
->eventq_read_ptr
;
696 for (i
= 0; i
< FALCON_EVQ_SIZE
; ++i
) {
697 efx_qword_t
*event
= falcon_event(channel
, read_ptr
);
698 int ev_code
, ev_sub_code
, ev_queue
, ev_failed
;
699 if (!falcon_event_present(event
))
702 ev_code
= EFX_QWORD_FIELD(*event
, EV_CODE
);
703 ev_sub_code
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_CODE
);
704 ev_queue
= EFX_QWORD_FIELD(*event
, DRIVER_EV_RX_DESCQ_ID
);
705 ev_failed
= EFX_QWORD_FIELD(*event
, DRIVER_EV_RX_FLUSH_FAIL
);
707 if ((ev_sub_code
== RX_DESCQ_FLS_DONE_EV_DECODE
) &&
708 (ev_queue
== rx_queue
->queue
)) {
710 EFX_INFO(efx
, "rx queue %d flush command "
711 "failed\n", rx_queue
->queue
);
714 EFX_LOG(efx
, "rx queue %d flush command "
715 "succesful\n", rx_queue
->queue
);
720 read_ptr
= (read_ptr
+ 1) & FALCON_EVQ_MASK
;
723 if (EFX_WORKAROUND_11557(efx
)) {
727 falcon_read_table(efx
, ®
, efx
->type
->rxd_ptr_tbl_base
,
729 enabled
= EFX_OWORD_FIELD(reg
, RX_DESCQ_EN
);
731 EFX_LOG(efx
, "rx queue %d disabled without a "
732 "flush event seen\n", rx_queue
->queue
);
737 EFX_ERR(efx
, "rx queue %d flush command timed out\n", rx_queue
->queue
);
741 void falcon_fini_rx(struct efx_rx_queue
*rx_queue
)
743 efx_oword_t rx_desc_ptr
;
744 struct efx_nic
*efx
= rx_queue
->efx
;
747 /* Try and flush the rx queue. This may need to be repeated */
748 for (i
= 0; i
< 5; i
++) {
749 rc
= falcon_flush_rx_queue(rx_queue
);
755 EFX_ERR(efx
, "failed to flush rx queue %d\n", rx_queue
->queue
);
756 efx_schedule_reset(efx
, RESET_TYPE_INVISIBLE
);
759 /* Remove RX descriptor ring from card */
760 EFX_ZERO_OWORD(rx_desc_ptr
);
761 falcon_write_table(efx
, &rx_desc_ptr
, efx
->type
->rxd_ptr_tbl_base
,
764 /* Unpin RX descriptor ring */
765 falcon_fini_special_buffer(efx
, &rx_queue
->rxd
);
768 /* Free buffers backing RX queue */
769 void falcon_remove_rx(struct efx_rx_queue
*rx_queue
)
771 falcon_free_special_buffer(rx_queue
->efx
, &rx_queue
->rxd
);
774 /**************************************************************************
776 * Falcon event queue processing
777 * Event queues are processed by per-channel tasklets.
779 **************************************************************************/
781 /* Update a channel's event queue's read pointer (RPTR) register
783 * This writes the EVQ_RPTR_REG register for the specified channel's
786 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
787 * whereas channel->eventq_read_ptr contains the index of the "next to
790 void falcon_eventq_read_ack(struct efx_channel
*channel
)
793 struct efx_nic
*efx
= channel
->efx
;
795 EFX_POPULATE_DWORD_1(reg
, EVQ_RPTR_DWORD
, channel
->eventq_read_ptr
);
796 falcon_writel_table(efx
, ®
, efx
->type
->evq_rptr_tbl_base
,
800 /* Use HW to insert a SW defined event */
801 void falcon_generate_event(struct efx_channel
*channel
, efx_qword_t
*event
)
803 efx_oword_t drv_ev_reg
;
805 EFX_POPULATE_OWORD_2(drv_ev_reg
,
806 DRV_EV_QID
, channel
->evqnum
,
808 EFX_QWORD_FIELD64(*event
, WHOLE_EVENT
));
809 falcon_write(channel
->efx
, &drv_ev_reg
, DRV_EV_REG_KER
);
812 /* Handle a transmit completion event
814 * Falcon batches TX completion events; the message we receive is of
815 * the form "complete all TX events up to this index".
817 static inline void falcon_handle_tx_event(struct efx_channel
*channel
,
820 unsigned int tx_ev_desc_ptr
;
821 unsigned int tx_ev_q_label
;
822 struct efx_tx_queue
*tx_queue
;
823 struct efx_nic
*efx
= channel
->efx
;
825 if (likely(EFX_QWORD_FIELD(*event
, TX_EV_COMP
))) {
826 /* Transmit completion */
827 tx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, TX_EV_DESC_PTR
);
828 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, TX_EV_Q_LABEL
);
829 tx_queue
= &efx
->tx_queue
[tx_ev_q_label
];
830 efx_xmit_done(tx_queue
, tx_ev_desc_ptr
);
831 } else if (EFX_QWORD_FIELD(*event
, TX_EV_WQ_FF_FULL
)) {
832 /* Rewrite the FIFO write pointer */
833 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, TX_EV_Q_LABEL
);
834 tx_queue
= &efx
->tx_queue
[tx_ev_q_label
];
836 if (efx_dev_registered(efx
))
837 netif_tx_lock(efx
->net_dev
);
838 falcon_notify_tx_desc(tx_queue
);
839 if (efx_dev_registered(efx
))
840 netif_tx_unlock(efx
->net_dev
);
841 } else if (EFX_QWORD_FIELD(*event
, TX_EV_PKT_ERR
) &&
842 EFX_WORKAROUND_10727(efx
)) {
843 efx_schedule_reset(efx
, RESET_TYPE_TX_DESC_FETCH
);
845 EFX_ERR(efx
, "channel %d unexpected TX event "
846 EFX_QWORD_FMT
"\n", channel
->channel
,
847 EFX_QWORD_VAL(*event
));
851 /* Detect errors included in the rx_evt_pkt_ok bit. */
852 static void falcon_handle_rx_not_ok(struct efx_rx_queue
*rx_queue
,
853 const efx_qword_t
*event
,
854 unsigned *rx_ev_pkt_ok
,
857 struct efx_nic
*efx
= rx_queue
->efx
;
858 unsigned rx_ev_buf_owner_id_err
, rx_ev_ip_hdr_chksum_err
;
859 unsigned rx_ev_tcp_udp_chksum_err
, rx_ev_eth_crc_err
;
860 unsigned rx_ev_frm_trunc
, rx_ev_drib_nib
, rx_ev_tobe_disc
;
861 unsigned rx_ev_pkt_type
, rx_ev_other_err
, rx_ev_pause_frm
;
862 unsigned rx_ev_ip_frag_err
, rx_ev_hdr_type
, rx_ev_mcast_pkt
;
864 rx_ev_hdr_type
= EFX_QWORD_FIELD(*event
, RX_EV_HDR_TYPE
);
865 rx_ev_mcast_pkt
= EFX_QWORD_FIELD(*event
, RX_EV_MCAST_PKT
);
866 rx_ev_tobe_disc
= EFX_QWORD_FIELD(*event
, RX_EV_TOBE_DISC
);
867 rx_ev_pkt_type
= EFX_QWORD_FIELD(*event
, RX_EV_PKT_TYPE
);
868 rx_ev_buf_owner_id_err
= EFX_QWORD_FIELD(*event
,
869 RX_EV_BUF_OWNER_ID_ERR
);
870 rx_ev_ip_frag_err
= EFX_QWORD_FIELD(*event
, RX_EV_IF_FRAG_ERR
);
871 rx_ev_ip_hdr_chksum_err
= EFX_QWORD_FIELD(*event
,
872 RX_EV_IP_HDR_CHKSUM_ERR
);
873 rx_ev_tcp_udp_chksum_err
= EFX_QWORD_FIELD(*event
,
874 RX_EV_TCP_UDP_CHKSUM_ERR
);
875 rx_ev_eth_crc_err
= EFX_QWORD_FIELD(*event
, RX_EV_ETH_CRC_ERR
);
876 rx_ev_frm_trunc
= EFX_QWORD_FIELD(*event
, RX_EV_FRM_TRUNC
);
877 rx_ev_drib_nib
= ((falcon_rev(efx
) >= FALCON_REV_B0
) ?
878 0 : EFX_QWORD_FIELD(*event
, RX_EV_DRIB_NIB
));
879 rx_ev_pause_frm
= EFX_QWORD_FIELD(*event
, RX_EV_PAUSE_FRM_ERR
);
881 /* Every error apart from tobe_disc and pause_frm */
882 rx_ev_other_err
= (rx_ev_drib_nib
| rx_ev_tcp_udp_chksum_err
|
883 rx_ev_buf_owner_id_err
| rx_ev_eth_crc_err
|
884 rx_ev_frm_trunc
| rx_ev_ip_hdr_chksum_err
);
886 /* Count errors that are not in MAC stats. */
888 ++rx_queue
->channel
->n_rx_frm_trunc
;
889 else if (rx_ev_tobe_disc
)
890 ++rx_queue
->channel
->n_rx_tobe_disc
;
891 else if (rx_ev_ip_hdr_chksum_err
)
892 ++rx_queue
->channel
->n_rx_ip_hdr_chksum_err
;
893 else if (rx_ev_tcp_udp_chksum_err
)
894 ++rx_queue
->channel
->n_rx_tcp_udp_chksum_err
;
895 if (rx_ev_ip_frag_err
)
896 ++rx_queue
->channel
->n_rx_ip_frag_err
;
898 /* The frame must be discarded if any of these are true. */
899 *discard
= (rx_ev_eth_crc_err
| rx_ev_frm_trunc
| rx_ev_drib_nib
|
900 rx_ev_tobe_disc
| rx_ev_pause_frm
);
902 /* TOBE_DISC is expected on unicast mismatches; don't print out an
903 * error message. FRM_TRUNC indicates RXDP dropped the packet due
904 * to a FIFO overflow.
906 #ifdef EFX_ENABLE_DEBUG
907 if (rx_ev_other_err
) {
908 EFX_INFO_RL(efx
, " RX queue %d unexpected RX event "
909 EFX_QWORD_FMT
"%s%s%s%s%s%s%s%s\n",
910 rx_queue
->queue
, EFX_QWORD_VAL(*event
),
911 rx_ev_buf_owner_id_err
? " [OWNER_ID_ERR]" : "",
912 rx_ev_ip_hdr_chksum_err
?
913 " [IP_HDR_CHKSUM_ERR]" : "",
914 rx_ev_tcp_udp_chksum_err
?
915 " [TCP_UDP_CHKSUM_ERR]" : "",
916 rx_ev_eth_crc_err
? " [ETH_CRC_ERR]" : "",
917 rx_ev_frm_trunc
? " [FRM_TRUNC]" : "",
918 rx_ev_drib_nib
? " [DRIB_NIB]" : "",
919 rx_ev_tobe_disc
? " [TOBE_DISC]" : "",
920 rx_ev_pause_frm
? " [PAUSE]" : "");
924 if (unlikely(rx_ev_eth_crc_err
&& EFX_WORKAROUND_10750(efx
) &&
925 efx
->phy_type
== PHY_TYPE_10XPRESS
))
926 tenxpress_crc_err(efx
);
929 /* Handle receive events that are not in-order. */
930 static void falcon_handle_rx_bad_index(struct efx_rx_queue
*rx_queue
,
933 struct efx_nic
*efx
= rx_queue
->efx
;
934 unsigned expected
, dropped
;
936 expected
= rx_queue
->removed_count
& FALCON_RXD_RING_MASK
;
937 dropped
= ((index
+ FALCON_RXD_RING_SIZE
- expected
) &
938 FALCON_RXD_RING_MASK
);
939 EFX_INFO(efx
, "dropped %d events (index=%d expected=%d)\n",
940 dropped
, index
, expected
);
942 efx_schedule_reset(efx
, EFX_WORKAROUND_5676(efx
) ?
943 RESET_TYPE_RX_RECOVERY
: RESET_TYPE_DISABLE
);
946 /* Handle a packet received event
948 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
949 * wrong destination address
950 * Also "is multicast" and "matches multicast filter" flags can be used to
951 * discard non-matching multicast packets.
953 static inline int falcon_handle_rx_event(struct efx_channel
*channel
,
954 const efx_qword_t
*event
)
956 unsigned int rx_ev_q_label
, rx_ev_desc_ptr
, rx_ev_byte_cnt
;
957 unsigned int rx_ev_pkt_ok
, rx_ev_hdr_type
, rx_ev_mcast_pkt
;
958 unsigned expected_ptr
;
959 int discard
= 0, checksummed
;
960 struct efx_rx_queue
*rx_queue
;
961 struct efx_nic
*efx
= channel
->efx
;
963 /* Basic packet information */
964 rx_ev_byte_cnt
= EFX_QWORD_FIELD(*event
, RX_EV_BYTE_CNT
);
965 rx_ev_pkt_ok
= EFX_QWORD_FIELD(*event
, RX_EV_PKT_OK
);
966 rx_ev_hdr_type
= EFX_QWORD_FIELD(*event
, RX_EV_HDR_TYPE
);
967 WARN_ON(EFX_QWORD_FIELD(*event
, RX_EV_JUMBO_CONT
));
968 WARN_ON(EFX_QWORD_FIELD(*event
, RX_EV_SOP
) != 1);
970 rx_ev_q_label
= EFX_QWORD_FIELD(*event
, RX_EV_Q_LABEL
);
971 rx_queue
= &efx
->rx_queue
[rx_ev_q_label
];
973 rx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, RX_EV_DESC_PTR
);
974 expected_ptr
= rx_queue
->removed_count
& FALCON_RXD_RING_MASK
;
975 if (unlikely(rx_ev_desc_ptr
!= expected_ptr
)) {
976 falcon_handle_rx_bad_index(rx_queue
, rx_ev_desc_ptr
);
977 return rx_ev_q_label
;
980 if (likely(rx_ev_pkt_ok
)) {
981 /* If packet is marked as OK and packet type is TCP/IPv4 or
982 * UDP/IPv4, then we can rely on the hardware checksum.
984 checksummed
= RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type
);
986 falcon_handle_rx_not_ok(rx_queue
, event
, &rx_ev_pkt_ok
,
991 /* Detect multicast packets that didn't match the filter */
992 rx_ev_mcast_pkt
= EFX_QWORD_FIELD(*event
, RX_EV_MCAST_PKT
);
993 if (rx_ev_mcast_pkt
) {
994 unsigned int rx_ev_mcast_hash_match
=
995 EFX_QWORD_FIELD(*event
, RX_EV_MCAST_HASH_MATCH
);
997 if (unlikely(!rx_ev_mcast_hash_match
))
1001 /* Handle received packet */
1002 efx_rx_packet(rx_queue
, rx_ev_desc_ptr
, rx_ev_byte_cnt
,
1003 checksummed
, discard
);
1005 return rx_ev_q_label
;
1008 /* Global events are basically PHY events */
1009 static void falcon_handle_global_event(struct efx_channel
*channel
,
1012 struct efx_nic
*efx
= channel
->efx
;
1013 int is_phy_event
= 0, handled
= 0;
1015 /* Check for interrupt on either port. Some boards have a
1016 * single PHY wired to the interrupt line for port 1. */
1017 if (EFX_QWORD_FIELD(*event
, G_PHY0_INTR
) ||
1018 EFX_QWORD_FIELD(*event
, G_PHY1_INTR
) ||
1019 EFX_QWORD_FIELD(*event
, XG_PHY_INTR
))
1022 if ((falcon_rev(efx
) >= FALCON_REV_B0
) &&
1023 EFX_OWORD_FIELD(*event
, XG_MNT_INTR_B0
))
1027 efx
->phy_op
->clear_interrupt(efx
);
1028 queue_work(efx
->workqueue
, &efx
->reconfigure_work
);
1032 if (EFX_QWORD_FIELD_VER(efx
, *event
, RX_RECOVERY
)) {
1033 EFX_ERR(efx
, "channel %d seen global RX_RESET "
1034 "event. Resetting.\n", channel
->channel
);
1036 atomic_inc(&efx
->rx_reset
);
1037 efx_schedule_reset(efx
, EFX_WORKAROUND_6555(efx
) ?
1038 RESET_TYPE_RX_RECOVERY
: RESET_TYPE_DISABLE
);
1043 EFX_ERR(efx
, "channel %d unknown global event "
1044 EFX_QWORD_FMT
"\n", channel
->channel
,
1045 EFX_QWORD_VAL(*event
));
1048 static void falcon_handle_driver_event(struct efx_channel
*channel
,
1051 struct efx_nic
*efx
= channel
->efx
;
1052 unsigned int ev_sub_code
;
1053 unsigned int ev_sub_data
;
1055 ev_sub_code
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_CODE
);
1056 ev_sub_data
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_DATA
);
1058 switch (ev_sub_code
) {
1059 case TX_DESCQ_FLS_DONE_EV_DECODE
:
1060 EFX_TRACE(efx
, "channel %d TXQ %d flushed\n",
1061 channel
->channel
, ev_sub_data
);
1063 case RX_DESCQ_FLS_DONE_EV_DECODE
:
1064 EFX_TRACE(efx
, "channel %d RXQ %d flushed\n",
1065 channel
->channel
, ev_sub_data
);
1067 case EVQ_INIT_DONE_EV_DECODE
:
1068 EFX_LOG(efx
, "channel %d EVQ %d initialised\n",
1069 channel
->channel
, ev_sub_data
);
1071 case SRM_UPD_DONE_EV_DECODE
:
1072 EFX_TRACE(efx
, "channel %d SRAM update done\n",
1075 case WAKE_UP_EV_DECODE
:
1076 EFX_TRACE(efx
, "channel %d RXQ %d wakeup event\n",
1077 channel
->channel
, ev_sub_data
);
1079 case TIMER_EV_DECODE
:
1080 EFX_TRACE(efx
, "channel %d RX queue %d timer expired\n",
1081 channel
->channel
, ev_sub_data
);
1083 case RX_RECOVERY_EV_DECODE
:
1084 EFX_ERR(efx
, "channel %d seen DRIVER RX_RESET event. "
1085 "Resetting.\n", channel
->channel
);
1086 atomic_inc(&efx
->rx_reset
);
1087 efx_schedule_reset(efx
,
1088 EFX_WORKAROUND_6555(efx
) ?
1089 RESET_TYPE_RX_RECOVERY
:
1090 RESET_TYPE_DISABLE
);
1092 case RX_DSC_ERROR_EV_DECODE
:
1093 EFX_ERR(efx
, "RX DMA Q %d reports descriptor fetch error."
1094 " RX Q %d is disabled.\n", ev_sub_data
, ev_sub_data
);
1095 efx_schedule_reset(efx
, RESET_TYPE_RX_DESC_FETCH
);
1097 case TX_DSC_ERROR_EV_DECODE
:
1098 EFX_ERR(efx
, "TX DMA Q %d reports descriptor fetch error."
1099 " TX Q %d is disabled.\n", ev_sub_data
, ev_sub_data
);
1100 efx_schedule_reset(efx
, RESET_TYPE_TX_DESC_FETCH
);
1103 EFX_TRACE(efx
, "channel %d unknown driver event code %d "
1104 "data %04x\n", channel
->channel
, ev_sub_code
,
1110 int falcon_process_eventq(struct efx_channel
*channel
, int *rx_quota
)
1112 unsigned int read_ptr
;
1113 efx_qword_t event
, *p_event
;
1118 read_ptr
= channel
->eventq_read_ptr
;
1121 p_event
= falcon_event(channel
, read_ptr
);
1124 if (!falcon_event_present(&event
))
1128 EFX_TRACE(channel
->efx
, "channel %d event is "EFX_QWORD_FMT
"\n",
1129 channel
->channel
, EFX_QWORD_VAL(event
));
1131 /* Clear this event by marking it all ones */
1132 EFX_SET_QWORD(*p_event
);
1134 ev_code
= EFX_QWORD_FIELD(event
, EV_CODE
);
1137 case RX_IP_EV_DECODE
:
1138 rxq
= falcon_handle_rx_event(channel
, &event
);
1139 rxdmaqs
|= (1 << rxq
);
1142 case TX_IP_EV_DECODE
:
1143 falcon_handle_tx_event(channel
, &event
);
1145 case DRV_GEN_EV_DECODE
:
1146 channel
->eventq_magic
1147 = EFX_QWORD_FIELD(event
, EVQ_MAGIC
);
1148 EFX_LOG(channel
->efx
, "channel %d received generated "
1149 "event "EFX_QWORD_FMT
"\n", channel
->channel
,
1150 EFX_QWORD_VAL(event
));
1152 case GLOBAL_EV_DECODE
:
1153 falcon_handle_global_event(channel
, &event
);
1155 case DRIVER_EV_DECODE
:
1156 falcon_handle_driver_event(channel
, &event
);
1159 EFX_ERR(channel
->efx
, "channel %d unknown event type %d"
1160 " (data " EFX_QWORD_FMT
")\n", channel
->channel
,
1161 ev_code
, EFX_QWORD_VAL(event
));
1164 /* Increment read pointer */
1165 read_ptr
= (read_ptr
+ 1) & FALCON_EVQ_MASK
;
1167 } while (*rx_quota
);
1169 channel
->eventq_read_ptr
= read_ptr
;
1173 void falcon_set_int_moderation(struct efx_channel
*channel
)
1175 efx_dword_t timer_cmd
;
1176 struct efx_nic
*efx
= channel
->efx
;
1178 /* Set timer register */
1179 if (channel
->irq_moderation
) {
1180 /* Round to resolution supported by hardware. The value we
1181 * program is based at 0. So actual interrupt moderation
1182 * achieved is ((x + 1) * res).
1184 unsigned int res
= 5;
1185 channel
->irq_moderation
-= (channel
->irq_moderation
% res
);
1186 if (channel
->irq_moderation
< res
)
1187 channel
->irq_moderation
= res
;
1188 EFX_POPULATE_DWORD_2(timer_cmd
,
1189 TIMER_MODE
, TIMER_MODE_INT_HLDOFF
,
1191 (channel
->irq_moderation
/ res
) - 1);
1193 EFX_POPULATE_DWORD_2(timer_cmd
,
1194 TIMER_MODE
, TIMER_MODE_DIS
,
1197 falcon_writel_page_locked(efx
, &timer_cmd
, TIMER_CMD_REG_KER
,
1202 /* Allocate buffer table entries for event queue */
1203 int falcon_probe_eventq(struct efx_channel
*channel
)
1205 struct efx_nic
*efx
= channel
->efx
;
1206 unsigned int evq_size
;
1208 evq_size
= FALCON_EVQ_SIZE
* sizeof(efx_qword_t
);
1209 return falcon_alloc_special_buffer(efx
, &channel
->eventq
, evq_size
);
1212 int falcon_init_eventq(struct efx_channel
*channel
)
1214 efx_oword_t evq_ptr
;
1215 struct efx_nic
*efx
= channel
->efx
;
1218 EFX_LOG(efx
, "channel %d event queue in special buffers %d-%d\n",
1219 channel
->channel
, channel
->eventq
.index
,
1220 channel
->eventq
.index
+ channel
->eventq
.entries
- 1);
1222 /* Pin event queue buffer */
1223 rc
= falcon_init_special_buffer(efx
, &channel
->eventq
);
1227 /* Fill event queue with all ones (i.e. empty events) */
1228 memset(channel
->eventq
.addr
, 0xff, channel
->eventq
.len
);
1230 /* Push event queue to card */
1231 EFX_POPULATE_OWORD_3(evq_ptr
,
1233 EVQ_SIZE
, FALCON_EVQ_ORDER
,
1234 EVQ_BUF_BASE_ID
, channel
->eventq
.index
);
1235 falcon_write_table(efx
, &evq_ptr
, efx
->type
->evq_ptr_tbl_base
,
1238 falcon_set_int_moderation(channel
);
1243 void falcon_fini_eventq(struct efx_channel
*channel
)
1245 efx_oword_t eventq_ptr
;
1246 struct efx_nic
*efx
= channel
->efx
;
1248 /* Remove event queue from card */
1249 EFX_ZERO_OWORD(eventq_ptr
);
1250 falcon_write_table(efx
, &eventq_ptr
, efx
->type
->evq_ptr_tbl_base
,
1253 /* Unpin event queue */
1254 falcon_fini_special_buffer(efx
, &channel
->eventq
);
1257 /* Free buffers backing event queue */
1258 void falcon_remove_eventq(struct efx_channel
*channel
)
1260 falcon_free_special_buffer(channel
->efx
, &channel
->eventq
);
1264 /* Generates a test event on the event queue. A subsequent call to
1265 * process_eventq() should pick up the event and place the value of
1266 * "magic" into channel->eventq_magic;
1268 void falcon_generate_test_event(struct efx_channel
*channel
, unsigned int magic
)
1270 efx_qword_t test_event
;
1272 EFX_POPULATE_QWORD_2(test_event
,
1273 EV_CODE
, DRV_GEN_EV_DECODE
,
1275 falcon_generate_event(channel
, &test_event
);
1279 /**************************************************************************
1281 * Falcon hardware interrupts
1282 * The hardware interrupt handler does very little work; all the event
1283 * queue processing is carried out by per-channel tasklets.
1285 **************************************************************************/
1287 /* Enable/disable/generate Falcon interrupts */
1288 static inline void falcon_interrupts(struct efx_nic
*efx
, int enabled
,
1291 efx_oword_t int_en_reg_ker
;
1293 EFX_POPULATE_OWORD_2(int_en_reg_ker
,
1295 DRV_INT_EN_KER
, enabled
);
1296 falcon_write(efx
, &int_en_reg_ker
, INT_EN_REG_KER
);
1299 void falcon_enable_interrupts(struct efx_nic
*efx
)
1301 efx_oword_t int_adr_reg_ker
;
1302 struct efx_channel
*channel
;
1304 EFX_ZERO_OWORD(*((efx_oword_t
*) efx
->irq_status
.addr
));
1305 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1307 /* Program address */
1308 EFX_POPULATE_OWORD_2(int_adr_reg_ker
,
1309 NORM_INT_VEC_DIS_KER
, EFX_INT_MODE_USE_MSI(efx
),
1310 INT_ADR_KER
, efx
->irq_status
.dma_addr
);
1311 falcon_write(efx
, &int_adr_reg_ker
, INT_ADR_REG_KER
);
1313 /* Enable interrupts */
1314 falcon_interrupts(efx
, 1, 0);
1316 /* Force processing of all the channels to get the EVQ RPTRs up to
1318 efx_for_each_channel_with_interrupt(channel
, efx
)
1319 efx_schedule_channel(channel
);
1322 void falcon_disable_interrupts(struct efx_nic
*efx
)
1324 /* Disable interrupts */
1325 falcon_interrupts(efx
, 0, 0);
1328 /* Generate a Falcon test interrupt
1329 * Interrupt must already have been enabled, otherwise nasty things
1332 void falcon_generate_interrupt(struct efx_nic
*efx
)
1334 falcon_interrupts(efx
, 1, 1);
1337 /* Acknowledge a legacy interrupt from Falcon
1339 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1341 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1342 * BIU. Interrupt acknowledge is read sensitive so must write instead
1343 * (then read to ensure the BIU collector is flushed)
1345 * NB most hardware supports MSI interrupts
1347 static inline void falcon_irq_ack_a1(struct efx_nic
*efx
)
1351 EFX_POPULATE_DWORD_1(reg
, INT_ACK_DUMMY_DATA
, 0xb7eb7e);
1352 falcon_writel(efx
, ®
, INT_ACK_REG_KER_A1
);
1353 falcon_readl(efx
, ®
, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1
);
1356 /* Process a fatal interrupt
1357 * Disable bus mastering ASAP and schedule a reset
1359 static irqreturn_t
falcon_fatal_interrupt(struct efx_nic
*efx
)
1361 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1362 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1363 efx_oword_t fatal_intr
;
1364 int error
, mem_perr
;
1365 static int n_int_errors
;
1367 falcon_read(efx
, &fatal_intr
, FATAL_INTR_REG_KER
);
1368 error
= EFX_OWORD_FIELD(fatal_intr
, INT_KER_ERROR
);
1370 EFX_ERR(efx
, "SYSTEM ERROR " EFX_OWORD_FMT
" status "
1371 EFX_OWORD_FMT
": %s\n", EFX_OWORD_VAL(*int_ker
),
1372 EFX_OWORD_VAL(fatal_intr
),
1373 error
? "disabling bus mastering" : "no recognised error");
1377 /* If this is a memory parity error dump which blocks are offending */
1378 mem_perr
= EFX_OWORD_FIELD(fatal_intr
, MEM_PERR_INT_KER
);
1381 falcon_read(efx
, ®
, MEM_STAT_REG_KER
);
1382 EFX_ERR(efx
, "SYSTEM ERROR: memory parity error "
1383 EFX_OWORD_FMT
"\n", EFX_OWORD_VAL(reg
));
1386 /* Disable DMA bus mastering on both devices */
1387 pci_disable_device(efx
->pci_dev
);
1388 if (FALCON_IS_DUAL_FUNC(efx
))
1389 pci_disable_device(nic_data
->pci_dev2
);
1391 if (++n_int_errors
< FALCON_MAX_INT_ERRORS
) {
1392 EFX_ERR(efx
, "SYSTEM ERROR - reset scheduled\n");
1393 efx_schedule_reset(efx
, RESET_TYPE_INT_ERROR
);
1395 EFX_ERR(efx
, "SYSTEM ERROR - max number of errors seen."
1396 "NIC will be disabled\n");
1397 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
1403 /* Handle a legacy interrupt from Falcon
1404 * Acknowledges the interrupt and schedule event queue processing.
1406 static irqreturn_t
falcon_legacy_interrupt_b0(int irq
, void *dev_id
)
1408 struct efx_nic
*efx
= dev_id
;
1409 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1410 struct efx_channel
*channel
;
1415 /* Read the ISR which also ACKs the interrupts */
1416 falcon_readl(efx
, ®
, INT_ISR0_B0
);
1417 queues
= EFX_EXTRACT_DWORD(reg
, 0, 31);
1419 /* Check to see if we have a serious error condition */
1420 syserr
= EFX_OWORD_FIELD(*int_ker
, FATAL_INT
);
1421 if (unlikely(syserr
))
1422 return falcon_fatal_interrupt(efx
);
1427 efx
->last_irq_cpu
= raw_smp_processor_id();
1428 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_DWORD_FMT
"\n",
1429 irq
, raw_smp_processor_id(), EFX_DWORD_VAL(reg
));
1431 /* Schedule processing of any interrupting queues */
1432 channel
= &efx
->channel
[0];
1435 efx_schedule_channel(channel
);
1444 static irqreturn_t
falcon_legacy_interrupt_a1(int irq
, void *dev_id
)
1446 struct efx_nic
*efx
= dev_id
;
1447 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1448 struct efx_channel
*channel
;
1452 /* Check to see if this is our interrupt. If it isn't, we
1453 * exit without having touched the hardware.
1455 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker
))) {
1456 EFX_TRACE(efx
, "IRQ %d on CPU %d not for me\n", irq
,
1457 raw_smp_processor_id());
1460 efx
->last_irq_cpu
= raw_smp_processor_id();
1461 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_OWORD_FMT
"\n",
1462 irq
, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker
));
1464 /* Check to see if we have a serious error condition */
1465 syserr
= EFX_OWORD_FIELD(*int_ker
, FATAL_INT
);
1466 if (unlikely(syserr
))
1467 return falcon_fatal_interrupt(efx
);
1469 /* Determine interrupting queues, clear interrupt status
1470 * register and acknowledge the device interrupt.
1472 BUILD_BUG_ON(INT_EVQS_WIDTH
> EFX_MAX_CHANNELS
);
1473 queues
= EFX_OWORD_FIELD(*int_ker
, INT_EVQS
);
1474 EFX_ZERO_OWORD(*int_ker
);
1475 wmb(); /* Ensure the vector is cleared before interrupt ack */
1476 falcon_irq_ack_a1(efx
);
1478 /* Schedule processing of any interrupting queues */
1479 channel
= &efx
->channel
[0];
1482 efx_schedule_channel(channel
);
1490 /* Handle an MSI interrupt from Falcon
1492 * Handle an MSI hardware interrupt. This routine schedules event
1493 * queue processing. No interrupt acknowledgement cycle is necessary.
1494 * Also, we never need to check that the interrupt is for us, since
1495 * MSI interrupts cannot be shared.
1497 static irqreturn_t
falcon_msi_interrupt(int irq
, void *dev_id
)
1499 struct efx_channel
*channel
= dev_id
;
1500 struct efx_nic
*efx
= channel
->efx
;
1501 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1504 efx
->last_irq_cpu
= raw_smp_processor_id();
1505 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_OWORD_FMT
"\n",
1506 irq
, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker
));
1508 /* Check to see if we have a serious error condition */
1509 syserr
= EFX_OWORD_FIELD(*int_ker
, FATAL_INT
);
1510 if (unlikely(syserr
))
1511 return falcon_fatal_interrupt(efx
);
1513 /* Schedule processing of the channel */
1514 efx_schedule_channel(channel
);
1520 /* Setup RSS indirection table.
1521 * This maps from the hash value of the packet to RXQ
1523 static void falcon_setup_rss_indir_table(struct efx_nic
*efx
)
1526 unsigned long offset
;
1529 if (falcon_rev(efx
) < FALCON_REV_B0
)
1532 for (offset
= RX_RSS_INDIR_TBL_B0
;
1533 offset
< RX_RSS_INDIR_TBL_B0
+ 0x800;
1535 EFX_POPULATE_DWORD_1(dword
, RX_RSS_INDIR_ENT_B0
,
1536 i
% efx
->rss_queues
);
1537 falcon_writel(efx
, &dword
, offset
);
1542 /* Hook interrupt handler(s)
1543 * Try MSI and then legacy interrupts.
1545 int falcon_init_interrupt(struct efx_nic
*efx
)
1547 struct efx_channel
*channel
;
1550 if (!EFX_INT_MODE_USE_MSI(efx
)) {
1551 irq_handler_t handler
;
1552 if (falcon_rev(efx
) >= FALCON_REV_B0
)
1553 handler
= falcon_legacy_interrupt_b0
;
1555 handler
= falcon_legacy_interrupt_a1
;
1557 rc
= request_irq(efx
->legacy_irq
, handler
, IRQF_SHARED
,
1560 EFX_ERR(efx
, "failed to hook legacy IRQ %d\n",
1567 /* Hook MSI or MSI-X interrupt */
1568 efx_for_each_channel_with_interrupt(channel
, efx
) {
1569 rc
= request_irq(channel
->irq
, falcon_msi_interrupt
,
1570 IRQF_PROBE_SHARED
, /* Not shared */
1571 efx
->name
, channel
);
1573 EFX_ERR(efx
, "failed to hook IRQ %d\n", channel
->irq
);
1581 efx_for_each_channel_with_interrupt(channel
, efx
)
1582 free_irq(channel
->irq
, channel
);
1587 void falcon_fini_interrupt(struct efx_nic
*efx
)
1589 struct efx_channel
*channel
;
1592 /* Disable MSI/MSI-X interrupts */
1593 efx_for_each_channel_with_interrupt(channel
, efx
) {
1595 free_irq(channel
->irq
, channel
);
1598 /* ACK legacy interrupt */
1599 if (falcon_rev(efx
) >= FALCON_REV_B0
)
1600 falcon_read(efx
, ®
, INT_ISR0_B0
);
1602 falcon_irq_ack_a1(efx
);
1604 /* Disable legacy interrupt */
1605 if (efx
->legacy_irq
)
1606 free_irq(efx
->legacy_irq
, efx
);
1609 /**************************************************************************
1613 **************************************************************************
1616 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1618 /* Wait for SPI command completion */
1619 static int falcon_spi_wait(struct efx_nic
*efx
)
1622 int cmd_en
, timer_active
;
1627 falcon_read(efx
, ®
, EE_SPI_HCMD_REG_KER
);
1628 cmd_en
= EFX_OWORD_FIELD(reg
, EE_SPI_HCMD_CMD_EN
);
1629 timer_active
= EFX_OWORD_FIELD(reg
, EE_WR_TIMER_ACTIVE
);
1630 if (!cmd_en
&& !timer_active
)
1633 } while (++count
< 10000); /* wait upto 100msec */
1634 EFX_ERR(efx
, "timed out waiting for SPI\n");
1639 falcon_spi_read(struct efx_nic
*efx
, int device_id
, unsigned int command
,
1640 unsigned int address
, unsigned int addr_len
,
1641 void *data
, unsigned int len
)
1646 BUG_ON(len
> FALCON_SPI_MAX_LEN
);
1648 /* Check SPI not currently being accessed */
1649 rc
= falcon_spi_wait(efx
);
1653 /* Program address register */
1654 EFX_POPULATE_OWORD_1(reg
, EE_SPI_HADR_ADR
, address
);
1655 falcon_write(efx
, ®
, EE_SPI_HADR_REG_KER
);
1657 /* Issue read command */
1658 EFX_POPULATE_OWORD_7(reg
,
1659 EE_SPI_HCMD_CMD_EN
, 1,
1660 EE_SPI_HCMD_SF_SEL
, device_id
,
1661 EE_SPI_HCMD_DABCNT
, len
,
1662 EE_SPI_HCMD_READ
, EE_SPI_READ
,
1663 EE_SPI_HCMD_DUBCNT
, 0,
1664 EE_SPI_HCMD_ADBCNT
, addr_len
,
1665 EE_SPI_HCMD_ENC
, command
);
1666 falcon_write(efx
, ®
, EE_SPI_HCMD_REG_KER
);
1668 /* Wait for read to complete */
1669 rc
= falcon_spi_wait(efx
);
1674 falcon_read(efx
, ®
, EE_SPI_HDATA_REG_KER
);
1675 memcpy(data
, ®
, len
);
1679 /**************************************************************************
1683 **************************************************************************
1685 void falcon_drain_tx_fifo(struct efx_nic
*efx
)
1690 if ((falcon_rev(efx
) < FALCON_REV_B0
) ||
1691 (efx
->loopback_mode
!= LOOPBACK_NONE
))
1694 falcon_read(efx
, &temp
, MAC0_CTRL_REG_KER
);
1695 /* There is no point in draining more than once */
1696 if (EFX_OWORD_FIELD(temp
, TXFIFO_DRAIN_EN_B0
))
1699 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1700 * the drain sequence with the statistics fetch */
1701 spin_lock(&efx
->stats_lock
);
1703 EFX_SET_OWORD_FIELD(temp
, TXFIFO_DRAIN_EN_B0
, 1);
1704 falcon_write(efx
, &temp
, MAC0_CTRL_REG_KER
);
1706 /* Reset the MAC and EM block. */
1707 falcon_read(efx
, &temp
, GLB_CTL_REG_KER
);
1708 EFX_SET_OWORD_FIELD(temp
, RST_XGTX
, 1);
1709 EFX_SET_OWORD_FIELD(temp
, RST_XGRX
, 1);
1710 EFX_SET_OWORD_FIELD(temp
, RST_EM
, 1);
1711 falcon_write(efx
, &temp
, GLB_CTL_REG_KER
);
1715 falcon_read(efx
, &temp
, GLB_CTL_REG_KER
);
1716 if (!EFX_OWORD_FIELD(temp
, RST_XGTX
) &&
1717 !EFX_OWORD_FIELD(temp
, RST_XGRX
) &&
1718 !EFX_OWORD_FIELD(temp
, RST_EM
)) {
1719 EFX_LOG(efx
, "Completed MAC reset after %d loops\n",
1724 EFX_ERR(efx
, "MAC reset failed\n");
1731 spin_unlock(&efx
->stats_lock
);
1733 /* If we've reset the EM block and the link is up, then
1734 * we'll have to kick the XAUI link so the PHY can recover */
1735 if (efx
->link_up
&& EFX_WORKAROUND_5147(efx
))
1736 falcon_reset_xaui(efx
);
1739 void falcon_deconfigure_mac_wrapper(struct efx_nic
*efx
)
1743 if (falcon_rev(efx
) < FALCON_REV_B0
)
1746 /* Isolate the MAC -> RX */
1747 falcon_read(efx
, &temp
, RX_CFG_REG_KER
);
1748 EFX_SET_OWORD_FIELD(temp
, RX_INGR_EN_B0
, 0);
1749 falcon_write(efx
, &temp
, RX_CFG_REG_KER
);
1752 falcon_drain_tx_fifo(efx
);
1755 void falcon_reconfigure_mac_wrapper(struct efx_nic
*efx
)
1761 if (efx
->link_options
& GM_LPA_10000
)
1763 else if (efx
->link_options
& GM_LPA_1000
)
1765 else if (efx
->link_options
& GM_LPA_100
)
1769 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1770 * as advertised. Disable to ensure packets are not
1771 * indefinitely held and TX queue can be flushed at any point
1772 * while the link is down. */
1773 EFX_POPULATE_OWORD_5(reg
,
1774 MAC_XOFF_VAL
, 0xffff /* max pause time */,
1776 MAC_UC_PROM
, efx
->promiscuous
,
1777 MAC_LINK_STATUS
, 1, /* always set */
1778 MAC_SPEED
, link_speed
);
1779 /* On B0, MAC backpressure can be disabled and packets get
1781 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
1782 EFX_SET_OWORD_FIELD(reg
, TXFIFO_DRAIN_EN_B0
,
1786 falcon_write(efx
, ®
, MAC0_CTRL_REG_KER
);
1788 /* Restore the multicast hash registers. */
1789 falcon_set_multicast_hash(efx
);
1791 /* Transmission of pause frames when RX crosses the threshold is
1792 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1793 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1794 tx_fc
= (efx
->flow_control
& EFX_FC_TX
) ? 1 : 0;
1795 falcon_read(efx
, ®
, RX_CFG_REG_KER
);
1796 EFX_SET_OWORD_FIELD_VER(efx
, reg
, RX_XOFF_MAC_EN
, tx_fc
);
1798 /* Unisolate the MAC -> RX */
1799 if (falcon_rev(efx
) >= FALCON_REV_B0
)
1800 EFX_SET_OWORD_FIELD(reg
, RX_INGR_EN_B0
, 1);
1801 falcon_write(efx
, ®
, RX_CFG_REG_KER
);
1804 int falcon_dma_stats(struct efx_nic
*efx
, unsigned int done_offset
)
1810 if (disable_dma_stats
)
1813 /* Statistics fetch will fail if the MAC is in TX drain */
1814 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
1816 falcon_read(efx
, &temp
, MAC0_CTRL_REG_KER
);
1817 if (EFX_OWORD_FIELD(temp
, TXFIFO_DRAIN_EN_B0
))
1821 dma_done
= (efx
->stats_buffer
.addr
+ done_offset
);
1822 *dma_done
= FALCON_STATS_NOT_DONE
;
1823 wmb(); /* ensure done flag is clear */
1825 /* Initiate DMA transfer of stats */
1826 EFX_POPULATE_OWORD_2(reg
,
1827 MAC_STAT_DMA_CMD
, 1,
1829 efx
->stats_buffer
.dma_addr
);
1830 falcon_write(efx
, ®
, MAC0_STAT_DMA_REG_KER
);
1832 /* Wait for transfer to complete */
1833 for (i
= 0; i
< 400; i
++) {
1834 if (*(volatile u32
*)dma_done
== FALCON_STATS_DONE
)
1839 EFX_ERR(efx
, "timed out waiting for statistics\n");
1843 /**************************************************************************
1845 * PHY access via GMII
1847 **************************************************************************
1850 /* Use the top bit of the MII PHY id to indicate the PHY type
1851 * (1G/10G), with the remaining bits as the actual PHY id.
1853 * This allows us to avoid leaking information from the mii_if_info
1854 * structure into other data structures.
1856 #define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
1857 #define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1858 #define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
1859 #define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
1860 #define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
1863 /* Packing the clause 45 port and device fields into a single value */
1864 #define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1865 #define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
1866 #define MD_DEV_ADR_COMP_LBN 0
1867 #define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
1870 /* Wait for GMII access to complete */
1871 static int falcon_gmii_wait(struct efx_nic
*efx
)
1873 efx_dword_t md_stat
;
1876 for (count
= 0; count
< 1000; count
++) { /* wait upto 10ms */
1877 falcon_readl(efx
, &md_stat
, MD_STAT_REG_KER
);
1878 if (EFX_DWORD_FIELD(md_stat
, MD_BSY
) == 0) {
1879 if (EFX_DWORD_FIELD(md_stat
, MD_LNFL
) != 0 ||
1880 EFX_DWORD_FIELD(md_stat
, MD_BSERR
) != 0) {
1881 EFX_ERR(efx
, "error from GMII access "
1883 EFX_DWORD_VAL(md_stat
));
1890 EFX_ERR(efx
, "timed out waiting for GMII\n");
1894 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
1895 static void falcon_mdio_write(struct net_device
*net_dev
, int phy_id
,
1896 int addr
, int value
)
1898 struct efx_nic
*efx
= netdev_priv(net_dev
);
1899 unsigned int phy_id2
= phy_id
& FALCON_PHY_ID_ID_MASK
;
1902 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
1903 * chosen so that the only current user, Falcon, can take the
1904 * packed value and use them directly.
1905 * Fail to build if this assumption is broken.
1907 BUILD_BUG_ON(FALCON_PHY_ID_10G
!= MDIO45_XPRT_ID_IS10G
);
1908 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH
!= MDIO45_PRT_DEV_WIDTH
);
1909 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN
!= MDIO45_PRT_ID_COMP_LBN
);
1910 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN
!= MDIO45_DEV_ID_COMP_LBN
);
1912 if (phy_id2
== PHY_ADDR_INVALID
)
1915 /* See falcon_mdio_read for an explanation. */
1916 if (!(phy_id
& FALCON_PHY_ID_10G
)) {
1917 int mmd
= ffs(efx
->phy_op
->mmds
) - 1;
1918 EFX_TRACE(efx
, "Fixing erroneous clause22 write\n");
1919 phy_id2
= mdio_clause45_pack(phy_id2
, mmd
)
1920 & FALCON_PHY_ID_ID_MASK
;
1923 EFX_REGDUMP(efx
, "writing GMII %d register %02x with %04x\n", phy_id
,
1926 spin_lock_bh(&efx
->phy_lock
);
1928 /* Check MII not currently being accessed */
1929 if (falcon_gmii_wait(efx
) != 0)
1932 /* Write the address/ID register */
1933 EFX_POPULATE_OWORD_1(reg
, MD_PHY_ADR
, addr
);
1934 falcon_write(efx
, ®
, MD_PHY_ADR_REG_KER
);
1936 EFX_POPULATE_OWORD_1(reg
, MD_PRT_DEV_ADR
, phy_id2
);
1937 falcon_write(efx
, ®
, MD_ID_REG_KER
);
1940 EFX_POPULATE_OWORD_1(reg
, MD_TXD
, value
);
1941 falcon_write(efx
, ®
, MD_TXD_REG_KER
);
1943 EFX_POPULATE_OWORD_2(reg
,
1946 falcon_write(efx
, ®
, MD_CS_REG_KER
);
1948 /* Wait for data to be written */
1949 if (falcon_gmii_wait(efx
) != 0) {
1950 /* Abort the write operation */
1951 EFX_POPULATE_OWORD_2(reg
,
1954 falcon_write(efx
, ®
, MD_CS_REG_KER
);
1959 spin_unlock_bh(&efx
->phy_lock
);
1962 /* Reads a GMII register from a PHY connected to Falcon. If no value
1963 * could be read, -1 will be returned. */
1964 static int falcon_mdio_read(struct net_device
*net_dev
, int phy_id
, int addr
)
1966 struct efx_nic
*efx
= netdev_priv(net_dev
);
1967 unsigned int phy_addr
= phy_id
& FALCON_PHY_ID_ID_MASK
;
1971 if (phy_addr
== PHY_ADDR_INVALID
)
1974 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
1975 * but the generic Linux code does not make any distinction or have
1976 * any state for this.
1977 * We spot the case where someone tried to talk 22 to a 45 PHY and
1978 * redirect the request to the lowest numbered MMD as a clause45
1979 * request. This is enough to allow simple queries like id and link
1980 * state to succeed. TODO: We may need to do more in future.
1982 if (!(phy_id
& FALCON_PHY_ID_10G
)) {
1983 int mmd
= ffs(efx
->phy_op
->mmds
) - 1;
1984 EFX_TRACE(efx
, "Fixing erroneous clause22 read\n");
1985 phy_addr
= mdio_clause45_pack(phy_addr
, mmd
)
1986 & FALCON_PHY_ID_ID_MASK
;
1989 spin_lock_bh(&efx
->phy_lock
);
1991 /* Check MII not currently being accessed */
1992 if (falcon_gmii_wait(efx
) != 0)
1995 EFX_POPULATE_OWORD_1(reg
, MD_PHY_ADR
, addr
);
1996 falcon_write(efx
, ®
, MD_PHY_ADR_REG_KER
);
1998 EFX_POPULATE_OWORD_1(reg
, MD_PRT_DEV_ADR
, phy_addr
);
1999 falcon_write(efx
, ®
, MD_ID_REG_KER
);
2001 /* Request data to be read */
2002 EFX_POPULATE_OWORD_2(reg
, MD_RDC
, 1, MD_GC
, 0);
2003 falcon_write(efx
, ®
, MD_CS_REG_KER
);
2005 /* Wait for data to become available */
2006 value
= falcon_gmii_wait(efx
);
2008 falcon_read(efx
, ®
, MD_RXD_REG_KER
);
2009 value
= EFX_OWORD_FIELD(reg
, MD_RXD
);
2010 EFX_REGDUMP(efx
, "read from GMII %d register %02x, got %04x\n",
2011 phy_id
, addr
, value
);
2013 /* Abort the read operation */
2014 EFX_POPULATE_OWORD_2(reg
,
2017 falcon_write(efx
, ®
, MD_CS_REG_KER
);
2019 EFX_LOG(efx
, "read from GMII 0x%x register %02x, got "
2020 "error %d\n", phy_id
, addr
, value
);
2024 spin_unlock_bh(&efx
->phy_lock
);
2029 static void falcon_init_mdio(struct mii_if_info
*gmii
)
2031 gmii
->mdio_read
= falcon_mdio_read
;
2032 gmii
->mdio_write
= falcon_mdio_write
;
2033 gmii
->phy_id_mask
= FALCON_PHY_ID_MASK
;
2034 gmii
->reg_num_mask
= ((1 << EFX_WIDTH(MD_PHY_ADR
)) - 1);
2037 static int falcon_probe_phy(struct efx_nic
*efx
)
2039 switch (efx
->phy_type
) {
2040 case PHY_TYPE_10XPRESS
:
2041 efx
->phy_op
= &falcon_tenxpress_phy_ops
;
2044 efx
->phy_op
= &falcon_xfp_phy_ops
;
2047 EFX_ERR(efx
, "Unknown PHY type %d\n",
2052 efx
->loopback_modes
= LOOPBACKS_10G_INTERNAL
| efx
->phy_op
->loopbacks
;
2056 /* This call is responsible for hooking in the MAC and PHY operations */
2057 int falcon_probe_port(struct efx_nic
*efx
)
2061 /* Hook in PHY operations table */
2062 rc
= falcon_probe_phy(efx
);
2066 /* Set up GMII structure for PHY */
2067 efx
->mii
.supports_gmii
= 1;
2068 falcon_init_mdio(&efx
->mii
);
2070 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2071 if (falcon_rev(efx
) >= FALCON_REV_B0
)
2072 efx
->flow_control
= EFX_FC_RX
| EFX_FC_TX
;
2074 efx
->flow_control
= EFX_FC_RX
;
2076 /* Allocate buffer for stats */
2077 rc
= falcon_alloc_buffer(efx
, &efx
->stats_buffer
,
2078 FALCON_MAC_STATS_SIZE
);
2081 EFX_LOG(efx
, "stats buffer at %llx (virt %p phys %lx)\n",
2082 (unsigned long long)efx
->stats_buffer
.dma_addr
,
2083 efx
->stats_buffer
.addr
,
2084 virt_to_phys(efx
->stats_buffer
.addr
));
2089 void falcon_remove_port(struct efx_nic
*efx
)
2091 falcon_free_buffer(efx
, &efx
->stats_buffer
);
2094 /**************************************************************************
2096 * Multicast filtering
2098 **************************************************************************
2101 void falcon_set_multicast_hash(struct efx_nic
*efx
)
2103 union efx_multicast_hash
*mc_hash
= &efx
->multicast_hash
;
2105 /* Broadcast packets go through the multicast hash filter.
2106 * ether_crc_le() of the broadcast address is 0xbe2612ff
2107 * so we always add bit 0xff to the mask.
2109 set_bit_le(0xff, mc_hash
->byte
);
2111 falcon_write(efx
, &mc_hash
->oword
[0], MAC_MCAST_HASH_REG0_KER
);
2112 falcon_write(efx
, &mc_hash
->oword
[1], MAC_MCAST_HASH_REG1_KER
);
2115 /**************************************************************************
2119 **************************************************************************
2122 /* Resets NIC to known state. This routine must be called in process
2123 * context and is allowed to sleep. */
2124 int falcon_reset_hw(struct efx_nic
*efx
, enum reset_type method
)
2126 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2127 efx_oword_t glb_ctl_reg_ker
;
2130 EFX_LOG(efx
, "performing hardware reset (%d)\n", method
);
2132 /* Initiate device reset */
2133 if (method
== RESET_TYPE_WORLD
) {
2134 rc
= pci_save_state(efx
->pci_dev
);
2136 EFX_ERR(efx
, "failed to backup PCI state of primary "
2137 "function prior to hardware reset\n");
2140 if (FALCON_IS_DUAL_FUNC(efx
)) {
2141 rc
= pci_save_state(nic_data
->pci_dev2
);
2143 EFX_ERR(efx
, "failed to backup PCI state of "
2144 "secondary function prior to "
2145 "hardware reset\n");
2150 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker
,
2151 EXT_PHY_RST_DUR
, 0x7,
2154 int reset_phy
= (method
== RESET_TYPE_INVISIBLE
?
2155 EXCLUDE_FROM_RESET
: 0);
2157 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker
,
2158 EXT_PHY_RST_CTL
, reset_phy
,
2159 PCIE_CORE_RST_CTL
, EXCLUDE_FROM_RESET
,
2160 PCIE_NSTCK_RST_CTL
, EXCLUDE_FROM_RESET
,
2161 PCIE_SD_RST_CTL
, EXCLUDE_FROM_RESET
,
2162 EE_RST_CTL
, EXCLUDE_FROM_RESET
,
2163 EXT_PHY_RST_DUR
, 0x7 /* 10ms */,
2166 falcon_write(efx
, &glb_ctl_reg_ker
, GLB_CTL_REG_KER
);
2168 EFX_LOG(efx
, "waiting for hardware reset\n");
2169 schedule_timeout_uninterruptible(HZ
/ 20);
2171 /* Restore PCI configuration if needed */
2172 if (method
== RESET_TYPE_WORLD
) {
2173 if (FALCON_IS_DUAL_FUNC(efx
)) {
2174 rc
= pci_restore_state(nic_data
->pci_dev2
);
2176 EFX_ERR(efx
, "failed to restore PCI config for "
2177 "the secondary function\n");
2181 rc
= pci_restore_state(efx
->pci_dev
);
2183 EFX_ERR(efx
, "failed to restore PCI config for the "
2184 "primary function\n");
2187 EFX_LOG(efx
, "successfully restored PCI config\n");
2190 /* Assert that reset complete */
2191 falcon_read(efx
, &glb_ctl_reg_ker
, GLB_CTL_REG_KER
);
2192 if (EFX_OWORD_FIELD(glb_ctl_reg_ker
, SWRST
) != 0) {
2194 EFX_ERR(efx
, "timed out waiting for hardware reset\n");
2197 EFX_LOG(efx
, "hardware reset complete\n");
2201 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2204 pci_restore_state(efx
->pci_dev
);
2211 /* Zeroes out the SRAM contents. This routine must be called in
2212 * process context and is allowed to sleep.
2214 static int falcon_reset_sram(struct efx_nic
*efx
)
2216 efx_oword_t srm_cfg_reg_ker
, gpio_cfg_reg_ker
;
2219 /* Set the SRAM wake/sleep GPIO appropriately. */
2220 falcon_read(efx
, &gpio_cfg_reg_ker
, GPIO_CTL_REG_KER
);
2221 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, GPIO1_OEN
, 1);
2222 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, GPIO1_OUT
, 1);
2223 falcon_write(efx
, &gpio_cfg_reg_ker
, GPIO_CTL_REG_KER
);
2225 /* Initiate SRAM reset */
2226 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker
,
2227 SRAM_OOB_BT_INIT_EN
, 1,
2228 SRM_NUM_BANKS_AND_BANK_SIZE
, 0);
2229 falcon_write(efx
, &srm_cfg_reg_ker
, SRM_CFG_REG_KER
);
2231 /* Wait for SRAM reset to complete */
2234 EFX_LOG(efx
, "waiting for SRAM reset (attempt %d)...\n", count
);
2236 /* SRAM reset is slow; expect around 16ms */
2237 schedule_timeout_uninterruptible(HZ
/ 50);
2239 /* Check for reset complete */
2240 falcon_read(efx
, &srm_cfg_reg_ker
, SRM_CFG_REG_KER
);
2241 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker
, SRAM_OOB_BT_INIT_EN
)) {
2242 EFX_LOG(efx
, "SRAM reset complete\n");
2246 } while (++count
< 20); /* wait upto 0.4 sec */
2248 EFX_ERR(efx
, "timed out waiting for SRAM reset\n");
2252 /* Extract non-volatile configuration */
2253 static int falcon_probe_nvconfig(struct efx_nic
*efx
)
2255 struct falcon_nvconfig
*nvconfig
;
2256 efx_oword_t nic_stat
;
2260 int magic_num
, struct_ver
, board_rev
;
2263 /* Find the boot device. */
2264 falcon_read(efx
, &nic_stat
, NIC_STAT_REG
);
2265 if (EFX_OWORD_FIELD(nic_stat
, SF_PRST
)) {
2266 device_id
= EE_SPI_FLASH
;
2268 } else if (EFX_OWORD_FIELD(nic_stat
, EE_PRST
)) {
2269 device_id
= EE_SPI_EEPROM
;
2275 nvconfig
= kmalloc(sizeof(*nvconfig
), GFP_KERNEL
);
2277 /* Read the whole configuration structure into memory. */
2278 for (offset
= 0; offset
< sizeof(*nvconfig
); offset
+= len
) {
2279 len
= min(sizeof(*nvconfig
) - offset
,
2280 (size_t) FALCON_SPI_MAX_LEN
);
2281 rc
= falcon_spi_read(efx
, device_id
, SPI_READ
,
2282 NVCONFIG_BASE
+ offset
, addr_len
,
2283 (char *)nvconfig
+ offset
, len
);
2288 /* Read the MAC addresses */
2289 memcpy(efx
->mac_address
, nvconfig
->mac_address
[0], ETH_ALEN
);
2291 /* Read the board configuration. */
2292 magic_num
= le16_to_cpu(nvconfig
->board_magic_num
);
2293 struct_ver
= le16_to_cpu(nvconfig
->board_struct_ver
);
2295 if (magic_num
!= NVCONFIG_BOARD_MAGIC_NUM
|| struct_ver
< 2) {
2296 EFX_ERR(efx
, "Non volatile memory bad magic=%x ver=%x "
2297 "therefore using defaults\n", magic_num
, struct_ver
);
2298 efx
->phy_type
= PHY_TYPE_NONE
;
2299 efx
->mii
.phy_id
= PHY_ADDR_INVALID
;
2302 struct falcon_nvconfig_board_v2
*v2
= &nvconfig
->board_v2
;
2304 efx
->phy_type
= v2
->port0_phy_type
;
2305 efx
->mii
.phy_id
= v2
->port0_phy_addr
;
2306 board_rev
= le16_to_cpu(v2
->board_revision
);
2309 EFX_LOG(efx
, "PHY is %d phy_id %d\n", efx
->phy_type
, efx
->mii
.phy_id
);
2311 efx_set_board_info(efx
, board_rev
);
2318 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2319 * count, port speed). Set workaround and feature flags accordingly.
2321 static int falcon_probe_nic_variant(struct efx_nic
*efx
)
2323 efx_oword_t altera_build
;
2325 falcon_read(efx
, &altera_build
, ALTERA_BUILD_REG_KER
);
2326 if (EFX_OWORD_FIELD(altera_build
, VER_ALL
)) {
2327 EFX_ERR(efx
, "Falcon FPGA not supported\n");
2331 switch (falcon_rev(efx
)) {
2334 EFX_ERR(efx
, "Falcon rev A0 not supported\n");
2337 case FALCON_REV_A1
:{
2338 efx_oword_t nic_stat
;
2340 falcon_read(efx
, &nic_stat
, NIC_STAT_REG
);
2342 if (EFX_OWORD_FIELD(nic_stat
, STRAP_PCIE
) == 0) {
2343 EFX_ERR(efx
, "Falcon rev A1 PCI-X not supported\n");
2346 if (!EFX_OWORD_FIELD(nic_stat
, STRAP_10G
)) {
2347 EFX_ERR(efx
, "1G mode not supported\n");
2357 EFX_ERR(efx
, "Unknown Falcon rev %d\n", falcon_rev(efx
));
2364 int falcon_probe_nic(struct efx_nic
*efx
)
2366 struct falcon_nic_data
*nic_data
;
2369 /* Allocate storage for hardware specific data */
2370 nic_data
= kzalloc(sizeof(*nic_data
), GFP_KERNEL
);
2371 efx
->nic_data
= nic_data
;
2373 /* Determine number of ports etc. */
2374 rc
= falcon_probe_nic_variant(efx
);
2378 /* Probe secondary function if expected */
2379 if (FALCON_IS_DUAL_FUNC(efx
)) {
2380 struct pci_dev
*dev
= pci_dev_get(efx
->pci_dev
);
2382 while ((dev
= pci_get_device(EFX_VENDID_SFC
, FALCON_A_S_DEVID
,
2384 if (dev
->bus
== efx
->pci_dev
->bus
&&
2385 dev
->devfn
== efx
->pci_dev
->devfn
+ 1) {
2386 nic_data
->pci_dev2
= dev
;
2390 if (!nic_data
->pci_dev2
) {
2391 EFX_ERR(efx
, "failed to find secondary function\n");
2397 /* Now we can reset the NIC */
2398 rc
= falcon_reset_hw(efx
, RESET_TYPE_ALL
);
2400 EFX_ERR(efx
, "failed to reset NIC\n");
2404 /* Allocate memory for INT_KER */
2405 rc
= falcon_alloc_buffer(efx
, &efx
->irq_status
, sizeof(efx_oword_t
));
2408 BUG_ON(efx
->irq_status
.dma_addr
& 0x0f);
2410 EFX_LOG(efx
, "INT_KER at %llx (virt %p phys %lx)\n",
2411 (unsigned long long)efx
->irq_status
.dma_addr
,
2412 efx
->irq_status
.addr
, virt_to_phys(efx
->irq_status
.addr
));
2414 /* Read in the non-volatile configuration */
2415 rc
= falcon_probe_nvconfig(efx
);
2419 /* Initialise I2C adapter */
2420 efx
->i2c_adap
.owner
= THIS_MODULE
;
2421 nic_data
->i2c_data
= falcon_i2c_bit_operations
;
2422 nic_data
->i2c_data
.data
= efx
;
2423 efx
->i2c_adap
.algo_data
= &nic_data
->i2c_data
;
2424 efx
->i2c_adap
.dev
.parent
= &efx
->pci_dev
->dev
;
2425 strlcpy(efx
->i2c_adap
.name
, "SFC4000 GPIO", sizeof(efx
->i2c_adap
.name
));
2426 rc
= i2c_bit_add_bus(&efx
->i2c_adap
);
2433 falcon_free_buffer(efx
, &efx
->irq_status
);
2436 if (nic_data
->pci_dev2
) {
2437 pci_dev_put(nic_data
->pci_dev2
);
2438 nic_data
->pci_dev2
= NULL
;
2442 kfree(efx
->nic_data
);
2446 /* This call performs hardware-specific global initialisation, such as
2447 * defining the descriptor cache sizes and number of RSS channels.
2448 * It does not set up any buffers, descriptor rings or event queues.
2450 int falcon_init_nic(struct efx_nic
*efx
)
2456 /* Set up the address region register. This is only needed
2457 * for the B0 FPGA, but since we are just pushing in the
2458 * reset defaults this may as well be unconditional. */
2459 EFX_POPULATE_OWORD_4(temp
, ADR_REGION0
, 0,
2460 ADR_REGION1
, (1 << 16),
2461 ADR_REGION2
, (2 << 16),
2462 ADR_REGION3
, (3 << 16));
2463 falcon_write(efx
, &temp
, ADR_REGION_REG_KER
);
2465 /* Use on-chip SRAM */
2466 falcon_read(efx
, &temp
, NIC_STAT_REG
);
2467 EFX_SET_OWORD_FIELD(temp
, ONCHIP_SRAM
, 1);
2468 falcon_write(efx
, &temp
, NIC_STAT_REG
);
2470 /* Set buffer table mode */
2471 EFX_POPULATE_OWORD_1(temp
, BUF_TBL_MODE
, BUF_TBL_MODE_FULL
);
2472 falcon_write(efx
, &temp
, BUF_TBL_CFG_REG_KER
);
2474 rc
= falcon_reset_sram(efx
);
2478 /* Set positions of descriptor caches in SRAM. */
2479 EFX_POPULATE_OWORD_1(temp
, SRM_TX_DC_BASE_ADR
, TX_DC_BASE
/ 8);
2480 falcon_write(efx
, &temp
, SRM_TX_DC_CFG_REG_KER
);
2481 EFX_POPULATE_OWORD_1(temp
, SRM_RX_DC_BASE_ADR
, RX_DC_BASE
/ 8);
2482 falcon_write(efx
, &temp
, SRM_RX_DC_CFG_REG_KER
);
2484 /* Set TX descriptor cache size. */
2485 BUILD_BUG_ON(TX_DC_ENTRIES
!= (16 << TX_DC_ENTRIES_ORDER
));
2486 EFX_POPULATE_OWORD_1(temp
, TX_DC_SIZE
, TX_DC_ENTRIES_ORDER
);
2487 falcon_write(efx
, &temp
, TX_DC_CFG_REG_KER
);
2489 /* Set RX descriptor cache size. Set low watermark to size-8, as
2490 * this allows most efficient prefetching.
2492 BUILD_BUG_ON(RX_DC_ENTRIES
!= (16 << RX_DC_ENTRIES_ORDER
));
2493 EFX_POPULATE_OWORD_1(temp
, RX_DC_SIZE
, RX_DC_ENTRIES_ORDER
);
2494 falcon_write(efx
, &temp
, RX_DC_CFG_REG_KER
);
2495 EFX_POPULATE_OWORD_1(temp
, RX_DC_PF_LWM
, RX_DC_ENTRIES
- 8);
2496 falcon_write(efx
, &temp
, RX_DC_PF_WM_REG_KER
);
2498 /* Clear the parity enables on the TX data fifos as
2499 * they produce false parity errors because of timing issues
2501 if (EFX_WORKAROUND_5129(efx
)) {
2502 falcon_read(efx
, &temp
, SPARE_REG_KER
);
2503 EFX_SET_OWORD_FIELD(temp
, MEM_PERR_EN_TX_DATA
, 0);
2504 falcon_write(efx
, &temp
, SPARE_REG_KER
);
2507 /* Enable all the genuinely fatal interrupts. (They are still
2508 * masked by the overall interrupt mask, controlled by
2509 * falcon_interrupts()).
2511 * Note: All other fatal interrupts are enabled
2513 EFX_POPULATE_OWORD_3(temp
,
2514 ILL_ADR_INT_KER_EN
, 1,
2515 RBUF_OWN_INT_KER_EN
, 1,
2516 TBUF_OWN_INT_KER_EN
, 1);
2517 EFX_INVERT_OWORD(temp
);
2518 falcon_write(efx
, &temp
, FATAL_INTR_REG_KER
);
2520 /* Set number of RSS queues for receive path. */
2521 falcon_read(efx
, &temp
, RX_FILTER_CTL_REG
);
2522 if (falcon_rev(efx
) >= FALCON_REV_B0
)
2523 EFX_SET_OWORD_FIELD(temp
, NUM_KER
, 0);
2525 EFX_SET_OWORD_FIELD(temp
, NUM_KER
, efx
->rss_queues
- 1);
2526 if (EFX_WORKAROUND_7244(efx
)) {
2527 EFX_SET_OWORD_FIELD(temp
, UDP_FULL_SRCH_LIMIT
, 8);
2528 EFX_SET_OWORD_FIELD(temp
, UDP_WILD_SRCH_LIMIT
, 8);
2529 EFX_SET_OWORD_FIELD(temp
, TCP_FULL_SRCH_LIMIT
, 8);
2530 EFX_SET_OWORD_FIELD(temp
, TCP_WILD_SRCH_LIMIT
, 8);
2532 falcon_write(efx
, &temp
, RX_FILTER_CTL_REG
);
2534 falcon_setup_rss_indir_table(efx
);
2536 /* Setup RX. Wait for descriptor is broken and must
2537 * be disabled. RXDP recovery shouldn't be needed, but is.
2539 falcon_read(efx
, &temp
, RX_SELF_RST_REG_KER
);
2540 EFX_SET_OWORD_FIELD(temp
, RX_NODESC_WAIT_DIS
, 1);
2541 EFX_SET_OWORD_FIELD(temp
, RX_RECOVERY_EN
, 1);
2542 if (EFX_WORKAROUND_5583(efx
))
2543 EFX_SET_OWORD_FIELD(temp
, RX_ISCSI_DIS
, 1);
2544 falcon_write(efx
, &temp
, RX_SELF_RST_REG_KER
);
2546 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2547 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2549 falcon_read(efx
, &temp
, TX_CFG2_REG_KER
);
2550 EFX_SET_OWORD_FIELD(temp
, TX_RX_SPACER
, 0xfe);
2551 EFX_SET_OWORD_FIELD(temp
, TX_RX_SPACER_EN
, 1);
2552 EFX_SET_OWORD_FIELD(temp
, TX_ONE_PKT_PER_Q
, 1);
2553 EFX_SET_OWORD_FIELD(temp
, TX_CSR_PUSH_EN
, 0);
2554 EFX_SET_OWORD_FIELD(temp
, TX_DIS_NON_IP_EV
, 1);
2555 /* Enable SW_EV to inherit in char driver - assume harmless here */
2556 EFX_SET_OWORD_FIELD(temp
, TX_SW_EV_EN
, 1);
2557 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2558 EFX_SET_OWORD_FIELD(temp
, TX_PREF_THRESHOLD
, 2);
2559 /* Squash TX of packets of 16 bytes or less */
2560 if (falcon_rev(efx
) >= FALCON_REV_B0
&& EFX_WORKAROUND_9141(efx
))
2561 EFX_SET_OWORD_FIELD(temp
, TX_FLUSH_MIN_LEN_EN_B0
, 1);
2562 falcon_write(efx
, &temp
, TX_CFG2_REG_KER
);
2564 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2565 * descriptors (which is bad).
2567 falcon_read(efx
, &temp
, TX_CFG_REG_KER
);
2568 EFX_SET_OWORD_FIELD(temp
, TX_NO_EOP_DISC_EN
, 0);
2569 falcon_write(efx
, &temp
, TX_CFG_REG_KER
);
2572 falcon_read(efx
, &temp
, RX_CFG_REG_KER
);
2573 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_DESC_PUSH_EN
, 0);
2574 if (EFX_WORKAROUND_7575(efx
))
2575 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_USR_BUF_SIZE
,
2577 if (falcon_rev(efx
) >= FALCON_REV_B0
)
2578 EFX_SET_OWORD_FIELD(temp
, RX_INGR_EN_B0
, 1);
2580 /* RX FIFO flow control thresholds */
2581 thresh
= ((rx_xon_thresh_bytes
>= 0) ?
2582 rx_xon_thresh_bytes
: efx
->type
->rx_xon_thresh
);
2583 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XON_MAC_TH
, thresh
/ 256);
2584 thresh
= ((rx_xoff_thresh_bytes
>= 0) ?
2585 rx_xoff_thresh_bytes
: efx
->type
->rx_xoff_thresh
);
2586 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XOFF_MAC_TH
, thresh
/ 256);
2587 /* RX control FIFO thresholds [32 entries] */
2588 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XON_TX_TH
, 20);
2589 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XOFF_TX_TH
, 25);
2590 falcon_write(efx
, &temp
, RX_CFG_REG_KER
);
2592 /* Set destination of both TX and RX Flush events */
2593 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
2594 EFX_POPULATE_OWORD_1(temp
, FLS_EVQ_ID
, 0);
2595 falcon_write(efx
, &temp
, DP_CTRL_REG
);
2601 void falcon_remove_nic(struct efx_nic
*efx
)
2603 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2606 rc
= i2c_del_adapter(&efx
->i2c_adap
);
2609 falcon_free_buffer(efx
, &efx
->irq_status
);
2611 falcon_reset_hw(efx
, RESET_TYPE_ALL
);
2613 /* Release the second function after the reset */
2614 if (nic_data
->pci_dev2
) {
2615 pci_dev_put(nic_data
->pci_dev2
);
2616 nic_data
->pci_dev2
= NULL
;
2619 /* Tear down the private nic state */
2620 kfree(efx
->nic_data
);
2621 efx
->nic_data
= NULL
;
2624 void falcon_update_nic_stats(struct efx_nic
*efx
)
2628 falcon_read(efx
, &cnt
, RX_NODESC_DROP_REG_KER
);
2629 efx
->n_rx_nodesc_drop_cnt
+= EFX_OWORD_FIELD(cnt
, RX_NODESC_DROP_CNT
);
2632 /**************************************************************************
2634 * Revision-dependent attributes used by efx.c
2636 **************************************************************************
2639 struct efx_nic_type falcon_a_nic_type
= {
2641 .mem_map_size
= 0x20000,
2642 .txd_ptr_tbl_base
= TX_DESC_PTR_TBL_KER_A1
,
2643 .rxd_ptr_tbl_base
= RX_DESC_PTR_TBL_KER_A1
,
2644 .buf_tbl_base
= BUF_TBL_KER_A1
,
2645 .evq_ptr_tbl_base
= EVQ_PTR_TBL_KER_A1
,
2646 .evq_rptr_tbl_base
= EVQ_RPTR_REG_KER_A1
,
2647 .txd_ring_mask
= FALCON_TXD_RING_MASK
,
2648 .rxd_ring_mask
= FALCON_RXD_RING_MASK
,
2649 .evq_size
= FALCON_EVQ_SIZE
,
2650 .max_dma_mask
= FALCON_DMA_MASK
,
2651 .tx_dma_mask
= FALCON_TX_DMA_MASK
,
2652 .bug5391_mask
= 0xf,
2653 .rx_xoff_thresh
= 2048,
2654 .rx_xon_thresh
= 512,
2655 .rx_buffer_padding
= 0x24,
2656 .max_interrupt_mode
= EFX_INT_MODE_MSI
,
2657 .phys_addr_channels
= 4,
2660 struct efx_nic_type falcon_b_nic_type
= {
2662 /* Map everything up to and including the RSS indirection
2663 * table. Don't map MSI-X table, MSI-X PBA since Linux
2664 * requires that they not be mapped. */
2665 .mem_map_size
= RX_RSS_INDIR_TBL_B0
+ 0x800,
2666 .txd_ptr_tbl_base
= TX_DESC_PTR_TBL_KER_B0
,
2667 .rxd_ptr_tbl_base
= RX_DESC_PTR_TBL_KER_B0
,
2668 .buf_tbl_base
= BUF_TBL_KER_B0
,
2669 .evq_ptr_tbl_base
= EVQ_PTR_TBL_KER_B0
,
2670 .evq_rptr_tbl_base
= EVQ_RPTR_REG_KER_B0
,
2671 .txd_ring_mask
= FALCON_TXD_RING_MASK
,
2672 .rxd_ring_mask
= FALCON_RXD_RING_MASK
,
2673 .evq_size
= FALCON_EVQ_SIZE
,
2674 .max_dma_mask
= FALCON_DMA_MASK
,
2675 .tx_dma_mask
= FALCON_TX_DMA_MASK
,
2677 .rx_xoff_thresh
= 54272, /* ~80Kb - 3*max MTU */
2678 .rx_xon_thresh
= 27648, /* ~3*max MTU */
2679 .rx_buffer_padding
= 0,
2680 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
2681 .phys_addr_channels
= 32, /* Hardware limit is 64, but the legacy
2682 * interrupt handler only supports 32