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iwlwifi: unify init driver flow
[firewire-audio.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
blob93f4cdbae0ff8e48a063b7204973cfcec4330e1a
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/version.h>
30 #include <linux/init.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <net/mac80211.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40
41 #include "iwl-eeprom.h"
42 #include "iwl-4965.h"
43 #include "iwl-core.h"
44 #include "iwl-io.h"
45 #include "iwl-helpers.h"
46 #include "iwl-calib.h"
47
48 /* module parameters */
49 static struct iwl_mod_params iwl4965_mod_params = {
50 .num_of_queues = IWL49_NUM_QUEUES,
51 .enable_qos = 1,
52 .amsdu_size_8K = 1,
53 /* the rest are 0 by default */
54 };
55
56 static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
57
58 #ifdef CONFIG_IWL4965_HT
59
60 static const u16 default_tid_to_tx_fifo[] = {
61 IWL_TX_FIFO_AC1,
62 IWL_TX_FIFO_AC0,
63 IWL_TX_FIFO_AC0,
64 IWL_TX_FIFO_AC1,
65 IWL_TX_FIFO_AC2,
66 IWL_TX_FIFO_AC2,
67 IWL_TX_FIFO_AC3,
68 IWL_TX_FIFO_AC3,
69 IWL_TX_FIFO_NONE,
70 IWL_TX_FIFO_NONE,
71 IWL_TX_FIFO_NONE,
72 IWL_TX_FIFO_NONE,
73 IWL_TX_FIFO_NONE,
74 IWL_TX_FIFO_NONE,
75 IWL_TX_FIFO_NONE,
76 IWL_TX_FIFO_NONE,
77 IWL_TX_FIFO_AC3
78 };
79
80 #endif /*CONFIG_IWL4965_HT */
81
82 /* check contents of special bootstrap uCode SRAM */
83 static int iwl4965_verify_bsm(struct iwl_priv *priv)
84 {
85 __le32 *image = priv->ucode_boot.v_addr;
86 u32 len = priv->ucode_boot.len;
87 u32 reg;
88 u32 val;
89
90 IWL_DEBUG_INFO("Begin verify bsm\n");
91
92 /* verify BSM SRAM contents */
93 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
94 for (reg = BSM_SRAM_LOWER_BOUND;
95 reg < BSM_SRAM_LOWER_BOUND + len;
96 reg += sizeof(u32), image++) {
97 val = iwl_read_prph(priv, reg);
98 if (val != le32_to_cpu(*image)) {
99 IWL_ERROR("BSM uCode verification failed at "
100 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
101 BSM_SRAM_LOWER_BOUND,
102 reg - BSM_SRAM_LOWER_BOUND, len,
103 val, le32_to_cpu(*image));
104 return -EIO;
105 }
106 }
107
108 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
109
110 return 0;
111 }
112
113 /**
114 * iwl4965_load_bsm - Load bootstrap instructions
115 *
116 * BSM operation:
117 *
118 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
119 * in special SRAM that does not power down during RFKILL. When powering back
120 * up after power-saving sleeps (or during initial uCode load), the BSM loads
121 * the bootstrap program into the on-board processor, and starts it.
122 *
123 * The bootstrap program loads (via DMA) instructions and data for a new
124 * program from host DRAM locations indicated by the host driver in the
125 * BSM_DRAM_* registers. Once the new program is loaded, it starts
126 * automatically.
127 *
128 * When initializing the NIC, the host driver points the BSM to the
129 * "initialize" uCode image. This uCode sets up some internal data, then
130 * notifies host via "initialize alive" that it is complete.
131 *
132 * The host then replaces the BSM_DRAM_* pointer values to point to the
133 * normal runtime uCode instructions and a backup uCode data cache buffer
134 * (filled initially with starting data values for the on-board processor),
135 * then triggers the "initialize" uCode to load and launch the runtime uCode,
136 * which begins normal operation.
137 *
138 * When doing a power-save shutdown, runtime uCode saves data SRAM into
139 * the backup data cache in DRAM before SRAM is powered down.
140 *
141 * When powering back up, the BSM loads the bootstrap program. This reloads
142 * the runtime uCode instructions and the backup data cache into SRAM,
143 * and re-launches the runtime uCode from where it left off.
144 */
145 static int iwl4965_load_bsm(struct iwl_priv *priv)
146 {
147 __le32 *image = priv->ucode_boot.v_addr;
148 u32 len = priv->ucode_boot.len;
149 dma_addr_t pinst;
150 dma_addr_t pdata;
151 u32 inst_len;
152 u32 data_len;
153 int i;
154 u32 done;
155 u32 reg_offset;
156 int ret;
157
158 IWL_DEBUG_INFO("Begin load bsm\n");
159
160 /* make sure bootstrap program is no larger than BSM's SRAM size */
161 if (len > IWL_MAX_BSM_SIZE)
162 return -EINVAL;
163
164 /* Tell bootstrap uCode where to find the "Initialize" uCode
165 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
166 * NOTE: iwl4965_initialize_alive_start() will replace these values,
167 * after the "initialize" uCode has run, to point to
168 * runtime/protocol instructions and backup data cache. */
169 pinst = priv->ucode_init.p_addr >> 4;
170 pdata = priv->ucode_init_data.p_addr >> 4;
171 inst_len = priv->ucode_init.len;
172 data_len = priv->ucode_init_data.len;
173
174 ret = iwl_grab_nic_access(priv);
175 if (ret)
176 return ret;
177
178 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
179 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
180 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
181 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
182
183 /* Fill BSM memory with bootstrap instructions */
184 for (reg_offset = BSM_SRAM_LOWER_BOUND;
185 reg_offset < BSM_SRAM_LOWER_BOUND + len;
186 reg_offset += sizeof(u32), image++)
187 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
188
189 ret = iwl4965_verify_bsm(priv);
190 if (ret) {
191 iwl_release_nic_access(priv);
192 return ret;
193 }
194
195 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
196 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
197 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
198 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
199
200 /* Load bootstrap code into instruction SRAM now,
201 * to prepare to load "initialize" uCode */
202 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
203
204 /* Wait for load of bootstrap uCode to finish */
205 for (i = 0; i < 100; i++) {
206 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
207 if (!(done & BSM_WR_CTRL_REG_BIT_START))
208 break;
209 udelay(10);
210 }
211 if (i < 100)
212 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
213 else {
214 IWL_ERROR("BSM write did not complete!\n");
215 return -EIO;
216 }
217
218 /* Enable future boot loads whenever power management unit triggers it
219 * (e.g. when powering back up after power-save shutdown) */
220 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
221
222 iwl_release_nic_access(priv);
223
224 return 0;
225 }
226
227 static int is_fat_channel(__le32 rxon_flags)
228 {
229 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
230 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
231 }
232
233 int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
234 {
235 int idx = 0;
236
237 /* 4965 HT rate format */
238 if (rate_n_flags & RATE_MCS_HT_MSK) {
239 idx = (rate_n_flags & 0xff);
240
241 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
242 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
243
244 idx += IWL_FIRST_OFDM_RATE;
245 /* skip 9M not supported in ht*/
246 if (idx >= IWL_RATE_9M_INDEX)
247 idx += 1;
248 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
249 return idx;
250
251 /* 4965 legacy rate format, search for match in table */
252 } else {
253 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
254 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
255 return idx;
256 }
257
258 return -1;
259 }
260
261 /**
262 * translate ucode response to mac80211 tx status control values
263 */
264 void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
265 struct ieee80211_tx_control *control)
266 {
267 int rate_index;
268
269 control->antenna_sel_tx =
270 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
271 if (rate_n_flags & RATE_MCS_HT_MSK)
272 control->flags |= IEEE80211_TXCTL_OFDM_HT;
273 if (rate_n_flags & RATE_MCS_GF_MSK)
274 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
275 if (rate_n_flags & RATE_MCS_FAT_MSK)
276 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
277 if (rate_n_flags & RATE_MCS_DUP_MSK)
278 control->flags |= IEEE80211_TXCTL_DUP_DATA;
279 if (rate_n_flags & RATE_MCS_SGI_MSK)
280 control->flags |= IEEE80211_TXCTL_SHORT_GI;
281 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
282 * IEEE80211_BAND_2GHZ band as it contains all the rates */
283 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
284 if (rate_index == -1)
285 control->tx_rate = NULL;
286 else
287 control->tx_rate =
288 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
289 }
290
291 int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
292 {
293 int rc;
294 unsigned long flags;
295
296 spin_lock_irqsave(&priv->lock, flags);
297 rc = iwl_grab_nic_access(priv);
298 if (rc) {
299 spin_unlock_irqrestore(&priv->lock, flags);
300 return rc;
301 }
302
303 /* stop Rx DMA */
304 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
305 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
306 (1 << 24), 1000);
307 if (rc < 0)
308 IWL_ERROR("Can't stop Rx DMA.\n");
309
310 iwl_release_nic_access(priv);
311 spin_unlock_irqrestore(&priv->lock, flags);
312
313 return 0;
314 }
315
316 /*
317 * EEPROM handlers
318 */
319
320 static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
321 {
322 u16 eeprom_ver;
323 u16 calib_ver;
324
325 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
326
327 calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
328
329 if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
330 calib_ver < EEPROM_4965_TX_POWER_VERSION)
331 goto err;
332
333 return 0;
334 err:
335 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
336 eeprom_ver, EEPROM_4965_EEPROM_VERSION,
337 calib_ver, EEPROM_4965_TX_POWER_VERSION);
338 return -EINVAL;
339
340 }
341 int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
342 {
343 int ret;
344 unsigned long flags;
345
346 spin_lock_irqsave(&priv->lock, flags);
347 ret = iwl_grab_nic_access(priv);
348 if (ret) {
349 spin_unlock_irqrestore(&priv->lock, flags);
350 return ret;
351 }
352
353 if (src == IWL_PWR_SRC_VAUX) {
354 u32 val;
355 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
356 &val);
357
358 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
359 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
360 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
361 ~APMG_PS_CTRL_MSK_PWR_SRC);
362 }
363 } else {
364 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
365 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
366 ~APMG_PS_CTRL_MSK_PWR_SRC);
367 }
368
369 iwl_release_nic_access(priv);
370 spin_unlock_irqrestore(&priv->lock, flags);
371
372 return ret;
373 }
374
375 static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
376 {
377 int ret;
378 unsigned long flags;
379 unsigned int rb_size;
380
381 spin_lock_irqsave(&priv->lock, flags);
382 ret = iwl_grab_nic_access(priv);
383 if (ret) {
384 spin_unlock_irqrestore(&priv->lock, flags);
385 return ret;
386 }
387
388 if (priv->cfg->mod_params->amsdu_size_8K)
389 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
390 else
391 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
392
393 /* Stop Rx DMA */
394 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
395
396 /* Reset driver's Rx queue write index */
397 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
398
399 /* Tell device where to find RBD circular buffer in DRAM */
400 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
401 rxq->dma_addr >> 8);
402
403 /* Tell device where in DRAM to update its Rx status */
404 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
405 (priv->shared_phys +
406 offsetof(struct iwl4965_shared, rb_closed)) >> 4);
407
408 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
409 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
410 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
411 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
412 rb_size |
413 /* 0x10 << 4 | */
414 (RX_QUEUE_SIZE_LOG <<
415 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
416
417 /*
418 * iwl_write32(priv,CSR_INT_COAL_REG,0);
419 */
420
421 iwl_release_nic_access(priv);
422 spin_unlock_irqrestore(&priv->lock, flags);
423
424 return 0;
425 }
426
427 /* Tell 4965 where to find the "keep warm" buffer */
428 static int iwl4965_kw_init(struct iwl_priv *priv)
429 {
430 unsigned long flags;
431 int rc;
432
433 spin_lock_irqsave(&priv->lock, flags);
434 rc = iwl_grab_nic_access(priv);
435 if (rc)
436 goto out;
437
438 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
439 priv->kw.dma_addr >> 4);
440 iwl_release_nic_access(priv);
441 out:
442 spin_unlock_irqrestore(&priv->lock, flags);
443 return rc;
444 }
445
446 static int iwl4965_kw_alloc(struct iwl_priv *priv)
447 {
448 struct pci_dev *dev = priv->pci_dev;
449 struct iwl4965_kw *kw = &priv->kw;
450
451 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
452 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
453 if (!kw->v_addr)
454 return -ENOMEM;
455
456 return 0;
457 }
458
459 /**
460 * iwl4965_kw_free - Free the "keep warm" buffer
461 */
462 static void iwl4965_kw_free(struct iwl_priv *priv)
463 {
464 struct pci_dev *dev = priv->pci_dev;
465 struct iwl4965_kw *kw = &priv->kw;
466
467 if (kw->v_addr) {
468 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
469 memset(kw, 0, sizeof(*kw));
470 }
471 }
472
473 /**
474 * iwl4965_txq_ctx_reset - Reset TX queue context
475 * Destroys all DMA structures and initialise them again
476 *
477 * @param priv
478 * @return error code
479 */
480 static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
481 {
482 int rc = 0;
483 int txq_id, slots_num;
484 unsigned long flags;
485
486 iwl4965_kw_free(priv);
487
488 /* Free all tx/cmd queues and keep-warm buffer */
489 iwl4965_hw_txq_ctx_free(priv);
490
491 /* Alloc keep-warm buffer */
492 rc = iwl4965_kw_alloc(priv);
493 if (rc) {
494 IWL_ERROR("Keep Warm allocation failed");
495 goto error_kw;
496 }
497
498 spin_lock_irqsave(&priv->lock, flags);
499
500 rc = iwl_grab_nic_access(priv);
501 if (unlikely(rc)) {
502 IWL_ERROR("TX reset failed");
503 spin_unlock_irqrestore(&priv->lock, flags);
504 goto error_reset;
505 }
506
507 /* Turn off all Tx DMA channels */
508 iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
509 iwl_release_nic_access(priv);
510 spin_unlock_irqrestore(&priv->lock, flags);
511
512 /* Tell 4965 where to find the keep-warm buffer */
513 rc = iwl4965_kw_init(priv);
514 if (rc) {
515 IWL_ERROR("kw_init failed\n");
516 goto error_reset;
517 }
518
519 /* Alloc and init all (default 16) Tx queues,
520 * including the command queue (#4) */
521 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
522 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
523 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
524 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
525 txq_id);
526 if (rc) {
527 IWL_ERROR("Tx %d queue init failed\n", txq_id);
528 goto error;
529 }
530 }
531
532 return rc;
533
534 error:
535 iwl4965_hw_txq_ctx_free(priv);
536 error_reset:
537 iwl4965_kw_free(priv);
538 error_kw:
539 return rc;
540 }
541 static int iwl4965_apm_init(struct iwl_priv *priv)
542 {
543 unsigned long flags;
544 int ret = 0;
545
546 spin_lock_irqsave(&priv->lock, flags);
547 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
548 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
549
550 /* set "initialization complete" bit to move adapter
551 * D0U* --> D0A* state */
552 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
553
554 /* wait for clock stabilization */
555 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
556 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
557 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
558 if (ret < 0) {
559 IWL_DEBUG_INFO("Failed to init the card\n");
560 goto out;
561 }
562
563 ret = iwl_grab_nic_access(priv);
564 if (ret)
565 goto out;
566
567 /* enable DMA */
568 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
569 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
570
571 udelay(20);
572
573 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
574 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
575
576 iwl_release_nic_access(priv);
577 out:
578 spin_unlock_irqrestore(&priv->lock, flags);
579 return ret;
580 }
581
582 int iwl4965_hw_nic_init(struct iwl_priv *priv)
583 {
584 unsigned long flags;
585 struct iwl4965_rx_queue *rxq = &priv->rxq;
586 u8 val_link;
587 u32 val;
588 int ret;
589
590 /* nic_init */
591 priv->cfg->ops->lib->apm_ops.init(priv);
592
593 spin_lock_irqsave(&priv->lock, flags);
594 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
595 spin_unlock_irqrestore(&priv->lock, flags);
596
597 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
598
599 spin_lock_irqsave(&priv->lock, flags);
600
601 if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
602 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
603 /* Enable No Snoop field */
604 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
605 val & ~(1 << 11));
606 }
607
608 spin_unlock_irqrestore(&priv->lock, flags);
609
610 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
611
612 /* disable L1 entry -- workaround for pre-B1 */
613 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
614
615 spin_lock_irqsave(&priv->lock, flags);
616
617 /* set CSR_HW_CONFIG_REG for uCode use */
618
619 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
620 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
621 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
622 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
623
624 ret = iwl_grab_nic_access(priv);
625 if (ret < 0) {
626 spin_unlock_irqrestore(&priv->lock, flags);
627 IWL_DEBUG_INFO("Failed to init the card\n");
628 return ret;
629 }
630
631 iwl_read_prph(priv, APMG_PS_CTRL_REG);
632 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
633 udelay(5);
634 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
635
636 iwl_release_nic_access(priv);
637 spin_unlock_irqrestore(&priv->lock, flags);
638
639 iwl4965_hw_card_show_info(priv);
640
641 /* end nic_init */
642
643 /* Allocate the RX queue, or reset if it is already allocated */
644 if (!rxq->bd) {
645 ret = iwl4965_rx_queue_alloc(priv);
646 if (ret) {
647 IWL_ERROR("Unable to initialize Rx queue\n");
648 return -ENOMEM;
649 }
650 } else
651 iwl4965_rx_queue_reset(priv, rxq);
652
653 iwl4965_rx_replenish(priv);
654
655 iwl4965_rx_init(priv, rxq);
656
657 spin_lock_irqsave(&priv->lock, flags);
658
659 rxq->need_update = 1;
660 iwl4965_rx_queue_update_write_ptr(priv, rxq);
661
662 /* init the txpower calibration pointer */
663 priv->calib_info = (struct iwl_eeprom_calib_info *)
664 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
665
666 spin_unlock_irqrestore(&priv->lock, flags);
667
668 /* Allocate and init all Tx and Command queues */
669 ret = iwl4965_txq_ctx_reset(priv);
670 if (ret)
671 return ret;
672
673 set_bit(STATUS_INIT, &priv->status);
674
675 return 0;
676 }
677
678 int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
679 {
680 int rc = 0;
681 u32 reg_val;
682 unsigned long flags;
683
684 spin_lock_irqsave(&priv->lock, flags);
685
686 /* set stop master bit */
687 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
688
689 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
690
691 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
692 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
693 IWL_DEBUG_INFO("Card in power save, master is already "
694 "stopped\n");
695 else {
696 rc = iwl_poll_bit(priv, CSR_RESET,
697 CSR_RESET_REG_FLAG_MASTER_DISABLED,
698 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
699 if (rc < 0) {
700 spin_unlock_irqrestore(&priv->lock, flags);
701 return rc;
702 }
703 }
704
705 spin_unlock_irqrestore(&priv->lock, flags);
706 IWL_DEBUG_INFO("stop master\n");
707
708 return rc;
709 }
710
711 /**
712 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
713 */
714 void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
715 {
716
717 int txq_id;
718 unsigned long flags;
719
720 /* Stop each Tx DMA channel, and wait for it to be idle */
721 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
722 spin_lock_irqsave(&priv->lock, flags);
723 if (iwl_grab_nic_access(priv)) {
724 spin_unlock_irqrestore(&priv->lock, flags);
725 continue;
726 }
727
728 iwl_write_direct32(priv,
729 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
730 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
731 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
732 (txq_id), 200);
733 iwl_release_nic_access(priv);
734 spin_unlock_irqrestore(&priv->lock, flags);
735 }
736
737 /* Deallocate memory for all Tx queues */
738 iwl4965_hw_txq_ctx_free(priv);
739 }
740
741 int iwl4965_hw_nic_reset(struct iwl_priv *priv)
742 {
743 int rc = 0;
744 unsigned long flags;
745
746 iwl4965_hw_nic_stop_master(priv);
747
748 spin_lock_irqsave(&priv->lock, flags);
749
750 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
751
752 udelay(10);
753
754 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
755 rc = iwl_poll_bit(priv, CSR_RESET,
756 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
757 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
758
759 udelay(10);
760
761 rc = iwl_grab_nic_access(priv);
762 if (!rc) {
763 iwl_write_prph(priv, APMG_CLK_EN_REG,
764 APMG_CLK_VAL_DMA_CLK_RQT |
765 APMG_CLK_VAL_BSM_CLK_RQT);
766
767 udelay(10);
768
769 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
770 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
771
772 iwl_release_nic_access(priv);
773 }
774
775 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
776 wake_up_interruptible(&priv->wait_command_queue);
777
778 spin_unlock_irqrestore(&priv->lock, flags);
779
780 return rc;
781
782 }
783
784 #define REG_RECALIB_PERIOD (60)
785
786 /**
787 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
788 *
789 * This callback is provided in order to send a statistics request.
790 *
791 * This timer function is continually reset to execute within
792 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
793 * was received. We need to ensure we receive the statistics in order
794 * to update the temperature used for calibrating the TXPOWER.
795 */
796 static void iwl4965_bg_statistics_periodic(unsigned long data)
797 {
798 struct iwl_priv *priv = (struct iwl_priv *)data;
799
800 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
801 return;
802
803 iwl_send_statistics_request(priv, CMD_ASYNC);
804 }
805
806 void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
807 {
808 struct iwl4965_ct_kill_config cmd;
809 unsigned long flags;
810 int ret = 0;
811
812 spin_lock_irqsave(&priv->lock, flags);
813 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
814 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
815 spin_unlock_irqrestore(&priv->lock, flags);
816
817 cmd.critical_temperature_R =
818 cpu_to_le32(priv->hw_params.ct_kill_threshold);
819
820 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
821 sizeof(cmd), &cmd);
822 if (ret)
823 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
824 else
825 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
826 "critical temperature is %d\n",
827 cmd.critical_temperature_R);
828 }
829
830 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
831
832 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
833 * Called after every association, but this runs only once!
834 * ... once chain noise is calibrated the first time, it's good forever. */
835 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
836 {
837 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
838
839 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
840 struct iwl4965_calibration_cmd cmd;
841
842 memset(&cmd, 0, sizeof(cmd));
843 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
844 cmd.diff_gain_a = 0;
845 cmd.diff_gain_b = 0;
846 cmd.diff_gain_c = 0;
847 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
848 sizeof(cmd), &cmd))
849 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
850 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
851 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
852 }
853 }
854
855 static void iwl4965_gain_computation(struct iwl_priv *priv,
856 u32 *average_noise,
857 u16 min_average_noise_antenna_i,
858 u32 min_average_noise)
859 {
860 int i, ret;
861 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
862
863 data->delta_gain_code[min_average_noise_antenna_i] = 0;
864
865 for (i = 0; i < NUM_RX_CHAINS; i++) {
866 s32 delta_g = 0;
867
868 if (!(data->disconn_array[i]) &&
869 (data->delta_gain_code[i] ==
870 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
871 delta_g = average_noise[i] - min_average_noise;
872 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
873 data->delta_gain_code[i] =
874 min(data->delta_gain_code[i],
875 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
876
877 data->delta_gain_code[i] =
878 (data->delta_gain_code[i] | (1 << 2));
879 } else {
880 data->delta_gain_code[i] = 0;
881 }
882 }
883 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
884 data->delta_gain_code[0],
885 data->delta_gain_code[1],
886 data->delta_gain_code[2]);
887
888 /* Differential gain gets sent to uCode only once */
889 if (!data->radio_write) {
890 struct iwl4965_calibration_cmd cmd;
891 data->radio_write = 1;
892
893 memset(&cmd, 0, sizeof(cmd));
894 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
895 cmd.diff_gain_a = data->delta_gain_code[0];
896 cmd.diff_gain_b = data->delta_gain_code[1];
897 cmd.diff_gain_c = data->delta_gain_code[2];
898 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
899 sizeof(cmd), &cmd);
900 if (ret)
901 IWL_DEBUG_CALIB("fail sending cmd "
902 "REPLY_PHY_CALIBRATION_CMD \n");
903
904 /* TODO we might want recalculate
905 * rx_chain in rxon cmd */
906
907 /* Mark so we run this algo only once! */
908 data->state = IWL_CHAIN_NOISE_CALIBRATED;
909 }
910 data->chain_noise_a = 0;
911 data->chain_noise_b = 0;
912 data->chain_noise_c = 0;
913 data->chain_signal_a = 0;
914 data->chain_signal_b = 0;
915 data->chain_signal_c = 0;
916 data->beacon_count = 0;
917 }
918
919 static void iwl4965_bg_sensitivity_work(struct work_struct *work)
920 {
921 struct iwl_priv *priv = container_of(work, struct iwl_priv,
922 sensitivity_work);
923
924 mutex_lock(&priv->mutex);
925
926 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
927 test_bit(STATUS_SCANNING, &priv->status)) {
928 mutex_unlock(&priv->mutex);
929 return;
930 }
931
932 if (priv->start_calib) {
933 iwl_chain_noise_calibration(priv, &priv->statistics);
934
935 iwl_sensitivity_calibration(priv, &priv->statistics);
936 }
937
938 mutex_unlock(&priv->mutex);
939 return;
940 }
941 #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
942
943 static void iwl4965_bg_txpower_work(struct work_struct *work)
944 {
945 struct iwl_priv *priv = container_of(work, struct iwl_priv,
946 txpower_work);
947
948 /* If a scan happened to start before we got here
949 * then just return; the statistics notification will
950 * kick off another scheduled work to compensate for
951 * any temperature delta we missed here. */
952 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
953 test_bit(STATUS_SCANNING, &priv->status))
954 return;
955
956 mutex_lock(&priv->mutex);
957
958 /* Regardless of if we are assocaited, we must reconfigure the
959 * TX power since frames can be sent on non-radar channels while
960 * not associated */
961 iwl4965_hw_reg_send_txpower(priv);
962
963 /* Update last_temperature to keep is_calib_needed from running
964 * when it isn't needed... */
965 priv->last_temperature = priv->temperature;
966
967 mutex_unlock(&priv->mutex);
968 }
969
970 /*
971 * Acquire priv->lock before calling this function !
972 */
973 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
974 {
975 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
976 (index & 0xff) | (txq_id << 8));
977 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
978 }
979
980 /**
981 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
982 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
983 * @scd_retry: (1) Indicates queue will be used in aggregation mode
984 *
985 * NOTE: Acquire priv->lock before calling this function !
986 */
987 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
988 struct iwl4965_tx_queue *txq,
989 int tx_fifo_id, int scd_retry)
990 {
991 int txq_id = txq->q.id;
992
993 /* Find out whether to activate Tx queue */
994 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
995
996 /* Set up and activate */
997 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
998 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
999 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
1000 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
1001 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1002 IWL49_SCD_QUEUE_STTS_REG_MSK);
1003
1004 txq->sched_retry = scd_retry;
1005
1006 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
1007 active ? "Activate" : "Deactivate",
1008 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1009 }
1010
1011 static const u16 default_queue_to_tx_fifo[] = {
1012 IWL_TX_FIFO_AC3,
1013 IWL_TX_FIFO_AC2,
1014 IWL_TX_FIFO_AC1,
1015 IWL_TX_FIFO_AC0,
1016 IWL49_CMD_FIFO_NUM,
1017 IWL_TX_FIFO_HCCA_1,
1018 IWL_TX_FIFO_HCCA_2
1019 };
1020
1021 static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1022 {
1023 set_bit(txq_id, &priv->txq_ctx_active_msk);
1024 }
1025
1026 static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1027 {
1028 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1029 }
1030
1031 int iwl4965_alive_notify(struct iwl_priv *priv)
1032 {
1033 u32 a;
1034 int i = 0;
1035 unsigned long flags;
1036 int ret;
1037
1038 spin_lock_irqsave(&priv->lock, flags);
1039
1040 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1041 memset(&(priv->sensitivity_data), 0,
1042 sizeof(struct iwl_sensitivity_data));
1043 memset(&(priv->chain_noise_data), 0,
1044 sizeof(struct iwl_chain_noise_data));
1045 for (i = 0; i < NUM_RX_CHAINS; i++)
1046 priv->chain_noise_data.delta_gain_code[i] =
1047 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
1048 #endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
1049 ret = iwl_grab_nic_access(priv);
1050 if (ret) {
1051 spin_unlock_irqrestore(&priv->lock, flags);
1052 return ret;
1053 }
1054
1055 /* Clear 4965's internal Tx Scheduler data base */
1056 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
1057 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
1058 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
1059 iwl_write_targ_mem(priv, a, 0);
1060 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
1061 iwl_write_targ_mem(priv, a, 0);
1062 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
1063 iwl_write_targ_mem(priv, a, 0);
1064
1065 /* Tel 4965 where to find Tx byte count tables */
1066 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
1067 (priv->shared_phys +
1068 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
1069
1070 /* Disable chain mode for all queues */
1071 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
1072
1073 /* Initialize each Tx queue (including the command queue) */
1074 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
1075
1076 /* TFD circular buffer read/write indexes */
1077 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
1078 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
1079
1080 /* Max Tx Window size for Scheduler-ACK mode */
1081 iwl_write_targ_mem(priv, priv->scd_base_addr +
1082 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
1083 (SCD_WIN_SIZE <<
1084 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1085 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1086
1087 /* Frame limit */
1088 iwl_write_targ_mem(priv, priv->scd_base_addr +
1089 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
1090 sizeof(u32),
1091 (SCD_FRAME_LIMIT <<
1092 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1093 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1094
1095 }
1096 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
1097 (1 << priv->hw_params.max_txq_num) - 1);
1098
1099 /* Activate all Tx DMA/FIFO channels */
1100 iwl_write_prph(priv, IWL49_SCD_TXFACT,
1101 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1102
1103 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
1104
1105 /* Map each Tx/cmd queue to its corresponding fifo */
1106 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1107 int ac = default_queue_to_tx_fifo[i];
1108 iwl4965_txq_ctx_activate(priv, i);
1109 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1110 }
1111
1112 iwl_release_nic_access(priv);
1113 spin_unlock_irqrestore(&priv->lock, flags);
1114
1115 /* Ask for statistics now, the uCode will send statistics notification
1116 * periodically after association */
1117 iwl_send_statistics_request(priv, CMD_ASYNC);
1118 return ret;
1119 }
1120
1121 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1122 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
1123 .min_nrg_cck = 97,
1124 .max_nrg_cck = 0,
1125
1126 .auto_corr_min_ofdm = 85,
1127 .auto_corr_min_ofdm_mrc = 170,
1128 .auto_corr_min_ofdm_x1 = 105,
1129 .auto_corr_min_ofdm_mrc_x1 = 220,
1130
1131 .auto_corr_max_ofdm = 120,
1132 .auto_corr_max_ofdm_mrc = 210,
1133 .auto_corr_max_ofdm_x1 = 140,
1134 .auto_corr_max_ofdm_mrc_x1 = 270,
1135
1136 .auto_corr_min_cck = 125,
1137 .auto_corr_max_cck = 200,
1138 .auto_corr_min_cck_mrc = 200,
1139 .auto_corr_max_cck_mrc = 400,
1140
1141 .nrg_th_cck = 100,
1142 .nrg_th_ofdm = 100,
1143 };
1144 #endif
1145
1146 /**
1147 * iwl4965_hw_set_hw_params
1148 *
1149 * Called when initializing driver
1150 */
1151 int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
1152 {
1153
1154 if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
1155 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
1156 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
1157 IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
1158 return -EINVAL;
1159 }
1160
1161 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
1162 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
1163 priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
1164 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1165 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1166 if (priv->cfg->mod_params->amsdu_size_8K)
1167 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1168 else
1169 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1170 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1171 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
1172 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
1173
1174 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
1175 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
1176 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
1177 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
1178
1179 priv->hw_params.tx_chains_num = 2;
1180 priv->hw_params.rx_chains_num = 2;
1181 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
1182 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
1183 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
1184
1185 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1186 priv->hw_params.sens = &iwl4965_sensitivity;
1187 #endif
1188
1189 return 0;
1190 }
1191
1192 /**
1193 * iwl4965_hw_txq_ctx_free - Free TXQ Context
1194 *
1195 * Destroy all TX DMA queues and structures
1196 */
1197 void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
1198 {
1199 int txq_id;
1200
1201 /* Tx queues */
1202 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1203 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
1204
1205 /* Keep-warm buffer */
1206 iwl4965_kw_free(priv);
1207 }
1208
1209 /**
1210 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
1211 *
1212 * Does NOT advance any TFD circular buffer read/write indexes
1213 * Does NOT free the TFD itself (which is within circular buffer)
1214 */
1215 int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
1216 {
1217 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1218 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
1219 struct pci_dev *dev = priv->pci_dev;
1220 int i;
1221 int counter = 0;
1222 int index, is_odd;
1223
1224 /* Host command buffers stay mapped in memory, nothing to clean */
1225 if (txq->q.id == IWL_CMD_QUEUE_NUM)
1226 return 0;
1227
1228 /* Sanity check on number of chunks */
1229 counter = IWL_GET_BITS(*bd, num_tbs);
1230 if (counter > MAX_NUM_OF_TBS) {
1231 IWL_ERROR("Too many chunks: %i\n", counter);
1232 /* @todo issue fatal error, it is quite serious situation */
1233 return 0;
1234 }
1235
1236 /* Unmap chunks, if any.
1237 * TFD info for odd chunks is different format than for even chunks. */
1238 for (i = 0; i < counter; i++) {
1239 index = i / 2;
1240 is_odd = i & 0x1;
1241
1242 if (is_odd)
1243 pci_unmap_single(
1244 dev,
1245 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1246 (IWL_GET_BITS(bd->pa[index],
1247 tb2_addr_hi20) << 16),
1248 IWL_GET_BITS(bd->pa[index], tb2_len),
1249 PCI_DMA_TODEVICE);
1250
1251 else if (i > 0)
1252 pci_unmap_single(dev,
1253 le32_to_cpu(bd->pa[index].tb1_addr),
1254 IWL_GET_BITS(bd->pa[index], tb1_len),
1255 PCI_DMA_TODEVICE);
1256
1257 /* Free SKB, if any, for this chunk */
1258 if (txq->txb[txq->q.read_ptr].skb[i]) {
1259 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
1260
1261 dev_kfree_skb(skb);
1262 txq->txb[txq->q.read_ptr].skb[i] = NULL;
1263 }
1264 }
1265 return 0;
1266 }
1267
1268 /* set card power command */
1269 static int iwl4965_set_power(struct iwl_priv *priv,
1270 void *cmd)
1271 {
1272 int ret = 0;
1273
1274 ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
1275 sizeof(struct iwl4965_powertable_cmd),
1276 cmd, NULL);
1277 return ret;
1278 }
1279 int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1280 {
1281 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
1282 return -EINVAL;
1283 }
1284
1285 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1286 {
1287 s32 sign = 1;
1288
1289 if (num < 0) {
1290 sign = -sign;
1291 num = -num;
1292 }
1293 if (denom < 0) {
1294 sign = -sign;
1295 denom = -denom;
1296 }
1297 *res = 1;
1298 *res = ((num * 2 + denom) / (denom * 2)) * sign;
1299
1300 return 1;
1301 }
1302
1303 /**
1304 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1305 *
1306 * Determines power supply voltage compensation for txpower calculations.
1307 * Returns number of 1/2-dB steps to subtract from gain table index,
1308 * to compensate for difference between power supply voltage during
1309 * factory measurements, vs. current power supply voltage.
1310 *
1311 * Voltage indication is higher for lower voltage.
1312 * Lower voltage requires more gain (lower gain table index).
1313 */
1314 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1315 s32 current_voltage)
1316 {
1317 s32 comp = 0;
1318
1319 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1320 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1321 return 0;
1322
1323 iwl4965_math_div_round(current_voltage - eeprom_voltage,
1324 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1325
1326 if (current_voltage > eeprom_voltage)
1327 comp *= 2;
1328 if ((comp < -2) || (comp > 2))
1329 comp = 0;
1330
1331 return comp;
1332 }
1333
1334 static const struct iwl_channel_info *
1335 iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
1336 enum ieee80211_band band, u16 channel)
1337 {
1338 const struct iwl_channel_info *ch_info;
1339
1340 ch_info = iwl_get_channel_info(priv, band, channel);
1341
1342 if (!is_channel_valid(ch_info))
1343 return NULL;
1344
1345 return ch_info;
1346 }
1347
1348 static s32 iwl4965_get_tx_atten_grp(u16 channel)
1349 {
1350 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1351 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1352 return CALIB_CH_GROUP_5;
1353
1354 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1355 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1356 return CALIB_CH_GROUP_1;
1357
1358 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1359 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1360 return CALIB_CH_GROUP_2;
1361
1362 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1363 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1364 return CALIB_CH_GROUP_3;
1365
1366 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1367 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1368 return CALIB_CH_GROUP_4;
1369
1370 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1371 return -1;
1372 }
1373
1374 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
1375 {
1376 s32 b = -1;
1377
1378 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
1379 if (priv->calib_info->band_info[b].ch_from == 0)
1380 continue;
1381
1382 if ((channel >= priv->calib_info->band_info[b].ch_from)
1383 && (channel <= priv->calib_info->band_info[b].ch_to))
1384 break;
1385 }
1386
1387 return b;
1388 }
1389
1390 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1391 {
1392 s32 val;
1393
1394 if (x2 == x1)
1395 return y1;
1396 else {
1397 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
1398 return val + y2;
1399 }
1400 }
1401
1402 /**
1403 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
1404 *
1405 * Interpolates factory measurements from the two sample channels within a
1406 * sub-band, to apply to channel of interest. Interpolation is proportional to
1407 * differences in channel frequencies, which is proportional to differences
1408 * in channel number.
1409 */
1410 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
1411 struct iwl_eeprom_calib_ch_info *chan_info)
1412 {
1413 s32 s = -1;
1414 u32 c;
1415 u32 m;
1416 const struct iwl_eeprom_calib_measure *m1;
1417 const struct iwl_eeprom_calib_measure *m2;
1418 struct iwl_eeprom_calib_measure *omeas;
1419 u32 ch_i1;
1420 u32 ch_i2;
1421
1422 s = iwl4965_get_sub_band(priv, channel);
1423 if (s >= EEPROM_TX_POWER_BANDS) {
1424 IWL_ERROR("Tx Power can not find channel %d ", channel);
1425 return -1;
1426 }
1427
1428 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
1429 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
1430 chan_info->ch_num = (u8) channel;
1431
1432 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1433 channel, s, ch_i1, ch_i2);
1434
1435 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1436 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
1437 m1 = &(priv->calib_info->band_info[s].ch1.
1438 measurements[c][m]);
1439 m2 = &(priv->calib_info->band_info[s].ch2.
1440 measurements[c][m]);
1441 omeas = &(chan_info->measurements[c][m]);
1442
1443 omeas->actual_pow =
1444 (u8) iwl4965_interpolate_value(channel, ch_i1,
1445 m1->actual_pow,
1446 ch_i2,
1447 m2->actual_pow);
1448 omeas->gain_idx =
1449 (u8) iwl4965_interpolate_value(channel, ch_i1,
1450 m1->gain_idx, ch_i2,
1451 m2->gain_idx);
1452 omeas->temperature =
1453 (u8) iwl4965_interpolate_value(channel, ch_i1,
1454 m1->temperature,
1455 ch_i2,
1456 m2->temperature);
1457 omeas->pa_det =
1458 (s8) iwl4965_interpolate_value(channel, ch_i1,
1459 m1->pa_det, ch_i2,
1460 m2->pa_det);
1461
1462 IWL_DEBUG_TXPOWER
1463 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1464 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1465 IWL_DEBUG_TXPOWER
1466 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1467 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1468 IWL_DEBUG_TXPOWER
1469 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1470 m1->pa_det, m2->pa_det, omeas->pa_det);
1471 IWL_DEBUG_TXPOWER
1472 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1473 m1->temperature, m2->temperature,
1474 omeas->temperature);
1475 }
1476 }
1477
1478 return 0;
1479 }
1480
1481 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1482 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1483 static s32 back_off_table[] = {
1484 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1485 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1486 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1487 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1488 10 /* CCK */
1489 };
1490
1491 /* Thermal compensation values for txpower for various frequency ranges ...
1492 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
1493 static struct iwl4965_txpower_comp_entry {
1494 s32 degrees_per_05db_a;
1495 s32 degrees_per_05db_a_denom;
1496 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1497 {9, 2}, /* group 0 5.2, ch 34-43 */
1498 {4, 1}, /* group 1 5.2, ch 44-70 */
1499 {4, 1}, /* group 2 5.2, ch 71-124 */
1500 {4, 1}, /* group 3 5.2, ch 125-200 */
1501 {3, 1} /* group 4 2.4, ch all */
1502 };
1503
1504 static s32 get_min_power_index(s32 rate_power_index, u32 band)
1505 {
1506 if (!band) {
1507 if ((rate_power_index & 7) <= 4)
1508 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1509 }
1510 return MIN_TX_GAIN_INDEX;
1511 }
1512
1513 struct gain_entry {
1514 u8 dsp;
1515 u8 radio;
1516 };
1517
1518 static const struct gain_entry gain_table[2][108] = {
1519 /* 5.2GHz power gain index table */
1520 {
1521 {123, 0x3F}, /* highest txpower */
1522 {117, 0x3F},
1523 {110, 0x3F},
1524 {104, 0x3F},
1525 {98, 0x3F},
1526 {110, 0x3E},
1527 {104, 0x3E},
1528 {98, 0x3E},
1529 {110, 0x3D},
1530 {104, 0x3D},
1531 {98, 0x3D},
1532 {110, 0x3C},
1533 {104, 0x3C},
1534 {98, 0x3C},
1535 {110, 0x3B},
1536 {104, 0x3B},
1537 {98, 0x3B},
1538 {110, 0x3A},
1539 {104, 0x3A},
1540 {98, 0x3A},
1541 {110, 0x39},
1542 {104, 0x39},
1543 {98, 0x39},
1544 {110, 0x38},
1545 {104, 0x38},
1546 {98, 0x38},
1547 {110, 0x37},
1548 {104, 0x37},
1549 {98, 0x37},
1550 {110, 0x36},
1551 {104, 0x36},
1552 {98, 0x36},
1553 {110, 0x35},
1554 {104, 0x35},
1555 {98, 0x35},
1556 {110, 0x34},
1557 {104, 0x34},
1558 {98, 0x34},
1559 {110, 0x33},
1560 {104, 0x33},
1561 {98, 0x33},
1562 {110, 0x32},
1563 {104, 0x32},
1564 {98, 0x32},
1565 {110, 0x31},
1566 {104, 0x31},
1567 {98, 0x31},
1568 {110, 0x30},
1569 {104, 0x30},
1570 {98, 0x30},
1571 {110, 0x25},
1572 {104, 0x25},
1573 {98, 0x25},
1574 {110, 0x24},
1575 {104, 0x24},
1576 {98, 0x24},
1577 {110, 0x23},
1578 {104, 0x23},
1579 {98, 0x23},
1580 {110, 0x22},
1581 {104, 0x18},
1582 {98, 0x18},
1583 {110, 0x17},
1584 {104, 0x17},
1585 {98, 0x17},
1586 {110, 0x16},
1587 {104, 0x16},
1588 {98, 0x16},
1589 {110, 0x15},
1590 {104, 0x15},
1591 {98, 0x15},
1592 {110, 0x14},
1593 {104, 0x14},
1594 {98, 0x14},
1595 {110, 0x13},
1596 {104, 0x13},
1597 {98, 0x13},
1598 {110, 0x12},
1599 {104, 0x08},
1600 {98, 0x08},
1601 {110, 0x07},
1602 {104, 0x07},
1603 {98, 0x07},
1604 {110, 0x06},
1605 {104, 0x06},
1606 {98, 0x06},
1607 {110, 0x05},
1608 {104, 0x05},
1609 {98, 0x05},
1610 {110, 0x04},
1611 {104, 0x04},
1612 {98, 0x04},
1613 {110, 0x03},
1614 {104, 0x03},
1615 {98, 0x03},
1616 {110, 0x02},
1617 {104, 0x02},
1618 {98, 0x02},
1619 {110, 0x01},
1620 {104, 0x01},
1621 {98, 0x01},
1622 {110, 0x00},
1623 {104, 0x00},
1624 {98, 0x00},
1625 {93, 0x00},
1626 {88, 0x00},
1627 {83, 0x00},
1628 {78, 0x00},
1629 },
1630 /* 2.4GHz power gain index table */
1631 {
1632 {110, 0x3f}, /* highest txpower */
1633 {104, 0x3f},
1634 {98, 0x3f},
1635 {110, 0x3e},
1636 {104, 0x3e},
1637 {98, 0x3e},
1638 {110, 0x3d},
1639 {104, 0x3d},
1640 {98, 0x3d},
1641 {110, 0x3c},
1642 {104, 0x3c},
1643 {98, 0x3c},
1644 {110, 0x3b},
1645 {104, 0x3b},
1646 {98, 0x3b},
1647 {110, 0x3a},
1648 {104, 0x3a},
1649 {98, 0x3a},
1650 {110, 0x39},
1651 {104, 0x39},
1652 {98, 0x39},
1653 {110, 0x38},
1654 {104, 0x38},
1655 {98, 0x38},
1656 {110, 0x37},
1657 {104, 0x37},
1658 {98, 0x37},
1659 {110, 0x36},
1660 {104, 0x36},
1661 {98, 0x36},
1662 {110, 0x35},
1663 {104, 0x35},
1664 {98, 0x35},
1665 {110, 0x34},
1666 {104, 0x34},
1667 {98, 0x34},
1668 {110, 0x33},
1669 {104, 0x33},
1670 {98, 0x33},
1671 {110, 0x32},
1672 {104, 0x32},
1673 {98, 0x32},
1674 {110, 0x31},
1675 {104, 0x31},
1676 {98, 0x31},
1677 {110, 0x30},
1678 {104, 0x30},
1679 {98, 0x30},
1680 {110, 0x6},
1681 {104, 0x6},
1682 {98, 0x6},
1683 {110, 0x5},
1684 {104, 0x5},
1685 {98, 0x5},
1686 {110, 0x4},
1687 {104, 0x4},
1688 {98, 0x4},
1689 {110, 0x3},
1690 {104, 0x3},
1691 {98, 0x3},
1692 {110, 0x2},
1693 {104, 0x2},
1694 {98, 0x2},
1695 {110, 0x1},
1696 {104, 0x1},
1697 {98, 0x1},
1698 {110, 0x0},
1699 {104, 0x0},
1700 {98, 0x0},
1701 {97, 0},
1702 {96, 0},
1703 {95, 0},
1704 {94, 0},
1705 {93, 0},
1706 {92, 0},
1707 {91, 0},
1708 {90, 0},
1709 {89, 0},
1710 {88, 0},
1711 {87, 0},
1712 {86, 0},
1713 {85, 0},
1714 {84, 0},
1715 {83, 0},
1716 {82, 0},
1717 {81, 0},
1718 {80, 0},
1719 {79, 0},
1720 {78, 0},
1721 {77, 0},
1722 {76, 0},
1723 {75, 0},
1724 {74, 0},
1725 {73, 0},
1726 {72, 0},
1727 {71, 0},
1728 {70, 0},
1729 {69, 0},
1730 {68, 0},
1731 {67, 0},
1732 {66, 0},
1733 {65, 0},
1734 {64, 0},
1735 {63, 0},
1736 {62, 0},
1737 {61, 0},
1738 {60, 0},
1739 {59, 0},
1740 }
1741 };
1742
1743 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1744 u8 is_fat, u8 ctrl_chan_high,
1745 struct iwl4965_tx_power_db *tx_power_tbl)
1746 {
1747 u8 saturation_power;
1748 s32 target_power;
1749 s32 user_target_power;
1750 s32 power_limit;
1751 s32 current_temp;
1752 s32 reg_limit;
1753 s32 current_regulatory;
1754 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1755 int i;
1756 int c;
1757 const struct iwl_channel_info *ch_info = NULL;
1758 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1759 const struct iwl_eeprom_calib_measure *measurement;
1760 s16 voltage;
1761 s32 init_voltage;
1762 s32 voltage_compensation;
1763 s32 degrees_per_05db_num;
1764 s32 degrees_per_05db_denom;
1765 s32 factory_temp;
1766 s32 temperature_comp[2];
1767 s32 factory_gain_index[2];
1768 s32 factory_actual_pwr[2];
1769 s32 power_index;
1770
1771 /* Sanity check requested level (dBm) */
1772 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
1773 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
1774 priv->user_txpower_limit);
1775 return -EINVAL;
1776 }
1777 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
1778 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1779 priv->user_txpower_limit);
1780 return -EINVAL;
1781 }
1782
1783 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1784 * are used for indexing into txpower table) */
1785 user_target_power = 2 * priv->user_txpower_limit;
1786
1787 /* Get current (RXON) channel, band, width */
1788 ch_info =
1789 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
1790
1791 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1792 is_fat);
1793
1794 if (!ch_info)
1795 return -EINVAL;
1796
1797 /* get txatten group, used to select 1) thermal txpower adjustment
1798 * and 2) mimo txpower balance between Tx chains. */
1799 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1800 if (txatten_grp < 0)
1801 return -EINVAL;
1802
1803 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1804 channel, txatten_grp);
1805
1806 if (is_fat) {
1807 if (ctrl_chan_high)
1808 channel -= 2;
1809 else
1810 channel += 2;
1811 }
1812
1813 /* hardware txpower limits ...
1814 * saturation (clipping distortion) txpowers are in half-dBm */
1815 if (band)
1816 saturation_power = priv->calib_info->saturation_power24;
1817 else
1818 saturation_power = priv->calib_info->saturation_power52;
1819
1820 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1821 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1822 if (band)
1823 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1824 else
1825 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1826 }
1827
1828 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1829 * max_power_avg values are in dBm, convert * 2 */
1830 if (is_fat)
1831 reg_limit = ch_info->fat_max_power_avg * 2;
1832 else
1833 reg_limit = ch_info->max_power_avg * 2;
1834
1835 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1836 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1837 if (band)
1838 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1839 else
1840 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1841 }
1842
1843 /* Interpolate txpower calibration values for this channel,
1844 * based on factory calibration tests on spaced channels. */
1845 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1846
1847 /* calculate tx gain adjustment based on power supply voltage */
1848 voltage = priv->calib_info->voltage;
1849 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1850 voltage_compensation =
1851 iwl4965_get_voltage_compensation(voltage, init_voltage);
1852
1853 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
1854 init_voltage,
1855 voltage, voltage_compensation);
1856
1857 /* get current temperature (Celsius) */
1858 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1859 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1860 current_temp = KELVIN_TO_CELSIUS(current_temp);
1861
1862 /* select thermal txpower adjustment params, based on channel group
1863 * (same frequency group used for mimo txatten adjustment) */
1864 degrees_per_05db_num =
1865 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1866 degrees_per_05db_denom =
1867 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1868
1869 /* get per-chain txpower values from factory measurements */
1870 for (c = 0; c < 2; c++) {
1871 measurement = &ch_eeprom_info.measurements[c][1];
1872
1873 /* txgain adjustment (in half-dB steps) based on difference
1874 * between factory and current temperature */
1875 factory_temp = measurement->temperature;
1876 iwl4965_math_div_round((current_temp - factory_temp) *
1877 degrees_per_05db_denom,
1878 degrees_per_05db_num,
1879 &temperature_comp[c]);
1880
1881 factory_gain_index[c] = measurement->gain_idx;
1882 factory_actual_pwr[c] = measurement->actual_pow;
1883
1884 IWL_DEBUG_TXPOWER("chain = %d\n", c);
1885 IWL_DEBUG_TXPOWER("fctry tmp %d, "
1886 "curr tmp %d, comp %d steps\n",
1887 factory_temp, current_temp,
1888 temperature_comp[c]);
1889
1890 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
1891 factory_gain_index[c],
1892 factory_actual_pwr[c]);
1893 }
1894
1895 /* for each of 33 bit-rates (including 1 for CCK) */
1896 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1897 u8 is_mimo_rate;
1898 union iwl4965_tx_power_dual_stream tx_power;
1899
1900 /* for mimo, reduce each chain's txpower by half
1901 * (3dB, 6 steps), so total output power is regulatory
1902 * compliant. */
1903 if (i & 0x8) {
1904 current_regulatory = reg_limit -
1905 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1906 is_mimo_rate = 1;
1907 } else {
1908 current_regulatory = reg_limit;
1909 is_mimo_rate = 0;
1910 }
1911
1912 /* find txpower limit, either hardware or regulatory */
1913 power_limit = saturation_power - back_off_table[i];
1914 if (power_limit > current_regulatory)
1915 power_limit = current_regulatory;
1916
1917 /* reduce user's txpower request if necessary
1918 * for this rate on this channel */
1919 target_power = user_target_power;
1920 if (target_power > power_limit)
1921 target_power = power_limit;
1922
1923 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
1924 i, saturation_power - back_off_table[i],
1925 current_regulatory, user_target_power,
1926 target_power);
1927
1928 /* for each of 2 Tx chains (radio transmitters) */
1929 for (c = 0; c < 2; c++) {
1930 s32 atten_value;
1931
1932 if (is_mimo_rate)
1933 atten_value =
1934 (s32)le32_to_cpu(priv->card_alive_init.
1935 tx_atten[txatten_grp][c]);
1936 else
1937 atten_value = 0;
1938
1939 /* calculate index; higher index means lower txpower */
1940 power_index = (u8) (factory_gain_index[c] -
1941 (target_power -
1942 factory_actual_pwr[c]) -
1943 temperature_comp[c] -
1944 voltage_compensation +
1945 atten_value);
1946
1947 /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
1948 power_index); */
1949
1950 if (power_index < get_min_power_index(i, band))
1951 power_index = get_min_power_index(i, band);
1952
1953 /* adjust 5 GHz index to support negative indexes */
1954 if (!band)
1955 power_index += 9;
1956
1957 /* CCK, rate 32, reduce txpower for CCK */
1958 if (i == POWER_TABLE_CCK_ENTRY)
1959 power_index +=
1960 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1961
1962 /* stay within the table! */
1963 if (power_index > 107) {
1964 IWL_WARNING("txpower index %d > 107\n",
1965 power_index);
1966 power_index = 107;
1967 }
1968 if (power_index < 0) {
1969 IWL_WARNING("txpower index %d < 0\n",
1970 power_index);
1971 power_index = 0;
1972 }
1973
1974 /* fill txpower command for this rate/chain */
1975 tx_power.s.radio_tx_gain[c] =
1976 gain_table[band][power_index].radio;
1977 tx_power.s.dsp_predis_atten[c] =
1978 gain_table[band][power_index].dsp;
1979
1980 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
1981 "gain 0x%02x dsp %d\n",
1982 c, atten_value, power_index,
1983 tx_power.s.radio_tx_gain[c],
1984 tx_power.s.dsp_predis_atten[c]);
1985 }/* for each chain */
1986
1987 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1988
1989 }/* for each rate */
1990
1991 return 0;
1992 }
1993
1994 /**
1995 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
1996 *
1997 * Uses the active RXON for channel, band, and characteristics (fat, high)
1998 * The power limit is taken from priv->user_txpower_limit.
1999 */
2000 int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
2001 {
2002 struct iwl4965_txpowertable_cmd cmd = { 0 };
2003 int ret;
2004 u8 band = 0;
2005 u8 is_fat = 0;
2006 u8 ctrl_chan_high = 0;
2007
2008 if (test_bit(STATUS_SCANNING, &priv->status)) {
2009 /* If this gets hit a lot, switch it to a BUG() and catch
2010 * the stack trace to find out who is calling this during
2011 * a scan. */
2012 IWL_WARNING("TX Power requested while scanning!\n");
2013 return -EAGAIN;
2014 }
2015
2016 band = priv->band == IEEE80211_BAND_2GHZ;
2017
2018 is_fat = is_fat_channel(priv->active_rxon.flags);
2019
2020 if (is_fat &&
2021 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2022 ctrl_chan_high = 1;
2023
2024 cmd.band = band;
2025 cmd.channel = priv->active_rxon.channel;
2026
2027 ret = iwl4965_fill_txpower_tbl(priv, band,
2028 le16_to_cpu(priv->active_rxon.channel),
2029 is_fat, ctrl_chan_high, &cmd.tx_power);
2030 if (ret)
2031 goto out;
2032
2033 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2034
2035 out:
2036 return ret;
2037 }
2038
2039 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
2040 {
2041 int ret = 0;
2042 struct iwl4965_rxon_assoc_cmd rxon_assoc;
2043 const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
2044 const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
2045
2046 if ((rxon1->flags == rxon2->flags) &&
2047 (rxon1->filter_flags == rxon2->filter_flags) &&
2048 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
2049 (rxon1->ofdm_ht_single_stream_basic_rates ==
2050 rxon2->ofdm_ht_single_stream_basic_rates) &&
2051 (rxon1->ofdm_ht_dual_stream_basic_rates ==
2052 rxon2->ofdm_ht_dual_stream_basic_rates) &&
2053 (rxon1->rx_chain == rxon2->rx_chain) &&
2054 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
2055 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
2056 return 0;
2057 }
2058
2059 rxon_assoc.flags = priv->staging_rxon.flags;
2060 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
2061 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
2062 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
2063 rxon_assoc.reserved = 0;
2064 rxon_assoc.ofdm_ht_single_stream_basic_rates =
2065 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
2066 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
2067 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
2068 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
2069
2070 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
2071 sizeof(rxon_assoc), &rxon_assoc, NULL);
2072 if (ret)
2073 return ret;
2074
2075 return ret;
2076 }
2077
2078
2079 int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
2080 {
2081 int rc;
2082 u8 band = 0;
2083 u8 is_fat = 0;
2084 u8 ctrl_chan_high = 0;
2085 struct iwl4965_channel_switch_cmd cmd = { 0 };
2086 const struct iwl_channel_info *ch_info;
2087
2088 band = priv->band == IEEE80211_BAND_2GHZ;
2089
2090 ch_info = iwl_get_channel_info(priv, priv->band, channel);
2091
2092 is_fat = is_fat_channel(priv->staging_rxon.flags);
2093
2094 if (is_fat &&
2095 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2096 ctrl_chan_high = 1;
2097
2098 cmd.band = band;
2099 cmd.expect_beacon = 0;
2100 cmd.channel = cpu_to_le16(channel);
2101 cmd.rxon_flags = priv->active_rxon.flags;
2102 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2103 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2104 if (ch_info)
2105 cmd.expect_beacon = is_channel_radar(ch_info);
2106 else
2107 cmd.expect_beacon = 1;
2108
2109 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2110 ctrl_chan_high, &cmd.tx_power);
2111 if (rc) {
2112 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2113 return rc;
2114 }
2115
2116 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
2117 return rc;
2118 }
2119
2120 #define RTS_HCCA_RETRY_LIMIT 3
2121 #define RTS_DFAULT_RETRY_LIMIT 60
2122
2123 void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
2124 struct iwl_cmd *cmd,
2125 struct ieee80211_tx_control *ctrl,
2126 struct ieee80211_hdr *hdr, int sta_id,
2127 int is_hcca)
2128 {
2129 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
2130 u8 rts_retry_limit = 0;
2131 u8 data_retry_limit = 0;
2132 u16 fc = le16_to_cpu(hdr->frame_control);
2133 u8 rate_plcp;
2134 u16 rate_flags = 0;
2135 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
2136
2137 rate_plcp = iwl4965_rates[rate_idx].plcp;
2138
2139 rts_retry_limit = (is_hcca) ?
2140 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2141
2142 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2143 rate_flags |= RATE_MCS_CCK_MSK;
2144
2145
2146 if (ieee80211_is_probe_response(fc)) {
2147 data_retry_limit = 3;
2148 if (data_retry_limit < rts_retry_limit)
2149 rts_retry_limit = data_retry_limit;
2150 } else
2151 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2152
2153 if (priv->data_retry_limit != -1)
2154 data_retry_limit = priv->data_retry_limit;
2155
2156
2157 if (ieee80211_is_data(fc)) {
2158 tx->initial_rate_index = 0;
2159 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2160 } else {
2161 switch (fc & IEEE80211_FCTL_STYPE) {
2162 case IEEE80211_STYPE_AUTH:
2163 case IEEE80211_STYPE_DEAUTH:
2164 case IEEE80211_STYPE_ASSOC_REQ:
2165 case IEEE80211_STYPE_REASSOC_REQ:
2166 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2167 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2168 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
2169 }
2170 break;
2171 default:
2172 break;
2173 }
2174
2175 /* Alternate between antenna A and B for successive frames */
2176 if (priv->use_ant_b_for_management_frame) {
2177 priv->use_ant_b_for_management_frame = 0;
2178 rate_flags |= RATE_MCS_ANT_B_MSK;
2179 } else {
2180 priv->use_ant_b_for_management_frame = 1;
2181 rate_flags |= RATE_MCS_ANT_A_MSK;
2182 }
2183 }
2184
2185 tx->rts_retry_limit = rts_retry_limit;
2186 tx->data_retry_limit = data_retry_limit;
2187 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
2188 }
2189
2190 int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
2191 {
2192 struct iwl4965_shared *s = priv->shared_virt;
2193 return le32_to_cpu(s->rb_closed) & 0xFFF;
2194 }
2195
2196 int iwl4965_hw_get_temperature(struct iwl_priv *priv)
2197 {
2198 return priv->temperature;
2199 }
2200
2201 unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
2202 struct iwl4965_frame *frame, u8 rate)
2203 {
2204 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
2205 unsigned int frame_size;
2206
2207 tx_beacon_cmd = &frame->u.beacon;
2208 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2209
2210 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2211 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2212
2213 frame_size = iwl4965_fill_beacon_frame(priv,
2214 tx_beacon_cmd->frame,
2215 iwl4965_broadcast_addr,
2216 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2217
2218 BUG_ON(frame_size > MAX_MPDU_SIZE);
2219 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2220
2221 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2222 tx_beacon_cmd->tx.rate_n_flags =
2223 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
2224 else
2225 tx_beacon_cmd->tx.rate_n_flags =
2226 iwl4965_hw_set_rate_n_flags(rate, 0);
2227
2228 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2229 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2230 return (sizeof(*tx_beacon_cmd) + frame_size);
2231 }
2232
2233 /*
2234 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2235 * given Tx queue, and enable the DMA channel used for that queue.
2236 *
2237 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2238 * channels supported in hardware.
2239 */
2240 int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
2241 {
2242 int rc;
2243 unsigned long flags;
2244 int txq_id = txq->q.id;
2245
2246 spin_lock_irqsave(&priv->lock, flags);
2247 rc = iwl_grab_nic_access(priv);
2248 if (rc) {
2249 spin_unlock_irqrestore(&priv->lock, flags);
2250 return rc;
2251 }
2252
2253 /* Circular buffer (TFD queue in DRAM) physical base address */
2254 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
2255 txq->q.dma_addr >> 8);
2256
2257 /* Enable DMA channel, using same id as for TFD queue */
2258 iwl_write_direct32(
2259 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2260 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2261 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
2262 iwl_release_nic_access(priv);
2263 spin_unlock_irqrestore(&priv->lock, flags);
2264
2265 return 0;
2266 }
2267
2268 int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
2269 dma_addr_t addr, u16 len)
2270 {
2271 int index, is_odd;
2272 struct iwl4965_tfd_frame *tfd = ptr;
2273 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2274
2275 /* Each TFD can point to a maximum 20 Tx buffers */
2276 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2277 IWL_ERROR("Error can not send more than %d chunks\n",
2278 MAX_NUM_OF_TBS);
2279 return -EINVAL;
2280 }
2281
2282 index = num_tbs / 2;
2283 is_odd = num_tbs & 0x1;
2284
2285 if (!is_odd) {
2286 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2287 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
2288 iwl_get_dma_hi_address(addr));
2289 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2290 } else {
2291 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2292 (u32) (addr & 0xffff));
2293 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2294 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2295 }
2296
2297 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2298
2299 return 0;
2300 }
2301
2302 static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
2303 {
2304 u16 hw_version = iwl_eeprom_query16(priv, EEPROM_4965_BOARD_REVISION);
2305
2306 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2307 ((hw_version >> 8) & 0x0F),
2308 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2309
2310 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
2311 &priv->eeprom[EEPROM_4965_BOARD_PBA]);
2312 }
2313
2314 static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
2315 {
2316 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
2317 sizeof(struct iwl4965_shared),
2318 &priv->shared_phys);
2319 if (!priv->shared_virt)
2320 return -ENOMEM;
2321
2322 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
2323
2324 return 0;
2325 }
2326
2327 static void iwl4965_free_shared_mem(struct iwl_priv *priv)
2328 {
2329 if (priv->shared_virt)
2330 pci_free_consistent(priv->pci_dev,
2331 sizeof(struct iwl4965_shared),
2332 priv->shared_virt,
2333 priv->shared_phys);
2334 }
2335
2336 /**
2337 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
2338 */
2339 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
2340 struct iwl4965_tx_queue *txq,
2341 u16 byte_cnt)
2342 {
2343 int len;
2344 int txq_id = txq->q.id;
2345 struct iwl4965_shared *shared_data = priv->shared_virt;
2346
2347 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2348
2349 /* Set up byte count within first 256 entries */
2350 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
2351 tfd_offset[txq->q.write_ptr], byte_cnt, len);
2352
2353 /* If within first 64 entries, duplicate at end */
2354 if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
2355 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
2356 tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
2357 byte_cnt, len);
2358 }
2359
2360 /**
2361 * sign_extend - Sign extend a value using specified bit as sign-bit
2362 *
2363 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
2364 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
2365 *
2366 * @param oper value to sign extend
2367 * @param index 0 based bit index (0<=index<32) to sign bit
2368 */
2369 static s32 sign_extend(u32 oper, int index)
2370 {
2371 u8 shift = 31 - index;
2372
2373 return (s32)(oper << shift) >> shift;
2374 }
2375
2376 /**
2377 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
2378 * @statistics: Provides the temperature reading from the uCode
2379 *
2380 * A return of <0 indicates bogus data in the statistics
2381 */
2382 int iwl4965_get_temperature(const struct iwl_priv *priv)
2383 {
2384 s32 temperature;
2385 s32 vt;
2386 s32 R1, R2, R3;
2387 u32 R4;
2388
2389 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
2390 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
2391 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
2392 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
2393 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
2394 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
2395 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
2396 } else {
2397 IWL_DEBUG_TEMP("Running temperature calibration\n");
2398 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
2399 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
2400 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
2401 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
2402 }
2403
2404 /*
2405 * Temperature is only 23 bits, so sign extend out to 32.
2406 *
2407 * NOTE If we haven't received a statistics notification yet
2408 * with an updated temperature, use R4 provided to us in the
2409 * "initialize" ALIVE response.
2410 */
2411 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
2412 vt = sign_extend(R4, 23);
2413 else
2414 vt = sign_extend(
2415 le32_to_cpu(priv->statistics.general.temperature), 23);
2416
2417 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
2418 R1, R2, R3, vt);
2419
2420 if (R3 == R1) {
2421 IWL_ERROR("Calibration conflict R1 == R3\n");
2422 return -1;
2423 }
2424
2425 /* Calculate temperature in degrees Kelvin, adjust by 97%.
2426 * Add offset to center the adjustment around 0 degrees Centigrade. */
2427 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
2428 temperature /= (R3 - R1);
2429 temperature = (temperature * 97) / 100 +
2430 TEMPERATURE_CALIB_KELVIN_OFFSET;
2431
2432 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
2433 KELVIN_TO_CELSIUS(temperature));
2434
2435 return temperature;
2436 }
2437
2438 /* Adjust Txpower only if temperature variance is greater than threshold. */
2439 #define IWL_TEMPERATURE_THRESHOLD 3
2440
2441 /**
2442 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
2443 *
2444 * If the temperature changed has changed sufficiently, then a recalibration
2445 * is needed.
2446 *
2447 * Assumes caller will replace priv->last_temperature once calibration
2448 * executed.
2449 */
2450 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
2451 {
2452 int temp_diff;
2453
2454 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
2455 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
2456 return 0;
2457 }
2458
2459 temp_diff = priv->temperature - priv->last_temperature;
2460
2461 /* get absolute value */
2462 if (temp_diff < 0) {
2463 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
2464 temp_diff = -temp_diff;
2465 } else if (temp_diff == 0)
2466 IWL_DEBUG_POWER("Same temp, \n");
2467 else
2468 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
2469
2470 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
2471 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
2472 return 0;
2473 }
2474
2475 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
2476
2477 return 1;
2478 }
2479
2480 /* Calculate noise level, based on measurements during network silence just
2481 * before arriving beacon. This measurement can be done only if we know
2482 * exactly when to expect beacons, therefore only when we're associated. */
2483 static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
2484 {
2485 struct statistics_rx_non_phy *rx_info
2486 = &(priv->statistics.rx.general);
2487 int num_active_rx = 0;
2488 int total_silence = 0;
2489 int bcn_silence_a =
2490 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
2491 int bcn_silence_b =
2492 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
2493 int bcn_silence_c =
2494 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
2495
2496 if (bcn_silence_a) {
2497 total_silence += bcn_silence_a;
2498 num_active_rx++;
2499 }
2500 if (bcn_silence_b) {
2501 total_silence += bcn_silence_b;
2502 num_active_rx++;
2503 }
2504 if (bcn_silence_c) {
2505 total_silence += bcn_silence_c;
2506 num_active_rx++;
2507 }
2508
2509 /* Average among active antennas */
2510 if (num_active_rx)
2511 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
2512 else
2513 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2514
2515 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
2516 bcn_silence_a, bcn_silence_b, bcn_silence_c,
2517 priv->last_rx_noise);
2518 }
2519
2520 void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
2521 {
2522 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
2523 int change;
2524 s32 temp;
2525
2526 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
2527 (int)sizeof(priv->statistics), pkt->len);
2528
2529 change = ((priv->statistics.general.temperature !=
2530 pkt->u.stats.general.temperature) ||
2531 ((priv->statistics.flag &
2532 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
2533 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
2534
2535 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
2536
2537 set_bit(STATUS_STATISTICS, &priv->status);
2538
2539 /* Reschedule the statistics timer to occur in
2540 * REG_RECALIB_PERIOD seconds to ensure we get a
2541 * thermal update even if the uCode doesn't give
2542 * us one */
2543 mod_timer(&priv->statistics_periodic, jiffies +
2544 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
2545
2546 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2547 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
2548 iwl4965_rx_calc_noise(priv);
2549 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
2550 queue_work(priv->workqueue, &priv->sensitivity_work);
2551 #endif
2552 }
2553
2554 iwl_leds_background(priv);
2555
2556 /* If the hardware hasn't reported a change in
2557 * temperature then don't bother computing a
2558 * calibrated temperature value */
2559 if (!change)
2560 return;
2561
2562 temp = iwl4965_get_temperature(priv);
2563 if (temp < 0)
2564 return;
2565
2566 if (priv->temperature != temp) {
2567 if (priv->temperature)
2568 IWL_DEBUG_TEMP("Temperature changed "
2569 "from %dC to %dC\n",
2570 KELVIN_TO_CELSIUS(priv->temperature),
2571 KELVIN_TO_CELSIUS(temp));
2572 else
2573 IWL_DEBUG_TEMP("Temperature "
2574 "initialized to %dC\n",
2575 KELVIN_TO_CELSIUS(temp));
2576 }
2577
2578 priv->temperature = temp;
2579 set_bit(STATUS_TEMPERATURE, &priv->status);
2580
2581 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2582 iwl4965_is_temp_calib_needed(priv))
2583 queue_work(priv->workqueue, &priv->txpower_work);
2584 }
2585
2586 static void iwl4965_add_radiotap(struct iwl_priv *priv,
2587 struct sk_buff *skb,
2588 struct iwl4965_rx_phy_res *rx_start,
2589 struct ieee80211_rx_status *stats,
2590 u32 ampdu_status)
2591 {
2592 s8 signal = stats->ssi;
2593 s8 noise = 0;
2594 int rate = stats->rate_idx;
2595 u64 tsf = stats->mactime;
2596 __le16 antenna;
2597 __le16 phy_flags_hw = rx_start->phy_flags;
2598 struct iwl4965_rt_rx_hdr {
2599 struct ieee80211_radiotap_header rt_hdr;
2600 __le64 rt_tsf; /* TSF */
2601 u8 rt_flags; /* radiotap packet flags */
2602 u8 rt_rate; /* rate in 500kb/s */
2603 __le16 rt_channelMHz; /* channel in MHz */
2604 __le16 rt_chbitmask; /* channel bitfield */
2605 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
2606 s8 rt_dbmnoise;
2607 u8 rt_antenna; /* antenna number */
2608 } __attribute__ ((packed)) *iwl4965_rt;
2609
2610 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2611 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2612 if (net_ratelimit())
2613 printk(KERN_ERR "not enough headroom [%d] for "
2614 "radiotap head [%zd]\n",
2615 skb_headroom(skb), sizeof(*iwl4965_rt));
2616 return;
2617 }
2618
2619 /* put radiotap header in front of 802.11 header and data */
2620 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2621
2622 /* initialise radiotap header */
2623 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2624 iwl4965_rt->rt_hdr.it_pad = 0;
2625
2626 /* total header + data */
2627 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2628 &iwl4965_rt->rt_hdr.it_len);
2629
2630 /* Indicate all the fields we add to the radiotap header */
2631 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2632 (1 << IEEE80211_RADIOTAP_FLAGS) |
2633 (1 << IEEE80211_RADIOTAP_RATE) |
2634 (1 << IEEE80211_RADIOTAP_CHANNEL) |
2635 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2636 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2637 (1 << IEEE80211_RADIOTAP_ANTENNA)),
2638 &iwl4965_rt->rt_hdr.it_present);
2639
2640 /* Zero the flags, we'll add to them as we go */
2641 iwl4965_rt->rt_flags = 0;
2642
2643 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2644
2645 iwl4965_rt->rt_dbmsignal = signal;
2646 iwl4965_rt->rt_dbmnoise = noise;
2647
2648 /* Convert the channel frequency and set the flags */
2649 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2650 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2651 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2652 IEEE80211_CHAN_5GHZ),
2653 &iwl4965_rt->rt_chbitmask);
2654 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2655 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2656 IEEE80211_CHAN_2GHZ),
2657 &iwl4965_rt->rt_chbitmask);
2658 else /* 802.11g */
2659 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2660 IEEE80211_CHAN_2GHZ),
2661 &iwl4965_rt->rt_chbitmask);
2662
2663 if (rate == -1)
2664 iwl4965_rt->rt_rate = 0;
2665 else
2666 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
2667
2668 /*
2669 * "antenna number"
2670 *
2671 * It seems that the antenna field in the phy flags value
2672 * is actually a bitfield. This is undefined by radiotap,
2673 * it wants an actual antenna number but I always get "7"
2674 * for most legacy frames I receive indicating that the
2675 * same frame was received on all three RX chains.
2676 *
2677 * I think this field should be removed in favour of a
2678 * new 802.11n radiotap field "RX chains" that is defined
2679 * as a bitmask.
2680 */
2681 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2682 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
2683
2684 /* set the preamble flag if appropriate */
2685 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2686 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2687
2688 stats->flag |= RX_FLAG_RADIOTAP;
2689 }
2690
2691 static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2692 {
2693 /* 0 - mgmt, 1 - cnt, 2 - data */
2694 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2695 priv->rx_stats[idx].cnt++;
2696 priv->rx_stats[idx].bytes += len;
2697 }
2698
2699 /*
2700 * returns non-zero if packet should be dropped
2701 */
2702 static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
2703 struct ieee80211_hdr *hdr,
2704 u32 decrypt_res,
2705 struct ieee80211_rx_status *stats)
2706 {
2707 u16 fc = le16_to_cpu(hdr->frame_control);
2708
2709 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2710 return 0;
2711
2712 if (!(fc & IEEE80211_FCTL_PROTECTED))
2713 return 0;
2714
2715 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2716 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2717 case RX_RES_STATUS_SEC_TYPE_TKIP:
2718 /* The uCode has got a bad phase 1 Key, pushes the packet.
2719 * Decryption will be done in SW. */
2720 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2721 RX_RES_STATUS_BAD_KEY_TTAK)
2722 break;
2723
2724 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2725 RX_RES_STATUS_BAD_ICV_MIC) {
2726 /* bad ICV, the packet is destroyed since the
2727 * decryption is inplace, drop it */
2728 IWL_DEBUG_RX("Packet destroyed\n");
2729 return -1;
2730 }
2731 case RX_RES_STATUS_SEC_TYPE_WEP:
2732 case RX_RES_STATUS_SEC_TYPE_CCMP:
2733 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2734 RX_RES_STATUS_DECRYPT_OK) {
2735 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2736 stats->flag |= RX_FLAG_DECRYPTED;
2737 }
2738 break;
2739
2740 default:
2741 break;
2742 }
2743 return 0;
2744 }
2745
2746 static u32 iwl4965_translate_rx_status(u32 decrypt_in)
2747 {
2748 u32 decrypt_out = 0;
2749
2750 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2751 RX_RES_STATUS_STATION_FOUND)
2752 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2753 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2754
2755 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2756
2757 /* packet was not encrypted */
2758 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2759 RX_RES_STATUS_SEC_TYPE_NONE)
2760 return decrypt_out;
2761
2762 /* packet was encrypted with unknown alg */
2763 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2764 RX_RES_STATUS_SEC_TYPE_ERR)
2765 return decrypt_out;
2766
2767 /* decryption was not done in HW */
2768 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2769 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2770 return decrypt_out;
2771
2772 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2773
2774 case RX_RES_STATUS_SEC_TYPE_CCMP:
2775 /* alg is CCM: check MIC only */
2776 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2777 /* Bad MIC */
2778 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2779 else
2780 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2781
2782 break;
2783
2784 case RX_RES_STATUS_SEC_TYPE_TKIP:
2785 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2786 /* Bad TTAK */
2787 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2788 break;
2789 }
2790 /* fall through if TTAK OK */
2791 default:
2792 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
2793 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2794 else
2795 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2796 break;
2797 };
2798
2799 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
2800 decrypt_in, decrypt_out);
2801
2802 return decrypt_out;
2803 }
2804
2805 static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
2806 int include_phy,
2807 struct iwl4965_rx_mem_buffer *rxb,
2808 struct ieee80211_rx_status *stats)
2809 {
2810 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
2811 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2812 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
2813 struct ieee80211_hdr *hdr;
2814 u16 len;
2815 __le32 *rx_end;
2816 unsigned int skblen;
2817 u32 ampdu_status;
2818 u32 ampdu_status_legacy;
2819
2820 if (!include_phy && priv->last_phy_res[0])
2821 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
2822
2823 if (!rx_start) {
2824 IWL_ERROR("MPDU frame without a PHY data\n");
2825 return;
2826 }
2827 if (include_phy) {
2828 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
2829 rx_start->cfg_phy_cnt);
2830
2831 len = le16_to_cpu(rx_start->byte_count);
2832
2833 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
2834 sizeof(struct iwl4965_rx_phy_res) +
2835 rx_start->cfg_phy_cnt + len);
2836
2837 } else {
2838 struct iwl4965_rx_mpdu_res_start *amsdu =
2839 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
2840
2841 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
2842 sizeof(struct iwl4965_rx_mpdu_res_start));
2843 len = le16_to_cpu(amsdu->byte_count);
2844 rx_start->byte_count = amsdu->byte_count;
2845 rx_end = (__le32 *) (((u8 *) hdr) + len);
2846 }
2847 if (len > priv->hw_params.max_pkt_size || len < 16) {
2848 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
2849 return;
2850 }
2851
2852 ampdu_status = le32_to_cpu(*rx_end);
2853 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
2854
2855 if (!include_phy) {
2856 /* New status scheme, need to translate */
2857 ampdu_status_legacy = ampdu_status;
2858 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
2859 }
2860
2861 /* start from MAC */
2862 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
2863 skb_put(rxb->skb, len); /* end where data ends */
2864
2865 /* We only process data packets if the interface is open */
2866 if (unlikely(!priv->is_open)) {
2867 IWL_DEBUG_DROP_LIMIT
2868 ("Dropping packet while interface is not open.\n");
2869 return;
2870 }
2871
2872 stats->flag = 0;
2873 hdr = (struct ieee80211_hdr *)rxb->skb->data;
2874
2875 /* in case of HW accelerated crypto and bad decryption, drop */
2876 if (!priv->hw_params.sw_crypto &&
2877 iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
2878 return;
2879
2880 if (priv->add_radiotap)
2881 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
2882
2883 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
2884 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
2885 priv->alloc_rxb_skb--;
2886 rxb->skb = NULL;
2887 }
2888
2889 /* Calc max signal level (dBm) among 3 possible receivers */
2890 static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
2891 {
2892 /* data from PHY/DSP regarding signal strength, etc.,
2893 * contents are always there, not configurable by host. */
2894 struct iwl4965_rx_non_cfg_phy *ncphy =
2895 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
2896 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
2897 >> IWL_AGC_DB_POS;
2898
2899 u32 valid_antennae =
2900 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
2901 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
2902 u8 max_rssi = 0;
2903 u32 i;
2904
2905 /* Find max rssi among 3 possible receivers.
2906 * These values are measured by the digital signal processor (DSP).
2907 * They should stay fairly constant even as the signal strength varies,
2908 * if the radio's automatic gain control (AGC) is working right.
2909 * AGC value (see below) will provide the "interesting" info. */
2910 for (i = 0; i < 3; i++)
2911 if (valid_antennae & (1 << i))
2912 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2913
2914 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2915 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2916 max_rssi, agc);
2917
2918 /* dBm = max_rssi dB - agc dB - constant.
2919 * Higher AGC (higher radio gain) means lower signal. */
2920 return (max_rssi - agc - IWL_RSSI_OFFSET);
2921 }
2922
2923 static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
2924 {
2925 unsigned long flags;
2926
2927 spin_lock_irqsave(&priv->sta_lock, flags);
2928 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
2929 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
2930 priv->stations[sta_id].sta.sta.modify_mask = 0;
2931 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
2932 spin_unlock_irqrestore(&priv->sta_lock, flags);
2933
2934 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
2935 }
2936
2937 static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
2938 {
2939 /* FIXME: need locking over ps_status ??? */
2940 u8 sta_id = iwl_find_station(priv, addr);
2941
2942 if (sta_id != IWL_INVALID_STATION) {
2943 u8 sta_awake = priv->stations[sta_id].
2944 ps_status == STA_PS_STATUS_WAKE;
2945
2946 if (sta_awake && ps_bit)
2947 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
2948 else if (!sta_awake && !ps_bit) {
2949 iwl4965_sta_modify_ps_wake(priv, sta_id);
2950 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
2951 }
2952 }
2953 }
2954 #ifdef CONFIG_IWLWIFI_DEBUG
2955
2956 /**
2957 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
2958 *
2959 * You may hack this function to show different aspects of received frames,
2960 * including selective frame dumps.
2961 * group100 parameter selects whether to show 1 out of 100 good frames.
2962 *
2963 * TODO: This was originally written for 3945, need to audit for
2964 * proper operation with 4965.
2965 */
2966 static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
2967 struct iwl4965_rx_packet *pkt,
2968 struct ieee80211_hdr *header, int group100)
2969 {
2970 u32 to_us;
2971 u32 print_summary = 0;
2972 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
2973 u32 hundred = 0;
2974 u32 dataframe = 0;
2975 u16 fc;
2976 u16 seq_ctl;
2977 u16 channel;
2978 u16 phy_flags;
2979 int rate_sym;
2980 u16 length;
2981 u16 status;
2982 u16 bcn_tmr;
2983 u32 tsf_low;
2984 u64 tsf;
2985 u8 rssi;
2986 u8 agc;
2987 u16 sig_avg;
2988 u16 noise_diff;
2989 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
2990 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
2991 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
2992 u8 *data = IWL_RX_DATA(pkt);
2993
2994 if (likely(!(iwl_debug_level & IWL_DL_RX)))
2995 return;
2996
2997 /* MAC header */
2998 fc = le16_to_cpu(header->frame_control);
2999 seq_ctl = le16_to_cpu(header->seq_ctrl);
3000
3001 /* metadata */
3002 channel = le16_to_cpu(rx_hdr->channel);
3003 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3004 rate_sym = rx_hdr->rate;
3005 length = le16_to_cpu(rx_hdr->len);
3006
3007 /* end-of-frame status and timestamp */
3008 status = le32_to_cpu(rx_end->status);
3009 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3010 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3011 tsf = le64_to_cpu(rx_end->timestamp);
3012
3013 /* signal statistics */
3014 rssi = rx_stats->rssi;
3015 agc = rx_stats->agc;
3016 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3017 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3018
3019 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3020
3021 /* if data frame is to us and all is good,
3022 * (optionally) print summary for only 1 out of every 100 */
3023 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3024 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3025 dataframe = 1;
3026 if (!group100)
3027 print_summary = 1; /* print each frame */
3028 else if (priv->framecnt_to_us < 100) {
3029 priv->framecnt_to_us++;
3030 print_summary = 0;
3031 } else {
3032 priv->framecnt_to_us = 0;
3033 print_summary = 1;
3034 hundred = 1;
3035 }
3036 } else {
3037 /* print summary for all other frames */
3038 print_summary = 1;
3039 }
3040
3041 if (print_summary) {
3042 char *title;
3043 int rate_idx;
3044 u32 bitrate;
3045
3046 if (hundred)
3047 title = "100Frames";
3048 else if (fc & IEEE80211_FCTL_RETRY)
3049 title = "Retry";
3050 else if (ieee80211_is_assoc_response(fc))
3051 title = "AscRsp";
3052 else if (ieee80211_is_reassoc_response(fc))
3053 title = "RasRsp";
3054 else if (ieee80211_is_probe_response(fc)) {
3055 title = "PrbRsp";
3056 print_dump = 1; /* dump frame contents */
3057 } else if (ieee80211_is_beacon(fc)) {
3058 title = "Beacon";
3059 print_dump = 1; /* dump frame contents */
3060 } else if (ieee80211_is_atim(fc))
3061 title = "ATIM";
3062 else if (ieee80211_is_auth(fc))
3063 title = "Auth";
3064 else if (ieee80211_is_deauth(fc))
3065 title = "DeAuth";
3066 else if (ieee80211_is_disassoc(fc))
3067 title = "DisAssoc";
3068 else
3069 title = "Frame";
3070
3071 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3072 if (unlikely(rate_idx == -1))
3073 bitrate = 0;
3074 else
3075 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3076
3077 /* print frame summary.
3078 * MAC addresses show just the last byte (for brevity),
3079 * but you can hack it to show more, if you'd like to. */
3080 if (dataframe)
3081 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3082 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3083 title, fc, header->addr1[5],
3084 length, rssi, channel, bitrate);
3085 else {
3086 /* src/dst addresses assume managed mode */
3087 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3088 "src=0x%02x, rssi=%u, tim=%lu usec, "
3089 "phy=0x%02x, chnl=%d\n",
3090 title, fc, header->addr1[5],
3091 header->addr3[5], rssi,
3092 tsf_low - priv->scan_start_tsf,
3093 phy_flags, channel);
3094 }
3095 }
3096 if (print_dump)
3097 iwl_print_hex_dump(IWL_DL_RX, data, length);
3098 }
3099 #else
3100 static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
3101 struct iwl4965_rx_packet *pkt,
3102 struct ieee80211_hdr *header,
3103 int group100)
3104 {
3105 }
3106 #endif
3107
3108
3109
3110 /* Called for REPLY_RX (legacy ABG frames), or
3111 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
3112 static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
3113 struct iwl4965_rx_mem_buffer *rxb)
3114 {
3115 struct ieee80211_hdr *header;
3116 struct ieee80211_rx_status rx_status;
3117 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3118 /* Use phy data (Rx signal strength, etc.) contained within
3119 * this rx packet for legacy frames,
3120 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
3121 int include_phy = (pkt->hdr.cmd == REPLY_RX);
3122 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3123 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3124 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3125 __le32 *rx_end;
3126 unsigned int len = 0;
3127 u16 fc;
3128 u8 network_packet;
3129
3130 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
3131 rx_status.freq =
3132 ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
3133 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3134 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
3135 rx_status.rate_idx =
3136 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
3137 if (rx_status.band == IEEE80211_BAND_5GHZ)
3138 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3139
3140 rx_status.antenna = 0;
3141 rx_status.flag = 0;
3142
3143 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
3144 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3145 rx_start->cfg_phy_cnt);
3146 return;
3147 }
3148
3149 if (!include_phy) {
3150 if (priv->last_phy_res[0])
3151 rx_start = (struct iwl4965_rx_phy_res *)
3152 &priv->last_phy_res[1];
3153 else
3154 rx_start = NULL;
3155 }
3156
3157 if (!rx_start) {
3158 IWL_ERROR("MPDU frame without a PHY data\n");
3159 return;
3160 }
3161
3162 if (include_phy) {
3163 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3164 + rx_start->cfg_phy_cnt);
3165
3166 len = le16_to_cpu(rx_start->byte_count);
3167 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
3168 sizeof(struct iwl4965_rx_phy_res) + len);
3169 } else {
3170 struct iwl4965_rx_mpdu_res_start *amsdu =
3171 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3172
3173 header = (void *)(pkt->u.raw +
3174 sizeof(struct iwl4965_rx_mpdu_res_start));
3175 len = le16_to_cpu(amsdu->byte_count);
3176 rx_end = (__le32 *) (pkt->u.raw +
3177 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3178 }
3179
3180 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3181 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3182 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3183 le32_to_cpu(*rx_end));
3184 return;
3185 }
3186
3187 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3188
3189 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
3190 rx_status.ssi = iwl4965_calc_rssi(rx_start);
3191
3192 /* Meaningful noise values are available only from beacon statistics,
3193 * which are gathered only when associated, and indicate noise
3194 * only for the associated network channel ...
3195 * Ignore these noise values while scanning (other channels) */
3196 if (iwl_is_associated(priv) &&
3197 !test_bit(STATUS_SCANNING, &priv->status)) {
3198 rx_status.noise = priv->last_rx_noise;
3199 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
3200 rx_status.noise);
3201 } else {
3202 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3203 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
3204 }
3205
3206 /* Reset beacon noise level if not associated. */
3207 if (!iwl_is_associated(priv))
3208 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3209
3210 /* Set "1" to report good data frames in groups of 100 */
3211 /* FIXME: need to optimze the call: */
3212 iwl4965_dbg_report_frame(priv, pkt, header, 1);
3213
3214 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
3215 rx_status.ssi, rx_status.noise, rx_status.signal,
3216 (unsigned long long)rx_status.mactime);
3217
3218 network_packet = iwl4965_is_network_packet(priv, header);
3219 if (network_packet) {
3220 priv->last_rx_rssi = rx_status.ssi;
3221 priv->last_beacon_time = priv->ucode_beacon_time;
3222 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3223 }
3224
3225 fc = le16_to_cpu(header->frame_control);
3226 switch (fc & IEEE80211_FCTL_FTYPE) {
3227 case IEEE80211_FTYPE_MGMT:
3228 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3229 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3230 header->addr2);
3231 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
3232 break;
3233
3234 case IEEE80211_FTYPE_CTL:
3235 #ifdef CONFIG_IWL4965_HT
3236 switch (fc & IEEE80211_FCTL_STYPE) {
3237 case IEEE80211_STYPE_BACK_REQ:
3238 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
3239 iwl4965_handle_data_packet(priv, 0, include_phy,
3240 rxb, &rx_status);
3241 break;
3242 default:
3243 break;
3244 }
3245 #endif
3246 break;
3247
3248 case IEEE80211_FTYPE_DATA: {
3249 DECLARE_MAC_BUF(mac1);
3250 DECLARE_MAC_BUF(mac2);
3251 DECLARE_MAC_BUF(mac3);
3252
3253 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3254 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3255 header->addr2);
3256
3257 if (unlikely(!network_packet))
3258 IWL_DEBUG_DROP("Dropping (non network): "
3259 "%s, %s, %s\n",
3260 print_mac(mac1, header->addr1),
3261 print_mac(mac2, header->addr2),
3262 print_mac(mac3, header->addr3));
3263 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
3264 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
3265 print_mac(mac1, header->addr1),
3266 print_mac(mac2, header->addr2),
3267 print_mac(mac3, header->addr3));
3268 else
3269 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
3270 &rx_status);
3271 break;
3272 }
3273 default:
3274 break;
3275
3276 }
3277 }
3278
3279 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
3280 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
3281 static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
3282 struct iwl4965_rx_mem_buffer *rxb)
3283 {
3284 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3285 priv->last_phy_res[0] = 1;
3286 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
3287 sizeof(struct iwl4965_rx_phy_res));
3288 }
3289 static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
3290 struct iwl4965_rx_mem_buffer *rxb)
3291
3292 {
3293 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
3294 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3295 struct iwl4965_missed_beacon_notif *missed_beacon;
3296
3297 missed_beacon = &pkt->u.missed_beacon;
3298 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
3299 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
3300 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
3301 le32_to_cpu(missed_beacon->total_missed_becons),
3302 le32_to_cpu(missed_beacon->num_recvd_beacons),
3303 le32_to_cpu(missed_beacon->num_expected_beacons));
3304 if (!test_bit(STATUS_SCANNING, &priv->status))
3305 iwl_init_sensitivity(priv);
3306 }
3307 #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
3308 }
3309 #ifdef CONFIG_IWL4965_HT
3310
3311 /**
3312 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
3313 */
3314 static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
3315 int sta_id, int tid)
3316 {
3317 unsigned long flags;
3318
3319 /* Remove "disable" flag, to enable Tx for this TID */
3320 spin_lock_irqsave(&priv->sta_lock, flags);
3321 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3322 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3323 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3324 spin_unlock_irqrestore(&priv->sta_lock, flags);
3325
3326 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
3327 }
3328
3329 /**
3330 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
3331 *
3332 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
3333 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
3334 */
3335 static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
3336 struct iwl4965_ht_agg *agg,
3337 struct iwl4965_compressed_ba_resp*
3338 ba_resp)
3339
3340 {
3341 int i, sh, ack;
3342 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
3343 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3344 u64 bitmap;
3345 int successes = 0;
3346 struct ieee80211_tx_status *tx_status;
3347
3348 if (unlikely(!agg->wait_for_ba)) {
3349 IWL_ERROR("Received BA when not expected\n");
3350 return -EINVAL;
3351 }
3352
3353 /* Mark that the expected block-ack response arrived */
3354 agg->wait_for_ba = 0;
3355 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
3356
3357 /* Calculate shift to align block-ack bits with our Tx window bits */
3358 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
3359 if (sh < 0) /* tbw something is wrong with indices */
3360 sh += 0x100;
3361
3362 /* don't use 64-bit values for now */
3363 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
3364
3365 if (agg->frame_count > (64 - sh)) {
3366 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
3367 return -1;
3368 }
3369
3370 /* check for success or failure according to the
3371 * transmitted bitmap and block-ack bitmap */
3372 bitmap &= agg->bitmap;
3373
3374 /* For each frame attempted in aggregation,
3375 * update driver's record of tx frame's status. */
3376 for (i = 0; i < agg->frame_count ; i++) {
3377 ack = bitmap & (1 << i);
3378 successes += !!ack;
3379 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
3380 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
3381 agg->start_idx + i);
3382 }
3383
3384 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
3385 tx_status->flags = IEEE80211_TX_STATUS_ACK;
3386 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
3387 tx_status->ampdu_ack_map = successes;
3388 tx_status->ampdu_ack_len = agg->frame_count;
3389 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
3390 &tx_status->control);
3391
3392 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
3393
3394 return 0;
3395 }
3396
3397 /**
3398 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
3399 */
3400 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
3401 u16 txq_id)
3402 {
3403 /* Simply stop the queue, but don't change any configuration;
3404 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3405 iwl_write_prph(priv,
3406 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
3407 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
3408 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
3409 }
3410
3411 /**
3412 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
3413 * priv->lock must be held by the caller
3414 */
3415 static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
3416 u16 ssn_idx, u8 tx_fifo)
3417 {
3418 int ret = 0;
3419
3420 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
3421 IWL_WARNING("queue number too small: %d, must be > %d\n",
3422 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3423 return -EINVAL;
3424 }
3425
3426 ret = iwl_grab_nic_access(priv);
3427 if (ret)
3428 return ret;
3429
3430 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3431
3432 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3433
3434 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3435 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3436 /* supposes that ssn_idx is valid (!= 0xFFF) */
3437 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3438
3439 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3440 iwl4965_txq_ctx_deactivate(priv, txq_id);
3441 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
3442
3443 iwl_release_nic_access(priv);
3444
3445 return 0;
3446 }
3447
3448 int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
3449 u8 tid, int txq_id)
3450 {
3451 struct iwl4965_queue *q = &priv->txq[txq_id].q;
3452 u8 *addr = priv->stations[sta_id].sta.sta.addr;
3453 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
3454
3455 switch (priv->stations[sta_id].tid[tid].agg.state) {
3456 case IWL_EMPTYING_HW_QUEUE_DELBA:
3457 /* We are reclaiming the last packet of the */
3458 /* aggregated HW queue */
3459 if (txq_id == tid_data->agg.txq_id &&
3460 q->read_ptr == q->write_ptr) {
3461 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
3462 int tx_fifo = default_tid_to_tx_fifo[tid];
3463 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
3464 iwl4965_tx_queue_agg_disable(priv, txq_id,
3465 ssn, tx_fifo);
3466 tid_data->agg.state = IWL_AGG_OFF;
3467 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3468 }
3469 break;
3470 case IWL_EMPTYING_HW_QUEUE_ADDBA:
3471 /* We are reclaiming the last packet of the queue */
3472 if (tid_data->tfds_in_queue == 0) {
3473 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
3474 tid_data->agg.state = IWL_AGG_ON;
3475 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3476 }
3477 break;
3478 }
3479 return 0;
3480 }
3481
3482 /**
3483 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
3484 * @index -- current index
3485 * @n_bd -- total number of entries in queue (s/b power of 2)
3486 */
3487 static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
3488 {
3489 return (index == 0) ? n_bd - 1 : index - 1;
3490 }
3491
3492 /**
3493 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
3494 *
3495 * Handles block-acknowledge notification from device, which reports success
3496 * of frames sent via aggregation.
3497 */
3498 static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
3499 struct iwl4965_rx_mem_buffer *rxb)
3500 {
3501 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3502 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
3503 int index;
3504 struct iwl4965_tx_queue *txq = NULL;
3505 struct iwl4965_ht_agg *agg;
3506 DECLARE_MAC_BUF(mac);
3507
3508 /* "flow" corresponds to Tx queue */
3509 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3510
3511 /* "ssn" is start of block-ack Tx window, corresponds to index
3512 * (in Tx queue's circular buffer) of first TFD/frame in window */
3513 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
3514
3515 if (scd_flow >= priv->hw_params.max_txq_num) {
3516 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
3517 return;
3518 }
3519
3520 txq = &priv->txq[scd_flow];
3521 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
3522
3523 /* Find index just before block-ack window */
3524 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
3525
3526 /* TODO: Need to get this copy more safely - now good for debug */
3527
3528 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
3529 "sta_id = %d\n",
3530 agg->wait_for_ba,
3531 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
3532 ba_resp->sta_id);
3533 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
3534 "%d, scd_ssn = %d\n",
3535 ba_resp->tid,
3536 ba_resp->seq_ctl,
3537 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
3538 ba_resp->scd_flow,
3539 ba_resp->scd_ssn);
3540 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
3541 agg->start_idx,
3542 (unsigned long long)agg->bitmap);
3543
3544 /* Update driver's record of ACK vs. not for each frame in window */
3545 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
3546
3547 /* Release all TFDs before the SSN, i.e. all TFDs in front of
3548 * block-ack window (we assume that they've been successfully
3549 * transmitted ... if not, it's too late anyway). */
3550 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
3551 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
3552 priv->stations[ba_resp->sta_id].
3553 tid[ba_resp->tid].tfds_in_queue -= freed;
3554 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3555 priv->mac80211_registered &&
3556 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3557 ieee80211_wake_queue(priv->hw, scd_flow);
3558 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
3559 ba_resp->tid, scd_flow);
3560 }
3561 }
3562
3563 /**
3564 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
3565 */
3566 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
3567 u16 txq_id)
3568 {
3569 u32 tbl_dw_addr;
3570 u32 tbl_dw;
3571 u16 scd_q2ratid;
3572
3573 scd_q2ratid = ra_tid & IWL49_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
3574
3575 tbl_dw_addr = priv->scd_base_addr +
3576 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
3577
3578 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
3579
3580 if (txq_id & 0x1)
3581 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
3582 else
3583 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
3584
3585 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
3586
3587 return 0;
3588 }
3589
3590
3591 /**
3592 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
3593 *
3594 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
3595 * i.e. it must be one of the higher queues used for aggregation
3596 */
3597 static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
3598 int tx_fifo, int sta_id, int tid,
3599 u16 ssn_idx)
3600 {
3601 unsigned long flags;
3602 int rc;
3603 u16 ra_tid;
3604
3605 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
3606 IWL_WARNING("queue number too small: %d, must be > %d\n",
3607 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3608
3609 ra_tid = BUILD_RAxTID(sta_id, tid);
3610
3611 /* Modify device's station table to Tx this TID */
3612 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
3613
3614 spin_lock_irqsave(&priv->lock, flags);
3615 rc = iwl_grab_nic_access(priv);
3616 if (rc) {
3617 spin_unlock_irqrestore(&priv->lock, flags);
3618 return rc;
3619 }
3620
3621 /* Stop this Tx queue before configuring it */
3622 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3623
3624 /* Map receiver-address / traffic-ID to this queue */
3625 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
3626
3627 /* Set this queue as a chain-building queue */
3628 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3629
3630 /* Place first TFD at index corresponding to start sequence number.
3631 * Assumes that ssn_idx is valid (!= 0xFFF) */
3632 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3633 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3634 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3635
3636 /* Set up Tx window size and frame limit for this queue */
3637 iwl_write_targ_mem(priv,
3638 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
3639 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
3640 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
3641
3642 iwl_write_targ_mem(priv, priv->scd_base_addr +
3643 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
3644 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
3645 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
3646
3647 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3648
3649 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
3650 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
3651
3652 iwl_release_nic_access(priv);
3653 spin_unlock_irqrestore(&priv->lock, flags);
3654
3655 return 0;
3656 }
3657
3658 #endif /* CONFIG_IWL4965_HT */
3659
3660 /**
3661 * iwl4965_add_station - Initialize a station's hardware rate table
3662 *
3663 * The uCode's station table contains a table of fallback rates
3664 * for automatic fallback during transmission.
3665 *
3666 * NOTE: This sets up a default set of values. These will be replaced later
3667 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
3668 * rc80211_simple.
3669 *
3670 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
3671 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
3672 * which requires station table entry to exist).
3673 */
3674 void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
3675 {
3676 int i, r;
3677 struct iwl_link_quality_cmd link_cmd = {
3678 .reserved1 = 0,
3679 };
3680 u16 rate_flags;
3681
3682 /* Set up the rate scaling to start at selected rate, fall back
3683 * all the way down to 1M in IEEE order, and then spin on 1M */
3684 if (is_ap)
3685 r = IWL_RATE_54M_INDEX;
3686 else if (priv->band == IEEE80211_BAND_5GHZ)
3687 r = IWL_RATE_6M_INDEX;
3688 else
3689 r = IWL_RATE_1M_INDEX;
3690
3691 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3692 rate_flags = 0;
3693 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
3694 rate_flags |= RATE_MCS_CCK_MSK;
3695
3696 /* Use Tx antenna B only */
3697 rate_flags |= RATE_MCS_ANT_B_MSK; /*FIXME:RS*/
3698
3699 link_cmd.rs_table[i].rate_n_flags =
3700 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
3701 r = iwl4965_get_prev_ieee_rate(r);
3702 }
3703
3704 link_cmd.general_params.single_stream_ant_msk = 2;
3705 link_cmd.general_params.dual_stream_ant_msk = 3;
3706 link_cmd.agg_params.agg_dis_start_th = 3;
3707 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
3708
3709 /* Update the rate scaling for control frame Tx to AP */
3710 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
3711
3712 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
3713 sizeof(link_cmd), &link_cmd, NULL);
3714 }
3715
3716 #ifdef CONFIG_IWL4965_HT
3717
3718 static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
3719 enum ieee80211_band band,
3720 u16 channel, u8 extension_chan_offset)
3721 {
3722 const struct iwl_channel_info *ch_info;
3723
3724 ch_info = iwl_get_channel_info(priv, band, channel);
3725 if (!is_channel_valid(ch_info))
3726 return 0;
3727
3728 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
3729 return 0;
3730
3731 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
3732 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
3733 return 1;
3734
3735 return 0;
3736 }
3737
3738 static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
3739 struct ieee80211_ht_info *sta_ht_inf)
3740 {
3741 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
3742
3743 if ((!iwl_ht_conf->is_ht) ||
3744 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
3745 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
3746 return 0;
3747
3748 if (sta_ht_inf) {
3749 if ((!sta_ht_inf->ht_supported) ||
3750 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
3751 return 0;
3752 }
3753
3754 return (iwl4965_is_channel_extension(priv, priv->band,
3755 iwl_ht_conf->control_channel,
3756 iwl_ht_conf->extension_chan_offset));
3757 }
3758
3759 void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
3760 {
3761 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
3762 u32 val;
3763
3764 if (!ht_info->is_ht)
3765 return;
3766
3767 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
3768 if (iwl4965_is_fat_tx_allowed(priv, NULL))
3769 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3770 else
3771 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
3772 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
3773
3774 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
3775 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
3776 le16_to_cpu(rxon->channel),
3777 ht_info->control_channel);
3778 rxon->channel = cpu_to_le16(ht_info->control_channel);
3779 return;
3780 }
3781
3782 /* Note: control channel is opposite of extension channel */
3783 switch (ht_info->extension_chan_offset) {
3784 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
3785 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
3786 break;
3787 case IWL_EXT_CHANNEL_OFFSET_BELOW:
3788 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
3789 break;
3790 case IWL_EXT_CHANNEL_OFFSET_NONE:
3791 default:
3792 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3793 break;
3794 }
3795
3796 val = ht_info->ht_protection;
3797
3798 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
3799
3800 iwl_set_rxon_chain(priv);
3801
3802 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
3803 "rxon flags 0x%X operation mode :0x%X "
3804 "extension channel offset 0x%x "
3805 "control chan %d\n",
3806 ht_info->supp_mcs_set[0],
3807 ht_info->supp_mcs_set[1],
3808 ht_info->supp_mcs_set[2],
3809 le32_to_cpu(rxon->flags), ht_info->ht_protection,
3810 ht_info->extension_chan_offset,
3811 ht_info->control_channel);
3812 return;
3813 }
3814
3815 void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
3816 struct ieee80211_ht_info *sta_ht_inf)
3817 {
3818 __le32 sta_flags;
3819 u8 mimo_ps_mode;
3820
3821 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
3822 goto done;
3823
3824 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
3825
3826 sta_flags = priv->stations[index].sta.station_flags;
3827
3828 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
3829
3830 switch (mimo_ps_mode) {
3831 case WLAN_HT_CAP_MIMO_PS_STATIC:
3832 sta_flags |= STA_FLG_MIMO_DIS_MSK;
3833 break;
3834 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
3835 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
3836 break;
3837 case WLAN_HT_CAP_MIMO_PS_DISABLED:
3838 break;
3839 default:
3840 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
3841 break;
3842 }
3843
3844 sta_flags |= cpu_to_le32(
3845 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
3846
3847 sta_flags |= cpu_to_le32(
3848 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
3849
3850 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
3851 sta_flags |= STA_FLG_FAT_EN_MSK;
3852 else
3853 sta_flags &= ~STA_FLG_FAT_EN_MSK;
3854
3855 priv->stations[index].sta.station_flags = sta_flags;
3856 done:
3857 return;
3858 }
3859
3860 static int iwl4965_rx_agg_start(struct iwl_priv *priv,
3861 const u8 *addr, int tid, u16 ssn)
3862 {
3863 unsigned long flags;
3864 int sta_id;
3865
3866 sta_id = iwl_find_station(priv, addr);
3867 if (sta_id == IWL_INVALID_STATION)
3868 return -ENXIO;
3869
3870 spin_lock_irqsave(&priv->sta_lock, flags);
3871 priv->stations[sta_id].sta.station_flags_msk = 0;
3872 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
3873 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
3874 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3875 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3876 spin_unlock_irqrestore(&priv->sta_lock, flags);
3877
3878 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
3879 CMD_ASYNC);
3880 }
3881
3882 static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
3883 const u8 *addr, int tid)
3884 {
3885 unsigned long flags;
3886 int sta_id;
3887
3888 sta_id = iwl_find_station(priv, addr);
3889 if (sta_id == IWL_INVALID_STATION)
3890 return -ENXIO;
3891
3892 spin_lock_irqsave(&priv->sta_lock, flags);
3893 priv->stations[sta_id].sta.station_flags_msk = 0;
3894 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
3895 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
3896 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3897 spin_unlock_irqrestore(&priv->sta_lock, flags);
3898
3899 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
3900 CMD_ASYNC);
3901 }
3902
3903 /*
3904 * Find first available (lowest unused) Tx Queue, mark it "active".
3905 * Called only when finding queue for aggregation.
3906 * Should never return anything < 7, because they should already
3907 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
3908 */
3909 static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
3910 {
3911 int txq_id;
3912
3913 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
3914 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
3915 return txq_id;
3916 return -1;
3917 }
3918
3919 static int iwl4965_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
3920 u16 tid, u16 *start_seq_num)
3921 {
3922 struct iwl_priv *priv = hw->priv;
3923 int sta_id;
3924 int tx_fifo;
3925 int txq_id;
3926 int ssn = -1;
3927 int ret = 0;
3928 unsigned long flags;
3929 struct iwl4965_tid_data *tid_data;
3930 DECLARE_MAC_BUF(mac);
3931
3932 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
3933 tx_fifo = default_tid_to_tx_fifo[tid];
3934 else
3935 return -EINVAL;
3936
3937 IWL_WARNING("%s on ra = %s tid = %d\n",
3938 __func__, print_mac(mac, ra), tid);
3939
3940 sta_id = iwl_find_station(priv, ra);
3941 if (sta_id == IWL_INVALID_STATION)
3942 return -ENXIO;
3943
3944 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
3945 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
3946 return -ENXIO;
3947 }
3948
3949 txq_id = iwl4965_txq_ctx_activate_free(priv);
3950 if (txq_id == -1)
3951 return -ENXIO;
3952
3953 spin_lock_irqsave(&priv->sta_lock, flags);
3954 tid_data = &priv->stations[sta_id].tid[tid];
3955 ssn = SEQ_TO_SN(tid_data->seq_number);
3956 tid_data->agg.txq_id = txq_id;
3957 spin_unlock_irqrestore(&priv->sta_lock, flags);
3958
3959 *start_seq_num = ssn;
3960 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
3961 sta_id, tid, ssn);
3962 if (ret)
3963 return ret;
3964
3965 ret = 0;
3966 if (tid_data->tfds_in_queue == 0) {
3967 printk(KERN_ERR "HW queue is empty\n");
3968 tid_data->agg.state = IWL_AGG_ON;
3969 ieee80211_start_tx_ba_cb_irqsafe(hw, ra, tid);
3970 } else {
3971 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
3972 tid_data->tfds_in_queue);
3973 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
3974 }
3975 return ret;
3976 }
3977
3978 static int iwl4965_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid)
3979 {
3980 struct iwl_priv *priv = hw->priv;
3981 int tx_fifo_id, txq_id, sta_id, ssn = -1;
3982 struct iwl4965_tid_data *tid_data;
3983 int ret, write_ptr, read_ptr;
3984 unsigned long flags;
3985 DECLARE_MAC_BUF(mac);
3986
3987 if (!ra) {
3988 IWL_ERROR("ra = NULL\n");
3989 return -EINVAL;
3990 }
3991
3992 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
3993 tx_fifo_id = default_tid_to_tx_fifo[tid];
3994 else
3995 return -EINVAL;
3996
3997 sta_id = iwl_find_station(priv, ra);
3998
3999 if (sta_id == IWL_INVALID_STATION)
4000 return -ENXIO;
4001
4002 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4003 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4004
4005 tid_data = &priv->stations[sta_id].tid[tid];
4006 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4007 txq_id = tid_data->agg.txq_id;
4008 write_ptr = priv->txq[txq_id].q.write_ptr;
4009 read_ptr = priv->txq[txq_id].q.read_ptr;
4010
4011 /* The queue is not empty */
4012 if (write_ptr != read_ptr) {
4013 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4014 priv->stations[sta_id].tid[tid].agg.state =
4015 IWL_EMPTYING_HW_QUEUE_DELBA;
4016 return 0;
4017 }
4018
4019 IWL_DEBUG_HT("HW queue is empty\n");
4020 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
4021
4022 spin_lock_irqsave(&priv->lock, flags);
4023 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
4024 spin_unlock_irqrestore(&priv->lock, flags);
4025
4026 if (ret)
4027 return ret;
4028
4029 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
4030
4031 return 0;
4032 }
4033
4034 int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4035 enum ieee80211_ampdu_mlme_action action,
4036 const u8 *addr, u16 tid, u16 *ssn)
4037 {
4038 struct iwl_priv *priv = hw->priv;
4039 DECLARE_MAC_BUF(mac);
4040
4041 IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
4042 print_mac(mac, addr), tid);
4043
4044 switch (action) {
4045 case IEEE80211_AMPDU_RX_START:
4046 IWL_DEBUG_HT("start Rx\n");
4047 return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
4048 case IEEE80211_AMPDU_RX_STOP:
4049 IWL_DEBUG_HT("stop Rx\n");
4050 return iwl4965_rx_agg_stop(priv, addr, tid);
4051 case IEEE80211_AMPDU_TX_START:
4052 IWL_DEBUG_HT("start Tx\n");
4053 return iwl4965_tx_agg_start(hw, addr, tid, ssn);
4054 case IEEE80211_AMPDU_TX_STOP:
4055 IWL_DEBUG_HT("stop Tx\n");
4056 return iwl4965_tx_agg_stop(hw, addr, tid);
4057 default:
4058 IWL_DEBUG_HT("unknown\n");
4059 return -EINVAL;
4060 break;
4061 }
4062 return 0;
4063 }
4064
4065 #endif /* CONFIG_IWL4965_HT */
4066
4067 /* Set up 4965-specific Rx frame reply handlers */
4068 void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
4069 {
4070 /* Legacy Rx frames */
4071 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
4072
4073 /* High-throughput (HT) Rx frames */
4074 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4075 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4076
4077 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4078 iwl4965_rx_missed_beacon_notif;
4079
4080 #ifdef CONFIG_IWL4965_HT
4081 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
4082 #endif /* CONFIG_IWL4965_HT */
4083 }
4084
4085 void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
4086 {
4087 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
4088 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4089 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4090 #endif
4091 init_timer(&priv->statistics_periodic);
4092 priv->statistics_periodic.data = (unsigned long)priv;
4093 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4094 }
4095
4096 void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
4097 {
4098 del_timer_sync(&priv->statistics_periodic);
4099
4100 cancel_delayed_work(&priv->init_alive_start);
4101 }
4102
4103
4104 static struct iwl_hcmd_ops iwl4965_hcmd = {
4105 .rxon_assoc = iwl4965_send_rxon_assoc,
4106 };
4107
4108 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4109 .enqueue_hcmd = iwl4965_enqueue_hcmd,
4110 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4111 .chain_noise_reset = iwl4965_chain_noise_reset,
4112 .gain_computation = iwl4965_gain_computation,
4113 #endif
4114 };
4115
4116 static struct iwl_lib_ops iwl4965_lib = {
4117 .set_hw_params = iwl4965_hw_set_hw_params,
4118 .alloc_shared_mem = iwl4965_alloc_shared_mem,
4119 .free_shared_mem = iwl4965_free_shared_mem,
4120 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
4121 .hw_nic_init = iwl4965_hw_nic_init,
4122 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4123 .alive_notify = iwl4965_alive_notify,
4124 .load_ucode = iwl4965_load_bsm,
4125 .apm_ops = {
4126 .init = iwl4965_apm_init,
4127 .set_pwr_src = iwl4965_set_pwr_src,
4128 },
4129 .eeprom_ops = {
4130 .regulatory_bands = {
4131 EEPROM_REGULATORY_BAND_1_CHANNELS,
4132 EEPROM_REGULATORY_BAND_2_CHANNELS,
4133 EEPROM_REGULATORY_BAND_3_CHANNELS,
4134 EEPROM_REGULATORY_BAND_4_CHANNELS,
4135 EEPROM_REGULATORY_BAND_5_CHANNELS,
4136 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
4137 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
4138 },
4139 .verify_signature = iwlcore_eeprom_verify_signature,
4140 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4141 .release_semaphore = iwlcore_eeprom_release_semaphore,
4142 .check_version = iwl4965_eeprom_check_version,
4143 .query_addr = iwlcore_eeprom_query_addr,
4144 },
4145 .radio_kill_sw = iwl4965_radio_kill_sw,
4146 .set_power = iwl4965_set_power,
4147 .update_chain_flags = iwl4965_update_chain_flags,
4148 };
4149
4150 static struct iwl_ops iwl4965_ops = {
4151 .lib = &iwl4965_lib,
4152 .hcmd = &iwl4965_hcmd,
4153 .utils = &iwl4965_hcmd_utils,
4154 };
4155
4156 struct iwl_cfg iwl4965_agn_cfg = {
4157 .name = "4965AGN",
4158 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
4159 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
4160 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
4161 .ops = &iwl4965_ops,
4162 .mod_params = &iwl4965_mod_params,
4163 };
4164
4165 module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4166 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4167 module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4168 MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
4169 module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
4170 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
4171 module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4172 MODULE_PARM_DESC(debug, "debug output mask");
4173 module_param_named(
4174 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
4175 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4176
4177 module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
4178 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4179
4180 /* QoS */
4181 module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
4182 MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
4183 module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
4184 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4185
AMDTP streaming driver for the Linux FireWire stack (Juju)