?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[CRYPTO] hifn_795x: Detect weak keys
[firewire-audio.git] / drivers / crypto / hifn_795x.c
blob391c20a3dff8708bac6a31e6c023db832597f0ad
1 /*
2 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/mm.h>
28 #include <linux/highmem.h>
29 #include <linux/crypto.h>
30
31 #include <crypto/algapi.h>
32 #include <crypto/des.h>
33
34 #include <asm/kmap_types.h>
35
36 #undef dprintk
37
38 #define HIFN_TEST
39 //#define HIFN_DEBUG
40
41 #ifdef HIFN_DEBUG
42 #define dprintk(f, a...) printk(f, ##a)
43 #else
44 #define dprintk(f, a...) do {} while (0)
45 #endif
46
47 static atomic_t hifn_dev_number;
48
49 #define ACRYPTO_OP_DECRYPT 0
50 #define ACRYPTO_OP_ENCRYPT 1
51 #define ACRYPTO_OP_HMAC 2
52 #define ACRYPTO_OP_RNG 3
53
54 #define ACRYPTO_MODE_ECB 0
55 #define ACRYPTO_MODE_CBC 1
56 #define ACRYPTO_MODE_CFB 2
57 #define ACRYPTO_MODE_OFB 3
58
59 #define ACRYPTO_TYPE_AES_128 0
60 #define ACRYPTO_TYPE_AES_192 1
61 #define ACRYPTO_TYPE_AES_256 2
62 #define ACRYPTO_TYPE_3DES 3
63 #define ACRYPTO_TYPE_DES 4
64
65 #define PCI_VENDOR_ID_HIFN 0x13A3
66 #define PCI_DEVICE_ID_HIFN_7955 0x0020
67 #define PCI_DEVICE_ID_HIFN_7956 0x001d
68
69 /* I/O region sizes */
70
71 #define HIFN_BAR0_SIZE 0x1000
72 #define HIFN_BAR1_SIZE 0x2000
73 #define HIFN_BAR2_SIZE 0x8000
74
75 /* DMA registres */
76
77 #define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */
78 #define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */
79 #define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */
80 #define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */
81 #define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */
82 #define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */
83 #define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */
84 #define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */
85 #define HIFN_CHIP_ID 0x98 /* Chip ID */
86
87 /*
88 * Processing Unit Registers (offset from BASEREG0)
89 */
90 #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
91 #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
92 #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
93 #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
94 #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
95 #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
96 #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
97 #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
98 #define HIFN_0_SPACESIZE 0x20 /* Register space size */
99
100 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
101 #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
102 #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */
103 #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */
104 #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */
105 #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */
106
107 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
108 #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */
109 #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */
110 #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
111 #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
112 #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */
113 #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */
114 #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */
115 #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */
116 #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */
117 #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */
118
119 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
120 #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */
121 #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */
122 #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */
123 #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
124 #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
125 #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
126 #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
127 #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
128 #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
129 #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */
130 #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */
131 #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */
132 #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */
133 #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */
134 #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */
135 #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */
136 #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */
137 #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */
138 #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */
139 #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */
140 #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */
141 #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */
142 #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */
143
144 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
145 #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */
146 #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */
147 #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
148 #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
149 #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */
150 #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */
151 #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */
152 #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */
153 #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */
154 #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */
155
156 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
157 #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */
158 #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */
159 #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
160 #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
161 #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */
162 #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */
163 #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */
164 #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */
165 #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */
166 #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */
167 #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */
168 #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */
169 #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */
170 #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */
171 #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */
172 #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */
173 #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
174
175 /* FIFO Status Register (HIFN_0_FIFOSTAT) */
176 #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */
177 #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
178
179 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
180 #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */
181
182 /*
183 * DMA Interface Registers (offset from BASEREG1)
184 */
185 #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
186 #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
187 #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */
188 #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
189 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
190 #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
191 #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
192 #define HIFN_1_PLL 0x4c /* 795x: PLL config */
193 #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */
194 #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
195 #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
196 #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */
197 #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
198 #define HIFN_1_REVID 0x98 /* Revision ID */
199 #define HIFN_1_UNLOCK_SECRET1 0xf4
200 #define HIFN_1_UNLOCK_SECRET2 0xfc
201 #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */
202 #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */
203 #define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */
204 #define HIFN_1_PUB_OP 0x308 /* Public Operand */
205 #define HIFN_1_PUB_STATUS 0x30c /* Public Status */
206 #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */
207 #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */
208 #define HIFN_1_RNG_DATA 0x318 /* RNG data */
209 #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */
210 #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */
211
212 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
213 #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
214 #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
215 #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */
216 #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */
217 #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
218 #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
219 #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
220 #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
221 #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
222 #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
223 #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
224 #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */
225 #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */
226 #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
227 #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
228 #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
229 #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
230 #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
231 #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
232 #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
233 #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */
234 #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */
235 #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
236 #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
237 #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
238 #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
239 #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */
240 #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */
241 #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
242 #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
243 #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */
244 #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */
245 #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
246 #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
247 #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
248 #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
249 #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */
250 #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */
251
252 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
253 #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
254 #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
255 #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
256 #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
257 #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
258 #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
259 #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
260 #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
261 #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
262 #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
263 #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
264 #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
265 #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
266 #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
267 #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */
268 #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */
269 #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
270 #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
271 #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
272 #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
273 #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */
274 #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */
275
276 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
277 #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */
278 #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */
279 #define HIFN_DMACNFG_UNLOCK 0x00000800
280 #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */
281 #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */
282 #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */
283 #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
284 #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
285
286 #define HIFN_PLL_7956 0x00001d18 /* 7956 PLL config value */
287
288 /* Public key reset register (HIFN_1_PUB_RESET) */
289 #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */
290
291 /* Public base address register (HIFN_1_PUB_BASE) */
292 #define HIFN_PUBBASE_ADDR 0x00003fff /* base address */
293
294 /* Public operand length register (HIFN_1_PUB_OPLEN) */
295 #define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */
296 #define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */
297 #define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */
298 #define HIFN_PUBOPLEN_EXP_S 7 /* exponent lenght shift */
299 #define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */
300 #define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */
301
302 /* Public operation register (HIFN_1_PUB_OP) */
303 #define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */
304 #define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */
305 #define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */
306 #define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */
307 #define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */
308 #define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */
309 #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */
310 #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */
311 #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */
312 #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */
313 #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */
314 #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */
315 #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */
316 #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */
317 #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */
318 #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */
319 #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */
320 #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */
321 #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */
322 #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */
323
324 /* Public status register (HIFN_1_PUB_STATUS) */
325 #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */
326 #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */
327
328 /* Public interrupt enable register (HIFN_1_PUB_IEN) */
329 #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */
330
331 /* Random number generator config register (HIFN_1_RNG_CONFIG) */
332 #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */
333
334 #define HIFN_NAMESIZE 32
335 #define HIFN_MAX_RESULT_ORDER 5
336
337 #define HIFN_D_CMD_RSIZE 24*4
338 #define HIFN_D_SRC_RSIZE 80*4
339 #define HIFN_D_DST_RSIZE 80*4
340 #define HIFN_D_RES_RSIZE 24*4
341
342 #define HIFN_QUEUE_LENGTH HIFN_D_CMD_RSIZE-5
343
344 #define AES_MIN_KEY_SIZE 16
345 #define AES_MAX_KEY_SIZE 32
346
347 #define HIFN_DES_KEY_LENGTH 8
348 #define HIFN_3DES_KEY_LENGTH 24
349 #define HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE
350 #define HIFN_IV_LENGTH 8
351 #define HIFN_AES_IV_LENGTH 16
352 #define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH
353
354 #define HIFN_MAC_KEY_LENGTH 64
355 #define HIFN_MD5_LENGTH 16
356 #define HIFN_SHA1_LENGTH 20
357 #define HIFN_MAC_TRUNC_LENGTH 12
358
359 #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260)
360 #define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4)
361 #define HIFN_USED_RESULT 12
362
363 struct hifn_desc
364 {
365 volatile u32 l;
366 volatile u32 p;
367 };
368
369 struct hifn_dma {
370 struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1];
371 struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1];
372 struct hifn_desc dstr[HIFN_D_DST_RSIZE+1];
373 struct hifn_desc resr[HIFN_D_RES_RSIZE+1];
374
375 u8 command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
376 u8 result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
377
378 u64 test_src, test_dst;
379
380 /*
381 * Our current positions for insertion and removal from the descriptor
382 * rings.
383 */
384 volatile int cmdi, srci, dsti, resi;
385 volatile int cmdu, srcu, dstu, resu;
386 int cmdk, srck, dstk, resk;
387 };
388
389 #define HIFN_FLAG_CMD_BUSY (1<<0)
390 #define HIFN_FLAG_SRC_BUSY (1<<1)
391 #define HIFN_FLAG_DST_BUSY (1<<2)
392 #define HIFN_FLAG_RES_BUSY (1<<3)
393 #define HIFN_FLAG_OLD_KEY (1<<4)
394
395 #define HIFN_DEFAULT_ACTIVE_NUM 5
396
397 struct hifn_device
398 {
399 char name[HIFN_NAMESIZE];
400
401 int irq;
402
403 struct pci_dev *pdev;
404 void __iomem *bar[3];
405
406 unsigned long result_mem;
407 dma_addr_t dst;
408
409 void *desc_virt;
410 dma_addr_t desc_dma;
411
412 u32 dmareg;
413
414 void *sa[HIFN_D_RES_RSIZE];
415
416 spinlock_t lock;
417
418 void *priv;
419
420 u32 flags;
421 int active, started;
422 struct delayed_work work;
423 unsigned long reset;
424 unsigned long success;
425 unsigned long prev_success;
426
427 u8 snum;
428
429 struct crypto_queue queue;
430 struct list_head alg_list;
431 };
432
433 #define HIFN_D_LENGTH 0x0000ffff
434 #define HIFN_D_NOINVALID 0x01000000
435 #define HIFN_D_MASKDONEIRQ 0x02000000
436 #define HIFN_D_DESTOVER 0x04000000
437 #define HIFN_D_OVER 0x08000000
438 #define HIFN_D_LAST 0x20000000
439 #define HIFN_D_JUMP 0x40000000
440 #define HIFN_D_VALID 0x80000000
441
442 struct hifn_base_command
443 {
444 volatile u16 masks;
445 volatile u16 session_num;
446 volatile u16 total_source_count;
447 volatile u16 total_dest_count;
448 };
449
450 #define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */
451 #define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */
452 #define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */
453 #define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */
454 #define HIFN_BASE_CMD_DECODE 0x2000
455 #define HIFN_BASE_CMD_SRCLEN_M 0xc000
456 #define HIFN_BASE_CMD_SRCLEN_S 14
457 #define HIFN_BASE_CMD_DSTLEN_M 0x3000
458 #define HIFN_BASE_CMD_DSTLEN_S 12
459 #define HIFN_BASE_CMD_LENMASK_HI 0x30000
460 #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff
461
462 /*
463 * Structure to help build up the command data structure.
464 */
465 struct hifn_crypt_command
466 {
467 volatile u16 masks;
468 volatile u16 header_skip;
469 volatile u16 source_count;
470 volatile u16 reserved;
471 };
472
473 #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */
474 #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */
475 #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */
476 #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */
477 #define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */
478 #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */
479 #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */
480 #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */
481 #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */
482 #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */
483 #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */
484 #define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */
485 #define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */
486 #define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */
487 #define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */
488 #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */
489 #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */
490 #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000
491 #define HIFN_CRYPT_CMD_SRCLEN_S 14
492
493 /*
494 * Structure to help build up the command data structure.
495 */
496 struct hifn_mac_command
497 {
498 volatile u16 masks;
499 volatile u16 header_skip;
500 volatile u16 source_count;
501 volatile u16 reserved;
502 };
503
504 #define HIFN_MAC_CMD_ALG_MASK 0x0001
505 #define HIFN_MAC_CMD_ALG_SHA1 0x0000
506 #define HIFN_MAC_CMD_ALG_MD5 0x0001
507 #define HIFN_MAC_CMD_MODE_MASK 0x000c
508 #define HIFN_MAC_CMD_MODE_HMAC 0x0000
509 #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004
510 #define HIFN_MAC_CMD_MODE_HASH 0x0008
511 #define HIFN_MAC_CMD_MODE_FULL 0x0004
512 #define HIFN_MAC_CMD_TRUNC 0x0010
513 #define HIFN_MAC_CMD_RESULT 0x0020
514 #define HIFN_MAC_CMD_APPEND 0x0040
515 #define HIFN_MAC_CMD_SRCLEN_M 0xc000
516 #define HIFN_MAC_CMD_SRCLEN_S 14
517
518 /*
519 * MAC POS IPsec initiates authentication after encryption on encodes
520 * and before decryption on decodes.
521 */
522 #define HIFN_MAC_CMD_POS_IPSEC 0x0200
523 #define HIFN_MAC_CMD_NEW_KEY 0x0800
524
525 struct hifn_comp_command
526 {
527 volatile u16 masks;
528 volatile u16 header_skip;
529 volatile u16 source_count;
530 volatile u16 reserved;
531 };
532
533 #define HIFN_COMP_CMD_SRCLEN_M 0xc000
534 #define HIFN_COMP_CMD_SRCLEN_S 14
535 #define HIFN_COMP_CMD_ONE 0x0100 /* must be one */
536 #define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */
537 #define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */
538 #define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */
539 #define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */
540 #define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */
541 #define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */
542 #define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */
543
544 struct hifn_base_result
545 {
546 volatile u16 flags;
547 volatile u16 session;
548 volatile u16 src_cnt; /* 15:0 of source count */
549 volatile u16 dst_cnt; /* 15:0 of dest count */
550 };
551
552 #define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */
553 #define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */
554 #define HIFN_BASE_RES_SRCLEN_S 14
555 #define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */
556 #define HIFN_BASE_RES_DSTLEN_S 12
557
558 struct hifn_comp_result
559 {
560 volatile u16 flags;
561 volatile u16 crc;
562 };
563
564 #define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */
565 #define HIFN_COMP_RES_LCB_S 8
566 #define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */
567 #define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */
568 #define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */
569
570 struct hifn_mac_result
571 {
572 volatile u16 flags;
573 volatile u16 reserved;
574 /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
575 };
576
577 #define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */
578 #define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */
579
580 struct hifn_crypt_result
581 {
582 volatile u16 flags;
583 volatile u16 reserved;
584 };
585
586 #define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */
587
588 #ifndef HIFN_POLL_FREQUENCY
589 #define HIFN_POLL_FREQUENCY 0x1
590 #endif
591
592 #ifndef HIFN_POLL_SCALAR
593 #define HIFN_POLL_SCALAR 0x0
594 #endif
595
596 #define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
597 #define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */
598
599 struct hifn_crypto_alg
600 {
601 struct list_head entry;
602 struct crypto_alg alg;
603 struct hifn_device *dev;
604 };
605
606 #define ASYNC_SCATTERLIST_CACHE 16
607
608 #define ASYNC_FLAGS_MISALIGNED (1<<0)
609
610 struct ablkcipher_walk
611 {
612 struct scatterlist cache[ASYNC_SCATTERLIST_CACHE];
613 u32 flags;
614 int num;
615 };
616
617 struct hifn_context
618 {
619 u8 key[HIFN_MAX_CRYPT_KEY_LENGTH], *iv;
620 struct hifn_device *dev;
621 unsigned int keysize, ivsize;
622 u8 op, type, mode, unused;
623 struct ablkcipher_walk walk;
624 atomic_t sg_num;
625 };
626
627 #define crypto_alg_to_hifn(alg) container_of(alg, struct hifn_crypto_alg, alg)
628
629 static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg)
630 {
631 u32 ret;
632
633 ret = readl((char *)(dev->bar[0]) + reg);
634
635 return ret;
636 }
637
638 static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg)
639 {
640 u32 ret;
641
642 ret = readl((char *)(dev->bar[1]) + reg);
643
644 return ret;
645 }
646
647 static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val)
648 {
649 writel(val, (char *)(dev->bar[0]) + reg);
650 }
651
652 static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)
653 {
654 writel(val, (char *)(dev->bar[1]) + reg);
655 }
656
657 static void hifn_wait_puc(struct hifn_device *dev)
658 {
659 int i;
660 u32 ret;
661
662 for (i=10000; i > 0; --i) {
663 ret = hifn_read_0(dev, HIFN_0_PUCTRL);
664 if (!(ret & HIFN_PUCTRL_RESET))
665 break;
666
667 udelay(1);
668 }
669
670 if (!i)
671 dprintk("%s: Failed to reset PUC unit.\n", dev->name);
672 }
673
674 static void hifn_reset_puc(struct hifn_device *dev)
675 {
676 hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
677 hifn_wait_puc(dev);
678 }
679
680 static void hifn_stop_device(struct hifn_device *dev)
681 {
682 hifn_write_1(dev, HIFN_1_DMA_CSR,
683 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
684 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS);
685 hifn_write_0(dev, HIFN_0_PUIER, 0);
686 hifn_write_1(dev, HIFN_1_DMA_IER, 0);
687 }
688
689 static void hifn_reset_dma(struct hifn_device *dev, int full)
690 {
691 hifn_stop_device(dev);
692
693 /*
694 * Setting poll frequency and others to 0.
695 */
696 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
697 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
698 mdelay(1);
699
700 /*
701 * Reset DMA.
702 */
703 if (full) {
704 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
705 mdelay(1);
706 } else {
707 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |
708 HIFN_DMACNFG_MSTRESET);
709 hifn_reset_puc(dev);
710 }
711
712 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
713 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
714
715 hifn_reset_puc(dev);
716 }
717
718 static u32 hifn_next_signature(u_int32_t a, u_int cnt)
719 {
720 int i;
721 u32 v;
722
723 for (i = 0; i < cnt; i++) {
724
725 /* get the parity */
726 v = a & 0x80080125;
727 v ^= v >> 16;
728 v ^= v >> 8;
729 v ^= v >> 4;
730 v ^= v >> 2;
731 v ^= v >> 1;
732
733 a = (v & 1) ^ (a << 1);
734 }
735
736 return a;
737 }
738
739 static struct pci2id {
740 u_short pci_vendor;
741 u_short pci_prod;
742 char card_id[13];
743 } pci2id[] = {
744 {
745 PCI_VENDOR_ID_HIFN,
746 PCI_DEVICE_ID_HIFN_7955,
747 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
748 0x00, 0x00, 0x00, 0x00, 0x00 }
749 },
750 {
751 PCI_VENDOR_ID_HIFN,
752 PCI_DEVICE_ID_HIFN_7956,
753 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
754 0x00, 0x00, 0x00, 0x00, 0x00 }
755 }
756 };
757
758 static int hifn_init_pubrng(struct hifn_device *dev)
759 {
760 int i;
761
762 hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
763 HIFN_PUBRST_RESET);
764
765 for (i=100; i > 0; --i) {
766 mdelay(1);
767
768 if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0)
769 break;
770 }
771
772 if (!i)
773 dprintk("Chip %s: Failed to initialise public key engine.\n",
774 dev->name);
775 else {
776 hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
777 dev->dmareg |= HIFN_DMAIER_PUBDONE;
778 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
779
780 dprintk("Chip %s: Public key engine has been sucessfully "
781 "initialised.\n", dev->name);
782 }
783
784 /*
785 * Enable RNG engine.
786 */
787
788 hifn_write_1(dev, HIFN_1_RNG_CONFIG,
789 hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA);
790 dprintk("Chip %s: RNG engine has been successfully initialised.\n",
791 dev->name);
792
793 return 0;
794 }
795
796 static int hifn_enable_crypto(struct hifn_device *dev)
797 {
798 u32 dmacfg, addr;
799 char *offtbl = NULL;
800 int i;
801
802 for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) {
803 if (pci2id[i].pci_vendor == dev->pdev->vendor &&
804 pci2id[i].pci_prod == dev->pdev->device) {
805 offtbl = pci2id[i].card_id;
806 break;
807 }
808 }
809
810 if (offtbl == NULL) {
811 dprintk("Chip %s: Unknown card!\n", dev->name);
812 return -ENODEV;
813 }
814
815 dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG);
816
817 hifn_write_1(dev, HIFN_1_DMA_CNFG,
818 HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET |
819 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
820 mdelay(1);
821 addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1);
822 mdelay(1);
823 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
824 mdelay(1);
825
826 for (i=0; i<12; ++i) {
827 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
828 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
829
830 mdelay(1);
831 }
832 hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
833
834 dprintk("Chip %s: %s.\n", dev->name, pci_name(dev->pdev));
835
836 return 0;
837 }
838
839 static void hifn_init_dma(struct hifn_device *dev)
840 {
841 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
842 u32 dptr = dev->desc_dma;
843 int i;
844
845 for (i=0; i<HIFN_D_CMD_RSIZE; ++i)
846 dma->cmdr[i].p = __cpu_to_le32(dptr +
847 offsetof(struct hifn_dma, command_bufs[i][0]));
848 for (i=0; i<HIFN_D_RES_RSIZE; ++i)
849 dma->resr[i].p = __cpu_to_le32(dptr +
850 offsetof(struct hifn_dma, result_bufs[i][0]));
851
852 /*
853 * Setup LAST descriptors.
854 */
855 dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr +
856 offsetof(struct hifn_dma, cmdr[0]));
857 dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr +
858 offsetof(struct hifn_dma, srcr[0]));
859 dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr +
860 offsetof(struct hifn_dma, dstr[0]));
861 dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr +
862 offsetof(struct hifn_dma, resr[0]));
863
864 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
865 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
866 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
867 }
868
869 static void hifn_init_registers(struct hifn_device *dev)
870 {
871 u32 dptr = dev->desc_dma;
872
873 /* Initialization magic... */
874 hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
875 hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
876 hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
877
878 /* write all 4 ring address registers */
879 hifn_write_1(dev, HIFN_1_DMA_CRAR, __cpu_to_le32(dptr +
880 offsetof(struct hifn_dma, cmdr[0])));
881 hifn_write_1(dev, HIFN_1_DMA_SRAR, __cpu_to_le32(dptr +
882 offsetof(struct hifn_dma, srcr[0])));
883 hifn_write_1(dev, HIFN_1_DMA_DRAR, __cpu_to_le32(dptr +
884 offsetof(struct hifn_dma, dstr[0])));
885 hifn_write_1(dev, HIFN_1_DMA_RRAR, __cpu_to_le32(dptr +
886 offsetof(struct hifn_dma, resr[0])));
887
888 mdelay(2);
889 #if 0
890 hifn_write_1(dev, HIFN_1_DMA_CSR,
891 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
892 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
893 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
894 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
895 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
896 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
897 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
898 HIFN_DMACSR_S_WAIT |
899 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
900 HIFN_DMACSR_C_WAIT |
901 HIFN_DMACSR_ENGINE |
902 HIFN_DMACSR_PUBDONE);
903 #else
904 hifn_write_1(dev, HIFN_1_DMA_CSR,
905 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
906 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA |
907 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
908 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
909 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
910 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
911 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
912 HIFN_DMACSR_S_WAIT |
913 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
914 HIFN_DMACSR_C_WAIT |
915 HIFN_DMACSR_ENGINE |
916 HIFN_DMACSR_PUBDONE);
917 #endif
918 hifn_read_1(dev, HIFN_1_DMA_CSR);
919
920 dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
921 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
922 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
923 HIFN_DMAIER_ENGINE;
924 dev->dmareg &= ~HIFN_DMAIER_C_WAIT;
925
926 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
927 hifn_read_1(dev, HIFN_1_DMA_IER);
928 #if 0
929 hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG |
930 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
931 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
932 HIFN_PUCNFG_DRAM);
933 #else
934 hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342);
935 #endif
936 hifn_write_1(dev, HIFN_1_PLL, HIFN_PLL_7956);
937
938 hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
939 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
940 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
941 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
942 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
943 }
944
945 static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf,
946 unsigned dlen, unsigned slen, u16 mask, u8 snum)
947 {
948 struct hifn_base_command *base_cmd;
949 u8 *buf_pos = buf;
950
951 base_cmd = (struct hifn_base_command *)buf_pos;
952 base_cmd->masks = __cpu_to_le16(mask);
953 base_cmd->total_source_count =
954 __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO);
955 base_cmd->total_dest_count =
956 __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO);
957
958 dlen >>= 16;
959 slen >>= 16;
960 base_cmd->session_num = __cpu_to_le16(snum |
961 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
962 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
963
964 return sizeof(struct hifn_base_command);
965 }
966
967 static int hifn_setup_crypto_command(struct hifn_device *dev,
968 u8 *buf, unsigned dlen, unsigned slen,
969 u8 *key, int keylen, u8 *iv, int ivsize, u16 mode)
970 {
971 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
972 struct hifn_crypt_command *cry_cmd;
973 u8 *buf_pos = buf;
974 u16 cmd_len;
975
976 cry_cmd = (struct hifn_crypt_command *)buf_pos;
977
978 cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff);
979 dlen >>= 16;
980 cry_cmd->masks = __cpu_to_le16(mode |
981 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) &
982 HIFN_CRYPT_CMD_SRCLEN_M));
983 cry_cmd->header_skip = 0;
984 cry_cmd->reserved = 0;
985
986 buf_pos += sizeof(struct hifn_crypt_command);
987
988 dma->cmdu++;
989 if (dma->cmdu > 1) {
990 dev->dmareg |= HIFN_DMAIER_C_WAIT;
991 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
992 }
993
994 if (keylen) {
995 memcpy(buf_pos, key, keylen);
996 buf_pos += keylen;
997 }
998 if (ivsize) {
999 memcpy(buf_pos, iv, ivsize);
1000 buf_pos += ivsize;
1001 }
1002
1003 cmd_len = buf_pos - buf;
1004
1005 return cmd_len;
1006 }
1007
1008 static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page,
1009 unsigned int offset, unsigned int size)
1010 {
1011 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1012 int idx;
1013 dma_addr_t addr;
1014
1015 addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE);
1016
1017 idx = dma->srci;
1018
1019 dma->srcr[idx].p = __cpu_to_le32(addr);
1020 dma->srcr[idx].l = __cpu_to_le32(size) | HIFN_D_VALID |
1021 HIFN_D_MASKDONEIRQ | HIFN_D_NOINVALID | HIFN_D_LAST;
1022
1023 if (++idx == HIFN_D_SRC_RSIZE) {
1024 dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1025 HIFN_D_JUMP |
1026 HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
1027 idx = 0;
1028 }
1029
1030 dma->srci = idx;
1031 dma->srcu++;
1032
1033 if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) {
1034 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1035 dev->flags |= HIFN_FLAG_SRC_BUSY;
1036 }
1037
1038 return size;
1039 }
1040
1041 static void hifn_setup_res_desc(struct hifn_device *dev)
1042 {
1043 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1044
1045 dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT |
1046 HIFN_D_VALID | HIFN_D_LAST);
1047 /*
1048 * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID |
1049 * HIFN_D_LAST | HIFN_D_NOINVALID);
1050 */
1051
1052 if (++dma->resi == HIFN_D_RES_RSIZE) {
1053 dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID |
1054 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
1055 dma->resi = 0;
1056 }
1057
1058 dma->resu++;
1059
1060 if (!(dev->flags & HIFN_FLAG_RES_BUSY)) {
1061 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
1062 dev->flags |= HIFN_FLAG_RES_BUSY;
1063 }
1064 }
1065
1066 static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page,
1067 unsigned offset, unsigned size)
1068 {
1069 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1070 int idx;
1071 dma_addr_t addr;
1072
1073 addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE);
1074
1075 idx = dma->dsti;
1076 dma->dstr[idx].p = __cpu_to_le32(addr);
1077 dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
1078 HIFN_D_MASKDONEIRQ | HIFN_D_NOINVALID | HIFN_D_LAST);
1079
1080 if (++idx == HIFN_D_DST_RSIZE) {
1081 dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1082 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
1083 HIFN_D_LAST | HIFN_D_NOINVALID);
1084 idx = 0;
1085 }
1086 dma->dsti = idx;
1087 dma->dstu++;
1088
1089 if (!(dev->flags & HIFN_FLAG_DST_BUSY)) {
1090 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
1091 dev->flags |= HIFN_FLAG_DST_BUSY;
1092 }
1093 }
1094
1095 static int hifn_setup_dma(struct hifn_device *dev, struct page *spage, unsigned int soff,
1096 struct page *dpage, unsigned int doff, unsigned int nbytes, void *priv,
1097 struct hifn_context *ctx)
1098 {
1099 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1100 int cmd_len, sa_idx;
1101 u8 *buf, *buf_pos;
1102 u16 mask;
1103
1104 dprintk("%s: spage: %p, soffset: %u, dpage: %p, doffset: %u, nbytes: %u, priv: %p, ctx: %p.\n",
1105 dev->name, spage, soff, dpage, doff, nbytes, priv, ctx);
1106
1107 sa_idx = dma->resi;
1108
1109 hifn_setup_src_desc(dev, spage, soff, nbytes);
1110
1111 buf_pos = buf = dma->command_bufs[dma->cmdi];
1112
1113 mask = 0;
1114 switch (ctx->op) {
1115 case ACRYPTO_OP_DECRYPT:
1116 mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE;
1117 break;
1118 case ACRYPTO_OP_ENCRYPT:
1119 mask = HIFN_BASE_CMD_CRYPT;
1120 break;
1121 case ACRYPTO_OP_HMAC:
1122 mask = HIFN_BASE_CMD_MAC;
1123 break;
1124 default:
1125 goto err_out;
1126 }
1127
1128 buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes,
1129 nbytes, mask, dev->snum);
1130
1131 if (ctx->op == ACRYPTO_OP_ENCRYPT || ctx->op == ACRYPTO_OP_DECRYPT) {
1132 u16 md = 0;
1133
1134 if (ctx->keysize)
1135 md |= HIFN_CRYPT_CMD_NEW_KEY;
1136 if (ctx->iv && ctx->mode != ACRYPTO_MODE_ECB)
1137 md |= HIFN_CRYPT_CMD_NEW_IV;
1138
1139 switch (ctx->mode) {
1140 case ACRYPTO_MODE_ECB:
1141 md |= HIFN_CRYPT_CMD_MODE_ECB;
1142 break;
1143 case ACRYPTO_MODE_CBC:
1144 md |= HIFN_CRYPT_CMD_MODE_CBC;
1145 break;
1146 case ACRYPTO_MODE_CFB:
1147 md |= HIFN_CRYPT_CMD_MODE_CFB;
1148 break;
1149 case ACRYPTO_MODE_OFB:
1150 md |= HIFN_CRYPT_CMD_MODE_OFB;
1151 break;
1152 default:
1153 goto err_out;
1154 }
1155
1156 switch (ctx->type) {
1157 case ACRYPTO_TYPE_AES_128:
1158 if (ctx->keysize != 16)
1159 goto err_out;
1160 md |= HIFN_CRYPT_CMD_KSZ_128 |
1161 HIFN_CRYPT_CMD_ALG_AES;
1162 break;
1163 case ACRYPTO_TYPE_AES_192:
1164 if (ctx->keysize != 24)
1165 goto err_out;
1166 md |= HIFN_CRYPT_CMD_KSZ_192 |
1167 HIFN_CRYPT_CMD_ALG_AES;
1168 break;
1169 case ACRYPTO_TYPE_AES_256:
1170 if (ctx->keysize != 32)
1171 goto err_out;
1172 md |= HIFN_CRYPT_CMD_KSZ_256 |
1173 HIFN_CRYPT_CMD_ALG_AES;
1174 break;
1175 case ACRYPTO_TYPE_3DES:
1176 if (ctx->keysize != 24)
1177 goto err_out;
1178 md |= HIFN_CRYPT_CMD_ALG_3DES;
1179 break;
1180 case ACRYPTO_TYPE_DES:
1181 if (ctx->keysize != 8)
1182 goto err_out;
1183 md |= HIFN_CRYPT_CMD_ALG_DES;
1184 break;
1185 default:
1186 goto err_out;
1187 }
1188
1189 buf_pos += hifn_setup_crypto_command(dev, buf_pos,
1190 nbytes, nbytes, ctx->key, ctx->keysize,
1191 ctx->iv, ctx->ivsize, md);
1192 }
1193
1194 dev->sa[sa_idx] = priv;
1195
1196 cmd_len = buf_pos - buf;
1197 dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID |
1198 HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
1199
1200 if (++dma->cmdi == HIFN_D_CMD_RSIZE) {
1201 dma->cmdr[dma->cmdi].l = __cpu_to_le32(HIFN_MAX_COMMAND |
1202 HIFN_D_VALID | HIFN_D_LAST |
1203 HIFN_D_MASKDONEIRQ | HIFN_D_JUMP);
1204 dma->cmdi = 0;
1205 } else
1206 dma->cmdr[dma->cmdi-1].l |= __cpu_to_le32(HIFN_D_VALID);
1207
1208 if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) {
1209 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1210 dev->flags |= HIFN_FLAG_CMD_BUSY;
1211 }
1212
1213 hifn_setup_dst_desc(dev, dpage, doff, nbytes);
1214 hifn_setup_res_desc(dev);
1215
1216 return 0;
1217
1218 err_out:
1219 return -EINVAL;
1220 }
1221
1222 static int ablkcipher_walk_init(struct ablkcipher_walk *w,
1223 int num, gfp_t gfp_flags)
1224 {
1225 int i;
1226
1227 num = min(ASYNC_SCATTERLIST_CACHE, num);
1228 sg_init_table(w->cache, num);
1229
1230 w->num = 0;
1231 for (i=0; i<num; ++i) {
1232 struct page *page = alloc_page(gfp_flags);
1233 struct scatterlist *s;
1234
1235 if (!page)
1236 break;
1237
1238 s = &w->cache[i];
1239
1240 sg_set_page(s, page, PAGE_SIZE, 0);
1241 w->num++;
1242 }
1243
1244 return i;
1245 }
1246
1247 static void ablkcipher_walk_exit(struct ablkcipher_walk *w)
1248 {
1249 int i;
1250
1251 for (i=0; i<w->num; ++i) {
1252 struct scatterlist *s = &w->cache[i];
1253
1254 __free_page(sg_page(s));
1255
1256 s->length = 0;
1257 }
1258
1259 w->num = 0;
1260 }
1261
1262 static int ablkcipher_add(void *daddr, unsigned int *drestp, struct scatterlist *src,
1263 unsigned int size, unsigned int *nbytesp)
1264 {
1265 unsigned int copy, drest = *drestp, nbytes = *nbytesp;
1266 int idx = 0;
1267 void *saddr;
1268
1269 if (drest < size || size > nbytes)
1270 return -EINVAL;
1271
1272 while (size) {
1273 copy = min(drest, src->length);
1274
1275 saddr = kmap_atomic(sg_page(src), KM_SOFTIRQ1);
1276 memcpy(daddr, saddr + src->offset, copy);
1277 kunmap_atomic(saddr, KM_SOFTIRQ1);
1278
1279 size -= copy;
1280 drest -= copy;
1281 nbytes -= copy;
1282 daddr += copy;
1283
1284 dprintk("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
1285 __func__, copy, size, drest, nbytes);
1286
1287 src++;
1288 idx++;
1289 }
1290
1291 *nbytesp = nbytes;
1292 *drestp = drest;
1293
1294 return idx;
1295 }
1296
1297 static int ablkcipher_walk(struct ablkcipher_request *req,
1298 struct ablkcipher_walk *w)
1299 {
1300 unsigned blocksize =
1301 crypto_ablkcipher_blocksize(crypto_ablkcipher_reqtfm(req));
1302 unsigned alignmask =
1303 crypto_ablkcipher_alignmask(crypto_ablkcipher_reqtfm(req));
1304 struct scatterlist *src, *dst, *t;
1305 void *daddr;
1306 unsigned int nbytes = req->nbytes, offset, copy, diff;
1307 int idx, tidx, err;
1308
1309 tidx = idx = 0;
1310 offset = 0;
1311 while (nbytes) {
1312 if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED))
1313 return -EINVAL;
1314
1315 src = &req->src[idx];
1316 dst = &req->dst[idx];
1317
1318 dprintk("\n%s: slen: %u, dlen: %u, soff: %u, doff: %u, offset: %u, "
1319 "blocksize: %u, nbytes: %u.\n",
1320 __func__, src->length, dst->length, src->offset,
1321 dst->offset, offset, blocksize, nbytes);
1322
1323 if (src->length & (blocksize - 1) ||
1324 src->offset & (alignmask - 1) ||
1325 dst->length & (blocksize - 1) ||
1326 dst->offset & (alignmask - 1) ||
1327 offset) {
1328 unsigned slen = src->length - offset;
1329 unsigned dlen = PAGE_SIZE;
1330
1331 t = &w->cache[idx];
1332
1333 daddr = kmap_atomic(sg_page(t), KM_SOFTIRQ0);
1334 err = ablkcipher_add(daddr, &dlen, src, slen, &nbytes);
1335 if (err < 0)
1336 goto err_out_unmap;
1337
1338 idx += err;
1339
1340 copy = slen & ~(blocksize - 1);
1341 diff = slen & (blocksize - 1);
1342
1343 if (dlen < nbytes) {
1344 /*
1345 * Destination page does not have enough space
1346 * to put there additional blocksized chunk,
1347 * so we mark that page as containing only
1348 * blocksize aligned chunks:
1349 * t->length = (slen & ~(blocksize - 1));
1350 * and increase number of bytes to be processed
1351 * in next chunk:
1352 * nbytes += diff;
1353 */
1354 nbytes += diff;
1355
1356 /*
1357 * Temporary of course...
1358 * Kick author if you will catch this one.
1359 */
1360 printk(KERN_ERR "%s: dlen: %u, nbytes: %u,"
1361 "slen: %u, offset: %u.\n",
1362 __func__, dlen, nbytes, slen, offset);
1363 printk(KERN_ERR "%s: please contact author to fix this "
1364 "issue, generally you should not catch "
1365 "this path under any condition but who "
1366 "knows how did you use crypto code.\n"
1367 "Thank you.\n", __func__);
1368 BUG();
1369 } else {
1370 copy += diff + nbytes;
1371
1372 src = &req->src[idx];
1373
1374 err = ablkcipher_add(daddr + slen, &dlen, src, nbytes, &nbytes);
1375 if (err < 0)
1376 goto err_out_unmap;
1377
1378 idx += err;
1379 }
1380
1381 t->length = copy;
1382 t->offset = offset;
1383
1384 kunmap_atomic(daddr, KM_SOFTIRQ0);
1385 } else {
1386 nbytes -= src->length;
1387 idx++;
1388 }
1389
1390 tidx++;
1391 }
1392
1393 return tidx;
1394
1395 err_out_unmap:
1396 kunmap_atomic(daddr, KM_SOFTIRQ0);
1397 return err;
1398 }
1399
1400 static int hifn_setup_session(struct ablkcipher_request *req)
1401 {
1402 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1403 struct hifn_device *dev = ctx->dev;
1404 struct page *spage, *dpage;
1405 unsigned long soff, doff, flags;
1406 unsigned int nbytes = req->nbytes, idx = 0, len;
1407 int err = -EINVAL, sg_num;
1408 struct scatterlist *src, *dst, *t;
1409 unsigned blocksize =
1410 crypto_ablkcipher_blocksize(crypto_ablkcipher_reqtfm(req));
1411 unsigned alignmask =
1412 crypto_ablkcipher_alignmask(crypto_ablkcipher_reqtfm(req));
1413
1414 if (ctx->iv && !ctx->ivsize && ctx->mode != ACRYPTO_MODE_ECB)
1415 goto err_out_exit;
1416
1417 ctx->walk.flags = 0;
1418
1419 while (nbytes) {
1420 src = &req->src[idx];
1421 dst = &req->dst[idx];
1422
1423 if (src->length & (blocksize - 1) ||
1424 src->offset & (alignmask - 1) ||
1425 dst->length & (blocksize - 1) ||
1426 dst->offset & (alignmask - 1)) {
1427 ctx->walk.flags |= ASYNC_FLAGS_MISALIGNED;
1428 }
1429
1430 nbytes -= src->length;
1431 idx++;
1432 }
1433
1434 if (ctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1435 err = ablkcipher_walk_init(&ctx->walk, idx, GFP_ATOMIC);
1436 if (err < 0)
1437 return err;
1438 }
1439
1440 nbytes = req->nbytes;
1441 idx = 0;
1442
1443 sg_num = ablkcipher_walk(req, &ctx->walk);
1444
1445 atomic_set(&ctx->sg_num, sg_num);
1446
1447 spin_lock_irqsave(&dev->lock, flags);
1448 if (dev->started + sg_num > HIFN_QUEUE_LENGTH) {
1449 err = -EAGAIN;
1450 goto err_out;
1451 }
1452
1453 dev->snum++;
1454 dev->started += sg_num;
1455
1456 while (nbytes) {
1457 src = &req->src[idx];
1458 dst = &req->dst[idx];
1459 t = &ctx->walk.cache[idx];
1460
1461 if (t->length) {
1462 spage = dpage = sg_page(t);
1463 soff = doff = 0;
1464 len = t->length;
1465 } else {
1466 spage = sg_page(src);
1467 soff = src->offset;
1468
1469 dpage = sg_page(dst);
1470 doff = dst->offset;
1471
1472 len = dst->length;
1473 }
1474
1475 idx++;
1476
1477 err = hifn_setup_dma(dev, spage, soff, dpage, doff, nbytes,
1478 req, ctx);
1479 if (err)
1480 goto err_out;
1481
1482 nbytes -= len;
1483 }
1484
1485 dev->active = HIFN_DEFAULT_ACTIVE_NUM;
1486 spin_unlock_irqrestore(&dev->lock, flags);
1487
1488 return 0;
1489
1490 err_out:
1491 spin_unlock_irqrestore(&dev->lock, flags);
1492 err_out_exit:
1493 if (err && printk_ratelimit())
1494 dprintk("%s: iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
1495 "type: %u, err: %d.\n",
1496 dev->name, ctx->iv, ctx->ivsize,
1497 ctx->key, ctx->keysize,
1498 ctx->mode, ctx->op, ctx->type, err);
1499
1500 return err;
1501 }
1502
1503 static int hifn_test(struct hifn_device *dev, int encdec, u8 snum)
1504 {
1505 int n, err;
1506 u8 src[16];
1507 struct hifn_context ctx;
1508 u8 fips_aes_ecb_from_zero[16] = {
1509 0x66, 0xE9, 0x4B, 0xD4,
1510 0xEF, 0x8A, 0x2C, 0x3B,
1511 0x88, 0x4C, 0xFA, 0x59,
1512 0xCA, 0x34, 0x2B, 0x2E};
1513
1514 memset(src, 0, sizeof(src));
1515 memset(ctx.key, 0, sizeof(ctx.key));
1516
1517 ctx.dev = dev;
1518 ctx.keysize = 16;
1519 ctx.ivsize = 0;
1520 ctx.iv = NULL;
1521 ctx.op = (encdec)?ACRYPTO_OP_ENCRYPT:ACRYPTO_OP_DECRYPT;
1522 ctx.mode = ACRYPTO_MODE_ECB;
1523 ctx.type = ACRYPTO_TYPE_AES_128;
1524 atomic_set(&ctx.sg_num, 1);
1525
1526 err = hifn_setup_dma(dev,
1527 virt_to_page(src), offset_in_page(src),
1528 virt_to_page(src), offset_in_page(src),
1529 sizeof(src), NULL, &ctx);
1530 if (err)
1531 goto err_out;
1532
1533 msleep(200);
1534
1535 dprintk("%s: decoded: ", dev->name);
1536 for (n=0; n<sizeof(src); ++n)
1537 dprintk("%02x ", src[n]);
1538 dprintk("\n");
1539 dprintk("%s: FIPS : ", dev->name);
1540 for (n=0; n<sizeof(fips_aes_ecb_from_zero); ++n)
1541 dprintk("%02x ", fips_aes_ecb_from_zero[n]);
1542 dprintk("\n");
1543
1544 if (!memcmp(src, fips_aes_ecb_from_zero, sizeof(fips_aes_ecb_from_zero))) {
1545 printk(KERN_INFO "%s: AES 128 ECB test has been successfully "
1546 "passed.\n", dev->name);
1547 return 0;
1548 }
1549
1550 err_out:
1551 printk(KERN_INFO "%s: AES 128 ECB test has been failed.\n", dev->name);
1552 return -1;
1553 }
1554
1555 static int hifn_start_device(struct hifn_device *dev)
1556 {
1557 int err;
1558
1559 hifn_reset_dma(dev, 1);
1560
1561 err = hifn_enable_crypto(dev);
1562 if (err)
1563 return err;
1564
1565 hifn_reset_puc(dev);
1566
1567 hifn_init_dma(dev);
1568
1569 hifn_init_registers(dev);
1570
1571 hifn_init_pubrng(dev);
1572
1573 return 0;
1574 }
1575
1576 static int ablkcipher_get(void *saddr, unsigned int *srestp, unsigned int offset,
1577 struct scatterlist *dst, unsigned int size, unsigned int *nbytesp)
1578 {
1579 unsigned int srest = *srestp, nbytes = *nbytesp, copy;
1580 void *daddr;
1581 int idx = 0;
1582
1583 if (srest < size || size > nbytes)
1584 return -EINVAL;
1585
1586 while (size) {
1587
1588 copy = min(dst->length, srest);
1589
1590 daddr = kmap_atomic(sg_page(dst), KM_IRQ0);
1591 memcpy(daddr + dst->offset + offset, saddr, copy);
1592 kunmap_atomic(daddr, KM_IRQ0);
1593
1594 nbytes -= copy;
1595 size -= copy;
1596 srest -= copy;
1597 saddr += copy;
1598 offset = 0;
1599
1600 dprintk("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n",
1601 __func__, copy, size, srest, nbytes);
1602
1603 dst++;
1604 idx++;
1605 }
1606
1607 *nbytesp = nbytes;
1608 *srestp = srest;
1609
1610 return idx;
1611 }
1612
1613 static void hifn_process_ready(struct ablkcipher_request *req, int error)
1614 {
1615 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1616 struct hifn_device *dev;
1617
1618 dprintk("%s: req: %p, ctx: %p.\n", __func__, req, ctx);
1619
1620 dev = ctx->dev;
1621 dprintk("%s: req: %p, started: %d, sg_num: %d.\n",
1622 __func__, req, dev->started, atomic_read(&ctx->sg_num));
1623
1624 if (--dev->started < 0)
1625 BUG();
1626
1627 if (atomic_dec_and_test(&ctx->sg_num)) {
1628 unsigned int nbytes = req->nbytes;
1629 int idx = 0, err;
1630 struct scatterlist *dst, *t;
1631 void *saddr;
1632
1633 if (ctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1634 while (nbytes) {
1635 t = &ctx->walk.cache[idx];
1636 dst = &req->dst[idx];
1637
1638 dprintk("\n%s: sg_page(t): %p, t->length: %u, "
1639 "sg_page(dst): %p, dst->length: %u, "
1640 "nbytes: %u.\n",
1641 __func__, sg_page(t), t->length,
1642 sg_page(dst), dst->length, nbytes);
1643
1644 if (!t->length) {
1645 nbytes -= dst->length;
1646 idx++;
1647 continue;
1648 }
1649
1650 saddr = kmap_atomic(sg_page(t), KM_IRQ1);
1651
1652 err = ablkcipher_get(saddr, &t->length, t->offset,
1653 dst, nbytes, &nbytes);
1654 if (err < 0) {
1655 kunmap_atomic(saddr, KM_IRQ1);
1656 break;
1657 }
1658
1659 idx += err;
1660 kunmap_atomic(saddr, KM_IRQ1);
1661 }
1662
1663 ablkcipher_walk_exit(&ctx->walk);
1664 }
1665
1666 req->base.complete(&req->base, error);
1667 }
1668 }
1669
1670 static void hifn_check_for_completion(struct hifn_device *dev, int error)
1671 {
1672 int i;
1673 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1674
1675 for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
1676 struct hifn_desc *d = &dma->resr[i];
1677
1678 if (!(d->l & __cpu_to_le32(HIFN_D_VALID)) && dev->sa[i]) {
1679 dev->success++;
1680 dev->reset = 0;
1681 hifn_process_ready(dev->sa[i], error);
1682 dev->sa[i] = NULL;
1683 }
1684
1685 if (d->l & __cpu_to_le32(HIFN_D_DESTOVER | HIFN_D_OVER))
1686 if (printk_ratelimit())
1687 printk("%s: overflow detected [d: %u, o: %u] "
1688 "at %d resr: l: %08x, p: %08x.\n",
1689 dev->name,
1690 !!(d->l & __cpu_to_le32(HIFN_D_DESTOVER)),
1691 !!(d->l & __cpu_to_le32(HIFN_D_OVER)),
1692 i, d->l, d->p);
1693 }
1694 }
1695
1696 static void hifn_clear_rings(struct hifn_device *dev)
1697 {
1698 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1699 int i, u;
1700
1701 dprintk("%s: ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1702 "k: %d.%d.%d.%d.\n",
1703 dev->name,
1704 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1705 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1706 dma->cmdk, dma->srck, dma->dstk, dma->resk);
1707
1708 i = dma->resk; u = dma->resu;
1709 while (u != 0) {
1710 if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID))
1711 break;
1712
1713 if (i != HIFN_D_RES_RSIZE)
1714 u--;
1715
1716 if (++i == (HIFN_D_RES_RSIZE + 1))
1717 i = 0;
1718 }
1719 dma->resk = i; dma->resu = u;
1720
1721 i = dma->srck; u = dma->srcu;
1722 while (u != 0) {
1723 if (i == HIFN_D_SRC_RSIZE)
1724 i = 0;
1725 if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID))
1726 break;
1727 i++, u--;
1728 }
1729 dma->srck = i; dma->srcu = u;
1730
1731 i = dma->cmdk; u = dma->cmdu;
1732 while (u != 0) {
1733 if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID))
1734 break;
1735 if (i != HIFN_D_CMD_RSIZE)
1736 u--;
1737 if (++i == (HIFN_D_CMD_RSIZE + 1))
1738 i = 0;
1739 }
1740 dma->cmdk = i; dma->cmdu = u;
1741
1742 i = dma->dstk; u = dma->dstu;
1743 while (u != 0) {
1744 if (i == HIFN_D_DST_RSIZE)
1745 i = 0;
1746 if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID))
1747 break;
1748 i++, u--;
1749 }
1750 dma->dstk = i; dma->dstu = u;
1751
1752 dprintk("%s: ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1753 "k: %d.%d.%d.%d.\n",
1754 dev->name,
1755 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1756 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1757 dma->cmdk, dma->srck, dma->dstk, dma->resk);
1758 }
1759
1760 static void hifn_work(struct work_struct *work)
1761 {
1762 struct delayed_work *dw = container_of(work, struct delayed_work, work);
1763 struct hifn_device *dev = container_of(dw, struct hifn_device, work);
1764 unsigned long flags;
1765 int reset = 0;
1766 u32 r = 0;
1767
1768 spin_lock_irqsave(&dev->lock, flags);
1769 if (dev->active == 0) {
1770 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1771
1772 if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) {
1773 dev->flags &= ~HIFN_FLAG_CMD_BUSY;
1774 r |= HIFN_DMACSR_C_CTRL_DIS;
1775 }
1776 if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) {
1777 dev->flags &= ~HIFN_FLAG_SRC_BUSY;
1778 r |= HIFN_DMACSR_S_CTRL_DIS;
1779 }
1780 if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) {
1781 dev->flags &= ~HIFN_FLAG_DST_BUSY;
1782 r |= HIFN_DMACSR_D_CTRL_DIS;
1783 }
1784 if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) {
1785 dev->flags &= ~HIFN_FLAG_RES_BUSY;
1786 r |= HIFN_DMACSR_R_CTRL_DIS;
1787 }
1788 if (r)
1789 hifn_write_1(dev, HIFN_1_DMA_CSR, r);
1790 } else
1791 dev->active--;
1792
1793 if (dev->prev_success == dev->success && dev->started)
1794 reset = 1;
1795 dev->prev_success = dev->success;
1796 spin_unlock_irqrestore(&dev->lock, flags);
1797
1798 if (reset) {
1799 dprintk("%s: r: %08x, active: %d, started: %d, "
1800 "success: %lu: reset: %d.\n",
1801 dev->name, r, dev->active, dev->started,
1802 dev->success, reset);
1803
1804 if (++dev->reset >= 5) {
1805 dprintk("%s: really hard reset.\n", dev->name);
1806 hifn_reset_dma(dev, 1);
1807 hifn_stop_device(dev);
1808 hifn_start_device(dev);
1809 dev->reset = 0;
1810 }
1811
1812 spin_lock_irqsave(&dev->lock, flags);
1813 hifn_check_for_completion(dev, -EBUSY);
1814 hifn_clear_rings(dev);
1815 dev->started = 0;
1816 spin_unlock_irqrestore(&dev->lock, flags);
1817 }
1818
1819 schedule_delayed_work(&dev->work, HZ);
1820 }
1821
1822 static irqreturn_t hifn_interrupt(int irq, void *data)
1823 {
1824 struct hifn_device *dev = (struct hifn_device *)data;
1825 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1826 u32 dmacsr, restart;
1827
1828 dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR);
1829
1830 dprintk("%s: 1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], "
1831 "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n",
1832 dev->name, dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi,
1833 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1834 dma->cmdi, dma->srci, dma->dsti, dma->resi);
1835
1836 if ((dmacsr & dev->dmareg) == 0)
1837 return IRQ_NONE;
1838
1839 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);
1840
1841 if (dmacsr & HIFN_DMACSR_ENGINE)
1842 hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR));
1843 if (dmacsr & HIFN_DMACSR_PUBDONE)
1844 hifn_write_1(dev, HIFN_1_PUB_STATUS,
1845 hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
1846
1847 restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER);
1848 if (restart) {
1849 u32 puisr = hifn_read_0(dev, HIFN_0_PUISR);
1850
1851 if (printk_ratelimit())
1852 printk("%s: overflow: r: %d, d: %d, puisr: %08x, d: %u.\n",
1853 dev->name, !!(dmacsr & HIFN_DMACSR_R_OVER),
1854 !!(dmacsr & HIFN_DMACSR_D_OVER),
1855 puisr, !!(puisr & HIFN_PUISR_DSTOVER));
1856 if (!!(puisr & HIFN_PUISR_DSTOVER))
1857 hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1858 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |
1859 HIFN_DMACSR_D_OVER));
1860 }
1861
1862 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
1863 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
1864 if (restart) {
1865 if (printk_ratelimit())
1866 printk("%s: abort: c: %d, s: %d, d: %d, r: %d.\n",
1867 dev->name, !!(dmacsr & HIFN_DMACSR_C_ABORT),
1868 !!(dmacsr & HIFN_DMACSR_S_ABORT),
1869 !!(dmacsr & HIFN_DMACSR_D_ABORT),
1870 !!(dmacsr & HIFN_DMACSR_R_ABORT));
1871 hifn_reset_dma(dev, 1);
1872 hifn_init_dma(dev);
1873 hifn_init_registers(dev);
1874 }
1875
1876 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
1877 dprintk("%s: wait on command.\n", dev->name);
1878 dev->dmareg &= ~(HIFN_DMAIER_C_WAIT);
1879 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1880 }
1881
1882 hifn_check_for_completion(dev, 0);
1883 hifn_clear_rings(dev);
1884
1885 return IRQ_HANDLED;
1886 }
1887
1888 static void hifn_flush(struct hifn_device *dev)
1889 {
1890 unsigned long flags;
1891 struct crypto_async_request *async_req;
1892 struct hifn_context *ctx;
1893 struct ablkcipher_request *req;
1894 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1895 int i;
1896
1897 spin_lock_irqsave(&dev->lock, flags);
1898 for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
1899 struct hifn_desc *d = &dma->resr[i];
1900
1901 if (dev->sa[i]) {
1902 hifn_process_ready(dev->sa[i],
1903 (d->l & __cpu_to_le32(HIFN_D_VALID))?-ENODEV:0);
1904 }
1905 }
1906
1907 while ((async_req = crypto_dequeue_request(&dev->queue))) {
1908 ctx = crypto_tfm_ctx(async_req->tfm);
1909 req = container_of(async_req, struct ablkcipher_request, base);
1910
1911 hifn_process_ready(req, -ENODEV);
1912 }
1913 spin_unlock_irqrestore(&dev->lock, flags);
1914 }
1915
1916 static int hifn_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
1917 unsigned int len)
1918 {
1919 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
1920 struct hifn_context *ctx = crypto_tfm_ctx(tfm);
1921 struct hifn_device *dev = ctx->dev;
1922
1923 if (len > HIFN_MAX_CRYPT_KEY_LENGTH) {
1924 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1925 return -1;
1926 }
1927
1928 if (len == HIFN_DES_KEY_LENGTH) {
1929 u32 tmp[DES_EXPKEY_WORDS];
1930 int ret = des_ekey(tmp, key);
1931
1932 if (unlikely(ret == 0) && (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
1933 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
1934 return -EINVAL;
1935 }
1936 }
1937
1938 dev->flags &= ~HIFN_FLAG_OLD_KEY;
1939
1940 memcpy(ctx->key, key, len);
1941 ctx->keysize = len;
1942
1943 return 0;
1944 }
1945
1946 static int hifn_handle_req(struct ablkcipher_request *req)
1947 {
1948 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1949 struct hifn_device *dev = ctx->dev;
1950 int err = -EAGAIN;
1951
1952 if (dev->started + DIV_ROUND_UP(req->nbytes, PAGE_SIZE) <= HIFN_QUEUE_LENGTH)
1953 err = hifn_setup_session(req);
1954
1955 if (err == -EAGAIN) {
1956 unsigned long flags;
1957
1958 spin_lock_irqsave(&dev->lock, flags);
1959 err = ablkcipher_enqueue_request(&dev->queue, req);
1960 spin_unlock_irqrestore(&dev->lock, flags);
1961 }
1962
1963 return err;
1964 }
1965
1966 static int hifn_setup_crypto_req(struct ablkcipher_request *req, u8 op,
1967 u8 type, u8 mode)
1968 {
1969 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1970 unsigned ivsize;
1971
1972 ivsize = crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req));
1973
1974 if (req->info && mode != ACRYPTO_MODE_ECB) {
1975 if (type == ACRYPTO_TYPE_AES_128)
1976 ivsize = HIFN_AES_IV_LENGTH;
1977 else if (type == ACRYPTO_TYPE_DES)
1978 ivsize = HIFN_DES_KEY_LENGTH;
1979 else if (type == ACRYPTO_TYPE_3DES)
1980 ivsize = HIFN_3DES_KEY_LENGTH;
1981 }
1982
1983 if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) {
1984 if (ctx->keysize == 24)
1985 type = ACRYPTO_TYPE_AES_192;
1986 else if (ctx->keysize == 32)
1987 type = ACRYPTO_TYPE_AES_256;
1988 }
1989
1990 ctx->op = op;
1991 ctx->mode = mode;
1992 ctx->type = type;
1993 ctx->iv = req->info;
1994 ctx->ivsize = ivsize;
1995
1996 /*
1997 * HEAVY TODO: needs to kick Herbert XU to write documentation.
1998 * HEAVY TODO: needs to kick Herbert XU to write documentation.
1999 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2000 */
2001
2002 return hifn_handle_req(req);
2003 }
2004
2005 static int hifn_process_queue(struct hifn_device *dev)
2006 {
2007 struct crypto_async_request *async_req;
2008 struct hifn_context *ctx;
2009 struct ablkcipher_request *req;
2010 unsigned long flags;
2011 int err = 0;
2012
2013 while (dev->started < HIFN_QUEUE_LENGTH) {
2014 spin_lock_irqsave(&dev->lock, flags);
2015 async_req = crypto_dequeue_request(&dev->queue);
2016 spin_unlock_irqrestore(&dev->lock, flags);
2017
2018 if (!async_req)
2019 break;
2020
2021 ctx = crypto_tfm_ctx(async_req->tfm);
2022 req = container_of(async_req, struct ablkcipher_request, base);
2023
2024 err = hifn_handle_req(req);
2025 if (err)
2026 break;
2027 }
2028
2029 return err;
2030 }
2031
2032 static int hifn_setup_crypto(struct ablkcipher_request *req, u8 op,
2033 u8 type, u8 mode)
2034 {
2035 int err;
2036 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2037 struct hifn_device *dev = ctx->dev;
2038
2039 err = hifn_setup_crypto_req(req, op, type, mode);
2040 if (err)
2041 return err;
2042
2043 if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
2044 err = hifn_process_queue(dev);
2045
2046 return err;
2047 }
2048
2049 /*
2050 * AES ecryption functions.
2051 */
2052 static inline int hifn_encrypt_aes_ecb(struct ablkcipher_request *req)
2053 {
2054 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2055 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2056 }
2057 static inline int hifn_encrypt_aes_cbc(struct ablkcipher_request *req)
2058 {
2059 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2060 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2061 }
2062 static inline int hifn_encrypt_aes_cfb(struct ablkcipher_request *req)
2063 {
2064 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2065 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2066 }
2067 static inline int hifn_encrypt_aes_ofb(struct ablkcipher_request *req)
2068 {
2069 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2070 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2071 }
2072
2073 /*
2074 * AES decryption functions.
2075 */
2076 static inline int hifn_decrypt_aes_ecb(struct ablkcipher_request *req)
2077 {
2078 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2079 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2080 }
2081 static inline int hifn_decrypt_aes_cbc(struct ablkcipher_request *req)
2082 {
2083 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2084 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2085 }
2086 static inline int hifn_decrypt_aes_cfb(struct ablkcipher_request *req)
2087 {
2088 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2089 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2090 }
2091 static inline int hifn_decrypt_aes_ofb(struct ablkcipher_request *req)
2092 {
2093 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2094 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2095 }
2096
2097 /*
2098 * DES ecryption functions.
2099 */
2100 static inline int hifn_encrypt_des_ecb(struct ablkcipher_request *req)
2101 {
2102 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2103 ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2104 }
2105 static inline int hifn_encrypt_des_cbc(struct ablkcipher_request *req)
2106 {
2107 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2108 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2109 }
2110 static inline int hifn_encrypt_des_cfb(struct ablkcipher_request *req)
2111 {
2112 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2113 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2114 }
2115 static inline int hifn_encrypt_des_ofb(struct ablkcipher_request *req)
2116 {
2117 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2118 ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2119 }
2120
2121 /*
2122 * DES decryption functions.
2123 */
2124 static inline int hifn_decrypt_des_ecb(struct ablkcipher_request *req)
2125 {
2126 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2127 ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2128 }
2129 static inline int hifn_decrypt_des_cbc(struct ablkcipher_request *req)
2130 {
2131 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2132 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2133 }
2134 static inline int hifn_decrypt_des_cfb(struct ablkcipher_request *req)
2135 {
2136 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2137 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2138 }
2139 static inline int hifn_decrypt_des_ofb(struct ablkcipher_request *req)
2140 {
2141 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2142 ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2143 }
2144
2145 /*
2146 * 3DES ecryption functions.
2147 */
2148 static inline int hifn_encrypt_3des_ecb(struct ablkcipher_request *req)
2149 {
2150 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2151 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2152 }
2153 static inline int hifn_encrypt_3des_cbc(struct ablkcipher_request *req)
2154 {
2155 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2156 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2157 }
2158 static inline int hifn_encrypt_3des_cfb(struct ablkcipher_request *req)
2159 {
2160 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2161 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2162 }
2163 static inline int hifn_encrypt_3des_ofb(struct ablkcipher_request *req)
2164 {
2165 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2166 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2167 }
2168
2169 /*
2170 * 3DES decryption functions.
2171 */
2172 static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request *req)
2173 {
2174 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2175 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2176 }
2177 static inline int hifn_decrypt_3des_cbc(struct ablkcipher_request *req)
2178 {
2179 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2180 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2181 }
2182 static inline int hifn_decrypt_3des_cfb(struct ablkcipher_request *req)
2183 {
2184 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2185 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2186 }
2187 static inline int hifn_decrypt_3des_ofb(struct ablkcipher_request *req)
2188 {
2189 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2190 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2191 }
2192
2193 struct hifn_alg_template
2194 {
2195 char name[CRYPTO_MAX_ALG_NAME];
2196 char drv_name[CRYPTO_MAX_ALG_NAME];
2197 unsigned int bsize;
2198 struct ablkcipher_alg ablkcipher;
2199 };
2200
2201 static struct hifn_alg_template hifn_alg_templates[] = {
2202 /*
2203 * 3DES ECB, CBC, CFB and OFB modes.
2204 */
2205 {
2206 .name = "cfb(des3_ede)", .drv_name = "hifn-3des", .bsize = 8,
2207 .ablkcipher = {
2208 .min_keysize = HIFN_3DES_KEY_LENGTH,
2209 .max_keysize = HIFN_3DES_KEY_LENGTH,
2210 .setkey = hifn_setkey,
2211 .encrypt = hifn_encrypt_3des_cfb,
2212 .decrypt = hifn_decrypt_3des_cfb,
2213 },
2214 },
2215 {
2216 .name = "ofb(des3_ede)", .drv_name = "hifn-3des", .bsize = 8,
2217 .ablkcipher = {
2218 .min_keysize = HIFN_3DES_KEY_LENGTH,
2219 .max_keysize = HIFN_3DES_KEY_LENGTH,
2220 .setkey = hifn_setkey,
2221 .encrypt = hifn_encrypt_3des_ofb,
2222 .decrypt = hifn_decrypt_3des_ofb,
2223 },
2224 },
2225 {
2226 .name = "cbc(des3_ede)", .drv_name = "hifn-3des", .bsize = 8,
2227 .ablkcipher = {
2228 .min_keysize = HIFN_3DES_KEY_LENGTH,
2229 .max_keysize = HIFN_3DES_KEY_LENGTH,
2230 .setkey = hifn_setkey,
2231 .encrypt = hifn_encrypt_3des_cbc,
2232 .decrypt = hifn_decrypt_3des_cbc,
2233 },
2234 },
2235 {
2236 .name = "ecb(des3_ede)", .drv_name = "hifn-3des", .bsize = 8,
2237 .ablkcipher = {
2238 .min_keysize = HIFN_3DES_KEY_LENGTH,
2239 .max_keysize = HIFN_3DES_KEY_LENGTH,
2240 .setkey = hifn_setkey,
2241 .encrypt = hifn_encrypt_3des_ecb,
2242 .decrypt = hifn_decrypt_3des_ecb,
2243 },
2244 },
2245
2246 /*
2247 * DES ECB, CBC, CFB and OFB modes.
2248 */
2249 {
2250 .name = "cfb(des)", .drv_name = "hifn-des", .bsize = 8,
2251 .ablkcipher = {
2252 .min_keysize = HIFN_DES_KEY_LENGTH,
2253 .max_keysize = HIFN_DES_KEY_LENGTH,
2254 .setkey = hifn_setkey,
2255 .encrypt = hifn_encrypt_des_cfb,
2256 .decrypt = hifn_decrypt_des_cfb,
2257 },
2258 },
2259 {
2260 .name = "ofb(des)", .drv_name = "hifn-des", .bsize = 8,
2261 .ablkcipher = {
2262 .min_keysize = HIFN_DES_KEY_LENGTH,
2263 .max_keysize = HIFN_DES_KEY_LENGTH,
2264 .setkey = hifn_setkey,
2265 .encrypt = hifn_encrypt_des_ofb,
2266 .decrypt = hifn_decrypt_des_ofb,
2267 },
2268 },
2269 {
2270 .name = "cbc(des)", .drv_name = "hifn-des", .bsize = 8,
2271 .ablkcipher = {
2272 .min_keysize = HIFN_DES_KEY_LENGTH,
2273 .max_keysize = HIFN_DES_KEY_LENGTH,
2274 .setkey = hifn_setkey,
2275 .encrypt = hifn_encrypt_des_cbc,
2276 .decrypt = hifn_decrypt_des_cbc,
2277 },
2278 },
2279 {
2280 .name = "ecb(des)", .drv_name = "hifn-des", .bsize = 8,
2281 .ablkcipher = {
2282 .min_keysize = HIFN_DES_KEY_LENGTH,
2283 .max_keysize = HIFN_DES_KEY_LENGTH,
2284 .setkey = hifn_setkey,
2285 .encrypt = hifn_encrypt_des_ecb,
2286 .decrypt = hifn_decrypt_des_ecb,
2287 },
2288 },
2289
2290 /*
2291 * AES ECB, CBC, CFB and OFB modes.
2292 */
2293 {
2294 .name = "ecb(aes)", .drv_name = "hifn-aes", .bsize = 16,
2295 .ablkcipher = {
2296 .min_keysize = AES_MIN_KEY_SIZE,
2297 .max_keysize = AES_MAX_KEY_SIZE,
2298 .setkey = hifn_setkey,
2299 .encrypt = hifn_encrypt_aes_ecb,
2300 .decrypt = hifn_decrypt_aes_ecb,
2301 },
2302 },
2303 {
2304 .name = "cbc(aes)", .drv_name = "hifn-aes", .bsize = 16,
2305 .ablkcipher = {
2306 .min_keysize = AES_MIN_KEY_SIZE,
2307 .max_keysize = AES_MAX_KEY_SIZE,
2308 .setkey = hifn_setkey,
2309 .encrypt = hifn_encrypt_aes_cbc,
2310 .decrypt = hifn_decrypt_aes_cbc,
2311 },
2312 },
2313 {
2314 .name = "cfb(aes)", .drv_name = "hifn-aes", .bsize = 16,
2315 .ablkcipher = {
2316 .min_keysize = AES_MIN_KEY_SIZE,
2317 .max_keysize = AES_MAX_KEY_SIZE,
2318 .setkey = hifn_setkey,
2319 .encrypt = hifn_encrypt_aes_cfb,
2320 .decrypt = hifn_decrypt_aes_cfb,
2321 },
2322 },
2323 {
2324 .name = "ofb(aes)", .drv_name = "hifn-aes", .bsize = 16,
2325 .ablkcipher = {
2326 .min_keysize = AES_MIN_KEY_SIZE,
2327 .max_keysize = AES_MAX_KEY_SIZE,
2328 .setkey = hifn_setkey,
2329 .encrypt = hifn_encrypt_aes_ofb,
2330 .decrypt = hifn_decrypt_aes_ofb,
2331 },
2332 },
2333 };
2334
2335 static int hifn_cra_init(struct crypto_tfm *tfm)
2336 {
2337 struct crypto_alg *alg = tfm->__crt_alg;
2338 struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg);
2339 struct hifn_context *ctx = crypto_tfm_ctx(tfm);
2340
2341 ctx->dev = ha->dev;
2342
2343 return 0;
2344 }
2345
2346 static int hifn_alg_alloc(struct hifn_device *dev, struct hifn_alg_template *t)
2347 {
2348 struct hifn_crypto_alg *alg;
2349 int err;
2350
2351 alg = kzalloc(sizeof(struct hifn_crypto_alg), GFP_KERNEL);
2352 if (!alg)
2353 return -ENOMEM;
2354
2355 snprintf(alg->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name);
2356 snprintf(alg->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", t->drv_name);
2357
2358 alg->alg.cra_priority = 300;
2359 alg->alg.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | CRYPTO_ALG_ASYNC;
2360 alg->alg.cra_blocksize = t->bsize;
2361 alg->alg.cra_ctxsize = sizeof(struct hifn_context);
2362 alg->alg.cra_alignmask = 15;
2363 if (t->bsize == 8)
2364 alg->alg.cra_alignmask = 3;
2365 alg->alg.cra_type = &crypto_ablkcipher_type;
2366 alg->alg.cra_module = THIS_MODULE;
2367 alg->alg.cra_u.ablkcipher = t->ablkcipher;
2368 alg->alg.cra_init = hifn_cra_init;
2369
2370 alg->dev = dev;
2371
2372 list_add_tail(&alg->entry, &dev->alg_list);
2373
2374 err = crypto_register_alg(&alg->alg);
2375 if (err) {
2376 list_del(&alg->entry);
2377 kfree(alg);
2378 }
2379
2380 return err;
2381 }
2382
2383 static void hifn_unregister_alg(struct hifn_device *dev)
2384 {
2385 struct hifn_crypto_alg *a, *n;
2386
2387 list_for_each_entry_safe(a, n, &dev->alg_list, entry) {
2388 list_del(&a->entry);
2389 crypto_unregister_alg(&a->alg);
2390 kfree(a);
2391 }
2392 }
2393
2394 static int hifn_register_alg(struct hifn_device *dev)
2395 {
2396 int i, err;
2397
2398 for (i=0; i<ARRAY_SIZE(hifn_alg_templates); ++i) {
2399 err = hifn_alg_alloc(dev, &hifn_alg_templates[i]);
2400 if (err)
2401 goto err_out_exit;
2402 }
2403
2404 return 0;
2405
2406 err_out_exit:
2407 hifn_unregister_alg(dev);
2408 return err;
2409 }
2410
2411 static int hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2412 {
2413 int err, i;
2414 struct hifn_device *dev;
2415 char name[8];
2416
2417 err = pci_enable_device(pdev);
2418 if (err)
2419 return err;
2420 pci_set_master(pdev);
2421
2422 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2423 if (err)
2424 goto err_out_disable_pci_device;
2425
2426 snprintf(name, sizeof(name), "hifn%d",
2427 atomic_inc_return(&hifn_dev_number)-1);
2428
2429 err = pci_request_regions(pdev, name);
2430 if (err)
2431 goto err_out_disable_pci_device;
2432
2433 if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE ||
2434 pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE ||
2435 pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) {
2436 dprintk("%s: Broken hardware - I/O regions are too small.\n",
2437 pci_name(pdev));
2438 err = -ENODEV;
2439 goto err_out_free_regions;
2440 }
2441
2442 dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg),
2443 GFP_KERNEL);
2444 if (!dev) {
2445 err = -ENOMEM;
2446 goto err_out_free_regions;
2447 }
2448
2449 INIT_LIST_HEAD(&dev->alg_list);
2450
2451 snprintf(dev->name, sizeof(dev->name), "%s", name);
2452 spin_lock_init(&dev->lock);
2453
2454 for (i=0; i<3; ++i) {
2455 unsigned long addr, size;
2456
2457 addr = pci_resource_start(pdev, i);
2458 size = pci_resource_len(pdev, i);
2459
2460 dev->bar[i] = ioremap_nocache(addr, size);
2461 if (!dev->bar[i])
2462 goto err_out_unmap_bars;
2463 }
2464
2465 dev->result_mem = __get_free_pages(GFP_KERNEL, HIFN_MAX_RESULT_ORDER);
2466 if (!dev->result_mem) {
2467 dprintk("Failed to allocate %d pages for result_mem.\n",
2468 HIFN_MAX_RESULT_ORDER);
2469 goto err_out_unmap_bars;
2470 }
2471 memset((void *)dev->result_mem, 0, PAGE_SIZE*(1<<HIFN_MAX_RESULT_ORDER));
2472
2473 dev->dst = pci_map_single(pdev, (void *)dev->result_mem,
2474 PAGE_SIZE << HIFN_MAX_RESULT_ORDER, PCI_DMA_FROMDEVICE);
2475
2476 dev->desc_virt = pci_alloc_consistent(pdev, sizeof(struct hifn_dma),
2477 &dev->desc_dma);
2478 if (!dev->desc_virt) {
2479 dprintk("Failed to allocate descriptor rings.\n");
2480 goto err_out_free_result_pages;
2481 }
2482 memset(dev->desc_virt, 0, sizeof(struct hifn_dma));
2483
2484 dev->pdev = pdev;
2485 dev->irq = pdev->irq;
2486
2487 for (i=0; i<HIFN_D_RES_RSIZE; ++i)
2488 dev->sa[i] = NULL;
2489
2490 pci_set_drvdata(pdev, dev);
2491
2492 crypto_init_queue(&dev->queue, 1);
2493
2494 err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev);
2495 if (err) {
2496 dprintk("Failed to request IRQ%d: err: %d.\n", dev->irq, err);
2497 dev->irq = 0;
2498 goto err_out_free_desc;
2499 }
2500
2501 err = hifn_start_device(dev);
2502 if (err)
2503 goto err_out_free_irq;
2504
2505 err = hifn_test(dev, 1, 0);
2506 if (err)
2507 goto err_out_stop_device;
2508
2509 err = hifn_register_alg(dev);
2510 if (err)
2511 goto err_out_stop_device;
2512
2513 INIT_DELAYED_WORK(&dev->work, hifn_work);
2514 schedule_delayed_work(&dev->work, HZ);
2515
2516 dprintk("HIFN crypto accelerator card at %s has been "
2517 "successfully registered as %s.\n",
2518 pci_name(pdev), dev->name);
2519
2520 return 0;
2521
2522 err_out_stop_device:
2523 hifn_reset_dma(dev, 1);
2524 hifn_stop_device(dev);
2525 err_out_free_irq:
2526 free_irq(dev->irq, dev->name);
2527 err_out_free_desc:
2528 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2529 dev->desc_virt, dev->desc_dma);
2530
2531 err_out_free_result_pages:
2532 pci_unmap_single(pdev, dev->dst, PAGE_SIZE << HIFN_MAX_RESULT_ORDER,
2533 PCI_DMA_FROMDEVICE);
2534 free_pages(dev->result_mem, HIFN_MAX_RESULT_ORDER);
2535
2536 err_out_unmap_bars:
2537 for (i=0; i<3; ++i)
2538 if (dev->bar[i])
2539 iounmap(dev->bar[i]);
2540
2541 err_out_free_regions:
2542 pci_release_regions(pdev);
2543
2544 err_out_disable_pci_device:
2545 pci_disable_device(pdev);
2546
2547 return err;
2548 }
2549
2550 static void hifn_remove(struct pci_dev *pdev)
2551 {
2552 int i;
2553 struct hifn_device *dev;
2554
2555 dev = pci_get_drvdata(pdev);
2556
2557 if (dev) {
2558 cancel_delayed_work(&dev->work);
2559 flush_scheduled_work();
2560
2561 hifn_unregister_alg(dev);
2562 hifn_reset_dma(dev, 1);
2563 hifn_stop_device(dev);
2564
2565 free_irq(dev->irq, dev->name);
2566
2567 hifn_flush(dev);
2568
2569 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2570 dev->desc_virt, dev->desc_dma);
2571 pci_unmap_single(pdev, dev->dst,
2572 PAGE_SIZE << HIFN_MAX_RESULT_ORDER,
2573 PCI_DMA_FROMDEVICE);
2574 free_pages(dev->result_mem, HIFN_MAX_RESULT_ORDER);
2575 for (i=0; i<3; ++i)
2576 if (dev->bar[i])
2577 iounmap(dev->bar[i]);
2578
2579 kfree(dev);
2580 }
2581
2582 pci_release_regions(pdev);
2583 pci_disable_device(pdev);
2584 }
2585
2586 static struct pci_device_id hifn_pci_tbl[] = {
2587 { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) },
2588 { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) },
2589 { 0 }
2590 };
2591 MODULE_DEVICE_TABLE(pci, hifn_pci_tbl);
2592
2593 static struct pci_driver hifn_pci_driver = {
2594 .name = "hifn795x",
2595 .id_table = hifn_pci_tbl,
2596 .probe = hifn_probe,
2597 .remove = __devexit_p(hifn_remove),
2598 };
2599
2600 static int __devinit hifn_init(void)
2601 {
2602 int err;
2603
2604 err = pci_register_driver(&hifn_pci_driver);
2605 if (err < 0) {
2606 dprintk("Failed to register PCI driver for %s device.\n",
2607 hifn_pci_driver.name);
2608 return -ENODEV;
2609 }
2610
2611 printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip "
2612 "has been successfully registered.\n");
2613
2614 return 0;
2615 }
2616
2617 static void __devexit hifn_fini(void)
2618 {
2619 pci_unregister_driver(&hifn_pci_driver);
2620
2621 printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip "
2622 "has been successfully unregistered.\n");
2623 }
2624
2625 module_init(hifn_init);
2626 module_exit(hifn_fini);
2627
2628 MODULE_LICENSE("GPL");
2629 MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
2630 MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip.");
AMDTP streaming driver for the Linux FireWire stack (Juju)