2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dmapool.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/slab.h>
27 #include <linux/smp_lock.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/timer.h>
31 #include <linux/list.h>
32 #include <linux/interrupt.h>
33 #include <linux/reboot.h>
34 #include <linux/usb.h>
35 #include <linux/moduleparam.h>
36 #include <linux/dma-mapping.h>
38 #include "../core/hcd.h"
40 #include <asm/byteorder.h>
43 #include <asm/system.h>
44 #include <asm/unaligned.h>
46 #include <asm/firmware.h>
50 /*-------------------------------------------------------------------------*/
53 * EHCI hc_driver implementation ... experimental, incomplete.
54 * Based on the final 1.0 register interface specification.
56 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
57 * First was PCMCIA, like ISA; then CardBus, which is PCI.
58 * Next comes "CardBay", using USB 2.0 signals.
60 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
61 * Special thanks to Intel and VIA for providing host controllers to
62 * test this driver on, and Cypress (including In-System Design) for
63 * providing early devices for those host controllers to talk to!
67 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
68 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
69 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
70 * <sojkam@centrum.cz>, updates by DB).
72 * 2002-11-29 Correct handling for hw async_next register.
73 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
74 * only scheduling is different, no arbitrary limitations.
75 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
76 * clean up HC run state handshaking.
77 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
78 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
79 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
80 * 2002-05-07 Some error path cleanups to report better errors; wmb();
81 * use non-CVS version id; better iso bandwidth claim.
82 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
83 * errors in submit path. Bugfixes to interrupt scheduling/processing.
84 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
85 * more checking to generic hcd framework (db). Make it work with
86 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
87 * 2002-01-14 Minor cleanup; version synch.
88 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
89 * 2002-01-04 Control/Bulk queuing behaves.
91 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
92 * 2001-June Works with usb-storage and NEC EHCI on 2.4
95 #define DRIVER_VERSION "10 Dec 2004"
96 #define DRIVER_AUTHOR "David Brownell"
97 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
99 static const char hcd_name
[] = "ehci_hcd";
102 #undef EHCI_VERBOSE_DEBUG
103 #undef EHCI_URB_TRACE
109 /* magic numbers that can affect system performance */
110 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
111 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
112 #define EHCI_TUNE_RL_TT 0
113 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
114 #define EHCI_TUNE_MULT_TT 1
115 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
117 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
118 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
119 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
120 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
122 /* Initial IRQ latency: faster than hw default */
123 static int log2_irq_thresh
= 0; // 0 to 6
124 module_param (log2_irq_thresh
, int, S_IRUGO
);
125 MODULE_PARM_DESC (log2_irq_thresh
, "log2 IRQ latency, 1-64 microframes");
127 /* initial park setting: slower than hw default */
128 static unsigned park
= 0;
129 module_param (park
, uint
, S_IRUGO
);
130 MODULE_PARM_DESC (park
, "park setting; 1-3 back-to-back async packets");
132 /* for flakey hardware, ignore overcurrent indicators */
133 static int ignore_oc
= 0;
134 module_param (ignore_oc
, bool, S_IRUGO
);
135 MODULE_PARM_DESC (ignore_oc
, "ignore bogus hardware overcurrent indications");
137 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
139 /*-------------------------------------------------------------------------*/
142 #include "ehci-dbg.c"
144 /*-------------------------------------------------------------------------*/
147 * handshake - spin reading hc until handshake completes or fails
148 * @ptr: address of hc register to be read
149 * @mask: bits to look at in result of read
150 * @done: value of those bits when handshake succeeds
151 * @usec: timeout in microseconds
153 * Returns negative errno, or zero on success
155 * Success happens when the "mask" bits have the specified value (hardware
156 * handshake done). There are two failure modes: "usec" have passed (major
157 * hardware flakeout), or the register reads as all-ones (hardware removed).
159 * That last failure should_only happen in cases like physical cardbus eject
160 * before driver shutdown. But it also seems to be caused by bugs in cardbus
161 * bridge shutdown: shutting down the bridge before the devices using it.
163 static int handshake (struct ehci_hcd
*ehci
, void __iomem
*ptr
,
164 u32 mask
, u32 done
, int usec
)
169 result
= ehci_readl(ehci
, ptr
);
170 if (result
== ~(u32
)0) /* card removed */
181 /* force HC to halt state from unknown (EHCI spec section 2.3) */
182 static int ehci_halt (struct ehci_hcd
*ehci
)
184 u32 temp
= ehci_readl(ehci
, &ehci
->regs
->status
);
186 /* disable any irqs left enabled by previous code */
187 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
189 if ((temp
& STS_HALT
) != 0)
192 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
194 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
195 return handshake (ehci
, &ehci
->regs
->status
,
196 STS_HALT
, STS_HALT
, 16 * 125);
199 /* put TDI/ARC silicon into EHCI mode */
200 static void tdi_reset (struct ehci_hcd
*ehci
)
202 u32 __iomem
*reg_ptr
;
205 reg_ptr
= (u32 __iomem
*)(((u8 __iomem
*)ehci
->regs
) + 0x68);
206 tmp
= ehci_readl(ehci
, reg_ptr
);
208 ehci_writel(ehci
, tmp
, reg_ptr
);
211 /* reset a non-running (STS_HALT == 1) controller */
212 static int ehci_reset (struct ehci_hcd
*ehci
)
215 u32 command
= ehci_readl(ehci
, &ehci
->regs
->command
);
217 command
|= CMD_RESET
;
218 dbg_cmd (ehci
, "reset", command
);
219 ehci_writel(ehci
, command
, &ehci
->regs
->command
);
220 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
221 ehci
->next_statechange
= jiffies
;
222 retval
= handshake (ehci
, &ehci
->regs
->command
,
223 CMD_RESET
, 0, 250 * 1000);
228 if (ehci_is_TDI(ehci
))
234 /* idle the controller (from running) */
235 static void ehci_quiesce (struct ehci_hcd
*ehci
)
240 if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
))
244 /* wait for any schedule enables/disables to take effect */
245 temp
= ehci_readl(ehci
, &ehci
->regs
->command
) << 10;
246 temp
&= STS_ASS
| STS_PSS
;
247 if (handshake (ehci
, &ehci
->regs
->status
, STS_ASS
| STS_PSS
,
248 temp
, 16 * 125) != 0) {
249 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
253 /* then disable anything that's still active */
254 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
255 temp
&= ~(CMD_ASE
| CMD_IAAD
| CMD_PSE
);
256 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
258 /* hardware can take 16 microframes to turn off ... */
259 if (handshake (ehci
, &ehci
->regs
->status
, STS_ASS
| STS_PSS
,
261 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
266 /*-------------------------------------------------------------------------*/
268 static void ehci_work(struct ehci_hcd
*ehci
);
270 #include "ehci-hub.c"
271 #include "ehci-mem.c"
273 #include "ehci-sched.c"
275 /*-------------------------------------------------------------------------*/
277 static void ehci_watchdog (unsigned long param
)
279 struct ehci_hcd
*ehci
= (struct ehci_hcd
*) param
;
282 spin_lock_irqsave (&ehci
->lock
, flags
);
284 /* lost IAA irqs wedge things badly; seen with a vt8235 */
286 u32 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
287 if (status
& STS_IAA
) {
288 ehci_vdbg (ehci
, "lost IAA\n");
289 COUNT (ehci
->stats
.lost_iaa
);
290 ehci_writel(ehci
, STS_IAA
, &ehci
->regs
->status
);
291 ehci
->reclaim_ready
= 1;
295 /* stop async processing after it's idled a bit */
296 if (test_bit (TIMER_ASYNC_OFF
, &ehci
->actions
))
297 start_unlink_async (ehci
, ehci
->async
);
299 /* ehci could run by timer, without IRQs ... */
302 spin_unlock_irqrestore (&ehci
->lock
, flags
);
305 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
306 * This forcibly disables dma and IRQs, helping kexec and other cases
307 * where the next system software may expect clean state.
310 ehci_shutdown (struct usb_hcd
*hcd
)
312 struct ehci_hcd
*ehci
;
314 ehci
= hcd_to_ehci (hcd
);
315 (void) ehci_halt (ehci
);
317 /* make BIOS/etc use companion controller during reboot */
318 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
321 static void ehci_port_power (struct ehci_hcd
*ehci
, int is_on
)
325 if (!HCS_PPC (ehci
->hcs_params
))
328 ehci_dbg (ehci
, "...power%s ports...\n", is_on
? "up" : "down");
329 for (port
= HCS_N_PORTS (ehci
->hcs_params
); port
> 0; )
330 (void) ehci_hub_control(ehci_to_hcd(ehci
),
331 is_on
? SetPortFeature
: ClearPortFeature
,
337 /*-------------------------------------------------------------------------*/
340 * ehci_work is called from some interrupts, timers, and so on.
341 * it calls driver completion functions, after dropping ehci->lock.
343 static void ehci_work (struct ehci_hcd
*ehci
)
345 timer_action_done (ehci
, TIMER_IO_WATCHDOG
);
346 if (ehci
->reclaim_ready
)
347 end_unlink_async (ehci
);
349 /* another CPU may drop ehci->lock during a schedule scan while
350 * it reports urb completions. this flag guards against bogus
351 * attempts at re-entrant schedule scanning.
357 if (ehci
->next_uframe
!= -1)
358 scan_periodic (ehci
);
361 /* the IO watchdog guards against hardware or driver bugs that
362 * misplace IRQs, and should let us run completely without IRQs.
363 * such lossage has been observed on both VT6202 and VT8235.
365 if (HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) &&
366 (ehci
->async
->qh_next
.ptr
!= NULL
||
367 ehci
->periodic_sched
!= 0))
368 timer_action (ehci
, TIMER_IO_WATCHDOG
);
371 static void ehci_stop (struct usb_hcd
*hcd
)
373 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
375 ehci_dbg (ehci
, "stop\n");
377 /* Turn off port power on all root hub ports. */
378 ehci_port_power (ehci
, 0);
380 /* no more interrupts ... */
381 del_timer_sync (&ehci
->watchdog
);
383 spin_lock_irq(&ehci
->lock
);
384 if (HC_IS_RUNNING (hcd
->state
))
388 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
389 spin_unlock_irq(&ehci
->lock
);
391 /* let companion controllers work when we aren't */
392 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
394 remove_companion_file(ehci
);
395 remove_debug_files (ehci
);
397 /* root hub is shut down separately (first, when possible) */
398 spin_lock_irq (&ehci
->lock
);
401 spin_unlock_irq (&ehci
->lock
);
402 ehci_mem_cleanup (ehci
);
405 ehci_dbg (ehci
, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
406 ehci
->stats
.normal
, ehci
->stats
.error
, ehci
->stats
.reclaim
,
407 ehci
->stats
.lost_iaa
);
408 ehci_dbg (ehci
, "complete %ld unlink %ld\n",
409 ehci
->stats
.complete
, ehci
->stats
.unlink
);
412 dbg_status (ehci
, "ehci_stop completed",
413 ehci_readl(ehci
, &ehci
->regs
->status
));
416 /* one-time init, only for memory state */
417 static int ehci_init(struct usb_hcd
*hcd
)
419 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
424 spin_lock_init(&ehci
->lock
);
426 init_timer(&ehci
->watchdog
);
427 ehci
->watchdog
.function
= ehci_watchdog
;
428 ehci
->watchdog
.data
= (unsigned long) ehci
;
431 * hw default: 1K periodic list heads, one per frame.
432 * periodic_size can shrink by USBCMD update if hcc_params allows.
434 ehci
->periodic_size
= DEFAULT_I_TDPS
;
435 if ((retval
= ehci_mem_init(ehci
, GFP_KERNEL
)) < 0)
438 /* controllers may cache some of the periodic schedule ... */
439 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
440 if (HCC_ISOC_CACHE(hcc_params
)) // full frame cache
442 else // N microframes cached
443 ehci
->i_thresh
= 2 + HCC_ISOC_THRES(hcc_params
);
445 ehci
->reclaim
= NULL
;
446 ehci
->reclaim_ready
= 0;
447 ehci
->next_uframe
= -1;
450 * dedicate a qh for the async ring head, since we couldn't unlink
451 * a 'real' qh without stopping the async schedule [4.8]. use it
452 * as the 'reclamation list head' too.
453 * its dummy is used in hw_alt_next of many tds, to prevent the qh
454 * from automatically advancing to the next td after short reads.
456 ehci
->async
->qh_next
.qh
= NULL
;
457 ehci
->async
->hw_next
= QH_NEXT(ehci
->async
->qh_dma
);
458 ehci
->async
->hw_info1
= cpu_to_le32(QH_HEAD
);
459 ehci
->async
->hw_token
= cpu_to_le32(QTD_STS_HALT
);
460 ehci
->async
->hw_qtd_next
= EHCI_LIST_END
;
461 ehci
->async
->qh_state
= QH_STATE_LINKED
;
462 ehci
->async
->hw_alt_next
= QTD_NEXT(ehci
->async
->dummy
->qtd_dma
);
464 /* clear interrupt enables, set irq latency */
465 if (log2_irq_thresh
< 0 || log2_irq_thresh
> 6)
467 temp
= 1 << (16 + log2_irq_thresh
);
468 if (HCC_CANPARK(hcc_params
)) {
469 /* HW default park == 3, on hardware that supports it (like
470 * NVidia and ALI silicon), maximizes throughput on the async
471 * schedule by avoiding QH fetches between transfers.
473 * With fast usb storage devices and NForce2, "park" seems to
474 * make problems: throughput reduction (!), data errors...
477 park
= min(park
, (unsigned) 3);
481 ehci_dbg(ehci
, "park %d\n", park
);
483 if (HCC_PGM_FRAMELISTLEN(hcc_params
)) {
484 /* periodic schedule size can be smaller than default */
486 temp
|= (EHCI_TUNE_FLS
<< 2);
487 switch (EHCI_TUNE_FLS
) {
488 case 0: ehci
->periodic_size
= 1024; break;
489 case 1: ehci
->periodic_size
= 512; break;
490 case 2: ehci
->periodic_size
= 256; break;
494 ehci
->command
= temp
;
499 /* start HC running; it's halted, ehci_init() has been run (once) */
500 static int ehci_run (struct usb_hcd
*hcd
)
502 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
507 hcd
->uses_new_polling
= 1;
510 /* EHCI spec section 4.1 */
511 if ((retval
= ehci_reset(ehci
)) != 0) {
512 ehci_mem_cleanup(ehci
);
515 ehci_writel(ehci
, ehci
->periodic_dma
, &ehci
->regs
->frame_list
);
516 ehci_writel(ehci
, (u32
)ehci
->async
->qh_dma
, &ehci
->regs
->async_next
);
519 * hcc_params controls whether ehci->regs->segment must (!!!)
520 * be used; it constrains QH/ITD/SITD and QTD locations.
521 * pci_pool consistent memory always uses segment zero.
522 * streaming mappings for I/O buffers, like pci_map_single(),
523 * can return segments above 4GB, if the device allows.
525 * NOTE: the dma mask is visible through dma_supported(), so
526 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
527 * Scsi_Host.highmem_io, and so forth. It's readonly to all
528 * host side drivers though.
530 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
531 if (HCC_64BIT_ADDR(hcc_params
)) {
532 ehci_writel(ehci
, 0, &ehci
->regs
->segment
);
534 // this is deeply broken on almost all architectures
535 if (!dma_set_mask(hcd
->self
.controller
, DMA_64BIT_MASK
))
536 ehci_info(ehci
, "enabled 64bit DMA\n");
541 // Philips, Intel, and maybe others need CMD_RUN before the
542 // root hub will detect new devices (why?); NEC doesn't
543 ehci
->command
&= ~(CMD_LRESET
|CMD_IAAD
|CMD_PSE
|CMD_ASE
|CMD_RESET
);
544 ehci
->command
|= CMD_RUN
;
545 ehci_writel(ehci
, ehci
->command
, &ehci
->regs
->command
);
546 dbg_cmd (ehci
, "init", ehci
->command
);
549 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
550 * are explicitly handed to companion controller(s), so no TT is
551 * involved with the root hub. (Except where one is integrated,
552 * and there's no companion controller unless maybe for USB OTG.)
554 hcd
->state
= HC_STATE_RUNNING
;
555 ehci_writel(ehci
, FLAG_CF
, &ehci
->regs
->configured_flag
);
556 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted writes */
558 temp
= HC_VERSION(ehci_readl(ehci
, &ehci
->caps
->hc_capbase
));
560 "USB %x.%x started, EHCI %x.%02x, driver %s%s\n",
561 ((ehci
->sbrn
& 0xf0)>>4), (ehci
->sbrn
& 0x0f),
562 temp
>> 8, temp
& 0xff, DRIVER_VERSION
,
563 ignore_oc
? ", overcurrent ignored" : "");
565 ehci_writel(ehci
, INTR_MASK
,
566 &ehci
->regs
->intr_enable
); /* Turn On Interrupts */
568 /* GRR this is run-once init(), being done every time the HC starts.
569 * So long as they're part of class devices, we can't do it init()
570 * since the class device isn't created that early.
572 create_debug_files(ehci
);
573 create_companion_file(ehci
);
578 /*-------------------------------------------------------------------------*/
580 static irqreturn_t
ehci_irq (struct usb_hcd
*hcd
)
582 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
583 u32 status
, pcd_status
= 0;
586 spin_lock (&ehci
->lock
);
588 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
590 /* e.g. cardbus physical eject */
591 if (status
== ~(u32
) 0) {
592 ehci_dbg (ehci
, "device removed\n");
597 if (!status
) { /* irq sharing? */
598 spin_unlock(&ehci
->lock
);
602 /* clear (just) interrupts */
603 ehci_writel(ehci
, status
, &ehci
->regs
->status
);
604 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted write */
607 #ifdef EHCI_VERBOSE_DEBUG
608 /* unrequested/ignored: Frame List Rollover */
609 dbg_status (ehci
, "irq", status
);
612 /* INT, ERR, and IAA interrupt rates can be throttled */
614 /* normal [4.15.1.2] or error [4.15.1.1] completion */
615 if (likely ((status
& (STS_INT
|STS_ERR
)) != 0)) {
616 if (likely ((status
& STS_ERR
) == 0))
617 COUNT (ehci
->stats
.normal
);
619 COUNT (ehci
->stats
.error
);
623 /* complete the unlinking of some qh [4.15.2.3] */
624 if (status
& STS_IAA
) {
625 COUNT (ehci
->stats
.reclaim
);
626 ehci
->reclaim_ready
= 1;
630 /* remote wakeup [4.3.1] */
631 if (status
& STS_PCD
) {
632 unsigned i
= HCS_N_PORTS (ehci
->hcs_params
);
635 /* resume root hub? */
636 if (!(ehci_readl(ehci
, &ehci
->regs
->command
) & CMD_RUN
))
637 usb_hcd_resume_root_hub(hcd
);
640 int pstatus
= ehci_readl(ehci
,
641 &ehci
->regs
->port_status
[i
]);
643 if (pstatus
& PORT_OWNER
)
645 if (!(pstatus
& PORT_RESUME
)
646 || ehci
->reset_done
[i
] != 0)
649 /* start 20 msec resume signaling from this port,
650 * and make khubd collect PORT_STAT_C_SUSPEND to
651 * stop that signaling.
653 ehci
->reset_done
[i
] = jiffies
+ msecs_to_jiffies (20);
654 ehci_dbg (ehci
, "port %d remote wakeup\n", i
+ 1);
658 /* PCI errors [4.15.2.4] */
659 if (unlikely ((status
& STS_FATAL
) != 0)) {
660 /* bogus "fatal" IRQs appear on some chips... why? */
661 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
662 dbg_cmd (ehci
, "fatal", ehci_readl(ehci
,
663 &ehci
->regs
->command
));
664 dbg_status (ehci
, "fatal", status
);
665 if (status
& STS_HALT
) {
666 ehci_err (ehci
, "fatal error\n");
669 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
670 /* generic layer kills/unlinks all urbs, then
671 * uses ehci_stop to clean up the rest
679 spin_unlock (&ehci
->lock
);
680 if (pcd_status
& STS_PCD
)
681 usb_hcd_poll_rh_status(hcd
);
685 /*-------------------------------------------------------------------------*/
688 * non-error returns are a promise to giveback() the urb later
689 * we drop ownership so next owner (or urb unlink) can get it
691 * urb + dev is in hcd.self.controller.urb_list
692 * we're queueing TDs onto software and hardware lists
694 * hcd-specific init for hcpriv hasn't been done yet
696 * NOTE: control, bulk, and interrupt share the same code to append TDs
697 * to a (possibly active) QH, and the same QH scanning code.
699 static int ehci_urb_enqueue (
701 struct usb_host_endpoint
*ep
,
705 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
706 struct list_head qtd_list
;
708 INIT_LIST_HEAD (&qtd_list
);
710 switch (usb_pipetype (urb
->pipe
)) {
711 // case PIPE_CONTROL:
714 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
716 return submit_async (ehci
, ep
, urb
, &qtd_list
, mem_flags
);
719 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
721 return intr_submit (ehci
, ep
, urb
, &qtd_list
, mem_flags
);
723 case PIPE_ISOCHRONOUS
:
724 if (urb
->dev
->speed
== USB_SPEED_HIGH
)
725 return itd_submit (ehci
, urb
, mem_flags
);
727 return sitd_submit (ehci
, urb
, mem_flags
);
731 static void unlink_async (struct ehci_hcd
*ehci
, struct ehci_qh
*qh
)
733 /* if we need to use IAA and it's busy, defer */
734 if (qh
->qh_state
== QH_STATE_LINKED
736 && HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
)) {
737 struct ehci_qh
*last
;
739 for (last
= ehci
->reclaim
;
741 last
= last
->reclaim
)
743 qh
->qh_state
= QH_STATE_UNLINK_WAIT
;
746 /* bypass IAA if the hc can't care */
747 } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) && ehci
->reclaim
)
748 end_unlink_async (ehci
);
750 /* something else might have unlinked the qh by now */
751 if (qh
->qh_state
== QH_STATE_LINKED
)
752 start_unlink_async (ehci
, qh
);
755 /* remove from hardware lists
756 * completions normally happen asynchronously
759 static int ehci_urb_dequeue (struct usb_hcd
*hcd
, struct urb
*urb
)
761 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
765 spin_lock_irqsave (&ehci
->lock
, flags
);
766 switch (usb_pipetype (urb
->pipe
)) {
767 // case PIPE_CONTROL:
770 qh
= (struct ehci_qh
*) urb
->hcpriv
;
773 unlink_async (ehci
, qh
);
777 qh
= (struct ehci_qh
*) urb
->hcpriv
;
780 switch (qh
->qh_state
) {
781 case QH_STATE_LINKED
:
782 intr_deschedule (ehci
, qh
);
785 qh_completions (ehci
, qh
);
788 ehci_dbg (ehci
, "bogus qh %p state %d\n",
793 /* reschedule QH iff another request is queued */
794 if (!list_empty (&qh
->qtd_list
)
795 && HC_IS_RUNNING (hcd
->state
)) {
798 status
= qh_schedule (ehci
, qh
);
799 spin_unlock_irqrestore (&ehci
->lock
, flags
);
802 // shouldn't happen often, but ...
803 // FIXME kill those tds' urbs
804 err ("can't reschedule qh %p, err %d",
811 case PIPE_ISOCHRONOUS
:
814 // wait till next completion, do it then.
815 // completion irqs can wait up to 1024 msec,
819 spin_unlock_irqrestore (&ehci
->lock
, flags
);
823 /*-------------------------------------------------------------------------*/
825 // bulk qh holds the data toggle
828 ehci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
830 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
832 struct ehci_qh
*qh
, *tmp
;
834 /* ASSERT: any requests/urbs are being unlinked */
835 /* ASSERT: nobody can be submitting urbs for this any more */
838 spin_lock_irqsave (&ehci
->lock
, flags
);
843 /* endpoints can be iso streams. for now, we don't
844 * accelerate iso completions ... so spin a while.
846 if (qh
->hw_info1
== 0) {
847 ehci_vdbg (ehci
, "iso delay\n");
851 if (!HC_IS_RUNNING (hcd
->state
))
852 qh
->qh_state
= QH_STATE_IDLE
;
853 switch (qh
->qh_state
) {
854 case QH_STATE_LINKED
:
855 for (tmp
= ehci
->async
->qh_next
.qh
;
857 tmp
= tmp
->qh_next
.qh
)
859 /* periodic qh self-unlinks on empty */
862 unlink_async (ehci
, qh
);
864 case QH_STATE_UNLINK
: /* wait for hw to finish? */
866 spin_unlock_irqrestore (&ehci
->lock
, flags
);
867 schedule_timeout_uninterruptible(1);
869 case QH_STATE_IDLE
: /* fully unlinked */
870 if (list_empty (&qh
->qtd_list
)) {
874 /* else FALL THROUGH */
877 /* caller was supposed to have unlinked any requests;
878 * that's not our job. just leak this memory.
880 ehci_err (ehci
, "qh %p (#%02x) state %d%s\n",
881 qh
, ep
->desc
.bEndpointAddress
, qh
->qh_state
,
882 list_empty (&qh
->qtd_list
) ? "" : "(has tds)");
887 spin_unlock_irqrestore (&ehci
->lock
, flags
);
891 static int ehci_get_frame (struct usb_hcd
*hcd
)
893 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
894 return (ehci_readl(ehci
, &ehci
->regs
->frame_index
) >> 3) %
898 /*-------------------------------------------------------------------------*/
900 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
902 MODULE_DESCRIPTION (DRIVER_INFO
);
903 MODULE_AUTHOR (DRIVER_AUTHOR
);
904 MODULE_LICENSE ("GPL");
907 #include "ehci-pci.c"
908 #define PCI_DRIVER ehci_pci_driver
911 #ifdef CONFIG_MPC834x
912 #include "ehci-fsl.c"
913 #define PLATFORM_DRIVER ehci_fsl_driver
916 #ifdef CONFIG_SOC_AU1200
917 #include "ehci-au1xxx.c"
918 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
921 #ifdef CONFIG_PPC_PS3
922 #include "ehci-ps3.c"
923 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_sb_driver
926 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
927 !defined(PS3_SYSTEM_BUS_DRIVER)
928 #error "missing bus glue for ehci-hcd"
931 static int __init
ehci_hcd_init(void)
935 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
937 sizeof(struct ehci_qh
), sizeof(struct ehci_qtd
),
938 sizeof(struct ehci_itd
), sizeof(struct ehci_sitd
));
940 #ifdef PLATFORM_DRIVER
941 retval
= platform_driver_register(&PLATFORM_DRIVER
);
947 retval
= pci_register_driver(&PCI_DRIVER
);
949 #ifdef PLATFORM_DRIVER
950 platform_driver_unregister(&PLATFORM_DRIVER
);
956 #ifdef PS3_SYSTEM_BUS_DRIVER
957 if (firmware_has_feature(FW_FEATURE_PS3_LV1
)) {
958 retval
= ps3_system_bus_driver_register(
959 &PS3_SYSTEM_BUS_DRIVER
);
961 #ifdef PLATFORM_DRIVER
962 platform_driver_unregister(&PLATFORM_DRIVER
);
965 pci_unregister_driver(&PCI_DRIVER
);
974 module_init(ehci_hcd_init
);
976 static void __exit
ehci_hcd_cleanup(void)
978 #ifdef PLATFORM_DRIVER
979 platform_driver_unregister(&PLATFORM_DRIVER
);
982 pci_unregister_driver(&PCI_DRIVER
);
984 #ifdef PS3_SYSTEM_BUS_DRIVER
985 if (firmware_has_feature(FW_FEATURE_PS3_LV1
))
986 ps3_system_bus_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
989 module_exit(ehci_hcd_cleanup
);