1 /******************************************************************************
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <net/mac80211.h>
32 #include "iwl-eeprom.h"
37 #include "iwl-helpers.h"
39 static const u16 default_tid_to_tx_fifo
[] = {
59 static inline int iwl_alloc_dma_ptr(struct iwl_priv
*priv
,
60 struct iwl_dma_ptr
*ptr
, size_t size
)
62 ptr
->addr
= pci_alloc_consistent(priv
->pci_dev
, size
, &ptr
->dma
);
69 static inline void iwl_free_dma_ptr(struct iwl_priv
*priv
,
70 struct iwl_dma_ptr
*ptr
)
72 if (unlikely(!ptr
->addr
))
75 pci_free_consistent(priv
->pci_dev
, ptr
->size
, ptr
->addr
, ptr
->dma
);
76 memset(ptr
, 0, sizeof(*ptr
));
80 * iwl_txq_update_write_ptr - Send new write index to hardware
82 int iwl_txq_update_write_ptr(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
86 int txq_id
= txq
->q
.id
;
88 if (txq
->need_update
== 0)
91 /* if we're trying to save power */
92 if (test_bit(STATUS_POWER_PMI
, &priv
->status
)) {
93 /* wake up nic if it's powered down ...
94 * uCode will wake up, and interrupt us again, so next
95 * time we'll skip this part. */
96 reg
= iwl_read32(priv
, CSR_UCODE_DRV_GP1
);
98 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
99 IWL_DEBUG_INFO(priv
, "Requesting wakeup, GP1 = 0x%x\n", reg
);
100 iwl_set_bit(priv
, CSR_GP_CNTRL
,
101 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
105 /* restore this queue's parameters in nic hardware. */
106 ret
= iwl_grab_nic_access(priv
);
109 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
,
110 txq
->q
.write_ptr
| (txq_id
<< 8));
111 iwl_release_nic_access(priv
);
113 /* else not in power-save mode, uCode will never sleep when we're
114 * trying to tx (during RFKILL, we're not trying to tx). */
116 iwl_write32(priv
, HBUS_TARG_WRPTR
,
117 txq
->q
.write_ptr
| (txq_id
<< 8));
119 txq
->need_update
= 0;
123 EXPORT_SYMBOL(iwl_txq_update_write_ptr
);
127 * iwl_tx_queue_free - Deallocate DMA queue.
128 * @txq: Transmit queue to deallocate.
130 * Empty queue by removing and destroying all BD's.
132 * 0-fill, but do not free "txq" descriptor structure.
134 void iwl_tx_queue_free(struct iwl_priv
*priv
, int txq_id
)
136 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
137 struct iwl_queue
*q
= &txq
->q
;
138 struct pci_dev
*dev
= priv
->pci_dev
;
144 /* first, empty all BD's */
145 for (; q
->write_ptr
!= q
->read_ptr
;
146 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
))
147 priv
->cfg
->ops
->lib
->txq_free_tfd(priv
, txq
);
149 len
= sizeof(struct iwl_cmd
) * q
->n_window
;
151 /* De-alloc array of command/tx buffers */
152 for (i
= 0; i
< TFD_TX_CMD_SLOTS
; i
++)
155 /* De-alloc circular buffer of TFDs */
157 pci_free_consistent(dev
, priv
->hw_params
.tfd_size
*
158 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
160 /* De-alloc array of per-TFD driver data */
164 /* 0-fill queue descriptor structure */
165 memset(txq
, 0, sizeof(*txq
));
167 EXPORT_SYMBOL(iwl_tx_queue_free
);
170 * iwl_cmd_queue_free - Deallocate DMA queue.
171 * @txq: Transmit queue to deallocate.
173 * Empty queue by removing and destroying all BD's.
175 * 0-fill, but do not free "txq" descriptor structure.
177 static void iwl_cmd_queue_free(struct iwl_priv
*priv
)
179 struct iwl_tx_queue
*txq
= &priv
->txq
[IWL_CMD_QUEUE_NUM
];
180 struct iwl_queue
*q
= &txq
->q
;
181 struct pci_dev
*dev
= priv
->pci_dev
;
187 len
= sizeof(struct iwl_cmd
) * q
->n_window
;
188 len
+= IWL_MAX_SCAN_SIZE
;
190 /* De-alloc array of command/tx buffers */
191 for (i
= 0; i
<= TFD_CMD_SLOTS
; i
++)
194 /* De-alloc circular buffer of TFDs */
196 pci_free_consistent(dev
, sizeof(struct iwl_tfd
) *
197 txq
->q
.n_bd
, txq
->tfds
, txq
->q
.dma_addr
);
199 /* 0-fill queue descriptor structure */
200 memset(txq
, 0, sizeof(*txq
));
202 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
205 * Theory of operation
207 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
208 * of buffer descriptors, each of which points to one or more data buffers for
209 * the device to read from or fill. Driver and device exchange status of each
210 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
211 * entries in each circular buffer, to protect against confusing empty and full
214 * The device reads or writes the data in the queues via the device's several
215 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
217 * For Tx queue, there are low mark and high mark limits. If, after queuing
218 * the packet for Tx, free space become < low mark, Tx queue stopped. When
219 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
222 * See more detailed info in iwl-4965-hw.h.
223 ***************************************************/
225 int iwl_queue_space(const struct iwl_queue
*q
)
227 int s
= q
->read_ptr
- q
->write_ptr
;
229 if (q
->read_ptr
> q
->write_ptr
)
234 /* keep some reserve to not confuse empty and full situations */
240 EXPORT_SYMBOL(iwl_queue_space
);
244 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
246 static int iwl_queue_init(struct iwl_priv
*priv
, struct iwl_queue
*q
,
247 int count
, int slots_num
, u32 id
)
250 q
->n_window
= slots_num
;
253 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
254 * and iwl_queue_dec_wrap are broken. */
255 BUG_ON(!is_power_of_2(count
));
257 /* slots_num must be power-of-two size, otherwise
258 * get_cmd_index is broken. */
259 BUG_ON(!is_power_of_2(slots_num
));
261 q
->low_mark
= q
->n_window
/ 4;
265 q
->high_mark
= q
->n_window
/ 8;
266 if (q
->high_mark
< 2)
269 q
->write_ptr
= q
->read_ptr
= 0;
275 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
277 static int iwl_tx_queue_alloc(struct iwl_priv
*priv
,
278 struct iwl_tx_queue
*txq
, u32 id
)
280 struct pci_dev
*dev
= priv
->pci_dev
;
281 size_t tfd_sz
= priv
->hw_params
.tfd_size
* TFD_QUEUE_SIZE_MAX
;
283 /* Driver private data, only for Tx (not command) queues,
284 * not shared with device. */
285 if (id
!= IWL_CMD_QUEUE_NUM
) {
286 txq
->txb
= kmalloc(sizeof(txq
->txb
[0]) *
287 TFD_QUEUE_SIZE_MAX
, GFP_KERNEL
);
289 IWL_ERR(priv
, "kmalloc for auxiliary BD "
290 "structures failed\n");
297 /* Circular buffer of transmit frame descriptors (TFDs),
298 * shared with device */
299 txq
->tfds
= pci_alloc_consistent(dev
, tfd_sz
, &txq
->q
.dma_addr
);
302 IWL_ERR(priv
, "pci_alloc_consistent(%zd) failed\n", tfd_sz
);
317 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
319 int iwl_tx_queue_init(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
,
320 int slots_num
, u32 txq_id
)
326 * Alloc buffer array for commands (Tx or other types of commands).
327 * For the command queue (#4), allocate command space + one big
328 * command for scan, since scan command is very huge; the system will
329 * not have two scans at the same time, so only one is needed.
330 * For normal Tx queues (all other queues), no super-size command
333 len
= sizeof(struct iwl_cmd
);
334 for (i
= 0; i
<= slots_num
; i
++) {
335 if (i
== slots_num
) {
336 if (txq_id
== IWL_CMD_QUEUE_NUM
)
337 len
+= IWL_MAX_SCAN_SIZE
;
342 txq
->cmd
[i
] = kmalloc(len
, GFP_KERNEL
);
347 /* Alloc driver data array and TFD circular buffer */
348 ret
= iwl_tx_queue_alloc(priv
, txq
, txq_id
);
352 txq
->need_update
= 0;
354 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
355 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
356 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
358 /* Initialize queue's high/low-water marks, and head/tail indexes */
359 iwl_queue_init(priv
, &txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
, txq_id
);
361 /* Tell device where to find queue */
362 priv
->cfg
->ops
->lib
->txq_init(priv
, txq
);
366 for (i
= 0; i
< slots_num
; i
++) {
371 if (txq_id
== IWL_CMD_QUEUE_NUM
) {
372 kfree(txq
->cmd
[slots_num
]);
373 txq
->cmd
[slots_num
] = NULL
;
377 EXPORT_SYMBOL(iwl_tx_queue_init
);
380 * iwl_hw_txq_ctx_free - Free TXQ Context
382 * Destroy all TX DMA queues and structures
384 void iwl_hw_txq_ctx_free(struct iwl_priv
*priv
)
389 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
390 if (txq_id
== IWL_CMD_QUEUE_NUM
)
391 iwl_cmd_queue_free(priv
);
393 iwl_tx_queue_free(priv
, txq_id
);
395 iwl_free_dma_ptr(priv
, &priv
->kw
);
397 iwl_free_dma_ptr(priv
, &priv
->scd_bc_tbls
);
399 EXPORT_SYMBOL(iwl_hw_txq_ctx_free
);
402 * iwl_txq_ctx_reset - Reset TX queue context
403 * Destroys all DMA structures and initialize them again
408 int iwl_txq_ctx_reset(struct iwl_priv
*priv
)
411 int txq_id
, slots_num
;
414 /* Free all tx/cmd queues and keep-warm buffer */
415 iwl_hw_txq_ctx_free(priv
);
417 ret
= iwl_alloc_dma_ptr(priv
, &priv
->scd_bc_tbls
,
418 priv
->hw_params
.scd_bc_tbls_size
);
420 IWL_ERR(priv
, "Scheduler BC Table allocation failed\n");
423 /* Alloc keep-warm buffer */
424 ret
= iwl_alloc_dma_ptr(priv
, &priv
->kw
, IWL_KW_SIZE
);
426 IWL_ERR(priv
, "Keep Warm allocation failed\n");
429 spin_lock_irqsave(&priv
->lock
, flags
);
430 ret
= iwl_grab_nic_access(priv
);
432 spin_unlock_irqrestore(&priv
->lock
, flags
);
436 /* Turn off all Tx DMA fifos */
437 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
439 /* Tell NIC where to find the "keep warm" buffer */
440 iwl_write_direct32(priv
, FH_KW_MEM_ADDR_REG
, priv
->kw
.dma
>> 4);
442 iwl_release_nic_access(priv
);
443 spin_unlock_irqrestore(&priv
->lock
, flags
);
445 /* Alloc and init all Tx queues, including the command queue (#4) */
446 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
447 slots_num
= (txq_id
== IWL_CMD_QUEUE_NUM
) ?
448 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
449 ret
= iwl_tx_queue_init(priv
, &priv
->txq
[txq_id
], slots_num
,
452 IWL_ERR(priv
, "Tx %d queue init failed\n", txq_id
);
460 iwl_hw_txq_ctx_free(priv
);
462 iwl_free_dma_ptr(priv
, &priv
->kw
);
464 iwl_free_dma_ptr(priv
, &priv
->scd_bc_tbls
);
470 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
472 void iwl_txq_ctx_stop(struct iwl_priv
*priv
)
477 /* Turn off all Tx DMA fifos */
478 spin_lock_irqsave(&priv
->lock
, flags
);
479 if (iwl_grab_nic_access(priv
)) {
480 spin_unlock_irqrestore(&priv
->lock
, flags
);
484 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
486 /* Stop each Tx DMA channel, and wait for it to be idle */
487 for (ch
= 0; ch
< priv
->hw_params
.dma_chnl_num
; ch
++) {
488 iwl_write_direct32(priv
, FH_TCSR_CHNL_TX_CONFIG_REG(ch
), 0x0);
489 iwl_poll_direct_bit(priv
, FH_TSSR_TX_STATUS_REG
,
490 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch
),
493 iwl_release_nic_access(priv
);
494 spin_unlock_irqrestore(&priv
->lock
, flags
);
496 /* Deallocate memory for all Tx queues */
497 iwl_hw_txq_ctx_free(priv
);
499 EXPORT_SYMBOL(iwl_txq_ctx_stop
);
502 * handle build REPLY_TX command notification.
504 static void iwl_tx_cmd_build_basic(struct iwl_priv
*priv
,
505 struct iwl_tx_cmd
*tx_cmd
,
506 struct ieee80211_tx_info
*info
,
507 struct ieee80211_hdr
*hdr
,
510 __le16 fc
= hdr
->frame_control
;
511 __le32 tx_flags
= tx_cmd
->tx_flags
;
513 tx_cmd
->stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
514 if (!(info
->flags
& IEEE80211_TX_CTL_NO_ACK
)) {
515 tx_flags
|= TX_CMD_FLG_ACK_MSK
;
516 if (ieee80211_is_mgmt(fc
))
517 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
518 if (ieee80211_is_probe_resp(fc
) &&
519 !(le16_to_cpu(hdr
->seq_ctrl
) & 0xf))
520 tx_flags
|= TX_CMD_FLG_TSF_MSK
;
522 tx_flags
&= (~TX_CMD_FLG_ACK_MSK
);
523 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
526 if (ieee80211_is_back_req(fc
))
527 tx_flags
|= TX_CMD_FLG_ACK_MSK
| TX_CMD_FLG_IMM_BA_RSP_MASK
;
530 tx_cmd
->sta_id
= std_id
;
531 if (ieee80211_has_morefrags(fc
))
532 tx_flags
|= TX_CMD_FLG_MORE_FRAG_MSK
;
534 if (ieee80211_is_data_qos(fc
)) {
535 u8
*qc
= ieee80211_get_qos_ctl(hdr
);
536 tx_cmd
->tid_tspec
= qc
[0] & 0xf;
537 tx_flags
&= ~TX_CMD_FLG_SEQ_CTL_MSK
;
539 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
542 priv
->cfg
->ops
->utils
->rts_tx_cmd_flag(info
, &tx_flags
);
544 if ((tx_flags
& TX_CMD_FLG_RTS_MSK
) || (tx_flags
& TX_CMD_FLG_CTS_MSK
))
545 tx_flags
|= TX_CMD_FLG_FULL_TXOP_PROT_MSK
;
547 tx_flags
&= ~(TX_CMD_FLG_ANT_SEL_MSK
);
548 if (ieee80211_is_mgmt(fc
)) {
549 if (ieee80211_is_assoc_req(fc
) || ieee80211_is_reassoc_req(fc
))
550 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(3);
552 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(2);
554 tx_cmd
->timeout
.pm_frame_timeout
= 0;
557 tx_cmd
->driver_txop
= 0;
558 tx_cmd
->tx_flags
= tx_flags
;
559 tx_cmd
->next_frame_len
= 0;
562 #define RTS_HCCA_RETRY_LIMIT 3
563 #define RTS_DFAULT_RETRY_LIMIT 60
565 static void iwl_tx_cmd_build_rate(struct iwl_priv
*priv
,
566 struct iwl_tx_cmd
*tx_cmd
,
567 struct ieee80211_tx_info
*info
,
568 __le16 fc
, int sta_id
,
573 u8 rts_retry_limit
= 0;
574 u8 data_retry_limit
= 0;
577 rate_idx
= min(ieee80211_get_tx_rate(priv
->hw
, info
)->hw_value
& 0xffff,
580 rate_plcp
= iwl_rates
[rate_idx
].plcp
;
582 rts_retry_limit
= (is_hcca
) ?
583 RTS_HCCA_RETRY_LIMIT
: RTS_DFAULT_RETRY_LIMIT
;
585 if ((rate_idx
>= IWL_FIRST_CCK_RATE
) && (rate_idx
<= IWL_LAST_CCK_RATE
))
586 rate_flags
|= RATE_MCS_CCK_MSK
;
589 if (ieee80211_is_probe_resp(fc
)) {
590 data_retry_limit
= 3;
591 if (data_retry_limit
< rts_retry_limit
)
592 rts_retry_limit
= data_retry_limit
;
594 data_retry_limit
= IWL_DEFAULT_TX_RETRY
;
596 if (priv
->data_retry_limit
!= -1)
597 data_retry_limit
= priv
->data_retry_limit
;
600 if (ieee80211_is_data(fc
)) {
601 tx_cmd
->initial_rate_index
= 0;
602 tx_cmd
->tx_flags
|= TX_CMD_FLG_STA_RATE_MSK
;
604 switch (fc
& cpu_to_le16(IEEE80211_FCTL_STYPE
)) {
605 case cpu_to_le16(IEEE80211_STYPE_AUTH
):
606 case cpu_to_le16(IEEE80211_STYPE_DEAUTH
):
607 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ
):
608 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ
):
609 if (tx_cmd
->tx_flags
& TX_CMD_FLG_RTS_MSK
) {
610 tx_cmd
->tx_flags
&= ~TX_CMD_FLG_RTS_MSK
;
611 tx_cmd
->tx_flags
|= TX_CMD_FLG_CTS_MSK
;
618 priv
->mgmt_tx_ant
= iwl_toggle_tx_ant(priv
, priv
->mgmt_tx_ant
);
619 rate_flags
|= iwl_ant_idx_to_flags(priv
->mgmt_tx_ant
);
622 tx_cmd
->rts_retry_limit
= rts_retry_limit
;
623 tx_cmd
->data_retry_limit
= data_retry_limit
;
624 tx_cmd
->rate_n_flags
= iwl_hw_set_rate_n_flags(rate_plcp
, rate_flags
);
627 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv
*priv
,
628 struct ieee80211_tx_info
*info
,
629 struct iwl_tx_cmd
*tx_cmd
,
630 struct sk_buff
*skb_frag
,
633 struct ieee80211_key_conf
*keyconf
= info
->control
.hw_key
;
635 switch (keyconf
->alg
) {
637 tx_cmd
->sec_ctl
= TX_CMD_SEC_CCM
;
638 memcpy(tx_cmd
->key
, keyconf
->key
, keyconf
->keylen
);
639 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
640 tx_cmd
->tx_flags
|= TX_CMD_FLG_AGG_CCMP_MSK
;
641 IWL_DEBUG_TX(priv
, "tx_cmd with AES hwcrypto\n");
645 tx_cmd
->sec_ctl
= TX_CMD_SEC_TKIP
;
646 ieee80211_get_tkip_key(keyconf
, skb_frag
,
647 IEEE80211_TKIP_P2_KEY
, tx_cmd
->key
);
648 IWL_DEBUG_TX(priv
, "tx_cmd with tkip hwcrypto\n");
652 tx_cmd
->sec_ctl
|= (TX_CMD_SEC_WEP
|
653 (keyconf
->keyidx
& TX_CMD_SEC_MSK
) << TX_CMD_SEC_SHIFT
);
655 if (keyconf
->keylen
== WEP_KEY_LEN_128
)
656 tx_cmd
->sec_ctl
|= TX_CMD_SEC_KEY128
;
658 memcpy(&tx_cmd
->key
[3], keyconf
->key
, keyconf
->keylen
);
660 IWL_DEBUG_TX(priv
, "Configuring packet for WEP encryption "
661 "with key %d\n", keyconf
->keyidx
);
665 IWL_ERR(priv
, "Unknown encode alg %d\n", keyconf
->alg
);
670 static void iwl_update_tx_stats(struct iwl_priv
*priv
, u16 fc
, u16 len
)
672 /* 0 - mgmt, 1 - cnt, 2 - data */
673 int idx
= (fc
& IEEE80211_FCTL_FTYPE
) >> 2;
674 priv
->tx_stats
[idx
].cnt
++;
675 priv
->tx_stats
[idx
].bytes
+= len
;
679 * start REPLY_TX command process
681 int iwl_tx_skb(struct iwl_priv
*priv
, struct sk_buff
*skb
)
683 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
684 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
685 struct iwl_tx_queue
*txq
;
687 struct iwl_cmd
*out_cmd
;
688 struct iwl_tx_cmd
*tx_cmd
;
690 dma_addr_t phys_addr
;
691 dma_addr_t txcmd_phys
;
692 dma_addr_t scratch_phys
;
698 u8 wait_write_ptr
= 0;
704 spin_lock_irqsave(&priv
->lock
, flags
);
705 if (iwl_is_rfkill(priv
)) {
706 IWL_DEBUG_DROP(priv
, "Dropping - RF KILL\n");
710 if ((ieee80211_get_tx_rate(priv
->hw
, info
)->hw_value
& 0xFF) ==
712 IWL_ERR(priv
, "ERROR: No TX rate available.\n");
716 fc
= hdr
->frame_control
;
718 #ifdef CONFIG_IWLWIFI_DEBUG
719 if (ieee80211_is_auth(fc
))
720 IWL_DEBUG_TX(priv
, "Sending AUTH frame\n");
721 else if (ieee80211_is_assoc_req(fc
))
722 IWL_DEBUG_TX(priv
, "Sending ASSOC frame\n");
723 else if (ieee80211_is_reassoc_req(fc
))
724 IWL_DEBUG_TX(priv
, "Sending REASSOC frame\n");
727 /* drop all data frame if we are not associated */
728 if (ieee80211_is_data(fc
) &&
729 (priv
->iw_mode
!= NL80211_IFTYPE_MONITOR
||
730 !(info
->flags
& IEEE80211_TX_CTL_INJECTED
)) && /* packet injection */
731 (!iwl_is_associated(priv
) ||
732 ((priv
->iw_mode
== NL80211_IFTYPE_STATION
) && !priv
->assoc_id
) ||
733 !priv
->assoc_station_added
)) {
734 IWL_DEBUG_DROP(priv
, "Dropping - !iwl_is_associated\n");
738 spin_unlock_irqrestore(&priv
->lock
, flags
);
740 hdr_len
= ieee80211_hdrlen(fc
);
742 /* Find (or create) index into station table for destination station */
743 sta_id
= iwl_get_sta_id(priv
, hdr
);
744 if (sta_id
== IWL_INVALID_STATION
) {
745 IWL_DEBUG_DROP(priv
, "Dropping - INVALID STATION: %pM\n",
750 IWL_DEBUG_TX(priv
, "station Id %d\n", sta_id
);
752 swq_id
= skb_get_queue_mapping(skb
);
754 if (ieee80211_is_data_qos(fc
)) {
755 qc
= ieee80211_get_qos_ctl(hdr
);
756 tid
= qc
[0] & IEEE80211_QOS_CTL_TID_MASK
;
757 seq_number
= priv
->stations
[sta_id
].tid
[tid
].seq_number
;
758 seq_number
&= IEEE80211_SCTL_SEQ
;
759 hdr
->seq_ctrl
= hdr
->seq_ctrl
&
760 cpu_to_le16(IEEE80211_SCTL_FRAG
);
761 hdr
->seq_ctrl
|= cpu_to_le16(seq_number
);
763 /* aggregation is on for this <sta,tid> */
764 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
765 txq_id
= priv
->stations
[sta_id
].tid
[tid
].agg
.txq_id
;
766 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
++;
769 txq
= &priv
->txq
[txq_id
];
771 txq
->swq_id
= swq_id
;
773 spin_lock_irqsave(&priv
->lock
, flags
);
775 /* Set up driver data for this TFD */
776 memset(&(txq
->txb
[q
->write_ptr
]), 0, sizeof(struct iwl_tx_info
));
777 txq
->txb
[q
->write_ptr
].skb
[0] = skb
;
779 /* Set up first empty entry in queue's array of Tx/cmd buffers */
780 out_cmd
= txq
->cmd
[q
->write_ptr
];
781 tx_cmd
= &out_cmd
->cmd
.tx
;
782 memset(&out_cmd
->hdr
, 0, sizeof(out_cmd
->hdr
));
783 memset(tx_cmd
, 0, sizeof(struct iwl_tx_cmd
));
786 * Set up the Tx-command (not MAC!) header.
787 * Store the chosen Tx queue and TFD index within the sequence field;
788 * after Tx, uCode's Tx response will return this value so driver can
789 * locate the frame within the tx queue and do post-tx processing.
791 out_cmd
->hdr
.cmd
= REPLY_TX
;
792 out_cmd
->hdr
.sequence
= cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
793 INDEX_TO_SEQ(q
->write_ptr
)));
795 /* Copy MAC header from skb into command buffer */
796 memcpy(tx_cmd
->hdr
, hdr
, hdr_len
);
799 * Use the first empty entry in this queue's command buffer array
800 * to contain the Tx command and MAC header concatenated together
801 * (payload data will be in another buffer).
802 * Size of this varies, due to varying MAC header length.
803 * If end is not dword aligned, we'll have 2 extra bytes at the end
804 * of the MAC header (device reads on dword boundaries).
805 * We'll tell device about this padding later.
807 len
= sizeof(struct iwl_tx_cmd
) +
808 sizeof(struct iwl_cmd_header
) + hdr_len
;
811 len
= (len
+ 3) & ~3;
818 /* Physical address of this Tx command's header (not MAC header!),
819 * within command buffer array. */
820 txcmd_phys
= pci_map_single(priv
->pci_dev
,
821 out_cmd
, sizeof(struct iwl_cmd
),
823 pci_unmap_addr_set(&out_cmd
->meta
, mapping
, txcmd_phys
);
824 pci_unmap_len_set(&out_cmd
->meta
, len
, sizeof(struct iwl_cmd
));
825 /* Add buffer containing Tx command and MAC(!) header to TFD's
827 txcmd_phys
+= offsetof(struct iwl_cmd
, hdr
);
828 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
829 txcmd_phys
, len
, 1, 0);
831 if (info
->control
.hw_key
)
832 iwl_tx_cmd_build_hwcrypto(priv
, info
, tx_cmd
, skb
, sta_id
);
834 /* Set up TFD's 2nd entry to point directly to remainder of skb,
835 * if any (802.11 null frames have no payload). */
836 len
= skb
->len
- hdr_len
;
838 phys_addr
= pci_map_single(priv
->pci_dev
, skb
->data
+ hdr_len
,
839 len
, PCI_DMA_TODEVICE
);
840 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
845 /* Tell NIC about any 2-byte padding after MAC header */
847 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
849 /* Total # bytes to be transmitted */
851 tx_cmd
->len
= cpu_to_le16(len
);
852 /* TODO need this for burst mode later on */
853 iwl_tx_cmd_build_basic(priv
, tx_cmd
, info
, hdr
, sta_id
);
855 /* set is_hcca to 0; it probably will never be implemented */
856 iwl_tx_cmd_build_rate(priv
, tx_cmd
, info
, fc
, sta_id
, 0);
858 iwl_update_tx_stats(priv
, le16_to_cpu(fc
), len
);
860 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
861 offsetof(struct iwl_tx_cmd
, scratch
);
862 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
863 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_addr(scratch_phys
);
865 if (!ieee80211_has_morefrags(hdr
->frame_control
)) {
866 txq
->need_update
= 1;
868 priv
->stations
[sta_id
].tid
[tid
].seq_number
= seq_number
;
871 txq
->need_update
= 0;
874 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
, sizeof(*tx_cmd
));
876 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
->hdr
, hdr_len
);
878 /* Set up entry for this TFD in Tx byte-count array */
879 priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl(priv
, txq
, len
);
881 /* Tell device the write index *just past* this latest filled TFD */
882 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
883 ret
= iwl_txq_update_write_ptr(priv
, txq
);
884 spin_unlock_irqrestore(&priv
->lock
, flags
);
889 if ((iwl_queue_space(q
) < q
->high_mark
) && priv
->mac80211_registered
) {
890 if (wait_write_ptr
) {
891 spin_lock_irqsave(&priv
->lock
, flags
);
892 txq
->need_update
= 1;
893 iwl_txq_update_write_ptr(priv
, txq
);
894 spin_unlock_irqrestore(&priv
->lock
, flags
);
896 ieee80211_stop_queue(priv
->hw
, txq
->swq_id
);
903 spin_unlock_irqrestore(&priv
->lock
, flags
);
907 EXPORT_SYMBOL(iwl_tx_skb
);
909 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
912 * iwl_enqueue_hcmd - enqueue a uCode command
913 * @priv: device private data point
914 * @cmd: a point to the ucode command structure
916 * The function returns < 0 values to indicate the operation is
917 * failed. On success, it turns the index (> 0) of command in the
920 int iwl_enqueue_hcmd(struct iwl_priv
*priv
, struct iwl_host_cmd
*cmd
)
922 struct iwl_tx_queue
*txq
= &priv
->txq
[IWL_CMD_QUEUE_NUM
];
923 struct iwl_queue
*q
= &txq
->q
;
924 struct iwl_cmd
*out_cmd
;
925 dma_addr_t phys_addr
;
931 cmd
->len
= priv
->cfg
->ops
->utils
->get_hcmd_size(cmd
->id
, cmd
->len
);
932 fix_size
= (u16
)(cmd
->len
+ sizeof(out_cmd
->hdr
));
934 /* If any of the command structures end up being larger than
935 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
936 * we will need to increase the size of the TFD entries */
937 BUG_ON((fix_size
> TFD_MAX_PAYLOAD_SIZE
) &&
938 !(cmd
->meta
.flags
& CMD_SIZE_HUGE
));
940 if (iwl_is_rfkill(priv
)) {
941 IWL_DEBUG_INFO(priv
, "Not sending command - RF KILL");
945 if (iwl_queue_space(q
) < ((cmd
->meta
.flags
& CMD_ASYNC
) ? 2 : 1)) {
946 IWL_ERR(priv
, "No space for Tx\n");
950 spin_lock_irqsave(&priv
->hcmd_lock
, flags
);
952 idx
= get_cmd_index(q
, q
->write_ptr
, cmd
->meta
.flags
& CMD_SIZE_HUGE
);
953 out_cmd
= txq
->cmd
[idx
];
955 out_cmd
->hdr
.cmd
= cmd
->id
;
956 memcpy(&out_cmd
->meta
, &cmd
->meta
, sizeof(cmd
->meta
));
957 memcpy(&out_cmd
->cmd
.payload
, cmd
->data
, cmd
->len
);
959 /* At this point, the out_cmd now has all of the incoming cmd
962 out_cmd
->hdr
.flags
= 0;
963 out_cmd
->hdr
.sequence
= cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM
) |
964 INDEX_TO_SEQ(q
->write_ptr
));
965 if (out_cmd
->meta
.flags
& CMD_SIZE_HUGE
)
966 out_cmd
->hdr
.sequence
|= SEQ_HUGE_FRAME
;
967 len
= (idx
== TFD_CMD_SLOTS
) ?
968 IWL_MAX_SCAN_SIZE
: sizeof(struct iwl_cmd
);
970 phys_addr
= pci_map_single(priv
->pci_dev
, out_cmd
,
971 len
, PCI_DMA_TODEVICE
);
972 pci_unmap_addr_set(&out_cmd
->meta
, mapping
, phys_addr
);
973 pci_unmap_len_set(&out_cmd
->meta
, len
, len
);
974 phys_addr
+= offsetof(struct iwl_cmd
, hdr
);
976 priv
->cfg
->ops
->lib
->txq_attach_buf_to_tfd(priv
, txq
,
977 phys_addr
, fix_size
, 1,
980 #ifdef CONFIG_IWLWIFI_DEBUG
981 switch (out_cmd
->hdr
.cmd
) {
982 case REPLY_TX_LINK_QUALITY_CMD
:
983 case SENSITIVITY_CMD
:
984 IWL_DEBUG_HC_DUMP(priv
, "Sending command %s (#%x), seq: 0x%04X, "
985 "%d bytes at %d[%d]:%d\n",
986 get_cmd_string(out_cmd
->hdr
.cmd
),
988 le16_to_cpu(out_cmd
->hdr
.sequence
), fix_size
,
989 q
->write_ptr
, idx
, IWL_CMD_QUEUE_NUM
);
992 IWL_DEBUG_HC(priv
, "Sending command %s (#%x), seq: 0x%04X, "
993 "%d bytes at %d[%d]:%d\n",
994 get_cmd_string(out_cmd
->hdr
.cmd
),
996 le16_to_cpu(out_cmd
->hdr
.sequence
), fix_size
,
997 q
->write_ptr
, idx
, IWL_CMD_QUEUE_NUM
);
1000 txq
->need_update
= 1;
1002 if (priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl
)
1003 /* Set up entry in queue's byte count circular buffer */
1004 priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl(priv
, txq
, 0);
1006 /* Increment and update queue's write index */
1007 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1008 ret
= iwl_txq_update_write_ptr(priv
, txq
);
1010 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
1011 return ret
? ret
: idx
;
1014 int iwl_tx_queue_reclaim(struct iwl_priv
*priv
, int txq_id
, int index
)
1016 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1017 struct iwl_queue
*q
= &txq
->q
;
1018 struct iwl_tx_info
*tx_info
;
1021 if ((index
>= q
->n_bd
) || (iwl_queue_used(q
, index
) == 0)) {
1022 IWL_ERR(priv
, "Read index for DMA queue txq id (%d), index %d, "
1023 "is out of range [0-%d] %d %d.\n", txq_id
,
1024 index
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
1028 for (index
= iwl_queue_inc_wrap(index
, q
->n_bd
);
1029 q
->read_ptr
!= index
;
1030 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1032 tx_info
= &txq
->txb
[txq
->q
.read_ptr
];
1033 ieee80211_tx_status_irqsafe(priv
->hw
, tx_info
->skb
[0]);
1034 tx_info
->skb
[0] = NULL
;
1036 if (priv
->cfg
->ops
->lib
->txq_inval_byte_cnt_tbl
)
1037 priv
->cfg
->ops
->lib
->txq_inval_byte_cnt_tbl(priv
, txq
);
1039 priv
->cfg
->ops
->lib
->txq_free_tfd(priv
, txq
);
1044 EXPORT_SYMBOL(iwl_tx_queue_reclaim
);
1048 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1050 * When FW advances 'R' index, all entries between old and new 'R' index
1051 * need to be reclaimed. As result, some free space forms. If there is
1052 * enough free space (> low mark), wake the stack that feeds us.
1054 static void iwl_hcmd_queue_reclaim(struct iwl_priv
*priv
, int txq_id
,
1055 int idx
, int cmd_idx
)
1057 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1058 struct iwl_queue
*q
= &txq
->q
;
1061 if ((idx
>= q
->n_bd
) || (iwl_queue_used(q
, idx
) == 0)) {
1062 IWL_ERR(priv
, "Read index for DMA queue txq id (%d), index %d, "
1063 "is out of range [0-%d] %d %d.\n", txq_id
,
1064 idx
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
1068 pci_unmap_single(priv
->pci_dev
,
1069 pci_unmap_addr(&txq
->cmd
[cmd_idx
]->meta
, mapping
),
1070 pci_unmap_len(&txq
->cmd
[cmd_idx
]->meta
, len
),
1073 for (idx
= iwl_queue_inc_wrap(idx
, q
->n_bd
); q
->read_ptr
!= idx
;
1074 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1077 IWL_ERR(priv
, "HCMD skipped: index (%d) %d %d\n", idx
,
1078 q
->write_ptr
, q
->read_ptr
);
1079 queue_work(priv
->workqueue
, &priv
->restart
);
1086 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1087 * @rxb: Rx buffer to reclaim
1089 * If an Rx buffer has an async callback associated with it the callback
1090 * will be executed. The attached skb (if present) will only be freed
1091 * if the callback returns 1
1093 void iwl_tx_cmd_complete(struct iwl_priv
*priv
, struct iwl_rx_mem_buffer
*rxb
)
1095 struct iwl_rx_packet
*pkt
= (struct iwl_rx_packet
*)rxb
->skb
->data
;
1096 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1097 int txq_id
= SEQ_TO_QUEUE(sequence
);
1098 int index
= SEQ_TO_INDEX(sequence
);
1100 bool huge
= !!(pkt
->hdr
.sequence
& SEQ_HUGE_FRAME
);
1101 struct iwl_cmd
*cmd
;
1103 /* If a Tx command is being handled and it isn't in the actual
1104 * command queue then there a command routing bug has been introduced
1105 * in the queue management code. */
1106 if (WARN(txq_id
!= IWL_CMD_QUEUE_NUM
,
1107 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1109 priv
->txq
[IWL_CMD_QUEUE_NUM
].q
.read_ptr
,
1110 priv
->txq
[IWL_CMD_QUEUE_NUM
].q
.write_ptr
)) {
1111 iwl_print_hex_dump(priv
, IWL_DL_INFO
, rxb
, 32);
1115 cmd_index
= get_cmd_index(&priv
->txq
[IWL_CMD_QUEUE_NUM
].q
, index
, huge
);
1116 cmd
= priv
->txq
[IWL_CMD_QUEUE_NUM
].cmd
[cmd_index
];
1118 /* Input error checking is done when commands are added to queue. */
1119 if (cmd
->meta
.flags
& CMD_WANT_SKB
) {
1120 cmd
->meta
.source
->u
.skb
= rxb
->skb
;
1122 } else if (cmd
->meta
.u
.callback
&&
1123 !cmd
->meta
.u
.callback(priv
, cmd
, rxb
->skb
))
1126 iwl_hcmd_queue_reclaim(priv
, txq_id
, index
, cmd_index
);
1128 if (!(cmd
->meta
.flags
& CMD_ASYNC
)) {
1129 clear_bit(STATUS_HCMD_ACTIVE
, &priv
->status
);
1130 wake_up_interruptible(&priv
->wait_command_queue
);
1133 EXPORT_SYMBOL(iwl_tx_cmd_complete
);
1136 * Find first available (lowest unused) Tx Queue, mark it "active".
1137 * Called only when finding queue for aggregation.
1138 * Should never return anything < 7, because they should already
1139 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1141 static int iwl_txq_ctx_activate_free(struct iwl_priv
*priv
)
1145 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
1146 if (!test_and_set_bit(txq_id
, &priv
->txq_ctx_active_msk
))
1151 int iwl_tx_agg_start(struct iwl_priv
*priv
, const u8
*ra
, u16 tid
, u16
*ssn
)
1157 unsigned long flags
;
1158 struct iwl_tid_data
*tid_data
;
1160 if (likely(tid
< ARRAY_SIZE(default_tid_to_tx_fifo
)))
1161 tx_fifo
= default_tid_to_tx_fifo
[tid
];
1165 IWL_WARN(priv
, "%s on ra = %pM tid = %d\n",
1168 sta_id
= iwl_find_station(priv
, ra
);
1169 if (sta_id
== IWL_INVALID_STATION
)
1172 if (priv
->stations
[sta_id
].tid
[tid
].agg
.state
!= IWL_AGG_OFF
) {
1173 IWL_ERR(priv
, "Start AGG when state is not IWL_AGG_OFF !\n");
1177 txq_id
= iwl_txq_ctx_activate_free(priv
);
1181 spin_lock_irqsave(&priv
->sta_lock
, flags
);
1182 tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1183 *ssn
= SEQ_TO_SN(tid_data
->seq_number
);
1184 tid_data
->agg
.txq_id
= txq_id
;
1185 spin_unlock_irqrestore(&priv
->sta_lock
, flags
);
1187 ret
= priv
->cfg
->ops
->lib
->txq_agg_enable(priv
, txq_id
, tx_fifo
,
1192 if (tid_data
->tfds_in_queue
== 0) {
1193 IWL_ERR(priv
, "HW queue is empty\n");
1194 tid_data
->agg
.state
= IWL_AGG_ON
;
1195 ieee80211_start_tx_ba_cb_irqsafe(priv
->hw
, ra
, tid
);
1197 IWL_DEBUG_HT(priv
, "HW queue is NOT empty: %d packets in HW queue\n",
1198 tid_data
->tfds_in_queue
);
1199 tid_data
->agg
.state
= IWL_EMPTYING_HW_QUEUE_ADDBA
;
1203 EXPORT_SYMBOL(iwl_tx_agg_start
);
1205 int iwl_tx_agg_stop(struct iwl_priv
*priv
, const u8
*ra
, u16 tid
)
1207 int tx_fifo_id
, txq_id
, sta_id
, ssn
= -1;
1208 struct iwl_tid_data
*tid_data
;
1209 int ret
, write_ptr
, read_ptr
;
1210 unsigned long flags
;
1213 IWL_ERR(priv
, "ra = NULL\n");
1217 if (likely(tid
< ARRAY_SIZE(default_tid_to_tx_fifo
)))
1218 tx_fifo_id
= default_tid_to_tx_fifo
[tid
];
1222 sta_id
= iwl_find_station(priv
, ra
);
1224 if (sta_id
== IWL_INVALID_STATION
)
1227 if (priv
->stations
[sta_id
].tid
[tid
].agg
.state
!= IWL_AGG_ON
)
1228 IWL_WARN(priv
, "Stopping AGG while state not IWL_AGG_ON\n");
1230 tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1231 ssn
= (tid_data
->seq_number
& IEEE80211_SCTL_SEQ
) >> 4;
1232 txq_id
= tid_data
->agg
.txq_id
;
1233 write_ptr
= priv
->txq
[txq_id
].q
.write_ptr
;
1234 read_ptr
= priv
->txq
[txq_id
].q
.read_ptr
;
1236 /* The queue is not empty */
1237 if (write_ptr
!= read_ptr
) {
1238 IWL_DEBUG_HT(priv
, "Stopping a non empty AGG HW QUEUE\n");
1239 priv
->stations
[sta_id
].tid
[tid
].agg
.state
=
1240 IWL_EMPTYING_HW_QUEUE_DELBA
;
1244 IWL_DEBUG_HT(priv
, "HW queue is empty\n");
1245 priv
->stations
[sta_id
].tid
[tid
].agg
.state
= IWL_AGG_OFF
;
1247 spin_lock_irqsave(&priv
->lock
, flags
);
1248 ret
= priv
->cfg
->ops
->lib
->txq_agg_disable(priv
, txq_id
, ssn
,
1250 spin_unlock_irqrestore(&priv
->lock
, flags
);
1255 ieee80211_stop_tx_ba_cb_irqsafe(priv
->hw
, ra
, tid
);
1259 EXPORT_SYMBOL(iwl_tx_agg_stop
);
1261 int iwl_txq_check_empty(struct iwl_priv
*priv
, int sta_id
, u8 tid
, int txq_id
)
1263 struct iwl_queue
*q
= &priv
->txq
[txq_id
].q
;
1264 u8
*addr
= priv
->stations
[sta_id
].sta
.sta
.addr
;
1265 struct iwl_tid_data
*tid_data
= &priv
->stations
[sta_id
].tid
[tid
];
1267 switch (priv
->stations
[sta_id
].tid
[tid
].agg
.state
) {
1268 case IWL_EMPTYING_HW_QUEUE_DELBA
:
1269 /* We are reclaiming the last packet of the */
1270 /* aggregated HW queue */
1271 if ((txq_id
== tid_data
->agg
.txq_id
) &&
1272 (q
->read_ptr
== q
->write_ptr
)) {
1273 u16 ssn
= SEQ_TO_SN(tid_data
->seq_number
);
1274 int tx_fifo
= default_tid_to_tx_fifo
[tid
];
1275 IWL_DEBUG_HT(priv
, "HW queue empty: continue DELBA flow\n");
1276 priv
->cfg
->ops
->lib
->txq_agg_disable(priv
, txq_id
,
1278 tid_data
->agg
.state
= IWL_AGG_OFF
;
1279 ieee80211_stop_tx_ba_cb_irqsafe(priv
->hw
, addr
, tid
);
1282 case IWL_EMPTYING_HW_QUEUE_ADDBA
:
1283 /* We are reclaiming the last packet of the queue */
1284 if (tid_data
->tfds_in_queue
== 0) {
1285 IWL_DEBUG_HT(priv
, "HW queue empty: continue ADDBA flow\n");
1286 tid_data
->agg
.state
= IWL_AGG_ON
;
1287 ieee80211_start_tx_ba_cb_irqsafe(priv
->hw
, addr
, tid
);
1293 EXPORT_SYMBOL(iwl_txq_check_empty
);
1296 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1298 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1299 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1301 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv
*priv
,
1302 struct iwl_ht_agg
*agg
,
1303 struct iwl_compressed_ba_resp
*ba_resp
)
1307 u16 seq_ctl
= le16_to_cpu(ba_resp
->seq_ctl
);
1308 u16 scd_flow
= le16_to_cpu(ba_resp
->scd_flow
);
1311 struct ieee80211_tx_info
*info
;
1313 if (unlikely(!agg
->wait_for_ba
)) {
1314 IWL_ERR(priv
, "Received BA when not expected\n");
1318 /* Mark that the expected block-ack response arrived */
1319 agg
->wait_for_ba
= 0;
1320 IWL_DEBUG_TX_REPLY(priv
, "BA %d %d\n", agg
->start_idx
, ba_resp
->seq_ctl
);
1322 /* Calculate shift to align block-ack bits with our Tx window bits */
1323 sh
= agg
->start_idx
- SEQ_TO_INDEX(seq_ctl
>> 4);
1324 if (sh
< 0) /* tbw something is wrong with indices */
1327 /* don't use 64-bit values for now */
1328 bitmap
= le64_to_cpu(ba_resp
->bitmap
) >> sh
;
1330 if (agg
->frame_count
> (64 - sh
)) {
1331 IWL_DEBUG_TX_REPLY(priv
, "more frames than bitmap size");
1335 /* check for success or failure according to the
1336 * transmitted bitmap and block-ack bitmap */
1337 bitmap
&= agg
->bitmap
;
1339 /* For each frame attempted in aggregation,
1340 * update driver's record of tx frame's status. */
1341 for (i
= 0; i
< agg
->frame_count
; i
++) {
1342 ack
= bitmap
& (1ULL << i
);
1344 IWL_DEBUG_TX_REPLY(priv
, "%s ON i=%d idx=%d raw=%d\n",
1345 ack
? "ACK" : "NACK", i
, (agg
->start_idx
+ i
) & 0xff,
1346 agg
->start_idx
+ i
);
1349 info
= IEEE80211_SKB_CB(priv
->txq
[scd_flow
].txb
[agg
->start_idx
].skb
[0]);
1350 memset(&info
->status
, 0, sizeof(info
->status
));
1351 info
->flags
= IEEE80211_TX_STAT_ACK
;
1352 info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
1353 info
->status
.ampdu_ack_map
= successes
;
1354 info
->status
.ampdu_ack_len
= agg
->frame_count
;
1355 iwl_hwrate_to_tx_control(priv
, agg
->rate_n_flags
, info
);
1357 IWL_DEBUG_TX_REPLY(priv
, "Bitmap %llx\n", (unsigned long long)bitmap
);
1363 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1365 * Handles block-acknowledge notification from device, which reports success
1366 * of frames sent via aggregation.
1368 void iwl_rx_reply_compressed_ba(struct iwl_priv
*priv
,
1369 struct iwl_rx_mem_buffer
*rxb
)
1371 struct iwl_rx_packet
*pkt
= (struct iwl_rx_packet
*)rxb
->skb
->data
;
1372 struct iwl_compressed_ba_resp
*ba_resp
= &pkt
->u
.compressed_ba
;
1373 struct iwl_tx_queue
*txq
= NULL
;
1374 struct iwl_ht_agg
*agg
;
1379 /* "flow" corresponds to Tx queue */
1380 u16 scd_flow
= le16_to_cpu(ba_resp
->scd_flow
);
1382 /* "ssn" is start of block-ack Tx window, corresponds to index
1383 * (in Tx queue's circular buffer) of first TFD/frame in window */
1384 u16 ba_resp_scd_ssn
= le16_to_cpu(ba_resp
->scd_ssn
);
1386 if (scd_flow
>= priv
->hw_params
.max_txq_num
) {
1388 "BUG_ON scd_flow is bigger than number of queues\n");
1392 txq
= &priv
->txq
[scd_flow
];
1393 sta_id
= ba_resp
->sta_id
;
1395 agg
= &priv
->stations
[sta_id
].tid
[tid
].agg
;
1397 /* Find index just before block-ack window */
1398 index
= iwl_queue_dec_wrap(ba_resp_scd_ssn
& 0xff, txq
->q
.n_bd
);
1400 /* TODO: Need to get this copy more safely - now good for debug */
1402 IWL_DEBUG_TX_REPLY(priv
, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1405 (u8
*) &ba_resp
->sta_addr_lo32
,
1407 IWL_DEBUG_TX_REPLY(priv
, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1408 "%d, scd_ssn = %d\n",
1411 (unsigned long long)le64_to_cpu(ba_resp
->bitmap
),
1414 IWL_DEBUG_TX_REPLY(priv
, "DAT start_idx = %d, bitmap = 0x%llx \n",
1416 (unsigned long long)agg
->bitmap
);
1418 /* Update driver's record of ACK vs. not for each frame in window */
1419 iwl_tx_status_reply_compressed_ba(priv
, agg
, ba_resp
);
1421 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1422 * block-ack window (we assume that they've been successfully
1423 * transmitted ... if not, it's too late anyway). */
1424 if (txq
->q
.read_ptr
!= (ba_resp_scd_ssn
& 0xff)) {
1425 /* calculate mac80211 ampdu sw queue to wake */
1426 int freed
= iwl_tx_queue_reclaim(priv
, scd_flow
, index
);
1427 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
-= freed
;
1429 if ((iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
) &&
1430 priv
->mac80211_registered
&&
1431 (agg
->state
!= IWL_EMPTYING_HW_QUEUE_DELBA
))
1432 ieee80211_wake_queue(priv
->hw
, txq
->swq_id
);
1434 iwl_txq_check_empty(priv
, sta_id
, tid
, scd_flow
);
1437 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba
);
1439 #ifdef CONFIG_IWLWIFI_DEBUG
1440 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1442 const char *iwl_get_tx_fail_reason(u32 status
)
1444 switch (status
& TX_STATUS_MSK
) {
1445 case TX_STATUS_SUCCESS
:
1447 TX_STATUS_ENTRY(SHORT_LIMIT
);
1448 TX_STATUS_ENTRY(LONG_LIMIT
);
1449 TX_STATUS_ENTRY(FIFO_UNDERRUN
);
1450 TX_STATUS_ENTRY(MGMNT_ABORT
);
1451 TX_STATUS_ENTRY(NEXT_FRAG
);
1452 TX_STATUS_ENTRY(LIFE_EXPIRE
);
1453 TX_STATUS_ENTRY(DEST_PS
);
1454 TX_STATUS_ENTRY(ABORTED
);
1455 TX_STATUS_ENTRY(BT_RETRY
);
1456 TX_STATUS_ENTRY(STA_INVALID
);
1457 TX_STATUS_ENTRY(FRAG_DROPPED
);
1458 TX_STATUS_ENTRY(TID_DISABLE
);
1459 TX_STATUS_ENTRY(FRAME_FLUSHED
);
1460 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL
);
1461 TX_STATUS_ENTRY(TX_LOCKED
);
1462 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR
);
1467 EXPORT_SYMBOL(iwl_get_tx_fail_reason
);
1468 #endif /* CONFIG_IWLWIFI_DEBUG */