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[NET]: Make NAPI polling independent of struct net_device objects.
[firewire-audio.git] / drivers / net / 8139too.c
blob20af6baecfcb58b01ec4826533c69823b24f40b9
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/ioport.h>
102 #include <linux/netdevice.h>
103 #include <linux/etherdevice.h>
104 #include <linux/rtnetlink.h>
105 #include <linux/delay.h>
106 #include <linux/ethtool.h>
107 #include <linux/mii.h>
108 #include <linux/completion.h>
109 #include <linux/crc32.h>
110 #include <asm/io.h>
111 #include <asm/uaccess.h>
112 #include <asm/irq.h>
113
114 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
115 #define PFX DRV_NAME ": "
116
117 /* Default Message level */
118 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
119 NETIF_MSG_PROBE | \
120 NETIF_MSG_LINK)
121
122
123 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
124 #ifdef CONFIG_8139TOO_PIO
125 #define USE_IO_OPS 1
126 #endif
127
128 /* define to 1, 2 or 3 to enable copious debugging info */
129 #define RTL8139_DEBUG 0
130
131 /* define to 1 to disable lightweight runtime debugging checks */
132 #undef RTL8139_NDEBUG
133
134
135 #if RTL8139_DEBUG
136 /* note: prints function name for you */
137 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
138 #else
139 # define DPRINTK(fmt, args...)
140 #endif
141
142 #ifdef RTL8139_NDEBUG
143 # define assert(expr) do {} while (0)
144 #else
145 # define assert(expr) \
146 if(unlikely(!(expr))) { \
147 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
148 #expr,__FILE__,__FUNCTION__,__LINE__); \
149 }
150 #endif
151
152
153 /* A few user-configurable values. */
154 /* media options */
155 #define MAX_UNITS 8
156 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
157 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
158
159 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
160 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
161 static int multicast_filter_limit = 32;
162
163 /* bitmapped message enable number */
164 static int debug = -1;
165
166 /*
167 * Receive ring size
168 * Warning: 64K ring has hardware issues and may lock up.
169 */
170 #if defined(CONFIG_SH_DREAMCAST)
171 #define RX_BUF_IDX 1 /* 16K ring */
172 #else
173 #define RX_BUF_IDX 2 /* 32K ring */
174 #endif
175 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
176 #define RX_BUF_PAD 16
177 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
178
179 #if RX_BUF_LEN == 65536
180 #define RX_BUF_TOT_LEN RX_BUF_LEN
181 #else
182 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
183 #endif
184
185 /* Number of Tx descriptor registers. */
186 #define NUM_TX_DESC 4
187
188 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
189 #define MAX_ETH_FRAME_SIZE 1536
190
191 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
192 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
193 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
194
195 /* PCI Tuning Parameters
196 Threshold is bytes transferred to chip before transmission starts. */
197 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
198
199 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
200 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
201 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
202 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
204
205 /* Operational parameters that usually are not changed. */
206 /* Time in jiffies before concluding the transmitter is hung. */
207 #define TX_TIMEOUT (6*HZ)
208
209
210 enum {
211 HAS_MII_XCVR = 0x010000,
212 HAS_CHIP_XCVR = 0x020000,
213 HAS_LNK_CHNG = 0x040000,
214 };
215
216 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
217 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
218 #define RTL_MIN_IO_SIZE 0x80
219 #define RTL8139B_IO_SIZE 256
220
221 #define RTL8129_CAPS HAS_MII_XCVR
222 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
223
224 typedef enum {
225 RTL8139 = 0,
226 RTL8129,
227 } board_t;
228
229
230 /* indexed by board_t, above */
231 static const struct {
232 const char *name;
233 u32 hw_flags;
234 } board_info[] __devinitdata = {
235 { "RealTek RTL8139", RTL8139_CAPS },
236 { "RealTek RTL8129", RTL8129_CAPS },
237 };
238
239
240 static struct pci_device_id rtl8139_pci_tbl[] = {
241 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260
261 #ifdef CONFIG_SH_SECUREEDGE5410
262 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
264 #endif
265 #ifdef CONFIG_8139TOO_8129
266 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
267 #endif
268
269 /* some crazy cards report invalid vendor ids like
270 * 0x0001 here. The other ids are valid and constant,
271 * so we simply don't match on the main vendor id.
272 */
273 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
274 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
276
277 {0,}
278 };
279 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
280
281 static struct {
282 const char str[ETH_GSTRING_LEN];
283 } ethtool_stats_keys[] = {
284 { "early_rx" },
285 { "tx_buf_mapped" },
286 { "tx_timeouts" },
287 { "rx_lost_in_ring" },
288 };
289
290 /* The rest of these values should never change. */
291
292 /* Symbolic offsets to registers. */
293 enum RTL8139_registers {
294 MAC0 = 0, /* Ethernet hardware address. */
295 MAR0 = 8, /* Multicast filter. */
296 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
297 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
298 RxBuf = 0x30,
299 ChipCmd = 0x37,
300 RxBufPtr = 0x38,
301 RxBufAddr = 0x3A,
302 IntrMask = 0x3C,
303 IntrStatus = 0x3E,
304 TxConfig = 0x40,
305 RxConfig = 0x44,
306 Timer = 0x48, /* A general-purpose counter. */
307 RxMissed = 0x4C, /* 24 bits valid, write clears. */
308 Cfg9346 = 0x50,
309 Config0 = 0x51,
310 Config1 = 0x52,
311 FlashReg = 0x54,
312 MediaStatus = 0x58,
313 Config3 = 0x59,
314 Config4 = 0x5A, /* absent on RTL-8139A */
315 HltClk = 0x5B,
316 MultiIntr = 0x5C,
317 TxSummary = 0x60,
318 BasicModeCtrl = 0x62,
319 BasicModeStatus = 0x64,
320 NWayAdvert = 0x66,
321 NWayLPAR = 0x68,
322 NWayExpansion = 0x6A,
323 /* Undocumented registers, but required for proper operation. */
324 FIFOTMS = 0x70, /* FIFO Control and test. */
325 CSCR = 0x74, /* Chip Status and Configuration Register. */
326 PARA78 = 0x78,
327 PARA7c = 0x7c, /* Magic transceiver parameter register. */
328 Config5 = 0xD8, /* absent on RTL-8139A */
329 };
330
331 enum ClearBitMasks {
332 MultiIntrClear = 0xF000,
333 ChipCmdClear = 0xE2,
334 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
335 };
336
337 enum ChipCmdBits {
338 CmdReset = 0x10,
339 CmdRxEnb = 0x08,
340 CmdTxEnb = 0x04,
341 RxBufEmpty = 0x01,
342 };
343
344 /* Interrupt register bits, using my own meaningful names. */
345 enum IntrStatusBits {
346 PCIErr = 0x8000,
347 PCSTimeout = 0x4000,
348 RxFIFOOver = 0x40,
349 RxUnderrun = 0x20,
350 RxOverflow = 0x10,
351 TxErr = 0x08,
352 TxOK = 0x04,
353 RxErr = 0x02,
354 RxOK = 0x01,
355
356 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
357 };
358
359 enum TxStatusBits {
360 TxHostOwns = 0x2000,
361 TxUnderrun = 0x4000,
362 TxStatOK = 0x8000,
363 TxOutOfWindow = 0x20000000,
364 TxAborted = 0x40000000,
365 TxCarrierLost = 0x80000000,
366 };
367 enum RxStatusBits {
368 RxMulticast = 0x8000,
369 RxPhysical = 0x4000,
370 RxBroadcast = 0x2000,
371 RxBadSymbol = 0x0020,
372 RxRunt = 0x0010,
373 RxTooLong = 0x0008,
374 RxCRCErr = 0x0004,
375 RxBadAlign = 0x0002,
376 RxStatusOK = 0x0001,
377 };
378
379 /* Bits in RxConfig. */
380 enum rx_mode_bits {
381 AcceptErr = 0x20,
382 AcceptRunt = 0x10,
383 AcceptBroadcast = 0x08,
384 AcceptMulticast = 0x04,
385 AcceptMyPhys = 0x02,
386 AcceptAllPhys = 0x01,
387 };
388
389 /* Bits in TxConfig. */
390 enum tx_config_bits {
391
392 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
393 TxIFGShift = 24,
394 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
395 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
396 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
397 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
398
399 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
400 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
401 TxClearAbt = (1 << 0), /* Clear abort (WO) */
402 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
403 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
404
405 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
406 };
407
408 /* Bits in Config1 */
409 enum Config1Bits {
410 Cfg1_PM_Enable = 0x01,
411 Cfg1_VPD_Enable = 0x02,
412 Cfg1_PIO = 0x04,
413 Cfg1_MMIO = 0x08,
414 LWAKE = 0x10, /* not on 8139, 8139A */
415 Cfg1_Driver_Load = 0x20,
416 Cfg1_LED0 = 0x40,
417 Cfg1_LED1 = 0x80,
418 SLEEP = (1 << 1), /* only on 8139, 8139A */
419 PWRDN = (1 << 0), /* only on 8139, 8139A */
420 };
421
422 /* Bits in Config3 */
423 enum Config3Bits {
424 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
425 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
426 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
427 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
428 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
429 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
430 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
431 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
432 };
433
434 /* Bits in Config4 */
435 enum Config4Bits {
436 LWPTN = (1 << 2), /* not on 8139, 8139A */
437 };
438
439 /* Bits in Config5 */
440 enum Config5Bits {
441 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
442 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
443 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
444 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
445 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
446 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
447 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
448 };
449
450 enum RxConfigBits {
451 /* rx fifo threshold */
452 RxCfgFIFOShift = 13,
453 RxCfgFIFONone = (7 << RxCfgFIFOShift),
454
455 /* Max DMA burst */
456 RxCfgDMAShift = 8,
457 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
458
459 /* rx ring buffer length */
460 RxCfgRcv8K = 0,
461 RxCfgRcv16K = (1 << 11),
462 RxCfgRcv32K = (1 << 12),
463 RxCfgRcv64K = (1 << 11) | (1 << 12),
464
465 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
466 RxNoWrap = (1 << 7),
467 };
468
469 /* Twister tuning parameters from RealTek.
470 Completely undocumented, but required to tune bad links on some boards. */
471 enum CSCRBits {
472 CSCR_LinkOKBit = 0x0400,
473 CSCR_LinkChangeBit = 0x0800,
474 CSCR_LinkStatusBits = 0x0f000,
475 CSCR_LinkDownOffCmd = 0x003c0,
476 CSCR_LinkDownCmd = 0x0f3c0,
477 };
478
479 enum Cfg9346Bits {
480 Cfg9346_Lock = 0x00,
481 Cfg9346_Unlock = 0xC0,
482 };
483
484 typedef enum {
485 CH_8139 = 0,
486 CH_8139_K,
487 CH_8139A,
488 CH_8139A_G,
489 CH_8139B,
490 CH_8130,
491 CH_8139C,
492 CH_8100,
493 CH_8100B_8139D,
494 CH_8101,
495 } chip_t;
496
497 enum chip_flags {
498 HasHltClk = (1 << 0),
499 HasLWake = (1 << 1),
500 };
501
502 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
503 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
504 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
505
506 /* directly indexed by chip_t, above */
507 static const struct {
508 const char *name;
509 u32 version; /* from RTL8139C/RTL8139D docs */
510 u32 flags;
511 } rtl_chip_info[] = {
512 { "RTL-8139",
513 HW_REVID(1, 0, 0, 0, 0, 0, 0),
514 HasHltClk,
515 },
516
517 { "RTL-8139 rev K",
518 HW_REVID(1, 1, 0, 0, 0, 0, 0),
519 HasHltClk,
520 },
521
522 { "RTL-8139A",
523 HW_REVID(1, 1, 1, 0, 0, 0, 0),
524 HasHltClk, /* XXX undocumented? */
525 },
526
527 { "RTL-8139A rev G",
528 HW_REVID(1, 1, 1, 0, 0, 1, 0),
529 HasHltClk, /* XXX undocumented? */
530 },
531
532 { "RTL-8139B",
533 HW_REVID(1, 1, 1, 1, 0, 0, 0),
534 HasLWake,
535 },
536
537 { "RTL-8130",
538 HW_REVID(1, 1, 1, 1, 1, 0, 0),
539 HasLWake,
540 },
541
542 { "RTL-8139C",
543 HW_REVID(1, 1, 1, 0, 1, 0, 0),
544 HasLWake,
545 },
546
547 { "RTL-8100",
548 HW_REVID(1, 1, 1, 1, 0, 1, 0),
549 HasLWake,
550 },
551
552 { "RTL-8100B/8139D",
553 HW_REVID(1, 1, 1, 0, 1, 0, 1),
554 HasHltClk /* XXX undocumented? */
555 | HasLWake,
556 },
557
558 { "RTL-8101",
559 HW_REVID(1, 1, 1, 0, 1, 1, 1),
560 HasLWake,
561 },
562 };
563
564 struct rtl_extra_stats {
565 unsigned long early_rx;
566 unsigned long tx_buf_mapped;
567 unsigned long tx_timeouts;
568 unsigned long rx_lost_in_ring;
569 };
570
571 struct rtl8139_private {
572 void __iomem *mmio_addr;
573 int drv_flags;
574 struct pci_dev *pci_dev;
575 u32 msg_enable;
576 struct napi_struct napi;
577 struct net_device *dev;
578 struct net_device_stats stats;
579 unsigned char *rx_ring;
580 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
581 unsigned int tx_flag;
582 unsigned long cur_tx;
583 unsigned long dirty_tx;
584 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
585 unsigned char *tx_bufs; /* Tx bounce buffer region. */
586 dma_addr_t rx_ring_dma;
587 dma_addr_t tx_bufs_dma;
588 signed char phys[4]; /* MII device addresses. */
589 char twistie, twist_row, twist_col; /* Twister tune state. */
590 unsigned int watchdog_fired : 1;
591 unsigned int default_port : 4; /* Last dev->if_port value. */
592 unsigned int have_thread : 1;
593 spinlock_t lock;
594 spinlock_t rx_lock;
595 chip_t chipset;
596 u32 rx_config;
597 struct rtl_extra_stats xstats;
598
599 struct delayed_work thread;
600
601 struct mii_if_info mii;
602 unsigned int regs_len;
603 unsigned long fifo_copy_timeout;
604 };
605
606 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
607 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
608 MODULE_LICENSE("GPL");
609 MODULE_VERSION(DRV_VERSION);
610
611 module_param(multicast_filter_limit, int, 0);
612 module_param_array(media, int, NULL, 0);
613 module_param_array(full_duplex, int, NULL, 0);
614 module_param(debug, int, 0);
615 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
616 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
617 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
618 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
619
620 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
621 static int rtl8139_open (struct net_device *dev);
622 static int mdio_read (struct net_device *dev, int phy_id, int location);
623 static void mdio_write (struct net_device *dev, int phy_id, int location,
624 int val);
625 static void rtl8139_start_thread(struct rtl8139_private *tp);
626 static void rtl8139_tx_timeout (struct net_device *dev);
627 static void rtl8139_init_ring (struct net_device *dev);
628 static int rtl8139_start_xmit (struct sk_buff *skb,
629 struct net_device *dev);
630 #ifdef CONFIG_NET_POLL_CONTROLLER
631 static void rtl8139_poll_controller(struct net_device *dev);
632 #endif
633 static int rtl8139_poll(struct napi_struct *napi, int budget);
634 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
635 static int rtl8139_close (struct net_device *dev);
636 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
637 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
638 static void rtl8139_set_rx_mode (struct net_device *dev);
639 static void __set_rx_mode (struct net_device *dev);
640 static void rtl8139_hw_start (struct net_device *dev);
641 static void rtl8139_thread (struct work_struct *work);
642 static void rtl8139_tx_timeout_task(struct work_struct *work);
643 static const struct ethtool_ops rtl8139_ethtool_ops;
644
645 /* write MMIO register, with flush */
646 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
647 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
648 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
649 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
650
651
652 #define MMIO_FLUSH_AUDIT_COMPLETE 1
653 #if MMIO_FLUSH_AUDIT_COMPLETE
654
655 /* write MMIO register */
656 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
657 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
658 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
659
660 #else
661
662 /* write MMIO register, then flush */
663 #define RTL_W8 RTL_W8_F
664 #define RTL_W16 RTL_W16_F
665 #define RTL_W32 RTL_W32_F
666
667 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
668
669 /* read MMIO register */
670 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
671 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
672 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
673
674
675 static const u16 rtl8139_intr_mask =
676 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
677 TxErr | TxOK | RxErr | RxOK;
678
679 static const u16 rtl8139_norx_intr_mask =
680 PCIErr | PCSTimeout | RxUnderrun |
681 TxErr | TxOK | RxErr ;
682
683 #if RX_BUF_IDX == 0
684 static const unsigned int rtl8139_rx_config =
685 RxCfgRcv8K | RxNoWrap |
686 (RX_FIFO_THRESH << RxCfgFIFOShift) |
687 (RX_DMA_BURST << RxCfgDMAShift);
688 #elif RX_BUF_IDX == 1
689 static const unsigned int rtl8139_rx_config =
690 RxCfgRcv16K | RxNoWrap |
691 (RX_FIFO_THRESH << RxCfgFIFOShift) |
692 (RX_DMA_BURST << RxCfgDMAShift);
693 #elif RX_BUF_IDX == 2
694 static const unsigned int rtl8139_rx_config =
695 RxCfgRcv32K | RxNoWrap |
696 (RX_FIFO_THRESH << RxCfgFIFOShift) |
697 (RX_DMA_BURST << RxCfgDMAShift);
698 #elif RX_BUF_IDX == 3
699 static const unsigned int rtl8139_rx_config =
700 RxCfgRcv64K |
701 (RX_FIFO_THRESH << RxCfgFIFOShift) |
702 (RX_DMA_BURST << RxCfgDMAShift);
703 #else
704 #error "Invalid configuration for 8139_RXBUF_IDX"
705 #endif
706
707 static const unsigned int rtl8139_tx_config =
708 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
709
710 static void __rtl8139_cleanup_dev (struct net_device *dev)
711 {
712 struct rtl8139_private *tp = netdev_priv(dev);
713 struct pci_dev *pdev;
714
715 assert (dev != NULL);
716 assert (tp->pci_dev != NULL);
717 pdev = tp->pci_dev;
718
719 #ifdef USE_IO_OPS
720 if (tp->mmio_addr)
721 ioport_unmap (tp->mmio_addr);
722 #else
723 if (tp->mmio_addr)
724 pci_iounmap (pdev, tp->mmio_addr);
725 #endif /* USE_IO_OPS */
726
727 /* it's ok to call this even if we have no regions to free */
728 pci_release_regions (pdev);
729
730 free_netdev(dev);
731 pci_set_drvdata (pdev, NULL);
732 }
733
734
735 static void rtl8139_chip_reset (void __iomem *ioaddr)
736 {
737 int i;
738
739 /* Soft reset the chip. */
740 RTL_W8 (ChipCmd, CmdReset);
741
742 /* Check that the chip has finished the reset. */
743 for (i = 1000; i > 0; i--) {
744 barrier();
745 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
746 break;
747 udelay (10);
748 }
749 }
750
751
752 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
753 struct net_device **dev_out)
754 {
755 void __iomem *ioaddr;
756 struct net_device *dev;
757 struct rtl8139_private *tp;
758 u8 tmp8;
759 int rc, disable_dev_on_err = 0;
760 unsigned int i;
761 unsigned long pio_start, pio_end, pio_flags, pio_len;
762 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
763 u32 version;
764
765 assert (pdev != NULL);
766
767 *dev_out = NULL;
768
769 /* dev and priv zeroed in alloc_etherdev */
770 dev = alloc_etherdev (sizeof (*tp));
771 if (dev == NULL) {
772 dev_err(&pdev->dev, "Unable to alloc new net device\n");
773 return -ENOMEM;
774 }
775 SET_MODULE_OWNER(dev);
776 SET_NETDEV_DEV(dev, &pdev->dev);
777
778 tp = netdev_priv(dev);
779 tp->pci_dev = pdev;
780
781 /* enable device (incl. PCI PM wakeup and hotplug setup) */
782 rc = pci_enable_device (pdev);
783 if (rc)
784 goto err_out;
785
786 pio_start = pci_resource_start (pdev, 0);
787 pio_end = pci_resource_end (pdev, 0);
788 pio_flags = pci_resource_flags (pdev, 0);
789 pio_len = pci_resource_len (pdev, 0);
790
791 mmio_start = pci_resource_start (pdev, 1);
792 mmio_end = pci_resource_end (pdev, 1);
793 mmio_flags = pci_resource_flags (pdev, 1);
794 mmio_len = pci_resource_len (pdev, 1);
795
796 /* set this immediately, we need to know before
797 * we talk to the chip directly */
798 DPRINTK("PIO region size == 0x%02X\n", pio_len);
799 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
800
801 #ifdef USE_IO_OPS
802 /* make sure PCI base addr 0 is PIO */
803 if (!(pio_flags & IORESOURCE_IO)) {
804 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
805 rc = -ENODEV;
806 goto err_out;
807 }
808 /* check for weird/broken PCI region reporting */
809 if (pio_len < RTL_MIN_IO_SIZE) {
810 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
811 rc = -ENODEV;
812 goto err_out;
813 }
814 #else
815 /* make sure PCI base addr 1 is MMIO */
816 if (!(mmio_flags & IORESOURCE_MEM)) {
817 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
818 rc = -ENODEV;
819 goto err_out;
820 }
821 if (mmio_len < RTL_MIN_IO_SIZE) {
822 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
823 rc = -ENODEV;
824 goto err_out;
825 }
826 #endif
827
828 rc = pci_request_regions (pdev, DRV_NAME);
829 if (rc)
830 goto err_out;
831 disable_dev_on_err = 1;
832
833 /* enable PCI bus-mastering */
834 pci_set_master (pdev);
835
836 #ifdef USE_IO_OPS
837 ioaddr = ioport_map(pio_start, pio_len);
838 if (!ioaddr) {
839 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
840 rc = -EIO;
841 goto err_out;
842 }
843 dev->base_addr = pio_start;
844 tp->mmio_addr = ioaddr;
845 tp->regs_len = pio_len;
846 #else
847 /* ioremap MMIO region */
848 ioaddr = pci_iomap(pdev, 1, 0);
849 if (ioaddr == NULL) {
850 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
851 rc = -EIO;
852 goto err_out;
853 }
854 dev->base_addr = (long) ioaddr;
855 tp->mmio_addr = ioaddr;
856 tp->regs_len = mmio_len;
857 #endif /* USE_IO_OPS */
858
859 /* Bring old chips out of low-power mode. */
860 RTL_W8 (HltClk, 'R');
861
862 /* check for missing/broken hardware */
863 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
864 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
865 rc = -EIO;
866 goto err_out;
867 }
868
869 /* identify chip attached to board */
870 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
871 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
872 if (version == rtl_chip_info[i].version) {
873 tp->chipset = i;
874 goto match;
875 }
876
877 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
878 dev_printk (KERN_DEBUG, &pdev->dev,
879 "unknown chip version, assuming RTL-8139\n");
880 dev_printk (KERN_DEBUG, &pdev->dev,
881 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
882 tp->chipset = 0;
883
884 match:
885 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
886 version, i, rtl_chip_info[i].name);
887
888 if (tp->chipset >= CH_8139B) {
889 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
890 DPRINTK("PCI PM wakeup\n");
891 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
892 (tmp8 & LWAKE))
893 new_tmp8 &= ~LWAKE;
894 new_tmp8 |= Cfg1_PM_Enable;
895 if (new_tmp8 != tmp8) {
896 RTL_W8 (Cfg9346, Cfg9346_Unlock);
897 RTL_W8 (Config1, tmp8);
898 RTL_W8 (Cfg9346, Cfg9346_Lock);
899 }
900 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
901 tmp8 = RTL_R8 (Config4);
902 if (tmp8 & LWPTN) {
903 RTL_W8 (Cfg9346, Cfg9346_Unlock);
904 RTL_W8 (Config4, tmp8 & ~LWPTN);
905 RTL_W8 (Cfg9346, Cfg9346_Lock);
906 }
907 }
908 } else {
909 DPRINTK("Old chip wakeup\n");
910 tmp8 = RTL_R8 (Config1);
911 tmp8 &= ~(SLEEP | PWRDN);
912 RTL_W8 (Config1, tmp8);
913 }
914
915 rtl8139_chip_reset (ioaddr);
916
917 *dev_out = dev;
918 return 0;
919
920 err_out:
921 __rtl8139_cleanup_dev (dev);
922 if (disable_dev_on_err)
923 pci_disable_device (pdev);
924 return rc;
925 }
926
927
928 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
929 const struct pci_device_id *ent)
930 {
931 struct net_device *dev = NULL;
932 struct rtl8139_private *tp;
933 int i, addr_len, option;
934 void __iomem *ioaddr;
935 static int board_idx = -1;
936
937 assert (pdev != NULL);
938 assert (ent != NULL);
939
940 board_idx++;
941
942 /* when we're built into the kernel, the driver version message
943 * is only printed if at least one 8139 board has been found
944 */
945 #ifndef MODULE
946 {
947 static int printed_version;
948 if (!printed_version++)
949 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
950 }
951 #endif
952
953 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
954 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
955 dev_info(&pdev->dev,
956 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
957 pdev->vendor, pdev->device, pdev->revision);
958 dev_info(&pdev->dev,
959 "Use the \"8139cp\" driver for improved performance and stability.\n");
960 }
961
962 i = rtl8139_init_board (pdev, &dev);
963 if (i < 0)
964 return i;
965
966 assert (dev != NULL);
967 tp = netdev_priv(dev);
968 tp->dev = dev;
969
970 ioaddr = tp->mmio_addr;
971 assert (ioaddr != NULL);
972
973 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
974 for (i = 0; i < 3; i++)
975 ((u16 *) (dev->dev_addr))[i] =
976 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
977 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
978
979 /* The Rtl8139-specific entries in the device structure. */
980 dev->open = rtl8139_open;
981 dev->hard_start_xmit = rtl8139_start_xmit;
982 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
983 dev->stop = rtl8139_close;
984 dev->get_stats = rtl8139_get_stats;
985 dev->set_multicast_list = rtl8139_set_rx_mode;
986 dev->do_ioctl = netdev_ioctl;
987 dev->ethtool_ops = &rtl8139_ethtool_ops;
988 dev->tx_timeout = rtl8139_tx_timeout;
989 dev->watchdog_timeo = TX_TIMEOUT;
990 #ifdef CONFIG_NET_POLL_CONTROLLER
991 dev->poll_controller = rtl8139_poll_controller;
992 #endif
993
994 /* note: the hardware is not capable of sg/csum/highdma, however
995 * through the use of skb_copy_and_csum_dev we enable these
996 * features
997 */
998 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
999
1000 dev->irq = pdev->irq;
1001
1002 /* tp zeroed and aligned in alloc_etherdev */
1003 tp = netdev_priv(dev);
1004
1005 /* note: tp->chipset set in rtl8139_init_board */
1006 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1007 tp->mmio_addr = ioaddr;
1008 tp->msg_enable =
1009 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1010 spin_lock_init (&tp->lock);
1011 spin_lock_init (&tp->rx_lock);
1012 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1013 tp->mii.dev = dev;
1014 tp->mii.mdio_read = mdio_read;
1015 tp->mii.mdio_write = mdio_write;
1016 tp->mii.phy_id_mask = 0x3f;
1017 tp->mii.reg_num_mask = 0x1f;
1018
1019 /* dev is fully set up and ready to use now */
1020 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1021 i = register_netdev (dev);
1022 if (i) goto err_out;
1023
1024 pci_set_drvdata (pdev, dev);
1025
1026 printk (KERN_INFO "%s: %s at 0x%lx, "
1027 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1028 "IRQ %d\n",
1029 dev->name,
1030 board_info[ent->driver_data].name,
1031 dev->base_addr,
1032 dev->dev_addr[0], dev->dev_addr[1],
1033 dev->dev_addr[2], dev->dev_addr[3],
1034 dev->dev_addr[4], dev->dev_addr[5],
1035 dev->irq);
1036
1037 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1038 dev->name, rtl_chip_info[tp->chipset].name);
1039
1040 /* Find the connected MII xcvrs.
1041 Doing this in open() would allow detecting external xcvrs later, but
1042 takes too much time. */
1043 #ifdef CONFIG_8139TOO_8129
1044 if (tp->drv_flags & HAS_MII_XCVR) {
1045 int phy, phy_idx = 0;
1046 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1047 int mii_status = mdio_read(dev, phy, 1);
1048 if (mii_status != 0xffff && mii_status != 0x0000) {
1049 u16 advertising = mdio_read(dev, phy, 4);
1050 tp->phys[phy_idx++] = phy;
1051 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1052 "advertising %4.4x.\n",
1053 dev->name, phy, mii_status, advertising);
1054 }
1055 }
1056 if (phy_idx == 0) {
1057 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1058 "transceiver.\n",
1059 dev->name);
1060 tp->phys[0] = 32;
1061 }
1062 } else
1063 #endif
1064 tp->phys[0] = 32;
1065 tp->mii.phy_id = tp->phys[0];
1066
1067 /* The lower four bits are the media type. */
1068 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1069 if (option > 0) {
1070 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1071 tp->default_port = option & 0xFF;
1072 if (tp->default_port)
1073 tp->mii.force_media = 1;
1074 }
1075 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1076 tp->mii.full_duplex = full_duplex[board_idx];
1077 if (tp->mii.full_duplex) {
1078 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1079 /* Changing the MII-advertised media because might prevent
1080 re-connection. */
1081 tp->mii.force_media = 1;
1082 }
1083 if (tp->default_port) {
1084 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1085 (option & 0x20 ? 100 : 10),
1086 (option & 0x10 ? "full" : "half"));
1087 mdio_write(dev, tp->phys[0], 0,
1088 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1089 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1090 }
1091
1092 /* Put the chip into low-power mode. */
1093 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1094 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1095
1096 return 0;
1097
1098 err_out:
1099 __rtl8139_cleanup_dev (dev);
1100 pci_disable_device (pdev);
1101 return i;
1102 }
1103
1104
1105 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1106 {
1107 struct net_device *dev = pci_get_drvdata (pdev);
1108
1109 assert (dev != NULL);
1110
1111 flush_scheduled_work();
1112
1113 unregister_netdev (dev);
1114
1115 __rtl8139_cleanup_dev (dev);
1116 pci_disable_device (pdev);
1117 }
1118
1119
1120 /* Serial EEPROM section. */
1121
1122 /* EEPROM_Ctrl bits. */
1123 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1124 #define EE_CS 0x08 /* EEPROM chip select. */
1125 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1126 #define EE_WRITE_0 0x00
1127 #define EE_WRITE_1 0x02
1128 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1129 #define EE_ENB (0x80 | EE_CS)
1130
1131 /* Delay between EEPROM clock transitions.
1132 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1133 */
1134
1135 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1136
1137 /* The EEPROM commands include the alway-set leading bit. */
1138 #define EE_WRITE_CMD (5)
1139 #define EE_READ_CMD (6)
1140 #define EE_ERASE_CMD (7)
1141
1142 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1143 {
1144 int i;
1145 unsigned retval = 0;
1146 int read_cmd = location | (EE_READ_CMD << addr_len);
1147
1148 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1149 RTL_W8 (Cfg9346, EE_ENB);
1150 eeprom_delay ();
1151
1152 /* Shift the read command bits out. */
1153 for (i = 4 + addr_len; i >= 0; i--) {
1154 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1155 RTL_W8 (Cfg9346, EE_ENB | dataval);
1156 eeprom_delay ();
1157 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1158 eeprom_delay ();
1159 }
1160 RTL_W8 (Cfg9346, EE_ENB);
1161 eeprom_delay ();
1162
1163 for (i = 16; i > 0; i--) {
1164 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1165 eeprom_delay ();
1166 retval =
1167 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1168 0);
1169 RTL_W8 (Cfg9346, EE_ENB);
1170 eeprom_delay ();
1171 }
1172
1173 /* Terminate the EEPROM access. */
1174 RTL_W8 (Cfg9346, ~EE_CS);
1175 eeprom_delay ();
1176
1177 return retval;
1178 }
1179
1180 /* MII serial management: mostly bogus for now. */
1181 /* Read and write the MII management registers using software-generated
1182 serial MDIO protocol.
1183 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1184 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1185 "overclocking" issues. */
1186 #define MDIO_DIR 0x80
1187 #define MDIO_DATA_OUT 0x04
1188 #define MDIO_DATA_IN 0x02
1189 #define MDIO_CLK 0x01
1190 #define MDIO_WRITE0 (MDIO_DIR)
1191 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1192
1193 #define mdio_delay() RTL_R8(Config4)
1194
1195
1196 static const char mii_2_8139_map[8] = {
1197 BasicModeCtrl,
1198 BasicModeStatus,
1199 0,
1200 0,
1201 NWayAdvert,
1202 NWayLPAR,
1203 NWayExpansion,
1204 0
1205 };
1206
1207
1208 #ifdef CONFIG_8139TOO_8129
1209 /* Syncronize the MII management interface by shifting 32 one bits out. */
1210 static void mdio_sync (void __iomem *ioaddr)
1211 {
1212 int i;
1213
1214 for (i = 32; i >= 0; i--) {
1215 RTL_W8 (Config4, MDIO_WRITE1);
1216 mdio_delay ();
1217 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1218 mdio_delay ();
1219 }
1220 }
1221 #endif
1222
1223 static int mdio_read (struct net_device *dev, int phy_id, int location)
1224 {
1225 struct rtl8139_private *tp = netdev_priv(dev);
1226 int retval = 0;
1227 #ifdef CONFIG_8139TOO_8129
1228 void __iomem *ioaddr = tp->mmio_addr;
1229 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1230 int i;
1231 #endif
1232
1233 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1234 void __iomem *ioaddr = tp->mmio_addr;
1235 return location < 8 && mii_2_8139_map[location] ?
1236 RTL_R16 (mii_2_8139_map[location]) : 0;
1237 }
1238
1239 #ifdef CONFIG_8139TOO_8129
1240 mdio_sync (ioaddr);
1241 /* Shift the read command bits out. */
1242 for (i = 15; i >= 0; i--) {
1243 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1244
1245 RTL_W8 (Config4, MDIO_DIR | dataval);
1246 mdio_delay ();
1247 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1248 mdio_delay ();
1249 }
1250
1251 /* Read the two transition, 16 data, and wire-idle bits. */
1252 for (i = 19; i > 0; i--) {
1253 RTL_W8 (Config4, 0);
1254 mdio_delay ();
1255 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1256 RTL_W8 (Config4, MDIO_CLK);
1257 mdio_delay ();
1258 }
1259 #endif
1260
1261 return (retval >> 1) & 0xffff;
1262 }
1263
1264
1265 static void mdio_write (struct net_device *dev, int phy_id, int location,
1266 int value)
1267 {
1268 struct rtl8139_private *tp = netdev_priv(dev);
1269 #ifdef CONFIG_8139TOO_8129
1270 void __iomem *ioaddr = tp->mmio_addr;
1271 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1272 int i;
1273 #endif
1274
1275 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1276 void __iomem *ioaddr = tp->mmio_addr;
1277 if (location == 0) {
1278 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1279 RTL_W16 (BasicModeCtrl, value);
1280 RTL_W8 (Cfg9346, Cfg9346_Lock);
1281 } else if (location < 8 && mii_2_8139_map[location])
1282 RTL_W16 (mii_2_8139_map[location], value);
1283 return;
1284 }
1285
1286 #ifdef CONFIG_8139TOO_8129
1287 mdio_sync (ioaddr);
1288
1289 /* Shift the command bits out. */
1290 for (i = 31; i >= 0; i--) {
1291 int dataval =
1292 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1293 RTL_W8 (Config4, dataval);
1294 mdio_delay ();
1295 RTL_W8 (Config4, dataval | MDIO_CLK);
1296 mdio_delay ();
1297 }
1298 /* Clear out extra bits. */
1299 for (i = 2; i > 0; i--) {
1300 RTL_W8 (Config4, 0);
1301 mdio_delay ();
1302 RTL_W8 (Config4, MDIO_CLK);
1303 mdio_delay ();
1304 }
1305 #endif
1306 }
1307
1308
1309 static int rtl8139_open (struct net_device *dev)
1310 {
1311 struct rtl8139_private *tp = netdev_priv(dev);
1312 int retval;
1313 void __iomem *ioaddr = tp->mmio_addr;
1314
1315 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1316 if (retval)
1317 return retval;
1318
1319 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1320 &tp->tx_bufs_dma);
1321 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1322 &tp->rx_ring_dma);
1323 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1324 free_irq(dev->irq, dev);
1325
1326 if (tp->tx_bufs)
1327 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1328 tp->tx_bufs, tp->tx_bufs_dma);
1329 if (tp->rx_ring)
1330 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1331 tp->rx_ring, tp->rx_ring_dma);
1332
1333 return -ENOMEM;
1334
1335 }
1336
1337 napi_enable(&tp->napi);
1338
1339 tp->mii.full_duplex = tp->mii.force_media;
1340 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1341
1342 rtl8139_init_ring (dev);
1343 rtl8139_hw_start (dev);
1344 netif_start_queue (dev);
1345
1346 if (netif_msg_ifup(tp))
1347 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1348 " GP Pins %2.2x %s-duplex.\n", dev->name,
1349 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1350 dev->irq, RTL_R8 (MediaStatus),
1351 tp->mii.full_duplex ? "full" : "half");
1352
1353 rtl8139_start_thread(tp);
1354
1355 return 0;
1356 }
1357
1358
1359 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1360 {
1361 struct rtl8139_private *tp = netdev_priv(dev);
1362
1363 if (tp->phys[0] >= 0) {
1364 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1365 }
1366 }
1367
1368 /* Start the hardware at open or resume. */
1369 static void rtl8139_hw_start (struct net_device *dev)
1370 {
1371 struct rtl8139_private *tp = netdev_priv(dev);
1372 void __iomem *ioaddr = tp->mmio_addr;
1373 u32 i;
1374 u8 tmp;
1375
1376 /* Bring old chips out of low-power mode. */
1377 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1378 RTL_W8 (HltClk, 'R');
1379
1380 rtl8139_chip_reset (ioaddr);
1381
1382 /* unlock Config[01234] and BMCR register writes */
1383 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1384 /* Restore our idea of the MAC address. */
1385 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1386 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1387
1388 /* Must enable Tx/Rx before setting transfer thresholds! */
1389 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1390
1391 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1392 RTL_W32 (RxConfig, tp->rx_config);
1393 RTL_W32 (TxConfig, rtl8139_tx_config);
1394
1395 tp->cur_rx = 0;
1396
1397 rtl_check_media (dev, 1);
1398
1399 if (tp->chipset >= CH_8139B) {
1400 /* Disable magic packet scanning, which is enabled
1401 * when PM is enabled in Config1. It can be reenabled
1402 * via ETHTOOL_SWOL if desired. */
1403 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1404 }
1405
1406 DPRINTK("init buffer addresses\n");
1407
1408 /* Lock Config[01234] and BMCR register writes */
1409 RTL_W8 (Cfg9346, Cfg9346_Lock);
1410
1411 /* init Rx ring buffer DMA address */
1412 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1413
1414 /* init Tx buffer DMA addresses */
1415 for (i = 0; i < NUM_TX_DESC; i++)
1416 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1417
1418 RTL_W32 (RxMissed, 0);
1419
1420 rtl8139_set_rx_mode (dev);
1421
1422 /* no early-rx interrupts */
1423 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1424
1425 /* make sure RxTx has started */
1426 tmp = RTL_R8 (ChipCmd);
1427 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1428 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1429
1430 /* Enable all known interrupts by setting the interrupt mask. */
1431 RTL_W16 (IntrMask, rtl8139_intr_mask);
1432 }
1433
1434
1435 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1436 static void rtl8139_init_ring (struct net_device *dev)
1437 {
1438 struct rtl8139_private *tp = netdev_priv(dev);
1439 int i;
1440
1441 tp->cur_rx = 0;
1442 tp->cur_tx = 0;
1443 tp->dirty_tx = 0;
1444
1445 for (i = 0; i < NUM_TX_DESC; i++)
1446 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1447 }
1448
1449
1450 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1451 static int next_tick = 3 * HZ;
1452
1453 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1454 static inline void rtl8139_tune_twister (struct net_device *dev,
1455 struct rtl8139_private *tp) {}
1456 #else
1457 enum TwisterParamVals {
1458 PARA78_default = 0x78fa8388,
1459 PARA7c_default = 0xcb38de43, /* param[0][3] */
1460 PARA7c_xxx = 0xcb38de43,
1461 };
1462
1463 static const unsigned long param[4][4] = {
1464 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1465 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1466 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1467 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1468 };
1469
1470 static void rtl8139_tune_twister (struct net_device *dev,
1471 struct rtl8139_private *tp)
1472 {
1473 int linkcase;
1474 void __iomem *ioaddr = tp->mmio_addr;
1475
1476 /* This is a complicated state machine to configure the "twister" for
1477 impedance/echos based on the cable length.
1478 All of this is magic and undocumented.
1479 */
1480 switch (tp->twistie) {
1481 case 1:
1482 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1483 /* We have link beat, let us tune the twister. */
1484 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1485 tp->twistie = 2; /* Change to state 2. */
1486 next_tick = HZ / 10;
1487 } else {
1488 /* Just put in some reasonable defaults for when beat returns. */
1489 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1490 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1491 RTL_W32 (PARA78, PARA78_default);
1492 RTL_W32 (PARA7c, PARA7c_default);
1493 tp->twistie = 0; /* Bail from future actions. */
1494 }
1495 break;
1496 case 2:
1497 /* Read how long it took to hear the echo. */
1498 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1499 if (linkcase == 0x7000)
1500 tp->twist_row = 3;
1501 else if (linkcase == 0x3000)
1502 tp->twist_row = 2;
1503 else if (linkcase == 0x1000)
1504 tp->twist_row = 1;
1505 else
1506 tp->twist_row = 0;
1507 tp->twist_col = 0;
1508 tp->twistie = 3; /* Change to state 2. */
1509 next_tick = HZ / 10;
1510 break;
1511 case 3:
1512 /* Put out four tuning parameters, one per 100msec. */
1513 if (tp->twist_col == 0)
1514 RTL_W16 (FIFOTMS, 0);
1515 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1516 [(int) tp->twist_col]);
1517 next_tick = HZ / 10;
1518 if (++tp->twist_col >= 4) {
1519 /* For short cables we are done.
1520 For long cables (row == 3) check for mistune. */
1521 tp->twistie =
1522 (tp->twist_row == 3) ? 4 : 0;
1523 }
1524 break;
1525 case 4:
1526 /* Special case for long cables: check for mistune. */
1527 if ((RTL_R16 (CSCR) &
1528 CSCR_LinkStatusBits) == 0x7000) {
1529 tp->twistie = 0;
1530 break;
1531 } else {
1532 RTL_W32 (PARA7c, 0xfb38de03);
1533 tp->twistie = 5;
1534 next_tick = HZ / 10;
1535 }
1536 break;
1537 case 5:
1538 /* Retune for shorter cable (column 2). */
1539 RTL_W32 (FIFOTMS, 0x20);
1540 RTL_W32 (PARA78, PARA78_default);
1541 RTL_W32 (PARA7c, PARA7c_default);
1542 RTL_W32 (FIFOTMS, 0x00);
1543 tp->twist_row = 2;
1544 tp->twist_col = 0;
1545 tp->twistie = 3;
1546 next_tick = HZ / 10;
1547 break;
1548
1549 default:
1550 /* do nothing */
1551 break;
1552 }
1553 }
1554 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1555
1556 static inline void rtl8139_thread_iter (struct net_device *dev,
1557 struct rtl8139_private *tp,
1558 void __iomem *ioaddr)
1559 {
1560 int mii_lpa;
1561
1562 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1563
1564 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1565 int duplex = (mii_lpa & LPA_100FULL)
1566 || (mii_lpa & 0x01C0) == 0x0040;
1567 if (tp->mii.full_duplex != duplex) {
1568 tp->mii.full_duplex = duplex;
1569
1570 if (mii_lpa) {
1571 printk (KERN_INFO
1572 "%s: Setting %s-duplex based on MII #%d link"
1573 " partner ability of %4.4x.\n",
1574 dev->name,
1575 tp->mii.full_duplex ? "full" : "half",
1576 tp->phys[0], mii_lpa);
1577 } else {
1578 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1579 dev->name);
1580 }
1581 #if 0
1582 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1583 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1584 RTL_W8 (Cfg9346, Cfg9346_Lock);
1585 #endif
1586 }
1587 }
1588
1589 next_tick = HZ * 60;
1590
1591 rtl8139_tune_twister (dev, tp);
1592
1593 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1594 dev->name, RTL_R16 (NWayLPAR));
1595 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1596 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1597 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1598 dev->name, RTL_R8 (Config0),
1599 RTL_R8 (Config1));
1600 }
1601
1602 static void rtl8139_thread (struct work_struct *work)
1603 {
1604 struct rtl8139_private *tp =
1605 container_of(work, struct rtl8139_private, thread.work);
1606 struct net_device *dev = tp->mii.dev;
1607 unsigned long thr_delay = next_tick;
1608
1609 rtnl_lock();
1610
1611 if (!netif_running(dev))
1612 goto out_unlock;
1613
1614 if (tp->watchdog_fired) {
1615 tp->watchdog_fired = 0;
1616 rtl8139_tx_timeout_task(work);
1617 } else
1618 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1619
1620 if (tp->have_thread)
1621 schedule_delayed_work(&tp->thread, thr_delay);
1622 out_unlock:
1623 rtnl_unlock ();
1624 }
1625
1626 static void rtl8139_start_thread(struct rtl8139_private *tp)
1627 {
1628 tp->twistie = 0;
1629 if (tp->chipset == CH_8139_K)
1630 tp->twistie = 1;
1631 else if (tp->drv_flags & HAS_LNK_CHNG)
1632 return;
1633
1634 tp->have_thread = 1;
1635 tp->watchdog_fired = 0;
1636
1637 schedule_delayed_work(&tp->thread, next_tick);
1638 }
1639
1640 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1641 {
1642 tp->cur_tx = 0;
1643 tp->dirty_tx = 0;
1644
1645 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1646 }
1647
1648 static void rtl8139_tx_timeout_task (struct work_struct *work)
1649 {
1650 struct rtl8139_private *tp =
1651 container_of(work, struct rtl8139_private, thread.work);
1652 struct net_device *dev = tp->mii.dev;
1653 void __iomem *ioaddr = tp->mmio_addr;
1654 int i;
1655 u8 tmp8;
1656
1657 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1658 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1659 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1660 /* Emit info to figure out what went wrong. */
1661 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1662 dev->name, tp->cur_tx, tp->dirty_tx);
1663 for (i = 0; i < NUM_TX_DESC; i++)
1664 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1665 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1666 i == tp->dirty_tx % NUM_TX_DESC ?
1667 " (queue head)" : "");
1668
1669 tp->xstats.tx_timeouts++;
1670
1671 /* disable Tx ASAP, if not already */
1672 tmp8 = RTL_R8 (ChipCmd);
1673 if (tmp8 & CmdTxEnb)
1674 RTL_W8 (ChipCmd, CmdRxEnb);
1675
1676 spin_lock_bh(&tp->rx_lock);
1677 /* Disable interrupts by clearing the interrupt mask. */
1678 RTL_W16 (IntrMask, 0x0000);
1679
1680 /* Stop a shared interrupt from scavenging while we are. */
1681 spin_lock_irq(&tp->lock);
1682 rtl8139_tx_clear (tp);
1683 spin_unlock_irq(&tp->lock);
1684
1685 /* ...and finally, reset everything */
1686 if (netif_running(dev)) {
1687 rtl8139_hw_start (dev);
1688 netif_wake_queue (dev);
1689 }
1690 spin_unlock_bh(&tp->rx_lock);
1691 }
1692
1693 static void rtl8139_tx_timeout (struct net_device *dev)
1694 {
1695 struct rtl8139_private *tp = netdev_priv(dev);
1696
1697 tp->watchdog_fired = 1;
1698 if (!tp->have_thread) {
1699 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1700 schedule_delayed_work(&tp->thread, next_tick);
1701 }
1702 }
1703
1704 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1705 {
1706 struct rtl8139_private *tp = netdev_priv(dev);
1707 void __iomem *ioaddr = tp->mmio_addr;
1708 unsigned int entry;
1709 unsigned int len = skb->len;
1710 unsigned long flags;
1711
1712 /* Calculate the next Tx descriptor entry. */
1713 entry = tp->cur_tx % NUM_TX_DESC;
1714
1715 /* Note: the chip doesn't have auto-pad! */
1716 if (likely(len < TX_BUF_SIZE)) {
1717 if (len < ETH_ZLEN)
1718 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1719 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1720 dev_kfree_skb(skb);
1721 } else {
1722 dev_kfree_skb(skb);
1723 tp->stats.tx_dropped++;
1724 return 0;
1725 }
1726
1727 spin_lock_irqsave(&tp->lock, flags);
1728 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1729 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1730
1731 dev->trans_start = jiffies;
1732
1733 tp->cur_tx++;
1734 wmb();
1735
1736 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1737 netif_stop_queue (dev);
1738 spin_unlock_irqrestore(&tp->lock, flags);
1739
1740 if (netif_msg_tx_queued(tp))
1741 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1742 dev->name, len, entry);
1743
1744 return 0;
1745 }
1746
1747
1748 static void rtl8139_tx_interrupt (struct net_device *dev,
1749 struct rtl8139_private *tp,
1750 void __iomem *ioaddr)
1751 {
1752 unsigned long dirty_tx, tx_left;
1753
1754 assert (dev != NULL);
1755 assert (ioaddr != NULL);
1756
1757 dirty_tx = tp->dirty_tx;
1758 tx_left = tp->cur_tx - dirty_tx;
1759 while (tx_left > 0) {
1760 int entry = dirty_tx % NUM_TX_DESC;
1761 int txstatus;
1762
1763 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1764
1765 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1766 break; /* It still hasn't been Txed */
1767
1768 /* Note: TxCarrierLost is always asserted at 100mbps. */
1769 if (txstatus & (TxOutOfWindow | TxAborted)) {
1770 /* There was an major error, log it. */
1771 if (netif_msg_tx_err(tp))
1772 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1773 dev->name, txstatus);
1774 tp->stats.tx_errors++;
1775 if (txstatus & TxAborted) {
1776 tp->stats.tx_aborted_errors++;
1777 RTL_W32 (TxConfig, TxClearAbt);
1778 RTL_W16 (IntrStatus, TxErr);
1779 wmb();
1780 }
1781 if (txstatus & TxCarrierLost)
1782 tp->stats.tx_carrier_errors++;
1783 if (txstatus & TxOutOfWindow)
1784 tp->stats.tx_window_errors++;
1785 } else {
1786 if (txstatus & TxUnderrun) {
1787 /* Add 64 to the Tx FIFO threshold. */
1788 if (tp->tx_flag < 0x00300000)
1789 tp->tx_flag += 0x00020000;
1790 tp->stats.tx_fifo_errors++;
1791 }
1792 tp->stats.collisions += (txstatus >> 24) & 15;
1793 tp->stats.tx_bytes += txstatus & 0x7ff;
1794 tp->stats.tx_packets++;
1795 }
1796
1797 dirty_tx++;
1798 tx_left--;
1799 }
1800
1801 #ifndef RTL8139_NDEBUG
1802 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1803 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1804 dev->name, dirty_tx, tp->cur_tx);
1805 dirty_tx += NUM_TX_DESC;
1806 }
1807 #endif /* RTL8139_NDEBUG */
1808
1809 /* only wake the queue if we did work, and the queue is stopped */
1810 if (tp->dirty_tx != dirty_tx) {
1811 tp->dirty_tx = dirty_tx;
1812 mb();
1813 netif_wake_queue (dev);
1814 }
1815 }
1816
1817
1818 /* TODO: clean this up! Rx reset need not be this intensive */
1819 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1820 struct rtl8139_private *tp, void __iomem *ioaddr)
1821 {
1822 u8 tmp8;
1823 #ifdef CONFIG_8139_OLD_RX_RESET
1824 int tmp_work;
1825 #endif
1826
1827 if (netif_msg_rx_err (tp))
1828 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1829 dev->name, rx_status);
1830 tp->stats.rx_errors++;
1831 if (!(rx_status & RxStatusOK)) {
1832 if (rx_status & RxTooLong) {
1833 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1834 dev->name, rx_status);
1835 /* A.C.: The chip hangs here. */
1836 }
1837 if (rx_status & (RxBadSymbol | RxBadAlign))
1838 tp->stats.rx_frame_errors++;
1839 if (rx_status & (RxRunt | RxTooLong))
1840 tp->stats.rx_length_errors++;
1841 if (rx_status & RxCRCErr)
1842 tp->stats.rx_crc_errors++;
1843 } else {
1844 tp->xstats.rx_lost_in_ring++;
1845 }
1846
1847 #ifndef CONFIG_8139_OLD_RX_RESET
1848 tmp8 = RTL_R8 (ChipCmd);
1849 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1850 RTL_W8 (ChipCmd, tmp8);
1851 RTL_W32 (RxConfig, tp->rx_config);
1852 tp->cur_rx = 0;
1853 #else
1854 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1855
1856 /* disable receive */
1857 RTL_W8_F (ChipCmd, CmdTxEnb);
1858 tmp_work = 200;
1859 while (--tmp_work > 0) {
1860 udelay(1);
1861 tmp8 = RTL_R8 (ChipCmd);
1862 if (!(tmp8 & CmdRxEnb))
1863 break;
1864 }
1865 if (tmp_work <= 0)
1866 printk (KERN_WARNING PFX "rx stop wait too long\n");
1867 /* restart receive */
1868 tmp_work = 200;
1869 while (--tmp_work > 0) {
1870 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1871 udelay(1);
1872 tmp8 = RTL_R8 (ChipCmd);
1873 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1874 break;
1875 }
1876 if (tmp_work <= 0)
1877 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1878
1879 /* and reinitialize all rx related registers */
1880 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1881 /* Must enable Tx/Rx before setting transfer thresholds! */
1882 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1883
1884 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1885 RTL_W32 (RxConfig, tp->rx_config);
1886 tp->cur_rx = 0;
1887
1888 DPRINTK("init buffer addresses\n");
1889
1890 /* Lock Config[01234] and BMCR register writes */
1891 RTL_W8 (Cfg9346, Cfg9346_Lock);
1892
1893 /* init Rx ring buffer DMA address */
1894 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1895
1896 /* A.C.: Reset the multicast list. */
1897 __set_rx_mode (dev);
1898 #endif
1899 }
1900
1901 #if RX_BUF_IDX == 3
1902 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1903 u32 offset, unsigned int size)
1904 {
1905 u32 left = RX_BUF_LEN - offset;
1906
1907 if (size > left) {
1908 skb_copy_to_linear_data(skb, ring + offset, left);
1909 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1910 } else
1911 skb_copy_to_linear_data(skb, ring + offset, size);
1912 }
1913 #endif
1914
1915 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1916 {
1917 void __iomem *ioaddr = tp->mmio_addr;
1918 u16 status;
1919
1920 status = RTL_R16 (IntrStatus) & RxAckBits;
1921
1922 /* Clear out errors and receive interrupts */
1923 if (likely(status != 0)) {
1924 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1925 tp->stats.rx_errors++;
1926 if (status & RxFIFOOver)
1927 tp->stats.rx_fifo_errors++;
1928 }
1929 RTL_W16_F (IntrStatus, RxAckBits);
1930 }
1931 }
1932
1933 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1934 int budget)
1935 {
1936 void __iomem *ioaddr = tp->mmio_addr;
1937 int received = 0;
1938 unsigned char *rx_ring = tp->rx_ring;
1939 unsigned int cur_rx = tp->cur_rx;
1940 unsigned int rx_size = 0;
1941
1942 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1943 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1944 RTL_R16 (RxBufAddr),
1945 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1946
1947 while (netif_running(dev) && received < budget
1948 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1949 u32 ring_offset = cur_rx % RX_BUF_LEN;
1950 u32 rx_status;
1951 unsigned int pkt_size;
1952 struct sk_buff *skb;
1953
1954 rmb();
1955
1956 /* read size+status of next frame from DMA ring buffer */
1957 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1958 rx_size = rx_status >> 16;
1959 pkt_size = rx_size - 4;
1960
1961 if (netif_msg_rx_status(tp))
1962 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1963 " cur %4.4x.\n", dev->name, rx_status,
1964 rx_size, cur_rx);
1965 #if RTL8139_DEBUG > 2
1966 {
1967 int i;
1968 DPRINTK ("%s: Frame contents ", dev->name);
1969 for (i = 0; i < 70; i++)
1970 printk (" %2.2x",
1971 rx_ring[ring_offset + i]);
1972 printk (".\n");
1973 }
1974 #endif
1975
1976 /* Packet copy from FIFO still in progress.
1977 * Theoretically, this should never happen
1978 * since EarlyRx is disabled.
1979 */
1980 if (unlikely(rx_size == 0xfff0)) {
1981 if (!tp->fifo_copy_timeout)
1982 tp->fifo_copy_timeout = jiffies + 2;
1983 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1984 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1985 rx_size = 0;
1986 goto no_early_rx;
1987 }
1988 if (netif_msg_intr(tp)) {
1989 printk(KERN_DEBUG "%s: fifo copy in progress.",
1990 dev->name);
1991 }
1992 tp->xstats.early_rx++;
1993 break;
1994 }
1995
1996 no_early_rx:
1997 tp->fifo_copy_timeout = 0;
1998
1999 /* If Rx err or invalid rx_size/rx_status received
2000 * (which happens if we get lost in the ring),
2001 * Rx process gets reset, so we abort any further
2002 * Rx processing.
2003 */
2004 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2005 (rx_size < 8) ||
2006 (!(rx_status & RxStatusOK)))) {
2007 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2008 received = -1;
2009 goto out;
2010 }
2011
2012 /* Malloc up new buffer, compatible with net-2e. */
2013 /* Omit the four octet CRC from the length. */
2014
2015 skb = dev_alloc_skb (pkt_size + 2);
2016 if (likely(skb)) {
2017 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2018 #if RX_BUF_IDX == 3
2019 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2020 #else
2021 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2022 #endif
2023 skb_put (skb, pkt_size);
2024
2025 skb->protocol = eth_type_trans (skb, dev);
2026
2027 dev->last_rx = jiffies;
2028 tp->stats.rx_bytes += pkt_size;
2029 tp->stats.rx_packets++;
2030
2031 netif_receive_skb (skb);
2032 } else {
2033 if (net_ratelimit())
2034 printk (KERN_WARNING
2035 "%s: Memory squeeze, dropping packet.\n",
2036 dev->name);
2037 tp->stats.rx_dropped++;
2038 }
2039 received++;
2040
2041 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2042 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2043
2044 rtl8139_isr_ack(tp);
2045 }
2046
2047 if (unlikely(!received || rx_size == 0xfff0))
2048 rtl8139_isr_ack(tp);
2049
2050 #if RTL8139_DEBUG > 1
2051 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2052 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2053 RTL_R16 (RxBufAddr),
2054 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2055 #endif
2056
2057 tp->cur_rx = cur_rx;
2058
2059 /*
2060 * The receive buffer should be mostly empty.
2061 * Tell NAPI to reenable the Rx irq.
2062 */
2063 if (tp->fifo_copy_timeout)
2064 received = budget;
2065
2066 out:
2067 return received;
2068 }
2069
2070
2071 static void rtl8139_weird_interrupt (struct net_device *dev,
2072 struct rtl8139_private *tp,
2073 void __iomem *ioaddr,
2074 int status, int link_changed)
2075 {
2076 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2077 dev->name, status);
2078
2079 assert (dev != NULL);
2080 assert (tp != NULL);
2081 assert (ioaddr != NULL);
2082
2083 /* Update the error count. */
2084 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2085 RTL_W32 (RxMissed, 0);
2086
2087 if ((status & RxUnderrun) && link_changed &&
2088 (tp->drv_flags & HAS_LNK_CHNG)) {
2089 rtl_check_media(dev, 0);
2090 status &= ~RxUnderrun;
2091 }
2092
2093 if (status & (RxUnderrun | RxErr))
2094 tp->stats.rx_errors++;
2095
2096 if (status & PCSTimeout)
2097 tp->stats.rx_length_errors++;
2098 if (status & RxUnderrun)
2099 tp->stats.rx_fifo_errors++;
2100 if (status & PCIErr) {
2101 u16 pci_cmd_status;
2102 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2103 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2104
2105 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2106 dev->name, pci_cmd_status);
2107 }
2108 }
2109
2110 static int rtl8139_poll(struct napi_struct *napi, int budget)
2111 {
2112 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2113 struct net_device *dev = tp->dev;
2114 void __iomem *ioaddr = tp->mmio_addr;
2115 int work_done;
2116
2117 spin_lock(&tp->rx_lock);
2118 work_done = 0;
2119 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2120 work_done += rtl8139_rx(dev, tp, budget);
2121
2122 if (work_done < budget) {
2123 unsigned long flags;
2124 /*
2125 * Order is important since data can get interrupted
2126 * again when we think we are done.
2127 */
2128 spin_lock_irqsave(&tp->lock, flags);
2129 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2130 __netif_rx_complete(dev, napi);
2131 spin_unlock_irqrestore(&tp->lock, flags);
2132 }
2133 spin_unlock(&tp->rx_lock);
2134
2135 return work_done;
2136 }
2137
2138 /* The interrupt handler does all of the Rx thread work and cleans up
2139 after the Tx thread. */
2140 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2141 {
2142 struct net_device *dev = (struct net_device *) dev_instance;
2143 struct rtl8139_private *tp = netdev_priv(dev);
2144 void __iomem *ioaddr = tp->mmio_addr;
2145 u16 status, ackstat;
2146 int link_changed = 0; /* avoid bogus "uninit" warning */
2147 int handled = 0;
2148
2149 spin_lock (&tp->lock);
2150 status = RTL_R16 (IntrStatus);
2151
2152 /* shared irq? */
2153 if (unlikely((status & rtl8139_intr_mask) == 0))
2154 goto out;
2155
2156 handled = 1;
2157
2158 /* h/w no longer present (hotplug?) or major error, bail */
2159 if (unlikely(status == 0xFFFF))
2160 goto out;
2161
2162 /* close possible race's with dev_close */
2163 if (unlikely(!netif_running(dev))) {
2164 RTL_W16 (IntrMask, 0);
2165 goto out;
2166 }
2167
2168 /* Acknowledge all of the current interrupt sources ASAP, but
2169 an first get an additional status bit from CSCR. */
2170 if (unlikely(status & RxUnderrun))
2171 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2172
2173 ackstat = status & ~(RxAckBits | TxErr);
2174 if (ackstat)
2175 RTL_W16 (IntrStatus, ackstat);
2176
2177 /* Receive packets are processed by poll routine.
2178 If not running start it now. */
2179 if (status & RxAckBits){
2180 if (netif_rx_schedule_prep(dev, &tp->napi)) {
2181 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2182 __netif_rx_schedule(dev, &tp->napi);
2183 }
2184 }
2185
2186 /* Check uncommon events with one test. */
2187 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2188 rtl8139_weird_interrupt (dev, tp, ioaddr,
2189 status, link_changed);
2190
2191 if (status & (TxOK | TxErr)) {
2192 rtl8139_tx_interrupt (dev, tp, ioaddr);
2193 if (status & TxErr)
2194 RTL_W16 (IntrStatus, TxErr);
2195 }
2196 out:
2197 spin_unlock (&tp->lock);
2198
2199 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2200 dev->name, RTL_R16 (IntrStatus));
2201 return IRQ_RETVAL(handled);
2202 }
2203
2204 #ifdef CONFIG_NET_POLL_CONTROLLER
2205 /*
2206 * Polling receive - used by netconsole and other diagnostic tools
2207 * to allow network i/o with interrupts disabled.
2208 */
2209 static void rtl8139_poll_controller(struct net_device *dev)
2210 {
2211 disable_irq(dev->irq);
2212 rtl8139_interrupt(dev->irq, dev);
2213 enable_irq(dev->irq);
2214 }
2215 #endif
2216
2217 static int rtl8139_close (struct net_device *dev)
2218 {
2219 struct rtl8139_private *tp = netdev_priv(dev);
2220 void __iomem *ioaddr = tp->mmio_addr;
2221 unsigned long flags;
2222
2223 netif_stop_queue(dev);
2224 napi_disable(&tp->napi);
2225
2226 if (netif_msg_ifdown(tp))
2227 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2228 dev->name, RTL_R16 (IntrStatus));
2229
2230 spin_lock_irqsave (&tp->lock, flags);
2231
2232 /* Stop the chip's Tx and Rx DMA processes. */
2233 RTL_W8 (ChipCmd, 0);
2234
2235 /* Disable interrupts by clearing the interrupt mask. */
2236 RTL_W16 (IntrMask, 0);
2237
2238 /* Update the error counts. */
2239 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2240 RTL_W32 (RxMissed, 0);
2241
2242 spin_unlock_irqrestore (&tp->lock, flags);
2243
2244 synchronize_irq (dev->irq); /* racy, but that's ok here */
2245 free_irq (dev->irq, dev);
2246
2247 rtl8139_tx_clear (tp);
2248
2249 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2250 tp->rx_ring, tp->rx_ring_dma);
2251 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2252 tp->tx_bufs, tp->tx_bufs_dma);
2253 tp->rx_ring = NULL;
2254 tp->tx_bufs = NULL;
2255
2256 /* Green! Put the chip in low-power mode. */
2257 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2258
2259 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2260 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2261
2262 return 0;
2263 }
2264
2265
2266 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2267 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2268 other threads or interrupts aren't messing with the 8139. */
2269 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2270 {
2271 struct rtl8139_private *np = netdev_priv(dev);
2272 void __iomem *ioaddr = np->mmio_addr;
2273
2274 spin_lock_irq(&np->lock);
2275 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2276 u8 cfg3 = RTL_R8 (Config3);
2277 u8 cfg5 = RTL_R8 (Config5);
2278
2279 wol->supported = WAKE_PHY | WAKE_MAGIC
2280 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2281
2282 wol->wolopts = 0;
2283 if (cfg3 & Cfg3_LinkUp)
2284 wol->wolopts |= WAKE_PHY;
2285 if (cfg3 & Cfg3_Magic)
2286 wol->wolopts |= WAKE_MAGIC;
2287 /* (KON)FIXME: See how netdev_set_wol() handles the
2288 following constants. */
2289 if (cfg5 & Cfg5_UWF)
2290 wol->wolopts |= WAKE_UCAST;
2291 if (cfg5 & Cfg5_MWF)
2292 wol->wolopts |= WAKE_MCAST;
2293 if (cfg5 & Cfg5_BWF)
2294 wol->wolopts |= WAKE_BCAST;
2295 }
2296 spin_unlock_irq(&np->lock);
2297 }
2298
2299
2300 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2301 that wol points to kernel memory and other threads or interrupts
2302 aren't messing with the 8139. */
2303 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2304 {
2305 struct rtl8139_private *np = netdev_priv(dev);
2306 void __iomem *ioaddr = np->mmio_addr;
2307 u32 support;
2308 u8 cfg3, cfg5;
2309
2310 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2311 ? (WAKE_PHY | WAKE_MAGIC
2312 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2313 : 0);
2314 if (wol->wolopts & ~support)
2315 return -EINVAL;
2316
2317 spin_lock_irq(&np->lock);
2318 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2319 if (wol->wolopts & WAKE_PHY)
2320 cfg3 |= Cfg3_LinkUp;
2321 if (wol->wolopts & WAKE_MAGIC)
2322 cfg3 |= Cfg3_Magic;
2323 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2324 RTL_W8 (Config3, cfg3);
2325 RTL_W8 (Cfg9346, Cfg9346_Lock);
2326
2327 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2328 /* (KON)FIXME: These are untested. We may have to set the
2329 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2330 documentation. */
2331 if (wol->wolopts & WAKE_UCAST)
2332 cfg5 |= Cfg5_UWF;
2333 if (wol->wolopts & WAKE_MCAST)
2334 cfg5 |= Cfg5_MWF;
2335 if (wol->wolopts & WAKE_BCAST)
2336 cfg5 |= Cfg5_BWF;
2337 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2338 spin_unlock_irq(&np->lock);
2339
2340 return 0;
2341 }
2342
2343 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2344 {
2345 struct rtl8139_private *np = netdev_priv(dev);
2346 strcpy(info->driver, DRV_NAME);
2347 strcpy(info->version, DRV_VERSION);
2348 strcpy(info->bus_info, pci_name(np->pci_dev));
2349 info->regdump_len = np->regs_len;
2350 }
2351
2352 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2353 {
2354 struct rtl8139_private *np = netdev_priv(dev);
2355 spin_lock_irq(&np->lock);
2356 mii_ethtool_gset(&np->mii, cmd);
2357 spin_unlock_irq(&np->lock);
2358 return 0;
2359 }
2360
2361 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2362 {
2363 struct rtl8139_private *np = netdev_priv(dev);
2364 int rc;
2365 spin_lock_irq(&np->lock);
2366 rc = mii_ethtool_sset(&np->mii, cmd);
2367 spin_unlock_irq(&np->lock);
2368 return rc;
2369 }
2370
2371 static int rtl8139_nway_reset(struct net_device *dev)
2372 {
2373 struct rtl8139_private *np = netdev_priv(dev);
2374 return mii_nway_restart(&np->mii);
2375 }
2376
2377 static u32 rtl8139_get_link(struct net_device *dev)
2378 {
2379 struct rtl8139_private *np = netdev_priv(dev);
2380 return mii_link_ok(&np->mii);
2381 }
2382
2383 static u32 rtl8139_get_msglevel(struct net_device *dev)
2384 {
2385 struct rtl8139_private *np = netdev_priv(dev);
2386 return np->msg_enable;
2387 }
2388
2389 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2390 {
2391 struct rtl8139_private *np = netdev_priv(dev);
2392 np->msg_enable = datum;
2393 }
2394
2395 /* TODO: we are too slack to do reg dumping for pio, for now */
2396 #ifdef CONFIG_8139TOO_PIO
2397 #define rtl8139_get_regs_len NULL
2398 #define rtl8139_get_regs NULL
2399 #else
2400 static int rtl8139_get_regs_len(struct net_device *dev)
2401 {
2402 struct rtl8139_private *np = netdev_priv(dev);
2403 return np->regs_len;
2404 }
2405
2406 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2407 {
2408 struct rtl8139_private *np = netdev_priv(dev);
2409
2410 regs->version = RTL_REGS_VER;
2411
2412 spin_lock_irq(&np->lock);
2413 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2414 spin_unlock_irq(&np->lock);
2415 }
2416 #endif /* CONFIG_8139TOO_MMIO */
2417
2418 static int rtl8139_get_stats_count(struct net_device *dev)
2419 {
2420 return RTL_NUM_STATS;
2421 }
2422
2423 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2424 {
2425 struct rtl8139_private *np = netdev_priv(dev);
2426
2427 data[0] = np->xstats.early_rx;
2428 data[1] = np->xstats.tx_buf_mapped;
2429 data[2] = np->xstats.tx_timeouts;
2430 data[3] = np->xstats.rx_lost_in_ring;
2431 }
2432
2433 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2434 {
2435 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2436 }
2437
2438 static const struct ethtool_ops rtl8139_ethtool_ops = {
2439 .get_drvinfo = rtl8139_get_drvinfo,
2440 .get_settings = rtl8139_get_settings,
2441 .set_settings = rtl8139_set_settings,
2442 .get_regs_len = rtl8139_get_regs_len,
2443 .get_regs = rtl8139_get_regs,
2444 .nway_reset = rtl8139_nway_reset,
2445 .get_link = rtl8139_get_link,
2446 .get_msglevel = rtl8139_get_msglevel,
2447 .set_msglevel = rtl8139_set_msglevel,
2448 .get_wol = rtl8139_get_wol,
2449 .set_wol = rtl8139_set_wol,
2450 .get_strings = rtl8139_get_strings,
2451 .get_stats_count = rtl8139_get_stats_count,
2452 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2453 };
2454
2455 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2456 {
2457 struct rtl8139_private *np = netdev_priv(dev);
2458 int rc;
2459
2460 if (!netif_running(dev))
2461 return -EINVAL;
2462
2463 spin_lock_irq(&np->lock);
2464 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2465 spin_unlock_irq(&np->lock);
2466
2467 return rc;
2468 }
2469
2470
2471 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2472 {
2473 struct rtl8139_private *tp = netdev_priv(dev);
2474 void __iomem *ioaddr = tp->mmio_addr;
2475 unsigned long flags;
2476
2477 if (netif_running(dev)) {
2478 spin_lock_irqsave (&tp->lock, flags);
2479 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2480 RTL_W32 (RxMissed, 0);
2481 spin_unlock_irqrestore (&tp->lock, flags);
2482 }
2483
2484 return &tp->stats;
2485 }
2486
2487 /* Set or clear the multicast filter for this adaptor.
2488 This routine is not state sensitive and need not be SMP locked. */
2489
2490 static void __set_rx_mode (struct net_device *dev)
2491 {
2492 struct rtl8139_private *tp = netdev_priv(dev);
2493 void __iomem *ioaddr = tp->mmio_addr;
2494 u32 mc_filter[2]; /* Multicast hash filter */
2495 int i, rx_mode;
2496 u32 tmp;
2497
2498 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2499 dev->name, dev->flags, RTL_R32 (RxConfig));
2500
2501 /* Note: do not reorder, GCC is clever about common statements. */
2502 if (dev->flags & IFF_PROMISC) {
2503 rx_mode =
2504 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2505 AcceptAllPhys;
2506 mc_filter[1] = mc_filter[0] = 0xffffffff;
2507 } else if ((dev->mc_count > multicast_filter_limit)
2508 || (dev->flags & IFF_ALLMULTI)) {
2509 /* Too many to filter perfectly -- accept all multicasts. */
2510 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2511 mc_filter[1] = mc_filter[0] = 0xffffffff;
2512 } else {
2513 struct dev_mc_list *mclist;
2514 rx_mode = AcceptBroadcast | AcceptMyPhys;
2515 mc_filter[1] = mc_filter[0] = 0;
2516 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2517 i++, mclist = mclist->next) {
2518 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2519
2520 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2521 rx_mode |= AcceptMulticast;
2522 }
2523 }
2524
2525 /* We can safely update without stopping the chip. */
2526 tmp = rtl8139_rx_config | rx_mode;
2527 if (tp->rx_config != tmp) {
2528 RTL_W32_F (RxConfig, tmp);
2529 tp->rx_config = tmp;
2530 }
2531 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2532 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2533 }
2534
2535 static void rtl8139_set_rx_mode (struct net_device *dev)
2536 {
2537 unsigned long flags;
2538 struct rtl8139_private *tp = netdev_priv(dev);
2539
2540 spin_lock_irqsave (&tp->lock, flags);
2541 __set_rx_mode(dev);
2542 spin_unlock_irqrestore (&tp->lock, flags);
2543 }
2544
2545 #ifdef CONFIG_PM
2546
2547 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2548 {
2549 struct net_device *dev = pci_get_drvdata (pdev);
2550 struct rtl8139_private *tp = netdev_priv(dev);
2551 void __iomem *ioaddr = tp->mmio_addr;
2552 unsigned long flags;
2553
2554 pci_save_state (pdev);
2555
2556 if (!netif_running (dev))
2557 return 0;
2558
2559 netif_device_detach (dev);
2560
2561 spin_lock_irqsave (&tp->lock, flags);
2562
2563 /* Disable interrupts, stop Tx and Rx. */
2564 RTL_W16 (IntrMask, 0);
2565 RTL_W8 (ChipCmd, 0);
2566
2567 /* Update the error counts. */
2568 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2569 RTL_W32 (RxMissed, 0);
2570
2571 spin_unlock_irqrestore (&tp->lock, flags);
2572
2573 pci_set_power_state (pdev, PCI_D3hot);
2574
2575 return 0;
2576 }
2577
2578
2579 static int rtl8139_resume (struct pci_dev *pdev)
2580 {
2581 struct net_device *dev = pci_get_drvdata (pdev);
2582
2583 pci_restore_state (pdev);
2584 if (!netif_running (dev))
2585 return 0;
2586 pci_set_power_state (pdev, PCI_D0);
2587 rtl8139_init_ring (dev);
2588 rtl8139_hw_start (dev);
2589 netif_device_attach (dev);
2590 return 0;
2591 }
2592
2593 #endif /* CONFIG_PM */
2594
2595
2596 static struct pci_driver rtl8139_pci_driver = {
2597 .name = DRV_NAME,
2598 .id_table = rtl8139_pci_tbl,
2599 .probe = rtl8139_init_one,
2600 .remove = __devexit_p(rtl8139_remove_one),
2601 #ifdef CONFIG_PM
2602 .suspend = rtl8139_suspend,
2603 .resume = rtl8139_resume,
2604 #endif /* CONFIG_PM */
2605 };
2606
2607
2608 static int __init rtl8139_init_module (void)
2609 {
2610 /* when we're a module, we always print a version message,
2611 * even if no 8139 board is found.
2612 */
2613 #ifdef MODULE
2614 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2615 #endif
2616
2617 return pci_register_driver(&rtl8139_pci_driver);
2618 }
2619
2620
2621 static void __exit rtl8139_cleanup_module (void)
2622 {
2623 pci_unregister_driver (&rtl8139_pci_driver);
2624 }
2625
2626
2627 module_init(rtl8139_init_module);
2628 module_exit(rtl8139_cleanup_module);
AMDTP streaming driver for the Linux FireWire stack (Juju)