2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spi/spi.h>
28 #include <linux/workqueue.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
34 #include <asm/delay.h>
37 #include <asm/arch/hardware.h>
38 #include <asm/arch/pxa-regs.h>
39 #include <asm/arch/regs-ssp.h>
40 #include <asm/arch/ssp.h>
41 #include <asm/arch/pxa2xx_spi.h>
43 MODULE_AUTHOR("Stephen Street");
44 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
45 MODULE_LICENSE("GPL");
46 MODULE_ALIAS("platform:pxa2xx-spi");
50 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
51 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
52 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
55 * for testing SSCR1 changes that require SSP restart, basically
56 * everything except the service and interrupt enables, the pxa270 developer
57 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
58 * list, but the PXA255 dev man says all bits without really meaning the
59 * service and interrupt enables
61 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
62 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
63 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
64 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
65 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
66 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
68 #define DEFINE_SSP_REG(reg, off) \
69 static inline u32 read_##reg(void const __iomem *p) \
70 { return __raw_readl(p + (off)); } \
72 static inline void write_##reg(u32 v, void __iomem *p) \
73 { __raw_writel(v, p + (off)); }
75 DEFINE_SSP_REG(SSCR0
, 0x00)
76 DEFINE_SSP_REG(SSCR1
, 0x04)
77 DEFINE_SSP_REG(SSSR
, 0x08)
78 DEFINE_SSP_REG(SSITR
, 0x0c)
79 DEFINE_SSP_REG(SSDR
, 0x10)
80 DEFINE_SSP_REG(SSTO
, 0x28)
81 DEFINE_SSP_REG(SSPSP
, 0x2c)
83 #define START_STATE ((void*)0)
84 #define RUNNING_STATE ((void*)1)
85 #define DONE_STATE ((void*)2)
86 #define ERROR_STATE ((void*)-1)
88 #define QUEUE_RUNNING 0
89 #define QUEUE_STOPPED 1
92 /* Driver model hookup */
93 struct platform_device
*pdev
;
96 struct ssp_device
*ssp
;
98 /* SPI framework hookup */
99 enum pxa_ssp_type ssp_type
;
100 struct spi_master
*master
;
103 struct pxa2xx_spi_master
*master_info
;
105 /* DMA setup stuff */
110 /* SSP register addresses */
111 void __iomem
*ioaddr
;
120 /* Driver message queue */
121 struct workqueue_struct
*workqueue
;
122 struct work_struct pump_messages
;
124 struct list_head queue
;
128 /* Message Transfer pump */
129 struct tasklet_struct pump_transfers
;
131 /* Current message transfer state info */
132 struct spi_message
* cur_msg
;
133 struct spi_transfer
* cur_transfer
;
134 struct chip_data
*cur_chip
;
148 int (*write
)(struct driver_data
*drv_data
);
149 int (*read
)(struct driver_data
*drv_data
);
150 irqreturn_t (*transfer_handler
)(struct driver_data
*drv_data
);
151 void (*cs_control
)(u32 command
);
167 int (*write
)(struct driver_data
*drv_data
);
168 int (*read
)(struct driver_data
*drv_data
);
169 void (*cs_control
)(u32 command
);
172 static void pump_messages(struct work_struct
*work
);
174 static int flush(struct driver_data
*drv_data
)
176 unsigned long limit
= loops_per_jiffy
<< 1;
178 void __iomem
*reg
= drv_data
->ioaddr
;
181 while (read_SSSR(reg
) & SSSR_RNE
) {
184 } while ((read_SSSR(reg
) & SSSR_BSY
) && limit
--);
185 write_SSSR(SSSR_ROR
, reg
);
190 static void null_cs_control(u32 command
)
194 static int null_writer(struct driver_data
*drv_data
)
196 void __iomem
*reg
= drv_data
->ioaddr
;
197 u8 n_bytes
= drv_data
->n_bytes
;
199 if (((read_SSSR(reg
) & 0x00000f00) == 0x00000f00)
200 || (drv_data
->tx
== drv_data
->tx_end
))
204 drv_data
->tx
+= n_bytes
;
209 static int null_reader(struct driver_data
*drv_data
)
211 void __iomem
*reg
= drv_data
->ioaddr
;
212 u8 n_bytes
= drv_data
->n_bytes
;
214 while ((read_SSSR(reg
) & SSSR_RNE
)
215 && (drv_data
->rx
< drv_data
->rx_end
)) {
217 drv_data
->rx
+= n_bytes
;
220 return drv_data
->rx
== drv_data
->rx_end
;
223 static int u8_writer(struct driver_data
*drv_data
)
225 void __iomem
*reg
= drv_data
->ioaddr
;
227 if (((read_SSSR(reg
) & 0x00000f00) == 0x00000f00)
228 || (drv_data
->tx
== drv_data
->tx_end
))
231 write_SSDR(*(u8
*)(drv_data
->tx
), reg
);
237 static int u8_reader(struct driver_data
*drv_data
)
239 void __iomem
*reg
= drv_data
->ioaddr
;
241 while ((read_SSSR(reg
) & SSSR_RNE
)
242 && (drv_data
->rx
< drv_data
->rx_end
)) {
243 *(u8
*)(drv_data
->rx
) = read_SSDR(reg
);
247 return drv_data
->rx
== drv_data
->rx_end
;
250 static int u16_writer(struct driver_data
*drv_data
)
252 void __iomem
*reg
= drv_data
->ioaddr
;
254 if (((read_SSSR(reg
) & 0x00000f00) == 0x00000f00)
255 || (drv_data
->tx
== drv_data
->tx_end
))
258 write_SSDR(*(u16
*)(drv_data
->tx
), reg
);
264 static int u16_reader(struct driver_data
*drv_data
)
266 void __iomem
*reg
= drv_data
->ioaddr
;
268 while ((read_SSSR(reg
) & SSSR_RNE
)
269 && (drv_data
->rx
< drv_data
->rx_end
)) {
270 *(u16
*)(drv_data
->rx
) = read_SSDR(reg
);
274 return drv_data
->rx
== drv_data
->rx_end
;
277 static int u32_writer(struct driver_data
*drv_data
)
279 void __iomem
*reg
= drv_data
->ioaddr
;
281 if (((read_SSSR(reg
) & 0x00000f00) == 0x00000f00)
282 || (drv_data
->tx
== drv_data
->tx_end
))
285 write_SSDR(*(u32
*)(drv_data
->tx
), reg
);
291 static int u32_reader(struct driver_data
*drv_data
)
293 void __iomem
*reg
= drv_data
->ioaddr
;
295 while ((read_SSSR(reg
) & SSSR_RNE
)
296 && (drv_data
->rx
< drv_data
->rx_end
)) {
297 *(u32
*)(drv_data
->rx
) = read_SSDR(reg
);
301 return drv_data
->rx
== drv_data
->rx_end
;
304 static void *next_transfer(struct driver_data
*drv_data
)
306 struct spi_message
*msg
= drv_data
->cur_msg
;
307 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
309 /* Move to next transfer */
310 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
311 drv_data
->cur_transfer
=
312 list_entry(trans
->transfer_list
.next
,
315 return RUNNING_STATE
;
320 static int map_dma_buffers(struct driver_data
*drv_data
)
322 struct spi_message
*msg
= drv_data
->cur_msg
;
323 struct device
*dev
= &msg
->spi
->dev
;
325 if (!drv_data
->cur_chip
->enable_dma
)
328 if (msg
->is_dma_mapped
)
329 return drv_data
->rx_dma
&& drv_data
->tx_dma
;
331 if (!IS_DMA_ALIGNED(drv_data
->rx
) || !IS_DMA_ALIGNED(drv_data
->tx
))
334 /* Modify setup if rx buffer is null */
335 if (drv_data
->rx
== NULL
) {
336 *drv_data
->null_dma_buf
= 0;
337 drv_data
->rx
= drv_data
->null_dma_buf
;
338 drv_data
->rx_map_len
= 4;
340 drv_data
->rx_map_len
= drv_data
->len
;
343 /* Modify setup if tx buffer is null */
344 if (drv_data
->tx
== NULL
) {
345 *drv_data
->null_dma_buf
= 0;
346 drv_data
->tx
= drv_data
->null_dma_buf
;
347 drv_data
->tx_map_len
= 4;
349 drv_data
->tx_map_len
= drv_data
->len
;
351 /* Stream map the rx buffer */
352 drv_data
->rx_dma
= dma_map_single(dev
, drv_data
->rx
,
353 drv_data
->rx_map_len
,
355 if (dma_mapping_error(dev
, drv_data
->rx_dma
))
358 /* Stream map the tx buffer */
359 drv_data
->tx_dma
= dma_map_single(dev
, drv_data
->tx
,
360 drv_data
->tx_map_len
,
363 if (dma_mapping_error(dev
, drv_data
->tx_dma
)) {
364 dma_unmap_single(dev
, drv_data
->rx_dma
,
365 drv_data
->rx_map_len
, DMA_FROM_DEVICE
);
372 static void unmap_dma_buffers(struct driver_data
*drv_data
)
376 if (!drv_data
->dma_mapped
)
379 if (!drv_data
->cur_msg
->is_dma_mapped
) {
380 dev
= &drv_data
->cur_msg
->spi
->dev
;
381 dma_unmap_single(dev
, drv_data
->rx_dma
,
382 drv_data
->rx_map_len
, DMA_FROM_DEVICE
);
383 dma_unmap_single(dev
, drv_data
->tx_dma
,
384 drv_data
->tx_map_len
, DMA_TO_DEVICE
);
387 drv_data
->dma_mapped
= 0;
390 /* caller already set message->status; dma and pio irqs are blocked */
391 static void giveback(struct driver_data
*drv_data
)
393 struct spi_transfer
* last_transfer
;
395 struct spi_message
*msg
;
397 spin_lock_irqsave(&drv_data
->lock
, flags
);
398 msg
= drv_data
->cur_msg
;
399 drv_data
->cur_msg
= NULL
;
400 drv_data
->cur_transfer
= NULL
;
401 drv_data
->cur_chip
= NULL
;
402 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
403 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
405 last_transfer
= list_entry(msg
->transfers
.prev
,
409 if (!last_transfer
->cs_change
)
410 drv_data
->cs_control(PXA2XX_CS_DEASSERT
);
414 msg
->complete(msg
->context
);
417 static int wait_ssp_rx_stall(void const __iomem
*ioaddr
)
419 unsigned long limit
= loops_per_jiffy
<< 1;
421 while ((read_SSSR(ioaddr
) & SSSR_BSY
) && limit
--)
427 static int wait_dma_channel_stop(int channel
)
429 unsigned long limit
= loops_per_jiffy
<< 1;
431 while (!(DCSR(channel
) & DCSR_STOPSTATE
) && limit
--)
437 static void dma_error_stop(struct driver_data
*drv_data
, const char *msg
)
439 void __iomem
*reg
= drv_data
->ioaddr
;
442 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
443 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
444 write_SSSR(drv_data
->clear_sr
, reg
);
445 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->dma_cr1
, reg
);
446 if (drv_data
->ssp_type
!= PXA25x_SSP
)
449 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
451 unmap_dma_buffers(drv_data
);
453 dev_err(&drv_data
->pdev
->dev
, "%s\n", msg
);
455 drv_data
->cur_msg
->state
= ERROR_STATE
;
456 tasklet_schedule(&drv_data
->pump_transfers
);
459 static void dma_transfer_complete(struct driver_data
*drv_data
)
461 void __iomem
*reg
= drv_data
->ioaddr
;
462 struct spi_message
*msg
= drv_data
->cur_msg
;
464 /* Clear and disable interrupts on SSP and DMA channels*/
465 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->dma_cr1
, reg
);
466 write_SSSR(drv_data
->clear_sr
, reg
);
467 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
468 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
470 if (wait_dma_channel_stop(drv_data
->rx_channel
) == 0)
471 dev_err(&drv_data
->pdev
->dev
,
472 "dma_handler: dma rx channel stop failed\n");
474 if (wait_ssp_rx_stall(drv_data
->ioaddr
) == 0)
475 dev_err(&drv_data
->pdev
->dev
,
476 "dma_transfer: ssp rx stall failed\n");
478 unmap_dma_buffers(drv_data
);
480 /* update the buffer pointer for the amount completed in dma */
481 drv_data
->rx
+= drv_data
->len
-
482 (DCMD(drv_data
->rx_channel
) & DCMD_LENGTH
);
484 /* read trailing data from fifo, it does not matter how many
485 * bytes are in the fifo just read until buffer is full
486 * or fifo is empty, which ever occurs first */
487 drv_data
->read(drv_data
);
489 /* return count of what was actually read */
490 msg
->actual_length
+= drv_data
->len
-
491 (drv_data
->rx_end
- drv_data
->rx
);
493 /* Release chip select if requested, transfer delays are
494 * handled in pump_transfers */
495 if (drv_data
->cs_change
)
496 drv_data
->cs_control(PXA2XX_CS_DEASSERT
);
498 /* Move to next transfer */
499 msg
->state
= next_transfer(drv_data
);
501 /* Schedule transfer tasklet */
502 tasklet_schedule(&drv_data
->pump_transfers
);
505 static void dma_handler(int channel
, void *data
)
507 struct driver_data
*drv_data
= data
;
508 u32 irq_status
= DCSR(channel
) & DMA_INT_MASK
;
510 if (irq_status
& DCSR_BUSERR
) {
512 if (channel
== drv_data
->tx_channel
)
513 dma_error_stop(drv_data
,
515 "bad bus address on tx channel");
517 dma_error_stop(drv_data
,
519 "bad bus address on rx channel");
523 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
524 if ((channel
== drv_data
->tx_channel
)
525 && (irq_status
& DCSR_ENDINTR
)
526 && (drv_data
->ssp_type
== PXA25x_SSP
)) {
528 /* Wait for rx to stall */
529 if (wait_ssp_rx_stall(drv_data
->ioaddr
) == 0)
530 dev_err(&drv_data
->pdev
->dev
,
531 "dma_handler: ssp rx stall failed\n");
533 /* finish this transfer, start the next */
534 dma_transfer_complete(drv_data
);
538 static irqreturn_t
dma_transfer(struct driver_data
*drv_data
)
541 void __iomem
*reg
= drv_data
->ioaddr
;
543 irq_status
= read_SSSR(reg
) & drv_data
->mask_sr
;
544 if (irq_status
& SSSR_ROR
) {
545 dma_error_stop(drv_data
, "dma_transfer: fifo overrun");
549 /* Check for false positive timeout */
550 if ((irq_status
& SSSR_TINT
)
551 && (DCSR(drv_data
->tx_channel
) & DCSR_RUN
)) {
552 write_SSSR(SSSR_TINT
, reg
);
556 if (irq_status
& SSSR_TINT
|| drv_data
->rx
== drv_data
->rx_end
) {
558 /* Clear and disable timeout interrupt, do the rest in
559 * dma_transfer_complete */
560 if (drv_data
->ssp_type
!= PXA25x_SSP
)
563 /* finish this transfer, start the next */
564 dma_transfer_complete(drv_data
);
569 /* Opps problem detected */
573 static void int_error_stop(struct driver_data
*drv_data
, const char* msg
)
575 void __iomem
*reg
= drv_data
->ioaddr
;
577 /* Stop and reset SSP */
578 write_SSSR(drv_data
->clear_sr
, reg
);
579 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->int_cr1
, reg
);
580 if (drv_data
->ssp_type
!= PXA25x_SSP
)
583 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
585 dev_err(&drv_data
->pdev
->dev
, "%s\n", msg
);
587 drv_data
->cur_msg
->state
= ERROR_STATE
;
588 tasklet_schedule(&drv_data
->pump_transfers
);
591 static void int_transfer_complete(struct driver_data
*drv_data
)
593 void __iomem
*reg
= drv_data
->ioaddr
;
596 write_SSSR(drv_data
->clear_sr
, reg
);
597 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->int_cr1
, reg
);
598 if (drv_data
->ssp_type
!= PXA25x_SSP
)
601 /* Update total byte transfered return count actual bytes read */
602 drv_data
->cur_msg
->actual_length
+= drv_data
->len
-
603 (drv_data
->rx_end
- drv_data
->rx
);
605 /* Release chip select if requested, transfer delays are
606 * handled in pump_transfers */
607 if (drv_data
->cs_change
)
608 drv_data
->cs_control(PXA2XX_CS_DEASSERT
);
610 /* Move to next transfer */
611 drv_data
->cur_msg
->state
= next_transfer(drv_data
);
613 /* Schedule transfer tasklet */
614 tasklet_schedule(&drv_data
->pump_transfers
);
617 static irqreturn_t
interrupt_transfer(struct driver_data
*drv_data
)
619 void __iomem
*reg
= drv_data
->ioaddr
;
621 u32 irq_mask
= (read_SSCR1(reg
) & SSCR1_TIE
) ?
622 drv_data
->mask_sr
: drv_data
->mask_sr
& ~SSSR_TFS
;
624 u32 irq_status
= read_SSSR(reg
) & irq_mask
;
626 if (irq_status
& SSSR_ROR
) {
627 int_error_stop(drv_data
, "interrupt_transfer: fifo overrun");
631 if (irq_status
& SSSR_TINT
) {
632 write_SSSR(SSSR_TINT
, reg
);
633 if (drv_data
->read(drv_data
)) {
634 int_transfer_complete(drv_data
);
639 /* Drain rx fifo, Fill tx fifo and prevent overruns */
641 if (drv_data
->read(drv_data
)) {
642 int_transfer_complete(drv_data
);
645 } while (drv_data
->write(drv_data
));
647 if (drv_data
->read(drv_data
)) {
648 int_transfer_complete(drv_data
);
652 if (drv_data
->tx
== drv_data
->tx_end
) {
653 write_SSCR1(read_SSCR1(reg
) & ~SSCR1_TIE
, reg
);
654 /* PXA25x_SSP has no timeout, read trailing bytes */
655 if (drv_data
->ssp_type
== PXA25x_SSP
) {
656 if (!wait_ssp_rx_stall(reg
))
658 int_error_stop(drv_data
, "interrupt_transfer: "
662 if (!drv_data
->read(drv_data
))
664 int_error_stop(drv_data
,
665 "interrupt_transfer: "
666 "trailing byte read failed");
669 int_transfer_complete(drv_data
);
673 /* We did something */
677 static irqreturn_t
ssp_int(int irq
, void *dev_id
)
679 struct driver_data
*drv_data
= dev_id
;
680 void __iomem
*reg
= drv_data
->ioaddr
;
682 if (!drv_data
->cur_msg
) {
684 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
685 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->int_cr1
, reg
);
686 if (drv_data
->ssp_type
!= PXA25x_SSP
)
688 write_SSSR(drv_data
->clear_sr
, reg
);
690 dev_err(&drv_data
->pdev
->dev
, "bad message state "
691 "in interrupt handler\n");
697 return drv_data
->transfer_handler(drv_data
);
700 static int set_dma_burst_and_threshold(struct chip_data
*chip
,
701 struct spi_device
*spi
,
702 u8 bits_per_word
, u32
*burst_code
,
705 struct pxa2xx_spi_chip
*chip_info
=
706 (struct pxa2xx_spi_chip
*)spi
->controller_data
;
713 /* Set the threshold (in registers) to equal the same amount of data
714 * as represented by burst size (in bytes). The computation below
715 * is (burst_size rounded up to nearest 8 byte, word or long word)
716 * divided by (bytes/register); the tx threshold is the inverse of
717 * the rx, so that there will always be enough data in the rx fifo
718 * to satisfy a burst, and there will always be enough space in the
719 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
720 * there is not enough space), there must always remain enough empty
721 * space in the rx fifo for any data loaded to the tx fifo.
722 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
723 * will be 8, or half the fifo;
724 * The threshold can only be set to 2, 4 or 8, but not 16, because
725 * to burst 16 to the tx fifo, the fifo would have to be empty;
726 * however, the minimum fifo trigger level is 1, and the tx will
727 * request service when the fifo is at this level, with only 15 spaces.
730 /* find bytes/word */
731 if (bits_per_word
<= 8)
733 else if (bits_per_word
<= 16)
738 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
740 req_burst_size
= chip_info
->dma_burst_size
;
742 switch (chip
->dma_burst_size
) {
744 /* if the default burst size is not set,
746 chip
->dma_burst_size
= DCMD_BURST8
;
758 if (req_burst_size
<= 8) {
759 *burst_code
= DCMD_BURST8
;
761 } else if (req_burst_size
<= 16) {
762 if (bytes_per_word
== 1) {
763 /* don't burst more than 1/2 the fifo */
764 *burst_code
= DCMD_BURST8
;
768 *burst_code
= DCMD_BURST16
;
772 if (bytes_per_word
== 1) {
773 /* don't burst more than 1/2 the fifo */
774 *burst_code
= DCMD_BURST8
;
777 } else if (bytes_per_word
== 2) {
778 /* don't burst more than 1/2 the fifo */
779 *burst_code
= DCMD_BURST16
;
783 *burst_code
= DCMD_BURST32
;
788 thresh_words
= burst_bytes
/ bytes_per_word
;
790 /* thresh_words will be between 2 and 8 */
791 *threshold
= (SSCR1_RxTresh(thresh_words
) & SSCR1_RFT
)
792 | (SSCR1_TxTresh(16-thresh_words
) & SSCR1_TFT
);
797 static unsigned int ssp_get_clk_div(struct ssp_device
*ssp
, int rate
)
799 unsigned long ssp_clk
= clk_get_rate(ssp
->clk
);
801 if (ssp
->type
== PXA25x_SSP
)
802 return ((ssp_clk
/ (2 * rate
) - 1) & 0xff) << 8;
804 return ((ssp_clk
/ rate
- 1) & 0xfff) << 8;
807 static void pump_transfers(unsigned long data
)
809 struct driver_data
*drv_data
= (struct driver_data
*)data
;
810 struct spi_message
*message
= NULL
;
811 struct spi_transfer
*transfer
= NULL
;
812 struct spi_transfer
*previous
= NULL
;
813 struct chip_data
*chip
= NULL
;
814 struct ssp_device
*ssp
= drv_data
->ssp
;
815 void __iomem
*reg
= drv_data
->ioaddr
;
821 u32 dma_thresh
= drv_data
->cur_chip
->dma_threshold
;
822 u32 dma_burst
= drv_data
->cur_chip
->dma_burst_size
;
824 /* Get current state information */
825 message
= drv_data
->cur_msg
;
826 transfer
= drv_data
->cur_transfer
;
827 chip
= drv_data
->cur_chip
;
829 /* Handle for abort */
830 if (message
->state
== ERROR_STATE
) {
831 message
->status
= -EIO
;
836 /* Handle end of message */
837 if (message
->state
== DONE_STATE
) {
843 /* Delay if requested at end of transfer*/
844 if (message
->state
== RUNNING_STATE
) {
845 previous
= list_entry(transfer
->transfer_list
.prev
,
848 if (previous
->delay_usecs
)
849 udelay(previous
->delay_usecs
);
852 /* Check transfer length */
853 if (transfer
->len
> 8191)
855 dev_warn(&drv_data
->pdev
->dev
, "pump_transfers: transfer "
856 "length greater than 8191\n");
857 message
->status
= -EINVAL
;
862 /* Setup the transfer state based on the type of transfer */
863 if (flush(drv_data
) == 0) {
864 dev_err(&drv_data
->pdev
->dev
, "pump_transfers: flush failed\n");
865 message
->status
= -EIO
;
869 drv_data
->n_bytes
= chip
->n_bytes
;
870 drv_data
->dma_width
= chip
->dma_width
;
871 drv_data
->cs_control
= chip
->cs_control
;
872 drv_data
->tx
= (void *)transfer
->tx_buf
;
873 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
874 drv_data
->rx
= transfer
->rx_buf
;
875 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
876 drv_data
->rx_dma
= transfer
->rx_dma
;
877 drv_data
->tx_dma
= transfer
->tx_dma
;
878 drv_data
->len
= transfer
->len
& DCMD_LENGTH
;
879 drv_data
->write
= drv_data
->tx
? chip
->write
: null_writer
;
880 drv_data
->read
= drv_data
->rx
? chip
->read
: null_reader
;
881 drv_data
->cs_change
= transfer
->cs_change
;
883 /* Change speed and bit per word on a per transfer */
885 if (transfer
->speed_hz
|| transfer
->bits_per_word
) {
887 bits
= chip
->bits_per_word
;
888 speed
= chip
->speed_hz
;
890 if (transfer
->speed_hz
)
891 speed
= transfer
->speed_hz
;
893 if (transfer
->bits_per_word
)
894 bits
= transfer
->bits_per_word
;
896 clk_div
= ssp_get_clk_div(ssp
, speed
);
899 drv_data
->n_bytes
= 1;
900 drv_data
->dma_width
= DCMD_WIDTH1
;
901 drv_data
->read
= drv_data
->read
!= null_reader
?
902 u8_reader
: null_reader
;
903 drv_data
->write
= drv_data
->write
!= null_writer
?
904 u8_writer
: null_writer
;
905 } else if (bits
<= 16) {
906 drv_data
->n_bytes
= 2;
907 drv_data
->dma_width
= DCMD_WIDTH2
;
908 drv_data
->read
= drv_data
->read
!= null_reader
?
909 u16_reader
: null_reader
;
910 drv_data
->write
= drv_data
->write
!= null_writer
?
911 u16_writer
: null_writer
;
912 } else if (bits
<= 32) {
913 drv_data
->n_bytes
= 4;
914 drv_data
->dma_width
= DCMD_WIDTH4
;
915 drv_data
->read
= drv_data
->read
!= null_reader
?
916 u32_reader
: null_reader
;
917 drv_data
->write
= drv_data
->write
!= null_writer
?
918 u32_writer
: null_writer
;
920 /* if bits/word is changed in dma mode, then must check the
921 * thresholds and burst also */
922 if (chip
->enable_dma
) {
923 if (set_dma_burst_and_threshold(chip
, message
->spi
,
926 if (printk_ratelimit())
927 dev_warn(&message
->spi
->dev
,
929 "DMA burst size reduced to "
930 "match bits_per_word\n");
935 | SSCR0_DataSize(bits
> 16 ? bits
- 16 : bits
)
937 | (bits
> 16 ? SSCR0_EDSS
: 0);
940 message
->state
= RUNNING_STATE
;
942 /* Try to map dma buffer and do a dma transfer if successful */
943 if ((drv_data
->dma_mapped
= map_dma_buffers(drv_data
))) {
945 /* Ensure we have the correct interrupt handler */
946 drv_data
->transfer_handler
= dma_transfer
;
948 /* Setup rx DMA Channel */
949 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
950 DSADR(drv_data
->rx_channel
) = drv_data
->ssdr_physical
;
951 DTADR(drv_data
->rx_channel
) = drv_data
->rx_dma
;
952 if (drv_data
->rx
== drv_data
->null_dma_buf
)
953 /* No target address increment */
954 DCMD(drv_data
->rx_channel
) = DCMD_FLOWSRC
955 | drv_data
->dma_width
959 DCMD(drv_data
->rx_channel
) = DCMD_INCTRGADDR
961 | drv_data
->dma_width
965 /* Setup tx DMA Channel */
966 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
967 DSADR(drv_data
->tx_channel
) = drv_data
->tx_dma
;
968 DTADR(drv_data
->tx_channel
) = drv_data
->ssdr_physical
;
969 if (drv_data
->tx
== drv_data
->null_dma_buf
)
970 /* No source address increment */
971 DCMD(drv_data
->tx_channel
) = DCMD_FLOWTRG
972 | drv_data
->dma_width
976 DCMD(drv_data
->tx_channel
) = DCMD_INCSRCADDR
978 | drv_data
->dma_width
982 /* Enable dma end irqs on SSP to detect end of transfer */
983 if (drv_data
->ssp_type
== PXA25x_SSP
)
984 DCMD(drv_data
->tx_channel
) |= DCMD_ENDIRQEN
;
986 /* Clear status and start DMA engine */
987 cr1
= chip
->cr1
| dma_thresh
| drv_data
->dma_cr1
;
988 write_SSSR(drv_data
->clear_sr
, reg
);
989 DCSR(drv_data
->rx_channel
) |= DCSR_RUN
;
990 DCSR(drv_data
->tx_channel
) |= DCSR_RUN
;
992 /* Ensure we have the correct interrupt handler */
993 drv_data
->transfer_handler
= interrupt_transfer
;
996 cr1
= chip
->cr1
| chip
->threshold
| drv_data
->int_cr1
;
997 write_SSSR(drv_data
->clear_sr
, reg
);
1000 /* see if we need to reload the config registers */
1001 if ((read_SSCR0(reg
) != cr0
)
1002 || (read_SSCR1(reg
) & SSCR1_CHANGE_MASK
) !=
1003 (cr1
& SSCR1_CHANGE_MASK
)) {
1005 /* stop the SSP, and update the other bits */
1006 write_SSCR0(cr0
& ~SSCR0_SSE
, reg
);
1007 if (drv_data
->ssp_type
!= PXA25x_SSP
)
1008 write_SSTO(chip
->timeout
, reg
);
1009 /* first set CR1 without interrupt and service enables */
1010 write_SSCR1(cr1
& SSCR1_CHANGE_MASK
, reg
);
1011 /* restart the SSP */
1012 write_SSCR0(cr0
, reg
);
1015 if (drv_data
->ssp_type
!= PXA25x_SSP
)
1016 write_SSTO(chip
->timeout
, reg
);
1019 /* FIXME, need to handle cs polarity,
1020 * this driver uses struct pxa2xx_spi_chip.cs_control to
1021 * specify a CS handling function, and it ignores most
1022 * struct spi_device.mode[s], including SPI_CS_HIGH */
1023 drv_data
->cs_control(PXA2XX_CS_ASSERT
);
1025 /* after chip select, release the data by enabling service
1026 * requests and interrupts, without changing any mode bits */
1027 write_SSCR1(cr1
, reg
);
1030 static void pump_messages(struct work_struct
*work
)
1032 struct driver_data
*drv_data
=
1033 container_of(work
, struct driver_data
, pump_messages
);
1034 unsigned long flags
;
1036 /* Lock queue and check for queue work */
1037 spin_lock_irqsave(&drv_data
->lock
, flags
);
1038 if (list_empty(&drv_data
->queue
) || drv_data
->run
== QUEUE_STOPPED
) {
1040 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1044 /* Make sure we are not already running a message */
1045 if (drv_data
->cur_msg
) {
1046 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1050 /* Extract head of queue */
1051 drv_data
->cur_msg
= list_entry(drv_data
->queue
.next
,
1052 struct spi_message
, queue
);
1053 list_del_init(&drv_data
->cur_msg
->queue
);
1055 /* Initial message state*/
1056 drv_data
->cur_msg
->state
= START_STATE
;
1057 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
1058 struct spi_transfer
,
1061 /* prepare to setup the SSP, in pump_transfers, using the per
1062 * chip configuration */
1063 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
1065 /* Mark as busy and launch transfers */
1066 tasklet_schedule(&drv_data
->pump_transfers
);
1069 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1072 static int transfer(struct spi_device
*spi
, struct spi_message
*msg
)
1074 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
1075 unsigned long flags
;
1077 spin_lock_irqsave(&drv_data
->lock
, flags
);
1079 if (drv_data
->run
== QUEUE_STOPPED
) {
1080 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1084 msg
->actual_length
= 0;
1085 msg
->status
= -EINPROGRESS
;
1086 msg
->state
= START_STATE
;
1088 list_add_tail(&msg
->queue
, &drv_data
->queue
);
1090 if (drv_data
->run
== QUEUE_RUNNING
&& !drv_data
->busy
)
1091 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
1093 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1098 /* the spi->mode bits understood by this driver: */
1099 #define MODEBITS (SPI_CPOL | SPI_CPHA)
1101 static int setup(struct spi_device
*spi
)
1103 struct pxa2xx_spi_chip
*chip_info
= NULL
;
1104 struct chip_data
*chip
;
1105 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
1106 struct ssp_device
*ssp
= drv_data
->ssp
;
1107 unsigned int clk_div
;
1109 if (!spi
->bits_per_word
)
1110 spi
->bits_per_word
= 8;
1112 if (drv_data
->ssp_type
!= PXA25x_SSP
1113 && (spi
->bits_per_word
< 4 || spi
->bits_per_word
> 32)) {
1114 dev_err(&spi
->dev
, "failed setup: ssp_type=%d, bits/wrd=%d "
1115 "b/w not 4-32 for type non-PXA25x_SSP\n",
1116 drv_data
->ssp_type
, spi
->bits_per_word
);
1119 else if (drv_data
->ssp_type
== PXA25x_SSP
1120 && (spi
->bits_per_word
< 4
1121 || spi
->bits_per_word
> 16)) {
1122 dev_err(&spi
->dev
, "failed setup: ssp_type=%d, bits/wrd=%d "
1123 "b/w not 4-16 for type PXA25x_SSP\n",
1124 drv_data
->ssp_type
, spi
->bits_per_word
);
1128 if (spi
->mode
& ~MODEBITS
) {
1129 dev_dbg(&spi
->dev
, "setup: unsupported mode bits %x\n",
1130 spi
->mode
& ~MODEBITS
);
1134 /* Only alloc on first setup */
1135 chip
= spi_get_ctldata(spi
);
1137 chip
= kzalloc(sizeof(struct chip_data
), GFP_KERNEL
);
1140 "failed setup: can't allocate chip data\n");
1144 chip
->cs_control
= null_cs_control
;
1145 chip
->enable_dma
= 0;
1146 chip
->timeout
= 1000;
1147 chip
->threshold
= SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
1148 chip
->dma_burst_size
= drv_data
->master_info
->enable_dma
?
1152 /* protocol drivers may change the chip settings, so...
1153 * if chip_info exists, use it */
1154 chip_info
= spi
->controller_data
;
1156 /* chip_info isn't always needed */
1159 if (chip_info
->cs_control
)
1160 chip
->cs_control
= chip_info
->cs_control
;
1162 chip
->timeout
= chip_info
->timeout
;
1164 chip
->threshold
= (SSCR1_RxTresh(chip_info
->rx_threshold
) &
1166 (SSCR1_TxTresh(chip_info
->tx_threshold
) &
1169 chip
->enable_dma
= chip_info
->dma_burst_size
!= 0
1170 && drv_data
->master_info
->enable_dma
;
1171 chip
->dma_threshold
= 0;
1173 if (chip_info
->enable_loopback
)
1174 chip
->cr1
= SSCR1_LBM
;
1177 /* set dma burst and threshold outside of chip_info path so that if
1178 * chip_info goes away after setting chip->enable_dma, the
1179 * burst and threshold can still respond to changes in bits_per_word */
1180 if (chip
->enable_dma
) {
1181 /* set up legal burst and threshold for dma */
1182 if (set_dma_burst_and_threshold(chip
, spi
, spi
->bits_per_word
,
1183 &chip
->dma_burst_size
,
1184 &chip
->dma_threshold
)) {
1185 dev_warn(&spi
->dev
, "in setup: DMA burst size reduced "
1186 "to match bits_per_word\n");
1190 clk_div
= ssp_get_clk_div(ssp
, spi
->max_speed_hz
);
1191 chip
->speed_hz
= spi
->max_speed_hz
;
1195 | SSCR0_DataSize(spi
->bits_per_word
> 16 ?
1196 spi
->bits_per_word
- 16 : spi
->bits_per_word
)
1198 | (spi
->bits_per_word
> 16 ? SSCR0_EDSS
: 0);
1199 chip
->cr1
&= ~(SSCR1_SPO
| SSCR1_SPH
);
1200 chip
->cr1
|= (((spi
->mode
& SPI_CPHA
) != 0) ? SSCR1_SPH
: 0)
1201 | (((spi
->mode
& SPI_CPOL
) != 0) ? SSCR1_SPO
: 0);
1203 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1204 if (drv_data
->ssp_type
!= PXA25x_SSP
)
1205 dev_dbg(&spi
->dev
, "%d bits/word, %ld Hz, mode %d\n",
1207 clk_get_rate(ssp
->clk
)
1208 / (1 + ((chip
->cr0
& SSCR0_SCR
) >> 8)),
1211 dev_dbg(&spi
->dev
, "%d bits/word, %ld Hz, mode %d\n",
1213 clk_get_rate(ssp
->clk
)
1214 / (1 + ((chip
->cr0
& SSCR0_SCR
) >> 8)),
1217 if (spi
->bits_per_word
<= 8) {
1219 chip
->dma_width
= DCMD_WIDTH1
;
1220 chip
->read
= u8_reader
;
1221 chip
->write
= u8_writer
;
1222 } else if (spi
->bits_per_word
<= 16) {
1224 chip
->dma_width
= DCMD_WIDTH2
;
1225 chip
->read
= u16_reader
;
1226 chip
->write
= u16_writer
;
1227 } else if (spi
->bits_per_word
<= 32) {
1228 chip
->cr0
|= SSCR0_EDSS
;
1230 chip
->dma_width
= DCMD_WIDTH4
;
1231 chip
->read
= u32_reader
;
1232 chip
->write
= u32_writer
;
1234 dev_err(&spi
->dev
, "invalid wordsize\n");
1237 chip
->bits_per_word
= spi
->bits_per_word
;
1239 spi_set_ctldata(spi
, chip
);
1244 static void cleanup(struct spi_device
*spi
)
1246 struct chip_data
*chip
= spi_get_ctldata(spi
);
1251 static int __init
init_queue(struct driver_data
*drv_data
)
1253 INIT_LIST_HEAD(&drv_data
->queue
);
1254 spin_lock_init(&drv_data
->lock
);
1256 drv_data
->run
= QUEUE_STOPPED
;
1259 tasklet_init(&drv_data
->pump_transfers
,
1260 pump_transfers
, (unsigned long)drv_data
);
1262 INIT_WORK(&drv_data
->pump_messages
, pump_messages
);
1263 drv_data
->workqueue
= create_singlethread_workqueue(
1264 drv_data
->master
->dev
.parent
->bus_id
);
1265 if (drv_data
->workqueue
== NULL
)
1271 static int start_queue(struct driver_data
*drv_data
)
1273 unsigned long flags
;
1275 spin_lock_irqsave(&drv_data
->lock
, flags
);
1277 if (drv_data
->run
== QUEUE_RUNNING
|| drv_data
->busy
) {
1278 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1282 drv_data
->run
= QUEUE_RUNNING
;
1283 drv_data
->cur_msg
= NULL
;
1284 drv_data
->cur_transfer
= NULL
;
1285 drv_data
->cur_chip
= NULL
;
1286 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1288 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
1293 static int stop_queue(struct driver_data
*drv_data
)
1295 unsigned long flags
;
1296 unsigned limit
= 500;
1299 spin_lock_irqsave(&drv_data
->lock
, flags
);
1301 /* This is a bit lame, but is optimized for the common execution path.
1302 * A wait_queue on the drv_data->busy could be used, but then the common
1303 * execution path (pump_messages) would be required to call wake_up or
1304 * friends on every SPI message. Do this instead */
1305 drv_data
->run
= QUEUE_STOPPED
;
1306 while (!list_empty(&drv_data
->queue
) && drv_data
->busy
&& limit
--) {
1307 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1309 spin_lock_irqsave(&drv_data
->lock
, flags
);
1312 if (!list_empty(&drv_data
->queue
) || drv_data
->busy
)
1315 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1320 static int destroy_queue(struct driver_data
*drv_data
)
1324 status
= stop_queue(drv_data
);
1325 /* we are unloading the module or failing to load (only two calls
1326 * to this routine), and neither call can handle a return value.
1327 * However, destroy_workqueue calls flush_workqueue, and that will
1328 * block until all work is done. If the reason that stop_queue
1329 * timed out is that the work will never finish, then it does no
1330 * good to call destroy_workqueue, so return anyway. */
1334 destroy_workqueue(drv_data
->workqueue
);
1339 static int __init
pxa2xx_spi_probe(struct platform_device
*pdev
)
1341 struct device
*dev
= &pdev
->dev
;
1342 struct pxa2xx_spi_master
*platform_info
;
1343 struct spi_master
*master
;
1344 struct driver_data
*drv_data
= NULL
;
1345 struct ssp_device
*ssp
;
1348 platform_info
= dev
->platform_data
;
1350 ssp
= ssp_request(pdev
->id
, pdev
->name
);
1352 dev_err(&pdev
->dev
, "failed to request SSP%d\n", pdev
->id
);
1356 /* Allocate master with space for drv_data and null dma buffer */
1357 master
= spi_alloc_master(dev
, sizeof(struct driver_data
) + 16);
1359 dev_err(&pdev
->dev
, "can not alloc spi_master\n");
1363 drv_data
= spi_master_get_devdata(master
);
1364 drv_data
->master
= master
;
1365 drv_data
->master_info
= platform_info
;
1366 drv_data
->pdev
= pdev
;
1367 drv_data
->ssp
= ssp
;
1369 master
->bus_num
= pdev
->id
;
1370 master
->num_chipselect
= platform_info
->num_chipselect
;
1371 master
->cleanup
= cleanup
;
1372 master
->setup
= setup
;
1373 master
->transfer
= transfer
;
1375 drv_data
->ssp_type
= ssp
->type
;
1376 drv_data
->null_dma_buf
= (u32
*)ALIGN((u32
)(drv_data
+
1377 sizeof(struct driver_data
)), 8);
1379 drv_data
->ioaddr
= ssp
->mmio_base
;
1380 drv_data
->ssdr_physical
= ssp
->phys_base
+ SSDR
;
1381 if (ssp
->type
== PXA25x_SSP
) {
1382 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
;
1383 drv_data
->dma_cr1
= 0;
1384 drv_data
->clear_sr
= SSSR_ROR
;
1385 drv_data
->mask_sr
= SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1387 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
| SSCR1_TINTE
;
1388 drv_data
->dma_cr1
= SSCR1_TSRE
| SSCR1_RSRE
| SSCR1_TINTE
;
1389 drv_data
->clear_sr
= SSSR_ROR
| SSSR_TINT
;
1390 drv_data
->mask_sr
= SSSR_TINT
| SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1393 status
= request_irq(ssp
->irq
, ssp_int
, 0, dev
->bus_id
, drv_data
);
1395 dev_err(&pdev
->dev
, "can not get IRQ\n");
1396 goto out_error_master_alloc
;
1399 /* Setup DMA if requested */
1400 drv_data
->tx_channel
= -1;
1401 drv_data
->rx_channel
= -1;
1402 if (platform_info
->enable_dma
) {
1404 /* Get two DMA channels (rx and tx) */
1405 drv_data
->rx_channel
= pxa_request_dma("pxa2xx_spi_ssp_rx",
1409 if (drv_data
->rx_channel
< 0) {
1410 dev_err(dev
, "problem (%d) requesting rx channel\n",
1411 drv_data
->rx_channel
);
1413 goto out_error_irq_alloc
;
1415 drv_data
->tx_channel
= pxa_request_dma("pxa2xx_spi_ssp_tx",
1419 if (drv_data
->tx_channel
< 0) {
1420 dev_err(dev
, "problem (%d) requesting tx channel\n",
1421 drv_data
->tx_channel
);
1423 goto out_error_dma_alloc
;
1426 DRCMR(ssp
->drcmr_rx
) = DRCMR_MAPVLD
| drv_data
->rx_channel
;
1427 DRCMR(ssp
->drcmr_tx
) = DRCMR_MAPVLD
| drv_data
->tx_channel
;
1430 /* Enable SOC clock */
1431 clk_enable(ssp
->clk
);
1433 /* Load default SSP configuration */
1434 write_SSCR0(0, drv_data
->ioaddr
);
1435 write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data
->ioaddr
);
1436 write_SSCR0(SSCR0_SerClkDiv(2)
1438 | SSCR0_DataSize(8),
1440 if (drv_data
->ssp_type
!= PXA25x_SSP
)
1441 write_SSTO(0, drv_data
->ioaddr
);
1442 write_SSPSP(0, drv_data
->ioaddr
);
1444 /* Initial and start queue */
1445 status
= init_queue(drv_data
);
1447 dev_err(&pdev
->dev
, "problem initializing queue\n");
1448 goto out_error_clock_enabled
;
1450 status
= start_queue(drv_data
);
1452 dev_err(&pdev
->dev
, "problem starting queue\n");
1453 goto out_error_clock_enabled
;
1456 /* Register with the SPI framework */
1457 platform_set_drvdata(pdev
, drv_data
);
1458 status
= spi_register_master(master
);
1460 dev_err(&pdev
->dev
, "problem registering spi master\n");
1461 goto out_error_queue_alloc
;
1466 out_error_queue_alloc
:
1467 destroy_queue(drv_data
);
1469 out_error_clock_enabled
:
1470 clk_disable(ssp
->clk
);
1472 out_error_dma_alloc
:
1473 if (drv_data
->tx_channel
!= -1)
1474 pxa_free_dma(drv_data
->tx_channel
);
1475 if (drv_data
->rx_channel
!= -1)
1476 pxa_free_dma(drv_data
->rx_channel
);
1478 out_error_irq_alloc
:
1479 free_irq(ssp
->irq
, drv_data
);
1481 out_error_master_alloc
:
1482 spi_master_put(master
);
1487 static int pxa2xx_spi_remove(struct platform_device
*pdev
)
1489 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1490 struct ssp_device
*ssp
= drv_data
->ssp
;
1496 /* Remove the queue */
1497 status
= destroy_queue(drv_data
);
1499 /* the kernel does not check the return status of this
1500 * this routine (mod->exit, within the kernel). Therefore
1501 * nothing is gained by returning from here, the module is
1502 * going away regardless, and we should not leave any more
1503 * resources allocated than necessary. We cannot free the
1504 * message memory in drv_data->queue, but we can release the
1505 * resources below. I think the kernel should honor -EBUSY
1507 dev_err(&pdev
->dev
, "pxa2xx_spi_remove: workqueue will not "
1508 "complete, message memory not freed\n");
1510 /* Disable the SSP at the peripheral and SOC level */
1511 write_SSCR0(0, drv_data
->ioaddr
);
1512 clk_disable(ssp
->clk
);
1515 if (drv_data
->master_info
->enable_dma
) {
1516 DRCMR(ssp
->drcmr_rx
) = 0;
1517 DRCMR(ssp
->drcmr_tx
) = 0;
1518 pxa_free_dma(drv_data
->tx_channel
);
1519 pxa_free_dma(drv_data
->rx_channel
);
1523 free_irq(ssp
->irq
, drv_data
);
1528 /* Disconnect from the SPI framework */
1529 spi_unregister_master(drv_data
->master
);
1531 /* Prevent double remove */
1532 platform_set_drvdata(pdev
, NULL
);
1537 static void pxa2xx_spi_shutdown(struct platform_device
*pdev
)
1541 if ((status
= pxa2xx_spi_remove(pdev
)) != 0)
1542 dev_err(&pdev
->dev
, "shutdown failed with %d\n", status
);
1547 static int pxa2xx_spi_suspend(struct platform_device
*pdev
, pm_message_t state
)
1549 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1550 struct ssp_device
*ssp
= drv_data
->ssp
;
1553 status
= stop_queue(drv_data
);
1556 write_SSCR0(0, drv_data
->ioaddr
);
1557 clk_disable(ssp
->clk
);
1562 static int pxa2xx_spi_resume(struct platform_device
*pdev
)
1564 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1565 struct ssp_device
*ssp
= drv_data
->ssp
;
1568 /* Enable the SSP clock */
1569 clk_enable(ssp
->clk
);
1571 /* Start the queue running */
1572 status
= start_queue(drv_data
);
1574 dev_err(&pdev
->dev
, "problem starting queue (%d)\n", status
);
1581 #define pxa2xx_spi_suspend NULL
1582 #define pxa2xx_spi_resume NULL
1583 #endif /* CONFIG_PM */
1585 static struct platform_driver driver
= {
1587 .name
= "pxa2xx-spi",
1588 .owner
= THIS_MODULE
,
1590 .remove
= pxa2xx_spi_remove
,
1591 .shutdown
= pxa2xx_spi_shutdown
,
1592 .suspend
= pxa2xx_spi_suspend
,
1593 .resume
= pxa2xx_spi_resume
,
1596 static int __init
pxa2xx_spi_init(void)
1598 return platform_driver_probe(&driver
, pxa2xx_spi_probe
);
1600 module_init(pxa2xx_spi_init
);
1602 static void __exit
pxa2xx_spi_exit(void)
1604 platform_driver_unregister(&driver
);
1606 module_exit(pxa2xx_spi_exit
);