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[libata ahci] error handling fixes
[firewire-audio.git] / drivers / scsi / ahci.c
blobc710a7def7a7fd2024ea18be6ac7cfe31a382624
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.01"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_RX_FIS_SZ = 256,
61 AHCI_CMD_TBL_HDR = 0x80,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
69
70 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
71
72 board_ahci = 0,
73
74 /* global controller registers */
75 HOST_CAP = 0x00, /* host capabilities */
76 HOST_CTL = 0x04, /* global host control */
77 HOST_IRQ_STAT = 0x08, /* interrupt status */
78 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
79 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
80
81 /* HOST_CTL bits */
82 HOST_RESET = (1 << 0), /* reset controller; self-clear */
83 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
84 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
85
86 /* HOST_CAP bits */
87 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
88
89 /* registers for each SATA port */
90 PORT_LST_ADDR = 0x00, /* command list DMA addr */
91 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
92 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
93 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
94 PORT_IRQ_STAT = 0x10, /* interrupt status */
95 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
96 PORT_CMD = 0x18, /* port command */
97 PORT_TFDATA = 0x20, /* taskfile data */
98 PORT_SIG = 0x24, /* device TF signature */
99 PORT_CMD_ISSUE = 0x38, /* command issue */
100 PORT_SCR = 0x28, /* SATA phy register block */
101 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
102 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
103 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
104 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
105
106 /* PORT_IRQ_{STAT,MASK} bits */
107 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
108 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
109 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
110 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
111 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
112 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
113 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
114 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
115
116 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
117 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
118 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
119 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
120 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
121 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
122 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
123 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
124 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
125
126 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
127 PORT_IRQ_HBUS_ERR |
128 PORT_IRQ_HBUS_DATA_ERR |
129 PORT_IRQ_IF_ERR,
130 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
131 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
132 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
133 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
134 PORT_IRQ_D2H_REG_FIS,
135
136 /* PORT_CMD bits */
137 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
138 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
139 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
140 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
141 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
142 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
143 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
144
145 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
146 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
147 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
148
149 /* hpriv->flags bits */
150 AHCI_FLAG_MSI = (1 << 0),
151 };
152
153 struct ahci_cmd_hdr {
154 u32 opts;
155 u32 status;
156 u32 tbl_addr;
157 u32 tbl_addr_hi;
158 u32 reserved[4];
159 };
160
161 struct ahci_sg {
162 u32 addr;
163 u32 addr_hi;
164 u32 reserved;
165 u32 flags_size;
166 };
167
168 struct ahci_host_priv {
169 unsigned long flags;
170 u32 cap; /* cache of HOST_CAP register */
171 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
172 };
173
174 struct ahci_port_priv {
175 struct ahci_cmd_hdr *cmd_slot;
176 dma_addr_t cmd_slot_dma;
177 void *cmd_tbl;
178 dma_addr_t cmd_tbl_dma;
179 struct ahci_sg *cmd_tbl_sg;
180 void *rx_fis;
181 dma_addr_t rx_fis_dma;
182 };
183
184 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
185 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
186 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
187 static int ahci_qc_issue(struct ata_queued_cmd *qc);
188 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
189 static void ahci_phy_reset(struct ata_port *ap);
190 static void ahci_irq_clear(struct ata_port *ap);
191 static void ahci_eng_timeout(struct ata_port *ap);
192 static int ahci_port_start(struct ata_port *ap);
193 static void ahci_port_stop(struct ata_port *ap);
194 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
195 static void ahci_qc_prep(struct ata_queued_cmd *qc);
196 static u8 ahci_check_status(struct ata_port *ap);
197 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
198 static void ahci_remove_one (struct pci_dev *pdev);
199
200 static struct scsi_host_template ahci_sht = {
201 .module = THIS_MODULE,
202 .name = DRV_NAME,
203 .ioctl = ata_scsi_ioctl,
204 .queuecommand = ata_scsi_queuecmd,
205 .eh_strategy_handler = ata_scsi_error,
206 .can_queue = ATA_DEF_QUEUE,
207 .this_id = ATA_SHT_THIS_ID,
208 .sg_tablesize = AHCI_MAX_SG,
209 .max_sectors = ATA_MAX_SECTORS,
210 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
211 .emulated = ATA_SHT_EMULATED,
212 .use_clustering = AHCI_USE_CLUSTERING,
213 .proc_name = DRV_NAME,
214 .dma_boundary = AHCI_DMA_BOUNDARY,
215 .slave_configure = ata_scsi_slave_config,
216 .bios_param = ata_std_bios_param,
217 .ordered_flush = 1,
218 };
219
220 static const struct ata_port_operations ahci_ops = {
221 .port_disable = ata_port_disable,
222
223 .check_status = ahci_check_status,
224 .check_altstatus = ahci_check_status,
225 .dev_select = ata_noop_dev_select,
226
227 .tf_read = ahci_tf_read,
228
229 .phy_reset = ahci_phy_reset,
230
231 .qc_prep = ahci_qc_prep,
232 .qc_issue = ahci_qc_issue,
233
234 .eng_timeout = ahci_eng_timeout,
235
236 .irq_handler = ahci_interrupt,
237 .irq_clear = ahci_irq_clear,
238
239 .scr_read = ahci_scr_read,
240 .scr_write = ahci_scr_write,
241
242 .port_start = ahci_port_start,
243 .port_stop = ahci_port_stop,
244 };
245
246 static struct ata_port_info ahci_port_info[] = {
247 /* board_ahci */
248 {
249 .sht = &ahci_sht,
250 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
251 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
252 ATA_FLAG_PIO_DMA,
253 .pio_mask = 0x1f, /* pio0-4 */
254 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
255 .port_ops = &ahci_ops,
256 },
257 };
258
259 static const struct pci_device_id ahci_pci_tbl[] = {
260 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_ahci }, /* ICH6 */
262 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ICH6M */
264 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ICH7 */
266 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ICH7M */
268 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ICH7R */
270 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ULi M5288 */
272 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_ahci }, /* ESB2 */
274 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
275 board_ahci }, /* ESB2 */
276 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
277 board_ahci }, /* ESB2 */
278 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
279 board_ahci }, /* ICH7-M DH */
280 { } /* terminate list */
281 };
282
283
284 static struct pci_driver ahci_pci_driver = {
285 .name = DRV_NAME,
286 .id_table = ahci_pci_tbl,
287 .probe = ahci_init_one,
288 .remove = ahci_remove_one,
289 };
290
291
292 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
293 {
294 return base + 0x100 + (port * 0x80);
295 }
296
297 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
298 {
299 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
300 }
301
302 static int ahci_port_start(struct ata_port *ap)
303 {
304 struct device *dev = ap->host_set->dev;
305 struct ahci_host_priv *hpriv = ap->host_set->private_data;
306 struct ahci_port_priv *pp;
307 void __iomem *mmio = ap->host_set->mmio_base;
308 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
309 void *mem;
310 dma_addr_t mem_dma;
311 int rc;
312
313 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
314 if (!pp)
315 return -ENOMEM;
316 memset(pp, 0, sizeof(*pp));
317
318 rc = ata_pad_alloc(ap, dev);
319 if (rc) {
320 kfree(pp);
321 return rc;
322 }
323
324 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
325 if (!mem) {
326 ata_pad_free(ap, dev);
327 kfree(pp);
328 return -ENOMEM;
329 }
330 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
331
332 /*
333 * First item in chunk of DMA memory: 32-slot command table,
334 * 32 bytes each in size
335 */
336 pp->cmd_slot = mem;
337 pp->cmd_slot_dma = mem_dma;
338
339 mem += AHCI_CMD_SLOT_SZ;
340 mem_dma += AHCI_CMD_SLOT_SZ;
341
342 /*
343 * Second item: Received-FIS area
344 */
345 pp->rx_fis = mem;
346 pp->rx_fis_dma = mem_dma;
347
348 mem += AHCI_RX_FIS_SZ;
349 mem_dma += AHCI_RX_FIS_SZ;
350
351 /*
352 * Third item: data area for storing a single command
353 * and its scatter-gather table
354 */
355 pp->cmd_tbl = mem;
356 pp->cmd_tbl_dma = mem_dma;
357
358 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
359
360 ap->private_data = pp;
361
362 if (hpriv->cap & HOST_CAP_64)
363 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
364 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
365 readl(port_mmio + PORT_LST_ADDR); /* flush */
366
367 if (hpriv->cap & HOST_CAP_64)
368 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
369 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
370 readl(port_mmio + PORT_FIS_ADDR); /* flush */
371
372 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
373 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
374 PORT_CMD_START, port_mmio + PORT_CMD);
375 readl(port_mmio + PORT_CMD); /* flush */
376
377 return 0;
378 }
379
380
381 static void ahci_port_stop(struct ata_port *ap)
382 {
383 struct device *dev = ap->host_set->dev;
384 struct ahci_port_priv *pp = ap->private_data;
385 void __iomem *mmio = ap->host_set->mmio_base;
386 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
387 u32 tmp;
388
389 tmp = readl(port_mmio + PORT_CMD);
390 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
391 writel(tmp, port_mmio + PORT_CMD);
392 readl(port_mmio + PORT_CMD); /* flush */
393
394 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
395 * this is slightly incorrect.
396 */
397 msleep(500);
398
399 ap->private_data = NULL;
400 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
401 pp->cmd_slot, pp->cmd_slot_dma);
402 ata_pad_free(ap, dev);
403 kfree(pp);
404 }
405
406 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
407 {
408 unsigned int sc_reg;
409
410 switch (sc_reg_in) {
411 case SCR_STATUS: sc_reg = 0; break;
412 case SCR_CONTROL: sc_reg = 1; break;
413 case SCR_ERROR: sc_reg = 2; break;
414 case SCR_ACTIVE: sc_reg = 3; break;
415 default:
416 return 0xffffffffU;
417 }
418
419 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
420 }
421
422
423 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
424 u32 val)
425 {
426 unsigned int sc_reg;
427
428 switch (sc_reg_in) {
429 case SCR_STATUS: sc_reg = 0; break;
430 case SCR_CONTROL: sc_reg = 1; break;
431 case SCR_ERROR: sc_reg = 2; break;
432 case SCR_ACTIVE: sc_reg = 3; break;
433 default:
434 return;
435 }
436
437 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
438 }
439
440 static void ahci_phy_reset(struct ata_port *ap)
441 {
442 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
443 struct ata_taskfile tf;
444 struct ata_device *dev = &ap->device[0];
445 u32 new_tmp, tmp;
446
447 __sata_phy_reset(ap);
448
449 if (ap->flags & ATA_FLAG_PORT_DISABLED)
450 return;
451
452 tmp = readl(port_mmio + PORT_SIG);
453 tf.lbah = (tmp >> 24) & 0xff;
454 tf.lbam = (tmp >> 16) & 0xff;
455 tf.lbal = (tmp >> 8) & 0xff;
456 tf.nsect = (tmp) & 0xff;
457
458 dev->class = ata_dev_classify(&tf);
459 if (!ata_dev_present(dev)) {
460 ata_port_disable(ap);
461 return;
462 }
463
464 /* Make sure port's ATAPI bit is set appropriately */
465 new_tmp = tmp = readl(port_mmio + PORT_CMD);
466 if (dev->class == ATA_DEV_ATAPI)
467 new_tmp |= PORT_CMD_ATAPI;
468 else
469 new_tmp &= ~PORT_CMD_ATAPI;
470 if (new_tmp != tmp) {
471 writel(new_tmp, port_mmio + PORT_CMD);
472 readl(port_mmio + PORT_CMD); /* flush */
473 }
474 }
475
476 static u8 ahci_check_status(struct ata_port *ap)
477 {
478 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
479
480 return readl(mmio + PORT_TFDATA) & 0xFF;
481 }
482
483 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
484 {
485 struct ahci_port_priv *pp = ap->private_data;
486 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
487
488 ata_tf_from_fis(d2h_fis, tf);
489 }
490
491 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
492 {
493 struct ahci_port_priv *pp = qc->ap->private_data;
494 struct scatterlist *sg;
495 struct ahci_sg *ahci_sg;
496 unsigned int n_sg = 0;
497
498 VPRINTK("ENTER\n");
499
500 /*
501 * Next, the S/G list.
502 */
503 ahci_sg = pp->cmd_tbl_sg;
504 ata_for_each_sg(sg, qc) {
505 dma_addr_t addr = sg_dma_address(sg);
506 u32 sg_len = sg_dma_len(sg);
507
508 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
509 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
510 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
511
512 ahci_sg++;
513 n_sg++;
514 }
515
516 return n_sg;
517 }
518
519 static void ahci_qc_prep(struct ata_queued_cmd *qc)
520 {
521 struct ata_port *ap = qc->ap;
522 struct ahci_port_priv *pp = ap->private_data;
523 u32 opts;
524 const u32 cmd_fis_len = 5; /* five dwords */
525 unsigned int n_elem;
526
527 /*
528 * Fill in command slot information (currently only one slot,
529 * slot 0, is currently since we don't do queueing)
530 */
531
532 opts = cmd_fis_len;
533 if (qc->tf.flags & ATA_TFLAG_WRITE)
534 opts |= AHCI_CMD_WRITE;
535 if (is_atapi_taskfile(&qc->tf))
536 opts |= AHCI_CMD_ATAPI;
537
538 pp->cmd_slot[0].opts = cpu_to_le32(opts);
539 pp->cmd_slot[0].status = 0;
540 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
541 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
542
543 /*
544 * Fill in command table information. First, the header,
545 * a SATA Register - Host to Device command FIS.
546 */
547 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
548 if (opts & AHCI_CMD_ATAPI) {
549 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
550 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
551 }
552
553 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
554 return;
555
556 n_elem = ahci_fill_sg(qc);
557
558 pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16);
559 }
560
561 static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
562 {
563 void __iomem *mmio = ap->host_set->mmio_base;
564 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
565 u32 tmp;
566 int work;
567
568 /* stop DMA */
569 tmp = readl(port_mmio + PORT_CMD);
570 tmp &= ~PORT_CMD_START;
571 writel(tmp, port_mmio + PORT_CMD);
572
573 /* wait for engine to stop. TODO: this could be
574 * as long as 500 msec
575 */
576 work = 1000;
577 while (work-- > 0) {
578 tmp = readl(port_mmio + PORT_CMD);
579 if ((tmp & PORT_CMD_LIST_ON) == 0)
580 break;
581 udelay(10);
582 }
583
584 /* clear SATA phy error, if any */
585 tmp = readl(port_mmio + PORT_SCR_ERR);
586 writel(tmp, port_mmio + PORT_SCR_ERR);
587
588 /* if DRQ/BSY is set, device needs to be reset.
589 * if so, issue COMRESET
590 */
591 tmp = readl(port_mmio + PORT_TFDATA);
592 if (tmp & (ATA_BUSY | ATA_DRQ)) {
593 writel(0x301, port_mmio + PORT_SCR_CTL);
594 readl(port_mmio + PORT_SCR_CTL); /* flush */
595 udelay(10);
596 writel(0x300, port_mmio + PORT_SCR_CTL);
597 readl(port_mmio + PORT_SCR_CTL); /* flush */
598 }
599
600 /* re-start DMA */
601 tmp = readl(port_mmio + PORT_CMD);
602 tmp |= PORT_CMD_START;
603 writel(tmp, port_mmio + PORT_CMD);
604 readl(port_mmio + PORT_CMD); /* flush */
605
606 printk(KERN_WARNING "ata%u: error occurred, port reset (%s%s%s%s)\n",
607 ap->id,
608 irq_stat & PORT_IRQ_TF_ERR ? "taskf " : "",
609 irq_stat & PORT_IRQ_HBUS_ERR ? "hbus " : "",
610 irq_stat & PORT_IRQ_HBUS_DATA_ERR ? "hbus_data " : "",
611 irq_stat & PORT_IRQ_IF_ERR ? "if " : "");
612 }
613
614 static void ahci_eng_timeout(struct ata_port *ap)
615 {
616 struct ata_host_set *host_set = ap->host_set;
617 void __iomem *mmio = host_set->mmio_base;
618 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
619 struct ata_queued_cmd *qc;
620 unsigned long flags;
621
622 DPRINTK("ENTER\n");
623
624 spin_lock_irqsave(&host_set->lock, flags);
625
626 qc = ata_qc_from_tag(ap, ap->active_tag);
627 if (!qc) {
628 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
629 ap->id);
630 } else {
631 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
632
633 /* hack alert! We cannot use the supplied completion
634 * function from inside the ->eh_strategy_handler() thread.
635 * libata is the only user of ->eh_strategy_handler() in
636 * any kernel, so the default scsi_done() assumes it is
637 * not being called from the SCSI EH.
638 */
639 qc->scsidone = scsi_finish_command;
640 ata_qc_complete(qc, AC_ERR_OTHER);
641 }
642
643 spin_unlock_irqrestore(&host_set->lock, flags);
644 }
645
646 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
647 {
648 void __iomem *mmio = ap->host_set->mmio_base;
649 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
650 u32 status, serr, ci;
651
652 serr = readl(port_mmio + PORT_SCR_ERR);
653 writel(serr, port_mmio + PORT_SCR_ERR);
654
655 status = readl(port_mmio + PORT_IRQ_STAT);
656 writel(status, port_mmio + PORT_IRQ_STAT);
657
658 ci = readl(port_mmio + PORT_CMD_ISSUE);
659 if (likely((ci & 0x1) == 0)) {
660 if (qc) {
661 ata_qc_complete(qc, 0);
662 qc = NULL;
663 }
664 }
665
666 if (status & PORT_IRQ_FATAL) {
667 unsigned int err_mask;
668 if (status & PORT_IRQ_TF_ERR)
669 err_mask = AC_ERR_DEV;
670 else if (status & PORT_IRQ_IF_ERR)
671 err_mask = AC_ERR_ATA_BUS;
672 else
673 err_mask = AC_ERR_HOST_BUS;
674
675 if (err_mask != AC_ERR_DEV)
676 ahci_intr_error(ap, status);
677 if (qc)
678 ata_qc_complete(qc, err_mask);
679 }
680
681 return 1;
682 }
683
684 static void ahci_irq_clear(struct ata_port *ap)
685 {
686 /* TODO */
687 }
688
689 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
690 {
691 struct ata_host_set *host_set = dev_instance;
692 struct ahci_host_priv *hpriv;
693 unsigned int i, handled = 0;
694 void __iomem *mmio;
695 u32 irq_stat, irq_ack = 0;
696
697 VPRINTK("ENTER\n");
698
699 hpriv = host_set->private_data;
700 mmio = host_set->mmio_base;
701
702 /* sigh. 0xffffffff is a valid return from h/w */
703 irq_stat = readl(mmio + HOST_IRQ_STAT);
704 irq_stat &= hpriv->port_map;
705 if (!irq_stat)
706 return IRQ_NONE;
707
708 spin_lock(&host_set->lock);
709
710 for (i = 0; i < host_set->n_ports; i++) {
711 struct ata_port *ap;
712
713 if (!(irq_stat & (1 << i)))
714 continue;
715
716 ap = host_set->ports[i];
717 if (ap) {
718 struct ata_queued_cmd *qc;
719 qc = ata_qc_from_tag(ap, ap->active_tag);
720 if (!ahci_host_intr(ap, qc))
721 if (ata_ratelimit()) {
722 struct pci_dev *pdev =
723 to_pci_dev(ap->host_set->dev);
724 dev_printk(KERN_WARNING, &pdev->dev,
725 "unhandled interrupt on port %u\n",
726 i);
727 }
728
729 VPRINTK("port %u\n", i);
730 } else {
731 VPRINTK("port %u (no irq)\n", i);
732 if (ata_ratelimit()) {
733 struct pci_dev *pdev =
734 to_pci_dev(ap->host_set->dev);
735 dev_printk(KERN_WARNING, &pdev->dev,
736 "interrupt on disabled port %u\n", i);
737 }
738 }
739
740 irq_ack |= (1 << i);
741 }
742
743 if (irq_ack) {
744 writel(irq_ack, mmio + HOST_IRQ_STAT);
745 handled = 1;
746 }
747
748 spin_unlock(&host_set->lock);
749
750 VPRINTK("EXIT\n");
751
752 return IRQ_RETVAL(handled);
753 }
754
755 static int ahci_qc_issue(struct ata_queued_cmd *qc)
756 {
757 struct ata_port *ap = qc->ap;
758 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
759
760 writel(1, port_mmio + PORT_CMD_ISSUE);
761 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
762
763 return 0;
764 }
765
766 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
767 unsigned int port_idx)
768 {
769 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
770 base = ahci_port_base_ul(base, port_idx);
771 VPRINTK("base now==0x%lx\n", base);
772
773 port->cmd_addr = base;
774 port->scr_addr = base + PORT_SCR;
775
776 VPRINTK("EXIT\n");
777 }
778
779 static int ahci_host_init(struct ata_probe_ent *probe_ent)
780 {
781 struct ahci_host_priv *hpriv = probe_ent->private_data;
782 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
783 void __iomem *mmio = probe_ent->mmio_base;
784 u32 tmp, cap_save;
785 u16 tmp16;
786 unsigned int i, j, using_dac;
787 int rc;
788 void __iomem *port_mmio;
789
790 cap_save = readl(mmio + HOST_CAP);
791 cap_save &= ( (1<<28) | (1<<17) );
792 cap_save |= (1 << 27);
793
794 /* global controller reset */
795 tmp = readl(mmio + HOST_CTL);
796 if ((tmp & HOST_RESET) == 0) {
797 writel(tmp | HOST_RESET, mmio + HOST_CTL);
798 readl(mmio + HOST_CTL); /* flush */
799 }
800
801 /* reset must complete within 1 second, or
802 * the hardware should be considered fried.
803 */
804 ssleep(1);
805
806 tmp = readl(mmio + HOST_CTL);
807 if (tmp & HOST_RESET) {
808 dev_printk(KERN_ERR, &pdev->dev,
809 "controller reset failed (0x%x)\n", tmp);
810 return -EIO;
811 }
812
813 writel(HOST_AHCI_EN, mmio + HOST_CTL);
814 (void) readl(mmio + HOST_CTL); /* flush */
815 writel(cap_save, mmio + HOST_CAP);
816 writel(0xf, mmio + HOST_PORTS_IMPL);
817 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
818
819 pci_read_config_word(pdev, 0x92, &tmp16);
820 tmp16 |= 0xf;
821 pci_write_config_word(pdev, 0x92, tmp16);
822
823 hpriv->cap = readl(mmio + HOST_CAP);
824 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
825 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
826
827 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
828 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
829
830 using_dac = hpriv->cap & HOST_CAP_64;
831 if (using_dac &&
832 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
833 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
834 if (rc) {
835 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
836 if (rc) {
837 dev_printk(KERN_ERR, &pdev->dev,
838 "64-bit DMA enable failed\n");
839 return rc;
840 }
841 }
842 } else {
843 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
844 if (rc) {
845 dev_printk(KERN_ERR, &pdev->dev,
846 "32-bit DMA enable failed\n");
847 return rc;
848 }
849 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
850 if (rc) {
851 dev_printk(KERN_ERR, &pdev->dev,
852 "32-bit consistent DMA enable failed\n");
853 return rc;
854 }
855 }
856
857 for (i = 0; i < probe_ent->n_ports; i++) {
858 #if 0 /* BIOSen initialize this incorrectly */
859 if (!(hpriv->port_map & (1 << i)))
860 continue;
861 #endif
862
863 port_mmio = ahci_port_base(mmio, i);
864 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
865
866 ahci_setup_port(&probe_ent->port[i],
867 (unsigned long) mmio, i);
868
869 /* make sure port is not active */
870 tmp = readl(port_mmio + PORT_CMD);
871 VPRINTK("PORT_CMD 0x%x\n", tmp);
872 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
873 PORT_CMD_FIS_RX | PORT_CMD_START)) {
874 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
875 PORT_CMD_FIS_RX | PORT_CMD_START);
876 writel(tmp, port_mmio + PORT_CMD);
877 readl(port_mmio + PORT_CMD); /* flush */
878
879 /* spec says 500 msecs for each bit, so
880 * this is slightly incorrect.
881 */
882 msleep(500);
883 }
884
885 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
886
887 j = 0;
888 while (j < 100) {
889 msleep(10);
890 tmp = readl(port_mmio + PORT_SCR_STAT);
891 if ((tmp & 0xf) == 0x3)
892 break;
893 j++;
894 }
895
896 tmp = readl(port_mmio + PORT_SCR_ERR);
897 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
898 writel(tmp, port_mmio + PORT_SCR_ERR);
899
900 /* ack any pending irq events for this port */
901 tmp = readl(port_mmio + PORT_IRQ_STAT);
902 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
903 if (tmp)
904 writel(tmp, port_mmio + PORT_IRQ_STAT);
905
906 writel(1 << i, mmio + HOST_IRQ_STAT);
907
908 /* set irq mask (enables interrupts) */
909 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
910 }
911
912 tmp = readl(mmio + HOST_CTL);
913 VPRINTK("HOST_CTL 0x%x\n", tmp);
914 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
915 tmp = readl(mmio + HOST_CTL);
916 VPRINTK("HOST_CTL 0x%x\n", tmp);
917
918 pci_set_master(pdev);
919
920 return 0;
921 }
922
923 static void ahci_print_info(struct ata_probe_ent *probe_ent)
924 {
925 struct ahci_host_priv *hpriv = probe_ent->private_data;
926 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
927 void __iomem *mmio = probe_ent->mmio_base;
928 u32 vers, cap, impl, speed;
929 const char *speed_s;
930 u16 cc;
931 const char *scc_s;
932
933 vers = readl(mmio + HOST_VERSION);
934 cap = hpriv->cap;
935 impl = hpriv->port_map;
936
937 speed = (cap >> 20) & 0xf;
938 if (speed == 1)
939 speed_s = "1.5";
940 else if (speed == 2)
941 speed_s = "3";
942 else
943 speed_s = "?";
944
945 pci_read_config_word(pdev, 0x0a, &cc);
946 if (cc == 0x0101)
947 scc_s = "IDE";
948 else if (cc == 0x0106)
949 scc_s = "SATA";
950 else if (cc == 0x0104)
951 scc_s = "RAID";
952 else
953 scc_s = "unknown";
954
955 dev_printk(KERN_INFO, &pdev->dev,
956 "AHCI %02x%02x.%02x%02x "
957 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
958 ,
959
960 (vers >> 24) & 0xff,
961 (vers >> 16) & 0xff,
962 (vers >> 8) & 0xff,
963 vers & 0xff,
964
965 ((cap >> 8) & 0x1f) + 1,
966 (cap & 0x1f) + 1,
967 speed_s,
968 impl,
969 scc_s);
970
971 dev_printk(KERN_INFO, &pdev->dev,
972 "flags: "
973 "%s%s%s%s%s%s"
974 "%s%s%s%s%s%s%s\n"
975 ,
976
977 cap & (1 << 31) ? "64bit " : "",
978 cap & (1 << 30) ? "ncq " : "",
979 cap & (1 << 28) ? "ilck " : "",
980 cap & (1 << 27) ? "stag " : "",
981 cap & (1 << 26) ? "pm " : "",
982 cap & (1 << 25) ? "led " : "",
983
984 cap & (1 << 24) ? "clo " : "",
985 cap & (1 << 19) ? "nz " : "",
986 cap & (1 << 18) ? "only " : "",
987 cap & (1 << 17) ? "pmp " : "",
988 cap & (1 << 15) ? "pio " : "",
989 cap & (1 << 14) ? "slum " : "",
990 cap & (1 << 13) ? "part " : ""
991 );
992 }
993
994 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
995 {
996 static int printed_version;
997 struct ata_probe_ent *probe_ent = NULL;
998 struct ahci_host_priv *hpriv;
999 unsigned long base;
1000 void __iomem *mmio_base;
1001 unsigned int board_idx = (unsigned int) ent->driver_data;
1002 int have_msi, pci_dev_busy = 0;
1003 int rc;
1004
1005 VPRINTK("ENTER\n");
1006
1007 if (!printed_version++)
1008 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1009
1010 rc = pci_enable_device(pdev);
1011 if (rc)
1012 return rc;
1013
1014 rc = pci_request_regions(pdev, DRV_NAME);
1015 if (rc) {
1016 pci_dev_busy = 1;
1017 goto err_out;
1018 }
1019
1020 if (pci_enable_msi(pdev) == 0)
1021 have_msi = 1;
1022 else {
1023 pci_intx(pdev, 1);
1024 have_msi = 0;
1025 }
1026
1027 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1028 if (probe_ent == NULL) {
1029 rc = -ENOMEM;
1030 goto err_out_msi;
1031 }
1032
1033 memset(probe_ent, 0, sizeof(*probe_ent));
1034 probe_ent->dev = pci_dev_to_dev(pdev);
1035 INIT_LIST_HEAD(&probe_ent->node);
1036
1037 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1038 if (mmio_base == NULL) {
1039 rc = -ENOMEM;
1040 goto err_out_free_ent;
1041 }
1042 base = (unsigned long) mmio_base;
1043
1044 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1045 if (!hpriv) {
1046 rc = -ENOMEM;
1047 goto err_out_iounmap;
1048 }
1049 memset(hpriv, 0, sizeof(*hpriv));
1050
1051 probe_ent->sht = ahci_port_info[board_idx].sht;
1052 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1053 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1054 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1055 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1056
1057 probe_ent->irq = pdev->irq;
1058 probe_ent->irq_flags = SA_SHIRQ;
1059 probe_ent->mmio_base = mmio_base;
1060 probe_ent->private_data = hpriv;
1061
1062 if (have_msi)
1063 hpriv->flags |= AHCI_FLAG_MSI;
1064
1065 /* initialize adapter */
1066 rc = ahci_host_init(probe_ent);
1067 if (rc)
1068 goto err_out_hpriv;
1069
1070 ahci_print_info(probe_ent);
1071
1072 /* FIXME: check ata_device_add return value */
1073 ata_device_add(probe_ent);
1074 kfree(probe_ent);
1075
1076 return 0;
1077
1078 err_out_hpriv:
1079 kfree(hpriv);
1080 err_out_iounmap:
1081 pci_iounmap(pdev, mmio_base);
1082 err_out_free_ent:
1083 kfree(probe_ent);
1084 err_out_msi:
1085 if (have_msi)
1086 pci_disable_msi(pdev);
1087 else
1088 pci_intx(pdev, 0);
1089 pci_release_regions(pdev);
1090 err_out:
1091 if (!pci_dev_busy)
1092 pci_disable_device(pdev);
1093 return rc;
1094 }
1095
1096 static void ahci_remove_one (struct pci_dev *pdev)
1097 {
1098 struct device *dev = pci_dev_to_dev(pdev);
1099 struct ata_host_set *host_set = dev_get_drvdata(dev);
1100 struct ahci_host_priv *hpriv = host_set->private_data;
1101 struct ata_port *ap;
1102 unsigned int i;
1103 int have_msi;
1104
1105 for (i = 0; i < host_set->n_ports; i++) {
1106 ap = host_set->ports[i];
1107
1108 scsi_remove_host(ap->host);
1109 }
1110
1111 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1112 free_irq(host_set->irq, host_set);
1113
1114 for (i = 0; i < host_set->n_ports; i++) {
1115 ap = host_set->ports[i];
1116
1117 ata_scsi_release(ap->host);
1118 scsi_host_put(ap->host);
1119 }
1120
1121 kfree(hpriv);
1122 pci_iounmap(pdev, host_set->mmio_base);
1123 kfree(host_set);
1124
1125 if (have_msi)
1126 pci_disable_msi(pdev);
1127 else
1128 pci_intx(pdev, 0);
1129 pci_release_regions(pdev);
1130 pci_disable_device(pdev);
1131 dev_set_drvdata(dev, NULL);
1132 }
1133
1134 static int __init ahci_init(void)
1135 {
1136 return pci_module_init(&ahci_pci_driver);
1137 }
1138
1139 static void __exit ahci_exit(void)
1140 {
1141 pci_unregister_driver(&ahci_pci_driver);
1142 }
1143
1144
1145 MODULE_AUTHOR("Jeff Garzik");
1146 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1147 MODULE_LICENSE("GPL");
1148 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1149 MODULE_VERSION(DRV_VERSION);
1150
1151 module_init(ahci_init);
1152 module_exit(ahci_exit);
AMDTP streaming driver for the Linux FireWire stack (Juju)