arch/i386/kernel/nmi.c

   1 /*
   2  *  linux/arch/i386/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Mikael Pettersson   : Pentium 4 support for local APIC NMI watchdog.
  12  *  Pavel Machek and
  13  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/mm.h>
  18 #include <linux/delay.h>
  19 #include <linux/bootmem.h>
  20 #include <linux/smp_lock.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/mc146818rtc.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/module.h>
  25 #include <linux/nmi.h>
  26 #include <linux/sysdev.h>
  27 #include <linux/sysctl.h>
  28
  29 #include <asm/smp.h>
  30 #include <asm/div64.h>
  31 #include <asm/nmi.h>
  32
  33 #include "mach_traps.h"
  34
  35 unsigned int nmi_watchdog = NMI_NONE;
  36 extern int unknown_nmi_panic;
  37 static unsigned int nmi_hz = HZ;
  38 static unsigned int nmi_perfctr_msr;    /* the MSR to reset in NMI handler */
  39 static unsigned int nmi_p4_cccr_val;
  40 extern void show_registers(struct pt_regs *regs);
  41
  42 /*
  43  * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
  44  * - it may be reserved by some other driver, or not
  45  * - when not reserved by some other driver, it may be used for
  46  *   the NMI watchdog, or not
  47  *
  48  * This is maintained separately from nmi_active because the NMI
  49  * watchdog may also be driven from the I/O APIC timer.
  50  */
  51 static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
  52 static unsigned int lapic_nmi_owner;
  53 #define LAPIC_NMI_WATCHDOG      (1<<0)
  54 #define LAPIC_NMI_RESERVED      (1<<1)
  55
  56 /* nmi_active:
  57  * +1: the lapic NMI watchdog is active, but can be disabled
  58  *  0: the lapic NMI watchdog has not been set up, and cannot
  59  *     be enabled
  60  * -1: the lapic NMI watchdog is disabled, but can be enabled
  61  */
  62 int nmi_active;
  63
  64 #define K7_EVNTSEL_ENABLE       (1 << 22)
  65 #define K7_EVNTSEL_INT          (1 << 20)
  66 #define K7_EVNTSEL_OS           (1 << 17)
  67 #define K7_EVNTSEL_USR          (1 << 16)
  68 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
  69 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
  70
  71 #define P6_EVNTSEL0_ENABLE      (1 << 22)
  72 #define P6_EVNTSEL_INT          (1 << 20)
  73 #define P6_EVNTSEL_OS           (1 << 17)
  74 #define P6_EVNTSEL_USR          (1 << 16)
  75 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED  0x79
  76 #define P6_NMI_EVENT            P6_EVENT_CPU_CLOCKS_NOT_HALTED
  77
  78 #define MSR_P4_MISC_ENABLE      0x1A0
  79 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
  80 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
  81 #define MSR_P4_PERFCTR0         0x300
  82 #define MSR_P4_CCCR0            0x360
  83 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
  84 #define P4_ESCR_OS              (1<<3)
  85 #define P4_ESCR_USR             (1<<2)
  86 #define P4_CCCR_OVF_PMI0        (1<<26)
  87 #define P4_CCCR_OVF_PMI1        (1<<27)
  88 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
  89 #define P4_CCCR_COMPLEMENT      (1<<19)
  90 #define P4_CCCR_COMPARE         (1<<18)
  91 #define P4_CCCR_REQUIRED        (3<<16)
  92 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
  93 #define P4_CCCR_ENABLE          (1<<12)
  94 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
  95    CRU_ESCR0 (with any non-null event selector) through a complemented
  96    max threshold. [IA32-Vol3, Section 14.9.9] */
  97 #define MSR_P4_IQ_COUNTER0      0x30C
  98 #define P4_NMI_CRU_ESCR0        (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
  99 #define P4_NMI_IQ_CCCR0 \
 100         (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT|     \
 101          P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
 102
 103 static int __init check_nmi_watchdog(void)
 104 {
 105         unsigned int prev_nmi_count[NR_CPUS];
 106         int cpu;
 107
 108         if (nmi_watchdog == NMI_NONE)
 109                 return 0;
 110
 111         printk(KERN_INFO "Testing NMI watchdog ... ");
 112
 113         for (cpu = 0; cpu < NR_CPUS; cpu++)
 114                 prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count;
 115         local_irq_enable();
 116         mdelay((10*1000)/nmi_hz); // wait 10 ticks
 117
 118         for (cpu = 0; cpu < NR_CPUS; cpu++) {
 119 #ifdef CONFIG_SMP
 120                 /* Check cpu_callin_map here because that is set
 121                    after the timer is started. */
 122                 if (!cpu_isset(cpu, cpu_callin_map))
 123                         continue;
 124 #endif
 125                 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
 126                         printk("CPU#%d: NMI appears to be stuck!\n", cpu);
 127                         nmi_active = 0;
 128                         lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
 129                         return -1;
 130                 }
 131         }
 132         printk("OK.\n");
 133
 134         /* now that we know it works we can reduce NMI frequency to
 135            something more reasonable; makes a difference in some configs */
 136         if (nmi_watchdog == NMI_LOCAL_APIC)
 137                 nmi_hz = 1;
 138
 139         return 0;
 140 }
 141 /* This needs to happen later in boot so counters are working */
 142 late_initcall(check_nmi_watchdog);
 143
 144 static int __init setup_nmi_watchdog(char *str)
 145 {
 146         int nmi;
 147
 148         get_option(&str, &nmi);
 149
 150         if (nmi >= NMI_INVALID)
 151                 return 0;
 152         if (nmi == NMI_NONE)
 153                 nmi_watchdog = nmi;
 154         /*
 155          * If any other x86 CPU has a local APIC, then
 156          * please test the NMI stuff there and send me the
 157          * missing bits. Right now Intel P6/P4 and AMD K7 only.
 158          */
 159         if ((nmi == NMI_LOCAL_APIC) &&
 160                         (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
 161                         (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
 162                 nmi_watchdog = nmi;
 163         if ((nmi == NMI_LOCAL_APIC) &&
 164                         (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
 165                         (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
 166                 nmi_watchdog = nmi;
 167         /*
 168          * We can enable the IO-APIC watchdog
 169          * unconditionally.
 170          */
 171         if (nmi == NMI_IO_APIC) {
 172                 nmi_active = 1;
 173                 nmi_watchdog = nmi;
 174         }
 175         return 1;
 176 }
 177
 178 __setup("nmi_watchdog=", setup_nmi_watchdog);
 179
 180 static void disable_lapic_nmi_watchdog(void)
 181 {
 182         if (nmi_active <= 0)
 183                 return;
 184         switch (boot_cpu_data.x86_vendor) {
 185         case X86_VENDOR_AMD:
 186                 wrmsr(MSR_K7_EVNTSEL0, 0, 0);
 187                 break;
 188         case X86_VENDOR_INTEL:
 189                 switch (boot_cpu_data.x86) {
 190                 case 6:
 191                         if (boot_cpu_data.x86_model > 0xd)
 192                                 break;
 193
 194                         wrmsr(MSR_P6_EVNTSEL0, 0, 0);
 195                         break;
 196                 case 15:
 197                         if (boot_cpu_data.x86_model > 0x4)
 198                                 break;
 199
 200                         wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
 201                         wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
 202                         break;
 203                 }
 204                 break;
 205         }
 206         nmi_active = -1;
 207         /* tell do_nmi() and others that we're not active any more */
 208         nmi_watchdog = 0;
 209 }
 210
 211 static void enable_lapic_nmi_watchdog(void)
 212 {
 213         if (nmi_active < 0) {
 214                 nmi_watchdog = NMI_LOCAL_APIC;
 215                 setup_apic_nmi_watchdog();
 216         }
 217 }
 218
 219 int reserve_lapic_nmi(void)
 220 {
 221         unsigned int old_owner;
 222
 223         spin_lock(&lapic_nmi_owner_lock);
 224         old_owner = lapic_nmi_owner;
 225         lapic_nmi_owner |= LAPIC_NMI_RESERVED;
 226         spin_unlock(&lapic_nmi_owner_lock);
 227         if (old_owner & LAPIC_NMI_RESERVED)
 228                 return -EBUSY;
 229         if (old_owner & LAPIC_NMI_WATCHDOG)
 230                 disable_lapic_nmi_watchdog();
 231         return 0;
 232 }
 233
 234 void release_lapic_nmi(void)
 235 {
 236         unsigned int new_owner;
 237
 238         spin_lock(&lapic_nmi_owner_lock);
 239         new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
 240         lapic_nmi_owner = new_owner;
 241         spin_unlock(&lapic_nmi_owner_lock);
 242         if (new_owner & LAPIC_NMI_WATCHDOG)
 243                 enable_lapic_nmi_watchdog();
 244 }
 245
 246 void disable_timer_nmi_watchdog(void)
 247 {
 248         if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
 249                 return;
 250
 251         unset_nmi_callback();
 252         nmi_active = -1;
 253         nmi_watchdog = NMI_NONE;
 254 }
 255
 256 void enable_timer_nmi_watchdog(void)
 257 {
 258         if (nmi_active < 0) {
 259                 nmi_watchdog = NMI_IO_APIC;
 260                 touch_nmi_watchdog();
 261                 nmi_active = 1;
 262         }
 263 }
 264
 265 #ifdef CONFIG_PM
 266
 267 static int nmi_pm_active; /* nmi_active before suspend */
 268
 269 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 270 {
 271         nmi_pm_active = nmi_active;
 272         disable_lapic_nmi_watchdog();
 273         return 0;
 274 }
 275
 276 static int lapic_nmi_resume(struct sys_device *dev)
 277 {
 278         if (nmi_pm_active > 0)
 279                 enable_lapic_nmi_watchdog();
 280         return 0;
 281 }
 282
 283
 284 static struct sysdev_class nmi_sysclass = {
 285         set_kset_name("lapic_nmi"),
 286         .resume         = lapic_nmi_resume,
 287         .suspend        = lapic_nmi_suspend,
 288 };
 289
 290 static struct sys_device device_lapic_nmi = {
 291         .id     = 0,
 292         .cls    = &nmi_sysclass,
 293 };
 294
 295 static int __init init_lapic_nmi_sysfs(void)
 296 {
 297         int error;
 298
 299         if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
 300                 return 0;
 301
 302         error = sysdev_class_register(&nmi_sysclass);
 303         if (!error)
 304                 error = sysdev_register(&device_lapic_nmi);
 305         return error;
 306 }
 307 /* must come after the local APIC's device_initcall() */
 308 late_initcall(init_lapic_nmi_sysfs);
 309
 310 #endif  /* CONFIG_PM */
 311
 312 /*
 313  * Activate the NMI watchdog via the local APIC.
 314  * Original code written by Keith Owens.
 315  */
 316
 317 static void clear_msr_range(unsigned int base, unsigned int n)
 318 {
 319         unsigned int i;
 320
 321         for(i = 0; i < n; ++i)
 322                 wrmsr(base+i, 0, 0);
 323 }
 324
 325 static inline void write_watchdog_counter(const char *descr)
 326 {
 327         u64 count = (u64)cpu_khz * 1000;
 328
 329         do_div(count, nmi_hz);
 330         if(descr)
 331                 Dprintk("setting %s to -0x%08Lx\n", descr, count);
 332         wrmsrl(nmi_perfctr_msr, 0 - count);
 333 }
 334
 335 static void setup_k7_watchdog(void)
 336 {
 337         unsigned int evntsel;
 338
 339         nmi_perfctr_msr = MSR_K7_PERFCTR0;
 340
 341         clear_msr_range(MSR_K7_EVNTSEL0, 4);
 342         clear_msr_range(MSR_K7_PERFCTR0, 4);
 343
 344         evntsel = K7_EVNTSEL_INT
 345                 | K7_EVNTSEL_OS
 346                 | K7_EVNTSEL_USR
 347                 | K7_NMI_EVENT;
 348
 349         wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
 350         write_watchdog_counter("K7_PERFCTR0");
 351         apic_write(APIC_LVTPC, APIC_DM_NMI);
 352         evntsel |= K7_EVNTSEL_ENABLE;
 353         wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
 354 }
 355
 356 static void setup_p6_watchdog(void)
 357 {
 358         unsigned int evntsel;
 359
 360         nmi_perfctr_msr = MSR_P6_PERFCTR0;
 361
 362         clear_msr_range(MSR_P6_EVNTSEL0, 2);
 363         clear_msr_range(MSR_P6_PERFCTR0, 2);
 364
 365         evntsel = P6_EVNTSEL_INT
 366                 | P6_EVNTSEL_OS
 367                 | P6_EVNTSEL_USR
 368                 | P6_NMI_EVENT;
 369
 370         wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
 371         write_watchdog_counter("P6_PERFCTR0");
 372         apic_write(APIC_LVTPC, APIC_DM_NMI);
 373         evntsel |= P6_EVNTSEL0_ENABLE;
 374         wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
 375 }
 376
 377 static int setup_p4_watchdog(void)
 378 {
 379         unsigned int misc_enable, dummy;
 380
 381         rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
 382         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 383                 return 0;
 384
 385         nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
 386         nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
 387 #ifdef CONFIG_SMP
 388         if (smp_num_siblings == 2)
 389                 nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
 390 #endif
 391
 392         if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
 393                 clear_msr_range(0x3F1, 2);
 394         /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
 395            docs doesn't fully define it, so leave it alone for now. */
 396         if (boot_cpu_data.x86_model >= 0x3) {
 397                 /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
 398                 clear_msr_range(0x3A0, 26);
 399                 clear_msr_range(0x3BC, 3);
 400         } else {
 401                 clear_msr_range(0x3A0, 31);
 402         }
 403         clear_msr_range(0x3C0, 6);
 404         clear_msr_range(0x3C8, 6);
 405         clear_msr_range(0x3E0, 2);
 406         clear_msr_range(MSR_P4_CCCR0, 18);
 407         clear_msr_range(MSR_P4_PERFCTR0, 18);
 408
 409         wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
 410         wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
 411         write_watchdog_counter("P4_IQ_COUNTER0");
 412         apic_write(APIC_LVTPC, APIC_DM_NMI);
 413         wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
 414         return 1;
 415 }
 416
 417 void setup_apic_nmi_watchdog (void)
 418 {
 419         switch (boot_cpu_data.x86_vendor) {
 420         case X86_VENDOR_AMD:
 421                 if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
 422                         return;
 423                 setup_k7_watchdog();
 424                 break;
 425         case X86_VENDOR_INTEL:
 426                 switch (boot_cpu_data.x86) {
 427                 case 6:
 428                         if (boot_cpu_data.x86_model > 0xd)
 429                                 return;
 430
 431                         setup_p6_watchdog();
 432                         break;
 433                 case 15:
 434                         if (boot_cpu_data.x86_model > 0x4)
 435                                 return;
 436
 437                         if (!setup_p4_watchdog())
 438                                 return;
 439                         break;
 440                 default:
 441                         return;
 442                 }
 443                 break;
 444         default:
 445                 return;
 446         }
 447         lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
 448         nmi_active = 1;
 449 }
 450
 451 /*
 452  * the best way to detect whether a CPU has a 'hard lockup' problem
 453  * is to check it's local APIC timer IRQ counts. If they are not
 454  * changing then that CPU has some problem.
 455  *
 456  * as these watchdog NMI IRQs are generated on every CPU, we only
 457  * have to check the current processor.
 458  *
 459  * since NMIs don't listen to _any_ locks, we have to be extremely
 460  * careful not to rely on unsafe variables. The printk might lock
 461  * up though, so we have to break up any console locks first ...
 462  * [when there will be more tty-related locks, break them up
 463  *  here too!]
 464  */
 465
 466 static unsigned int
 467         last_irq_sums [NR_CPUS],
 468         alert_counter [NR_CPUS];
 469
 470 void touch_nmi_watchdog (void)
 471 {
 472         int i;
 473
 474         /*
 475          * Just reset the alert counters, (other CPUs might be
 476          * spinning on locks we hold):
 477          */
 478         for (i = 0; i < NR_CPUS; i++)
 479                 alert_counter[i] = 0;
 480
 481         /*
 482          * Tickle the softlockup detector too:
 483          */
 484         touch_softlockup_watchdog();
 485 }
 486
 487 extern void die_nmi(struct pt_regs *, const char *msg);
 488
 489 void nmi_watchdog_tick (struct pt_regs * regs)
 490 {
 491
 492         /*
 493          * Since current_thread_info()-> is always on the stack, and we
 494          * always switch the stack NMI-atomically, it's safe to use
 495          * smp_processor_id().
 496          */
 497         int sum, cpu = smp_processor_id();
 498
 499         sum = per_cpu(irq_stat, cpu).apic_timer_irqs;
 500
 501         if (last_irq_sums[cpu] == sum) {
 502                 /*
 503                  * Ayiee, looks like this CPU is stuck ...
 504                  * wait a few IRQs (5 seconds) before doing the oops ...
 505                  */
 506                 alert_counter[cpu]++;
 507                 if (alert_counter[cpu] == 5*nmi_hz)
 508                         /*
 509                          * die_nmi will return ONLY if NOTIFY_STOP happens..
 510                          */
 511                         die_nmi(regs, "NMI Watchdog detected LOCKUP");
 512
 513                 last_irq_sums[cpu] = sum;
 514                 alert_counter[cpu] = 0;
 515         }
 516         if (nmi_perfctr_msr) {
 517                 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
 518                         /*
 519                          * P4 quirks:
 520                          * - An overflown perfctr will assert its interrupt
 521                          *   until the OVF flag in its CCCR is cleared.
 522                          * - LVTPC is masked on interrupt and must be
 523                          *   unmasked by the LVTPC handler.
 524                          */
 525                         wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
 526                         apic_write(APIC_LVTPC, APIC_DM_NMI);
 527                 }
 528                 else if (nmi_perfctr_msr == MSR_P6_PERFCTR0) {
 529                         /* Only P6 based Pentium M need to re-unmask
 530                          * the apic vector but it doesn't hurt
 531                          * other P6 variant */
 532                         apic_write(APIC_LVTPC, APIC_DM_NMI);
 533                 }
 534                 write_watchdog_counter(NULL);
 535         }
 536 }
 537
 538 #ifdef CONFIG_SYSCTL
 539
 540 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
 541 {
 542         unsigned char reason = get_nmi_reason();
 543         char buf[64];
 544
 545         if (!(reason & 0xc0)) {
 546                 sprintf(buf, "NMI received for unknown reason %02x\n", reason);
 547                 die_nmi(regs, buf);
 548         }
 549         return 0;
 550 }
 551
 552 /*
 553  * proc handler for /proc/sys/kernel/unknown_nmi_panic
 554  */
 555 int proc_unknown_nmi_panic(ctl_table *table, int write, struct file *file,
 556                         void __user *buffer, size_t *length, loff_t *ppos)
 557 {
 558         int old_state;
 559
 560         old_state = unknown_nmi_panic;
 561         proc_dointvec(table, write, file, buffer, length, ppos);
 562         if (!!old_state == !!unknown_nmi_panic)
 563                 return 0;
 564
 565         if (unknown_nmi_panic) {
 566                 if (reserve_lapic_nmi() < 0) {
 567                         unknown_nmi_panic = 0;
 568                         return -EBUSY;
 569                 } else {
 570                         set_nmi_callback(unknown_nmi_panic_callback);
 571                 }
 572         } else {
 573                 release_lapic_nmi();
 574                 unset_nmi_callback();
 575         }
 576         return 0;
 577 }
 578
 579 #endif
 580
 581 EXPORT_SYMBOL(nmi_active);
 582 EXPORT_SYMBOL(nmi_watchdog);
 583 EXPORT_SYMBOL(reserve_lapic_nmi);
 584 EXPORT_SYMBOL(release_lapic_nmi);
 585 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
 586 EXPORT_SYMBOL(enable_timer_nmi_watchdog);