include/asm-mips/jmr3927/tx3927.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2000 Toshiba Corporation
   7  */
   8 #ifndef __ASM_TX3927_H
   9 #define __ASM_TX3927_H
  10
  11 #include <asm/jmr3927/txx927.h>
  12
  13 #define TX3927_SDRAMC_REG       0xfffe8000
  14 #define TX3927_ROMC_REG         0xfffe9000
  15 #define TX3927_DMA_REG          0xfffeb000
  16 #define TX3927_IRC_REG          0xfffec000
  17 #define TX3927_PCIC_REG         0xfffed000
  18 #define TX3927_CCFG_REG         0xfffee000
  19 #define TX3927_NR_TMR   3
  20 #define TX3927_TMR_REG(ch)      (0xfffef000 + (ch) * 0x100)
  21 #define TX3927_NR_SIO   2
  22 #define TX3927_SIO_REG(ch)      (0xfffef300 + (ch) * 0x100)
  23 #define TX3927_PIO_REG          0xfffef500
  24
  25 struct tx3927_sdramc_reg {
  26         volatile unsigned long cr[8];
  27         volatile unsigned long tr[3];
  28         volatile unsigned long cmd;
  29         volatile unsigned long smrs[2];
  30 };
  31
  32 struct tx3927_romc_reg {
  33         volatile unsigned long cr[8];
  34 };
  35
  36 struct tx3927_dma_reg {
  37         struct tx3927_dma_ch_reg {
  38                 volatile unsigned long cha;
  39                 volatile unsigned long sar;
  40                 volatile unsigned long dar;
  41                 volatile unsigned long cntr;
  42                 volatile unsigned long sair;
  43                 volatile unsigned long dair;
  44                 volatile unsigned long ccr;
  45                 volatile unsigned long csr;
  46         } ch[4];
  47         volatile unsigned long dbr[8];
  48         volatile unsigned long tdhr;
  49         volatile unsigned long mcr;
  50         volatile unsigned long unused0;
  51 };
  52
  53 struct tx3927_irc_reg {
  54         volatile unsigned long cer;
  55         volatile unsigned long cr[2];
  56         volatile unsigned long unused0;
  57         volatile unsigned long ilr[8];
  58         volatile unsigned long unused1[4];
  59         volatile unsigned long imr;
  60         volatile unsigned long unused2[7];
  61         volatile unsigned long scr;
  62         volatile unsigned long unused3[7];
  63         volatile unsigned long ssr;
  64         volatile unsigned long unused4[7];
  65         volatile unsigned long csr;
  66 };
  67
  68 #include <asm/byteorder.h>
  69
  70 #ifdef __BIG_ENDIAN
  71 #define endian_def_s2(e1,e2)    \
  72         volatile unsigned short e1,e2
  73 #define endian_def_sb2(e1,e2,e3)        \
  74         volatile unsigned short e1;volatile unsigned char e2,e3
  75 #define endian_def_b2s(e1,e2,e3)        \
  76         volatile unsigned char e1,e2;volatile unsigned short e3
  77 #define endian_def_b4(e1,e2,e3,e4)      \
  78         volatile unsigned char e1,e2,e3,e4
  79 #else
  80 #define endian_def_s2(e1,e2)    \
  81         volatile unsigned short e2,e1
  82 #define endian_def_sb2(e1,e2,e3)        \
  83         volatile unsigned char e3,e2;volatile unsigned short e1
  84 #define endian_def_b2s(e1,e2,e3)        \
  85         volatile unsigned short e3;volatile unsigned char e2,e1
  86 #define endian_def_b4(e1,e2,e3,e4)      \
  87         volatile unsigned char e4,e3,e2,e1
  88 #endif
  89
  90 struct tx3927_pcic_reg {
  91         endian_def_s2(did, vid);
  92         endian_def_s2(pcistat, pcicmd);
  93         endian_def_b4(cc, scc, rpli, rid);
  94         endian_def_b4(unused0, ht, mlt, cls);
  95         volatile unsigned long ioba;            /* +10 */
  96         volatile unsigned long mba;
  97         volatile unsigned long unused1[5];
  98         endian_def_s2(svid, ssvid);
  99         volatile unsigned long unused2;         /* +30 */
 100         endian_def_sb2(unused3, unused4, capptr);
 101         volatile unsigned long unused5;
 102         endian_def_b4(ml, mg, ip, il);
 103         volatile unsigned long unused6;         /* +40 */
 104         volatile unsigned long istat;
 105         volatile unsigned long iim;
 106         volatile unsigned long rrt;
 107         volatile unsigned long unused7[3];              /* +50 */
 108         volatile unsigned long ipbmma;
 109         volatile unsigned long ipbioma;         /* +60 */
 110         volatile unsigned long ilbmma;
 111         volatile unsigned long ilbioma;
 112         volatile unsigned long unused8[9];
 113         volatile unsigned long tc;              /* +90 */
 114         volatile unsigned long tstat;
 115         volatile unsigned long tim;
 116         volatile unsigned long tccmd;
 117         volatile unsigned long pcirrt;          /* +a0 */
 118         volatile unsigned long pcirrt_cmd;
 119         volatile unsigned long pcirrdt;
 120         volatile unsigned long unused9[3];
 121         volatile unsigned long tlboap;
 122         volatile unsigned long tlbiap;
 123         volatile unsigned long tlbmma;          /* +c0 */
 124         volatile unsigned long tlbioma;
 125         volatile unsigned long sc_msg;
 126         volatile unsigned long sc_be;
 127         volatile unsigned long tbl;             /* +d0 */
 128         volatile unsigned long unused10[3];
 129         volatile unsigned long pwmng;           /* +e0 */
 130         volatile unsigned long pwmngs;
 131         volatile unsigned long unused11[6];
 132         volatile unsigned long req_trace;               /* +100 */
 133         volatile unsigned long pbapmc;
 134         volatile unsigned long pbapms;
 135         volatile unsigned long pbapmim;
 136         volatile unsigned long bm;              /* +110 */
 137         volatile unsigned long cpcibrs;
 138         volatile unsigned long cpcibgs;
 139         volatile unsigned long pbacs;
 140         volatile unsigned long iobas;           /* +120 */
 141         volatile unsigned long mbas;
 142         volatile unsigned long lbc;
 143         volatile unsigned long lbstat;
 144         volatile unsigned long lbim;            /* +130 */
 145         volatile unsigned long pcistatim;
 146         volatile unsigned long ica;
 147         volatile unsigned long icd;
 148         volatile unsigned long iiadp;           /* +140 */
 149         volatile unsigned long iscdp;
 150         volatile unsigned long mmas;
 151         volatile unsigned long iomas;
 152         volatile unsigned long ipciaddr;                /* +150 */
 153         volatile unsigned long ipcidata;
 154         volatile unsigned long ipcibe;
 155 };
 156
 157 struct tx3927_ccfg_reg {
 158         volatile unsigned long ccfg;
 159         volatile unsigned long crir;
 160         volatile unsigned long pcfg;
 161         volatile unsigned long tear;
 162         volatile unsigned long pdcr;
 163 };
 164
 165 /*
 166  * SDRAMC
 167  */
 168
 169 /*
 170  * ROMC
 171  */
 172
 173 /*
 174  * DMA
 175  */
 176 /* bits for MCR */
 177 #define TX3927_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
 178 #define TX3927_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
 179 #define TX3927_DMA_MCR_RSFIF    0x00000080
 180 #define TX3927_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
 181 #define TX3927_DMA_MCR_LE       0x00000004
 182 #define TX3927_DMA_MCR_RPRT     0x00000002
 183 #define TX3927_DMA_MCR_MSTEN    0x00000001
 184
 185 /* bits for CCRn */
 186 #define TX3927_DMA_CCR_DBINH    0x04000000
 187 #define TX3927_DMA_CCR_SBINH    0x02000000
 188 #define TX3927_DMA_CCR_CHRST    0x01000000
 189 #define TX3927_DMA_CCR_RVBYTE   0x00800000
 190 #define TX3927_DMA_CCR_ACKPOL   0x00400000
 191 #define TX3927_DMA_CCR_REQPL    0x00200000
 192 #define TX3927_DMA_CCR_EGREQ    0x00100000
 193 #define TX3927_DMA_CCR_CHDN     0x00080000
 194 #define TX3927_DMA_CCR_DNCTL    0x00060000
 195 #define TX3927_DMA_CCR_EXTRQ    0x00010000
 196 #define TX3927_DMA_CCR_INTRQD   0x0000e000
 197 #define TX3927_DMA_CCR_INTENE   0x00001000
 198 #define TX3927_DMA_CCR_INTENC   0x00000800
 199 #define TX3927_DMA_CCR_INTENT   0x00000400
 200 #define TX3927_DMA_CCR_CHNEN    0x00000200
 201 #define TX3927_DMA_CCR_XFACT    0x00000100
 202 #define TX3927_DMA_CCR_SNOP     0x00000080
 203 #define TX3927_DMA_CCR_DSTINC   0x00000040
 204 #define TX3927_DMA_CCR_SRCINC   0x00000020
 205 #define TX3927_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
 206 #define TX3927_DMA_CCR_XFSZ_1W  TX3927_DMA_CCR_XFSZ(2)
 207 #define TX3927_DMA_CCR_XFSZ_4W  TX3927_DMA_CCR_XFSZ(4)
 208 #define TX3927_DMA_CCR_XFSZ_8W  TX3927_DMA_CCR_XFSZ(5)
 209 #define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
 210 #define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
 211 #define TX3927_DMA_CCR_MEMIO    0x00000002
 212 #define TX3927_DMA_CCR_ONEAD    0x00000001
 213
 214 /* bits for CSRn */
 215 #define TX3927_DMA_CSR_CHNACT   0x00000100
 216 #define TX3927_DMA_CSR_ABCHC    0x00000080
 217 #define TX3927_DMA_CSR_NCHNC    0x00000040
 218 #define TX3927_DMA_CSR_NTRNFC   0x00000020
 219 #define TX3927_DMA_CSR_EXTDN    0x00000010
 220 #define TX3927_DMA_CSR_CFERR    0x00000008
 221 #define TX3927_DMA_CSR_CHERR    0x00000004
 222 #define TX3927_DMA_CSR_DESERR   0x00000002
 223 #define TX3927_DMA_CSR_SORERR   0x00000001
 224
 225 /*
 226  * IRC
 227  */
 228 #define TX3927_IR_MAX_LEVEL     7
 229
 230 /* IRCER : Int. Control Enable */
 231 #define TX3927_IRCER_ICE        0x00000001
 232
 233 /* IRCR : Int. Control */
 234 #define TX3927_IRCR_LOW 0x00000000
 235 #define TX3927_IRCR_HIGH        0x00000001
 236 #define TX3927_IRCR_DOWN        0x00000002
 237 #define TX3927_IRCR_UP  0x00000003
 238
 239 /* IRSCR : Int. Status Control */
 240 #define TX3927_IRSCR_EIClrE     0x00000100
 241 #define TX3927_IRSCR_EIClr_MASK 0x0000000f
 242
 243 /* IRCSR : Int. Current Status */
 244 #define TX3927_IRCSR_IF 0x00010000
 245 #define TX3927_IRCSR_ILV_MASK   0x00000700
 246 #define TX3927_IRCSR_IVL_MASK   0x0000001f
 247
 248 #define TX3927_IR_INT0  0
 249 #define TX3927_IR_INT1  1
 250 #define TX3927_IR_INT2  2
 251 #define TX3927_IR_INT3  3
 252 #define TX3927_IR_INT4  4
 253 #define TX3927_IR_INT5  5
 254 #define TX3927_IR_SIO0  6
 255 #define TX3927_IR_SIO1  7
 256 #define TX3927_IR_SIO(ch)       (6 + (ch))
 257 #define TX3927_IR_DMA   8
 258 #define TX3927_IR_PIO   9
 259 #define TX3927_IR_PCI   10
 260 #define TX3927_IR_TMR0  13
 261 #define TX3927_IR_TMR1  14
 262 #define TX3927_IR_TMR2  15
 263 #define TX3927_NUM_IR   16
 264
 265 /*
 266  * PCIC
 267  */
 268 /* bits for PCICMD */
 269 /* see PCI_COMMAND_XXX in linux/pci.h */
 270
 271 /* bits for PCISTAT */
 272 /* see PCI_STATUS_XXX in linux/pci.h */
 273 #define PCI_STATUS_NEW_CAP      0x0010
 274
 275 /* bits for TC */
 276 #define TX3927_PCIC_TC_OF16E    0x00000020
 277 #define TX3927_PCIC_TC_IF8E     0x00000010
 278 #define TX3927_PCIC_TC_OF8E     0x00000008
 279
 280 /* bits for IOBA/MBA */
 281 /* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
 282
 283 /* bits for PBAPMC */
 284 #define TX3927_PCIC_PBAPMC_RPBA 0x00000004
 285 #define TX3927_PCIC_PBAPMC_PBAEN        0x00000002
 286 #define TX3927_PCIC_PBAPMC_BMCEN        0x00000001
 287
 288 /* bits for LBSTAT/LBIM */
 289 #define TX3927_PCIC_LBIM_ALL    0x0000003e
 290
 291 /* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
 292 #define TX3927_PCIC_PCISTATIM_ALL       0x0000f900
 293
 294 /* bits for LBC */
 295 #define TX3927_PCIC_LBC_IBSE    0x00004000
 296 #define TX3927_PCIC_LBC_TIBSE   0x00002000
 297 #define TX3927_PCIC_LBC_TMFBSE  0x00001000
 298 #define TX3927_PCIC_LBC_HRST    0x00000800
 299 #define TX3927_PCIC_LBC_SRST    0x00000400
 300 #define TX3927_PCIC_LBC_EPCAD   0x00000200
 301 #define TX3927_PCIC_LBC_MSDSE   0x00000100
 302 #define TX3927_PCIC_LBC_CRR     0x00000080
 303 #define TX3927_PCIC_LBC_ILMDE   0x00000040
 304 #define TX3927_PCIC_LBC_ILIDE   0x00000020
 305
 306 #define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
 307 #define TX3927_PCIC_MAX_DEVNU   TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
 308
 309 /*
 310  * CCFG
 311  */
 312 /* CCFG : Chip Configuration */
 313 #define TX3927_CCFG_TLBOFF      0x00020000
 314 #define TX3927_CCFG_BEOW        0x00010000
 315 #define TX3927_CCFG_WR  0x00008000
 316 #define TX3927_CCFG_TOE 0x00004000
 317 #define TX3927_CCFG_PCIXARB     0x00002000
 318 #define TX3927_CCFG_PCI3        0x00001000
 319 #define TX3927_CCFG_PSNP        0x00000800
 320 #define TX3927_CCFG_PPRI        0x00000400
 321 #define TX3927_CCFG_PLLM        0x00000030
 322 #define TX3927_CCFG_ENDIAN      0x00000004
 323 #define TX3927_CCFG_HALT        0x00000002
 324 #define TX3927_CCFG_ACEHOLD     0x00000001
 325
 326 /* PCFG : Pin Configuration */
 327 #define TX3927_PCFG_SYSCLKEN    0x08000000
 328 #define TX3927_PCFG_SDRCLKEN_ALL        0x07c00000
 329 #define TX3927_PCFG_SDRCLKEN(ch)        (0x00400000<<(ch))
 330 #define TX3927_PCFG_PCICLKEN_ALL        0x003c0000
 331 #define TX3927_PCFG_PCICLKEN(ch)        (0x00040000<<(ch))
 332 #define TX3927_PCFG_SELALL      0x0003ffff
 333 #define TX3927_PCFG_SELCS       0x00020000
 334 #define TX3927_PCFG_SELDSF      0x00010000
 335 #define TX3927_PCFG_SELSIOC_ALL 0x0000c000
 336 #define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
 337 #define TX3927_PCFG_SELSIO_ALL  0x00003000
 338 #define TX3927_PCFG_SELSIO(ch)  (0x00001000<<(ch))
 339 #define TX3927_PCFG_SELTMR_ALL  0x00000e00
 340 #define TX3927_PCFG_SELTMR(ch)  (0x00000200<<(ch))
 341 #define TX3927_PCFG_SELDONE     0x00000100
 342 #define TX3927_PCFG_INTDMA_ALL  0x000000f0
 343 #define TX3927_PCFG_INTDMA(ch)  (0x00000010<<(ch))
 344 #define TX3927_PCFG_SELDMA_ALL  0x0000000f
 345 #define TX3927_PCFG_SELDMA(ch)  (0x00000001<<(ch))
 346
 347 #define tx3927_sdramcptr        ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
 348 #define tx3927_romcptr          ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
 349 #define tx3927_dmaptr           ((struct tx3927_dma_reg *)TX3927_DMA_REG)
 350 #define tx3927_ircptr           ((struct tx3927_irc_reg *)TX3927_IRC_REG)
 351 #define tx3927_pcicptr          ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
 352 #define tx3927_ccfgptr          ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
 353 #define tx3927_tmrptr(ch)       ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
 354 #define tx3927_sioptr(ch)       ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
 355 #define tx3927_pioptr           ((struct txx927_pio_reg *)TX3927_PIO_REG)
 356
 357 #endif /* __ASM_TX3927_H */