2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (c) 1999, 2000 Silicon Graphics, Inc.
12 #include <linux/compiler.h>
13 #include <linux/irqflags.h>
14 #include <linux/types.h>
15 #include <asm/barrier.h>
17 #include <asm/byteorder.h> /* sigh ... */
18 #include <asm/cpu-features.h>
19 #include <asm/sgidefs.h>
22 #if (_MIPS_SZLONG == 32)
24 #define SZLONG_MASK 31UL
29 #elif (_MIPS_SZLONG == 64)
31 #define SZLONG_MASK 63UL
39 * clear_bit() doesn't provide any barrier for the compiler.
41 #define smp_mb__before_clear_bit() smp_mb()
42 #define smp_mb__after_clear_bit() smp_mb()
45 * set_bit - Atomically set a bit in memory
47 * @addr: the address to start counting from
49 * This function is atomic and may not be reordered. See __set_bit()
50 * if you do not require the atomic guarantees.
51 * Note that @nr may be almost arbitrarily large; this function is not
52 * restricted to acting on a single-word quantity.
54 static inline void set_bit(unsigned long nr
, volatile unsigned long *addr
)
56 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
57 unsigned short bit
= nr
& SZLONG_MASK
;
60 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
63 "1: " __LL
"%0, %1 # set_bit \n"
68 : "=&r" (temp
), "=m" (*m
)
69 : "ir" (1UL << bit
), "m" (*m
));
70 #ifdef CONFIG_CPU_MIPSR2
71 } else if (__builtin_constant_p(bit
)) {
73 "1: " __LL
"%0, %1 # set_bit \n"
74 " " __INS
"%0, %4, %2, 1 \n"
80 : "=&r" (temp
), "=m" (*m
)
81 : "ir" (bit
), "m" (*m
), "r" (~0));
82 #endif /* CONFIG_CPU_MIPSR2 */
83 } else if (cpu_has_llsc
) {
86 "1: " __LL
"%0, %1 # set_bit \n"
94 : "=&r" (temp
), "=m" (*m
)
95 : "ir" (1UL << bit
), "m" (*m
));
97 volatile unsigned long *a
= addr
;
101 a
+= nr
>> SZLONG_LOG
;
103 raw_local_irq_save(flags
);
105 raw_local_irq_restore(flags
);
110 * clear_bit - Clears a bit in memory
112 * @addr: Address to start counting from
114 * clear_bit() is atomic and may not be reordered. However, it does
115 * not contain a memory barrier, so if it is used for locking purposes,
116 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
117 * in order to ensure changes are visible on other processors.
119 static inline void clear_bit(unsigned long nr
, volatile unsigned long *addr
)
121 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
122 unsigned short bit
= nr
& SZLONG_MASK
;
125 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
126 __asm__
__volatile__(
128 "1: " __LL
"%0, %1 # clear_bit \n"
133 : "=&r" (temp
), "=m" (*m
)
134 : "ir" (~(1UL << bit
)), "m" (*m
));
135 #ifdef CONFIG_CPU_MIPSR2
136 } else if (__builtin_constant_p(bit
)) {
137 __asm__
__volatile__(
138 "1: " __LL
"%0, %1 # clear_bit \n"
139 " " __INS
"%0, $0, %2, 1 \n"
145 : "=&r" (temp
), "=m" (*m
)
146 : "ir" (bit
), "m" (*m
));
147 #endif /* CONFIG_CPU_MIPSR2 */
148 } else if (cpu_has_llsc
) {
149 __asm__
__volatile__(
151 "1: " __LL
"%0, %1 # clear_bit \n"
159 : "=&r" (temp
), "=m" (*m
)
160 : "ir" (~(1UL << bit
)), "m" (*m
));
162 volatile unsigned long *a
= addr
;
166 a
+= nr
>> SZLONG_LOG
;
168 raw_local_irq_save(flags
);
170 raw_local_irq_restore(flags
);
175 * change_bit - Toggle a bit in memory
177 * @addr: Address to start counting from
179 * change_bit() is atomic and may not be reordered.
180 * Note that @nr may be almost arbitrarily large; this function is not
181 * restricted to acting on a single-word quantity.
183 static inline void change_bit(unsigned long nr
, volatile unsigned long *addr
)
185 unsigned short bit
= nr
& SZLONG_MASK
;
187 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
188 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
191 __asm__
__volatile__(
193 "1: " __LL
"%0, %1 # change_bit \n"
198 : "=&r" (temp
), "=m" (*m
)
199 : "ir" (1UL << bit
), "m" (*m
));
200 } else if (cpu_has_llsc
) {
201 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
204 __asm__
__volatile__(
206 "1: " __LL
"%0, %1 # change_bit \n"
214 : "=&r" (temp
), "=m" (*m
)
215 : "ir" (1UL << bit
), "m" (*m
));
217 volatile unsigned long *a
= addr
;
221 a
+= nr
>> SZLONG_LOG
;
223 raw_local_irq_save(flags
);
225 raw_local_irq_restore(flags
);
230 * test_and_set_bit - Set a bit and return its old value
232 * @addr: Address to count from
234 * This operation is atomic and cannot be reordered.
235 * It also implies a memory barrier.
237 static inline int test_and_set_bit(unsigned long nr
,
238 volatile unsigned long *addr
)
240 unsigned short bit
= nr
& SZLONG_MASK
;
243 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
244 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
247 __asm__
__volatile__(
249 "1: " __LL
"%0, %1 # test_and_set_bit \n"
255 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
256 : "r" (1UL << bit
), "m" (*m
)
258 } else if (cpu_has_llsc
) {
259 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
262 __asm__
__volatile__(
266 "1: " __LL
"%0, %1 # test_and_set_bit \n"
276 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
277 : "r" (1UL << bit
), "m" (*m
)
280 volatile unsigned long *a
= addr
;
284 a
+= nr
>> SZLONG_LOG
;
286 raw_local_irq_save(flags
);
289 raw_local_irq_restore(flags
);
298 * test_and_clear_bit - Clear a bit and return its old value
300 * @addr: Address to count from
302 * This operation is atomic and cannot be reordered.
303 * It also implies a memory barrier.
305 static inline int test_and_clear_bit(unsigned long nr
,
306 volatile unsigned long *addr
)
308 unsigned short bit
= nr
& SZLONG_MASK
;
311 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
312 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
315 __asm__
__volatile__(
317 "1: " __LL
"%0, %1 # test_and_clear_bit \n"
324 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
325 : "r" (1UL << bit
), "m" (*m
)
327 #ifdef CONFIG_CPU_MIPSR2
328 } else if (__builtin_constant_p(nr
)) {
329 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
332 __asm__
__volatile__(
333 "1: " __LL
"%0, %1 # test_and_clear_bit \n"
334 " " __EXT
"%2, %0, %3, 1 \n"
335 " " __INS
"%0, $0, %3, 1 \n"
341 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
342 : "ri" (bit
), "m" (*m
)
345 } else if (cpu_has_llsc
) {
346 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
349 __asm__
__volatile__(
353 "1: " __LL
"%0, %1 # test_and_clear_bit \n"
364 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
365 : "r" (1UL << bit
), "m" (*m
)
368 volatile unsigned long *a
= addr
;
372 a
+= nr
>> SZLONG_LOG
;
374 raw_local_irq_save(flags
);
377 raw_local_irq_restore(flags
);
386 * test_and_change_bit - Change a bit and return its old value
388 * @addr: Address to count from
390 * This operation is atomic and cannot be reordered.
391 * It also implies a memory barrier.
393 static inline int test_and_change_bit(unsigned long nr
,
394 volatile unsigned long *addr
)
396 unsigned short bit
= nr
& SZLONG_MASK
;
399 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
400 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
403 __asm__
__volatile__(
405 "1: " __LL
"%0, %1 # test_and_change_bit \n"
411 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
412 : "r" (1UL << bit
), "m" (*m
)
414 } else if (cpu_has_llsc
) {
415 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
418 __asm__
__volatile__(
422 "1: " __LL
"%0, %1 # test_and_change_bit \n"
424 " " __SC
"\t%2, %1 \n"
432 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
433 : "r" (1UL << bit
), "m" (*m
)
436 volatile unsigned long *a
= addr
;
440 a
+= nr
>> SZLONG_LOG
;
442 raw_local_irq_save(flags
);
445 raw_local_irq_restore(flags
);
453 #include <asm-generic/bitops/non-atomic.h>
456 * Return the bit position (0..63) of the most significant 1 bit in a word
457 * Returns -1 if no 1 bit exists
459 static inline int __ilog2(unsigned long x
)
463 if (sizeof(x
) == 4) {
475 BUG_ON(sizeof(x
) != 8);
488 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
491 * __ffs - find first bit in word.
492 * @word: The word to search
494 * Returns 0..SZLONG-1
495 * Undefined if no bit exists, so code should check against 0 first.
497 static inline unsigned long __ffs(unsigned long word
)
499 return __ilog2(word
& -word
);
503 * fls - find last bit set.
504 * @word: The word to search
506 * This is defined the same way as ffs.
507 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
509 static inline int fls(int word
)
511 __asm__ ("clz %0, %1" : "=r" (word
) : "r" (word
));
516 #if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64)
517 static inline int fls64(__u64 word
)
519 __asm__ ("dclz %0, %1" : "=r" (word
) : "r" (word
));
524 #include <asm-generic/bitops/fls64.h>
528 * ffs - find first bit set.
529 * @word: The word to search
531 * This is defined the same way as
532 * the libc and compiler builtin ffs routines, therefore
533 * differs in spirit from the above ffz (man ffs).
535 static inline int ffs(int word
)
540 return fls(word
& -word
);
545 #include <asm-generic/bitops/__ffs.h>
546 #include <asm-generic/bitops/ffs.h>
547 #include <asm-generic/bitops/fls.h>
548 #include <asm-generic/bitops/fls64.h>
550 #endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */
552 #include <asm-generic/bitops/ffz.h>
553 #include <asm-generic/bitops/find.h>
557 #include <asm-generic/bitops/sched.h>
558 #include <asm-generic/bitops/hweight.h>
559 #include <asm-generic/bitops/ext2-non-atomic.h>
560 #include <asm-generic/bitops/ext2-atomic.h>
561 #include <asm-generic/bitops/minix.h>
563 #endif /* __KERNEL__ */
565 #endif /* _ASM_BITOPS_H */