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firewire: sbp2: fix stall with "Unsolicited response"
[firewire-audio.git] / drivers / net / forcedeth.c
blob268ea4d566d732b1fd0705898d82dd854eb8be8f
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
42 #define FORCEDETH_VERSION "0.64"
43 #define DRV_NAME "forcedeth"
44
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/sched.h>
53 #include <linux/spinlock.h>
54 #include <linux/ethtool.h>
55 #include <linux/timer.h>
56 #include <linux/skbuff.h>
57 #include <linux/mii.h>
58 #include <linux/random.h>
59 #include <linux/init.h>
60 #include <linux/if_vlan.h>
61 #include <linux/dma-mapping.h>
62 #include <linux/slab.h>
63
64 #include <asm/irq.h>
65 #include <asm/io.h>
66 #include <asm/uaccess.h>
67 #include <asm/system.h>
68
69 #if 0
70 #define dprintk printk
71 #else
72 #define dprintk(x...) do { } while (0)
73 #endif
74
75 #define TX_WORK_PER_LOOP 64
76 #define RX_WORK_PER_LOOP 64
77
78 /*
79 * Hardware access:
80 */
81
82 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
83 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
84 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
85 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
86 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
87 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
88 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
89 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
90 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
91 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
92 #define DEV_HAS_STATISTICS_V2 0x0000600 /* device supports hw statistics version 2 */
93 #define DEV_HAS_STATISTICS_V3 0x0000e00 /* device supports hw statistics version 3 */
94 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
95 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
96 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
97 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
98 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
99 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
100 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
101 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
102 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
103 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
104 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
105 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
106 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
107
108 enum {
109 NvRegIrqStatus = 0x000,
110 #define NVREG_IRQSTAT_MIIEVENT 0x040
111 #define NVREG_IRQSTAT_MASK 0x83ff
112 NvRegIrqMask = 0x004,
113 #define NVREG_IRQ_RX_ERROR 0x0001
114 #define NVREG_IRQ_RX 0x0002
115 #define NVREG_IRQ_RX_NOBUF 0x0004
116 #define NVREG_IRQ_TX_ERR 0x0008
117 #define NVREG_IRQ_TX_OK 0x0010
118 #define NVREG_IRQ_TIMER 0x0020
119 #define NVREG_IRQ_LINK 0x0040
120 #define NVREG_IRQ_RX_FORCED 0x0080
121 #define NVREG_IRQ_TX_FORCED 0x0100
122 #define NVREG_IRQ_RECOVER_ERROR 0x8200
123 #define NVREG_IRQMASK_THROUGHPUT 0x00df
124 #define NVREG_IRQMASK_CPU 0x0060
125 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
126 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
127 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
128
129 NvRegUnknownSetupReg6 = 0x008,
130 #define NVREG_UNKSETUP6_VAL 3
131
132 /*
133 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
134 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
135 */
136 NvRegPollingInterval = 0x00c,
137 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
138 #define NVREG_POLL_DEFAULT_CPU 13
139 NvRegMSIMap0 = 0x020,
140 NvRegMSIMap1 = 0x024,
141 NvRegMSIIrqMask = 0x030,
142 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
143 NvRegMisc1 = 0x080,
144 #define NVREG_MISC1_PAUSE_TX 0x01
145 #define NVREG_MISC1_HD 0x02
146 #define NVREG_MISC1_FORCE 0x3b0f3c
147
148 NvRegMacReset = 0x34,
149 #define NVREG_MAC_RESET_ASSERT 0x0F3
150 NvRegTransmitterControl = 0x084,
151 #define NVREG_XMITCTL_START 0x01
152 #define NVREG_XMITCTL_MGMT_ST 0x40000000
153 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
154 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
155 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
156 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
157 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
158 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
159 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
160 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
161 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
162 #define NVREG_XMITCTL_DATA_START 0x00100000
163 #define NVREG_XMITCTL_DATA_READY 0x00010000
164 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
165 NvRegTransmitterStatus = 0x088,
166 #define NVREG_XMITSTAT_BUSY 0x01
167
168 NvRegPacketFilterFlags = 0x8c,
169 #define NVREG_PFF_PAUSE_RX 0x08
170 #define NVREG_PFF_ALWAYS 0x7F0000
171 #define NVREG_PFF_PROMISC 0x80
172 #define NVREG_PFF_MYADDR 0x20
173 #define NVREG_PFF_LOOPBACK 0x10
174
175 NvRegOffloadConfig = 0x90,
176 #define NVREG_OFFLOAD_HOMEPHY 0x601
177 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
178 NvRegReceiverControl = 0x094,
179 #define NVREG_RCVCTL_START 0x01
180 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
181 NvRegReceiverStatus = 0x98,
182 #define NVREG_RCVSTAT_BUSY 0x01
183
184 NvRegSlotTime = 0x9c,
185 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
186 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
187 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
188 #define NVREG_SLOTTIME_HALF 0x0000ff00
189 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
190 #define NVREG_SLOTTIME_MASK 0x000000ff
191
192 NvRegTxDeferral = 0xA0,
193 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
194 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
195 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
198 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
199 NvRegRxDeferral = 0xA4,
200 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
201 NvRegMacAddrA = 0xA8,
202 NvRegMacAddrB = 0xAC,
203 NvRegMulticastAddrA = 0xB0,
204 #define NVREG_MCASTADDRA_FORCE 0x01
205 NvRegMulticastAddrB = 0xB4,
206 NvRegMulticastMaskA = 0xB8,
207 #define NVREG_MCASTMASKA_NONE 0xffffffff
208 NvRegMulticastMaskB = 0xBC,
209 #define NVREG_MCASTMASKB_NONE 0xffff
210
211 NvRegPhyInterface = 0xC0,
212 #define PHY_RGMII 0x10000000
213 NvRegBackOffControl = 0xC4,
214 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
215 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
216 #define NVREG_BKOFFCTRL_SELECT 24
217 #define NVREG_BKOFFCTRL_GEAR 12
218
219 NvRegTxRingPhysAddr = 0x100,
220 NvRegRxRingPhysAddr = 0x104,
221 NvRegRingSizes = 0x108,
222 #define NVREG_RINGSZ_TXSHIFT 0
223 #define NVREG_RINGSZ_RXSHIFT 16
224 NvRegTransmitPoll = 0x10c,
225 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
226 NvRegLinkSpeed = 0x110,
227 #define NVREG_LINKSPEED_FORCE 0x10000
228 #define NVREG_LINKSPEED_10 1000
229 #define NVREG_LINKSPEED_100 100
230 #define NVREG_LINKSPEED_1000 50
231 #define NVREG_LINKSPEED_MASK (0xFFF)
232 NvRegUnknownSetupReg5 = 0x130,
233 #define NVREG_UNKSETUP5_BIT31 (1<<31)
234 NvRegTxWatermark = 0x13c,
235 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
236 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
237 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
238 NvRegTxRxControl = 0x144,
239 #define NVREG_TXRXCTL_KICK 0x0001
240 #define NVREG_TXRXCTL_BIT1 0x0002
241 #define NVREG_TXRXCTL_BIT2 0x0004
242 #define NVREG_TXRXCTL_IDLE 0x0008
243 #define NVREG_TXRXCTL_RESET 0x0010
244 #define NVREG_TXRXCTL_RXCHECK 0x0400
245 #define NVREG_TXRXCTL_DESC_1 0
246 #define NVREG_TXRXCTL_DESC_2 0x002100
247 #define NVREG_TXRXCTL_DESC_3 0xc02200
248 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
249 #define NVREG_TXRXCTL_VLANINS 0x00080
250 NvRegTxRingPhysAddrHigh = 0x148,
251 NvRegRxRingPhysAddrHigh = 0x14C,
252 NvRegTxPauseFrame = 0x170,
253 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
254 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
255 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
256 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
257 NvRegTxPauseFrameLimit = 0x174,
258 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
259 NvRegMIIStatus = 0x180,
260 #define NVREG_MIISTAT_ERROR 0x0001
261 #define NVREG_MIISTAT_LINKCHANGE 0x0008
262 #define NVREG_MIISTAT_MASK_RW 0x0007
263 #define NVREG_MIISTAT_MASK_ALL 0x000f
264 NvRegMIIMask = 0x184,
265 #define NVREG_MII_LINKCHANGE 0x0008
266
267 NvRegAdapterControl = 0x188,
268 #define NVREG_ADAPTCTL_START 0x02
269 #define NVREG_ADAPTCTL_LINKUP 0x04
270 #define NVREG_ADAPTCTL_PHYVALID 0x40000
271 #define NVREG_ADAPTCTL_RUNNING 0x100000
272 #define NVREG_ADAPTCTL_PHYSHIFT 24
273 NvRegMIISpeed = 0x18c,
274 #define NVREG_MIISPEED_BIT8 (1<<8)
275 #define NVREG_MIIDELAY 5
276 NvRegMIIControl = 0x190,
277 #define NVREG_MIICTL_INUSE 0x08000
278 #define NVREG_MIICTL_WRITE 0x00400
279 #define NVREG_MIICTL_ADDRSHIFT 5
280 NvRegMIIData = 0x194,
281 NvRegTxUnicast = 0x1a0,
282 NvRegTxMulticast = 0x1a4,
283 NvRegTxBroadcast = 0x1a8,
284 NvRegWakeUpFlags = 0x200,
285 #define NVREG_WAKEUPFLAGS_VAL 0x7770
286 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
287 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
288 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
289 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
290 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
291 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
292 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
293 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
294 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
295 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
296
297 NvRegMgmtUnitGetVersion = 0x204,
298 #define NVREG_MGMTUNITGETVERSION 0x01
299 NvRegMgmtUnitVersion = 0x208,
300 #define NVREG_MGMTUNITVERSION 0x08
301 NvRegPowerCap = 0x268,
302 #define NVREG_POWERCAP_D3SUPP (1<<30)
303 #define NVREG_POWERCAP_D2SUPP (1<<26)
304 #define NVREG_POWERCAP_D1SUPP (1<<25)
305 NvRegPowerState = 0x26c,
306 #define NVREG_POWERSTATE_POWEREDUP 0x8000
307 #define NVREG_POWERSTATE_VALID 0x0100
308 #define NVREG_POWERSTATE_MASK 0x0003
309 #define NVREG_POWERSTATE_D0 0x0000
310 #define NVREG_POWERSTATE_D1 0x0001
311 #define NVREG_POWERSTATE_D2 0x0002
312 #define NVREG_POWERSTATE_D3 0x0003
313 NvRegMgmtUnitControl = 0x278,
314 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
315 NvRegTxCnt = 0x280,
316 NvRegTxZeroReXmt = 0x284,
317 NvRegTxOneReXmt = 0x288,
318 NvRegTxManyReXmt = 0x28c,
319 NvRegTxLateCol = 0x290,
320 NvRegTxUnderflow = 0x294,
321 NvRegTxLossCarrier = 0x298,
322 NvRegTxExcessDef = 0x29c,
323 NvRegTxRetryErr = 0x2a0,
324 NvRegRxFrameErr = 0x2a4,
325 NvRegRxExtraByte = 0x2a8,
326 NvRegRxLateCol = 0x2ac,
327 NvRegRxRunt = 0x2b0,
328 NvRegRxFrameTooLong = 0x2b4,
329 NvRegRxOverflow = 0x2b8,
330 NvRegRxFCSErr = 0x2bc,
331 NvRegRxFrameAlignErr = 0x2c0,
332 NvRegRxLenErr = 0x2c4,
333 NvRegRxUnicast = 0x2c8,
334 NvRegRxMulticast = 0x2cc,
335 NvRegRxBroadcast = 0x2d0,
336 NvRegTxDef = 0x2d4,
337 NvRegTxFrame = 0x2d8,
338 NvRegRxCnt = 0x2dc,
339 NvRegTxPause = 0x2e0,
340 NvRegRxPause = 0x2e4,
341 NvRegRxDropFrame = 0x2e8,
342 NvRegVlanControl = 0x300,
343 #define NVREG_VLANCONTROL_ENABLE 0x2000
344 NvRegMSIXMap0 = 0x3e0,
345 NvRegMSIXMap1 = 0x3e4,
346 NvRegMSIXIrqStatus = 0x3f0,
347
348 NvRegPowerState2 = 0x600,
349 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
350 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
351 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
352 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
353 };
354
355 /* Big endian: should work, but is untested */
356 struct ring_desc {
357 __le32 buf;
358 __le32 flaglen;
359 };
360
361 struct ring_desc_ex {
362 __le32 bufhigh;
363 __le32 buflow;
364 __le32 txvlan;
365 __le32 flaglen;
366 };
367
368 union ring_type {
369 struct ring_desc* orig;
370 struct ring_desc_ex* ex;
371 };
372
373 #define FLAG_MASK_V1 0xffff0000
374 #define FLAG_MASK_V2 0xffffc000
375 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
376 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
377
378 #define NV_TX_LASTPACKET (1<<16)
379 #define NV_TX_RETRYERROR (1<<19)
380 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
381 #define NV_TX_FORCED_INTERRUPT (1<<24)
382 #define NV_TX_DEFERRED (1<<26)
383 #define NV_TX_CARRIERLOST (1<<27)
384 #define NV_TX_LATECOLLISION (1<<28)
385 #define NV_TX_UNDERFLOW (1<<29)
386 #define NV_TX_ERROR (1<<30)
387 #define NV_TX_VALID (1<<31)
388
389 #define NV_TX2_LASTPACKET (1<<29)
390 #define NV_TX2_RETRYERROR (1<<18)
391 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
392 #define NV_TX2_FORCED_INTERRUPT (1<<30)
393 #define NV_TX2_DEFERRED (1<<25)
394 #define NV_TX2_CARRIERLOST (1<<26)
395 #define NV_TX2_LATECOLLISION (1<<27)
396 #define NV_TX2_UNDERFLOW (1<<28)
397 /* error and valid are the same for both */
398 #define NV_TX2_ERROR (1<<30)
399 #define NV_TX2_VALID (1<<31)
400 #define NV_TX2_TSO (1<<28)
401 #define NV_TX2_TSO_SHIFT 14
402 #define NV_TX2_TSO_MAX_SHIFT 14
403 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
404 #define NV_TX2_CHECKSUM_L3 (1<<27)
405 #define NV_TX2_CHECKSUM_L4 (1<<26)
406
407 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
408
409 #define NV_RX_DESCRIPTORVALID (1<<16)
410 #define NV_RX_MISSEDFRAME (1<<17)
411 #define NV_RX_SUBSTRACT1 (1<<18)
412 #define NV_RX_ERROR1 (1<<23)
413 #define NV_RX_ERROR2 (1<<24)
414 #define NV_RX_ERROR3 (1<<25)
415 #define NV_RX_ERROR4 (1<<26)
416 #define NV_RX_CRCERR (1<<27)
417 #define NV_RX_OVERFLOW (1<<28)
418 #define NV_RX_FRAMINGERR (1<<29)
419 #define NV_RX_ERROR (1<<30)
420 #define NV_RX_AVAIL (1<<31)
421 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
422
423 #define NV_RX2_CHECKSUMMASK (0x1C000000)
424 #define NV_RX2_CHECKSUM_IP (0x10000000)
425 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
426 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
427 #define NV_RX2_DESCRIPTORVALID (1<<29)
428 #define NV_RX2_SUBSTRACT1 (1<<25)
429 #define NV_RX2_ERROR1 (1<<18)
430 #define NV_RX2_ERROR2 (1<<19)
431 #define NV_RX2_ERROR3 (1<<20)
432 #define NV_RX2_ERROR4 (1<<21)
433 #define NV_RX2_CRCERR (1<<22)
434 #define NV_RX2_OVERFLOW (1<<23)
435 #define NV_RX2_FRAMINGERR (1<<24)
436 /* error and avail are the same for both */
437 #define NV_RX2_ERROR (1<<30)
438 #define NV_RX2_AVAIL (1<<31)
439 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
440
441 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
442 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
443
444 /* Miscelaneous hardware related defines: */
445 #define NV_PCI_REGSZ_VER1 0x270
446 #define NV_PCI_REGSZ_VER2 0x2d4
447 #define NV_PCI_REGSZ_VER3 0x604
448 #define NV_PCI_REGSZ_MAX 0x604
449
450 /* various timeout delays: all in usec */
451 #define NV_TXRX_RESET_DELAY 4
452 #define NV_TXSTOP_DELAY1 10
453 #define NV_TXSTOP_DELAY1MAX 500000
454 #define NV_TXSTOP_DELAY2 100
455 #define NV_RXSTOP_DELAY1 10
456 #define NV_RXSTOP_DELAY1MAX 500000
457 #define NV_RXSTOP_DELAY2 100
458 #define NV_SETUP5_DELAY 5
459 #define NV_SETUP5_DELAYMAX 50000
460 #define NV_POWERUP_DELAY 5
461 #define NV_POWERUP_DELAYMAX 5000
462 #define NV_MIIBUSY_DELAY 50
463 #define NV_MIIPHY_DELAY 10
464 #define NV_MIIPHY_DELAYMAX 10000
465 #define NV_MAC_RESET_DELAY 64
466
467 #define NV_WAKEUPPATTERNS 5
468 #define NV_WAKEUPMASKENTRIES 4
469
470 /* General driver defaults */
471 #define NV_WATCHDOG_TIMEO (5*HZ)
472
473 #define RX_RING_DEFAULT 512
474 #define TX_RING_DEFAULT 256
475 #define RX_RING_MIN 128
476 #define TX_RING_MIN 64
477 #define RING_MAX_DESC_VER_1 1024
478 #define RING_MAX_DESC_VER_2_3 16384
479
480 /* rx/tx mac addr + type + vlan + align + slack*/
481 #define NV_RX_HEADERS (64)
482 /* even more slack. */
483 #define NV_RX_ALLOC_PAD (64)
484
485 /* maximum mtu size */
486 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
487 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
488
489 #define OOM_REFILL (1+HZ/20)
490 #define POLL_WAIT (1+HZ/100)
491 #define LINK_TIMEOUT (3*HZ)
492 #define STATS_INTERVAL (10*HZ)
493
494 /*
495 * desc_ver values:
496 * The nic supports three different descriptor types:
497 * - DESC_VER_1: Original
498 * - DESC_VER_2: support for jumbo frames.
499 * - DESC_VER_3: 64-bit format.
500 */
501 #define DESC_VER_1 1
502 #define DESC_VER_2 2
503 #define DESC_VER_3 3
504
505 /* PHY defines */
506 #define PHY_OUI_MARVELL 0x5043
507 #define PHY_OUI_CICADA 0x03f1
508 #define PHY_OUI_VITESSE 0x01c1
509 #define PHY_OUI_REALTEK 0x0732
510 #define PHY_OUI_REALTEK2 0x0020
511 #define PHYID1_OUI_MASK 0x03ff
512 #define PHYID1_OUI_SHFT 6
513 #define PHYID2_OUI_MASK 0xfc00
514 #define PHYID2_OUI_SHFT 10
515 #define PHYID2_MODEL_MASK 0x03f0
516 #define PHY_MODEL_REALTEK_8211 0x0110
517 #define PHY_REV_MASK 0x0001
518 #define PHY_REV_REALTEK_8211B 0x0000
519 #define PHY_REV_REALTEK_8211C 0x0001
520 #define PHY_MODEL_REALTEK_8201 0x0200
521 #define PHY_MODEL_MARVELL_E3016 0x0220
522 #define PHY_MARVELL_E3016_INITMASK 0x0300
523 #define PHY_CICADA_INIT1 0x0f000
524 #define PHY_CICADA_INIT2 0x0e00
525 #define PHY_CICADA_INIT3 0x01000
526 #define PHY_CICADA_INIT4 0x0200
527 #define PHY_CICADA_INIT5 0x0004
528 #define PHY_CICADA_INIT6 0x02000
529 #define PHY_VITESSE_INIT_REG1 0x1f
530 #define PHY_VITESSE_INIT_REG2 0x10
531 #define PHY_VITESSE_INIT_REG3 0x11
532 #define PHY_VITESSE_INIT_REG4 0x12
533 #define PHY_VITESSE_INIT_MSK1 0xc
534 #define PHY_VITESSE_INIT_MSK2 0x0180
535 #define PHY_VITESSE_INIT1 0x52b5
536 #define PHY_VITESSE_INIT2 0xaf8a
537 #define PHY_VITESSE_INIT3 0x8
538 #define PHY_VITESSE_INIT4 0x8f8a
539 #define PHY_VITESSE_INIT5 0xaf86
540 #define PHY_VITESSE_INIT6 0x8f86
541 #define PHY_VITESSE_INIT7 0xaf82
542 #define PHY_VITESSE_INIT8 0x0100
543 #define PHY_VITESSE_INIT9 0x8f82
544 #define PHY_VITESSE_INIT10 0x0
545 #define PHY_REALTEK_INIT_REG1 0x1f
546 #define PHY_REALTEK_INIT_REG2 0x19
547 #define PHY_REALTEK_INIT_REG3 0x13
548 #define PHY_REALTEK_INIT_REG4 0x14
549 #define PHY_REALTEK_INIT_REG5 0x18
550 #define PHY_REALTEK_INIT_REG6 0x11
551 #define PHY_REALTEK_INIT_REG7 0x01
552 #define PHY_REALTEK_INIT1 0x0000
553 #define PHY_REALTEK_INIT2 0x8e00
554 #define PHY_REALTEK_INIT3 0x0001
555 #define PHY_REALTEK_INIT4 0xad17
556 #define PHY_REALTEK_INIT5 0xfb54
557 #define PHY_REALTEK_INIT6 0xf5c7
558 #define PHY_REALTEK_INIT7 0x1000
559 #define PHY_REALTEK_INIT8 0x0003
560 #define PHY_REALTEK_INIT9 0x0008
561 #define PHY_REALTEK_INIT10 0x0005
562 #define PHY_REALTEK_INIT11 0x0200
563 #define PHY_REALTEK_INIT_MSK1 0x0003
564
565 #define PHY_GIGABIT 0x0100
566
567 #define PHY_TIMEOUT 0x1
568 #define PHY_ERROR 0x2
569
570 #define PHY_100 0x1
571 #define PHY_1000 0x2
572 #define PHY_HALF 0x100
573
574 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
575 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
576 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
577 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
578 #define NV_PAUSEFRAME_RX_REQ 0x0010
579 #define NV_PAUSEFRAME_TX_REQ 0x0020
580 #define NV_PAUSEFRAME_AUTONEG 0x0040
581
582 /* MSI/MSI-X defines */
583 #define NV_MSI_X_MAX_VECTORS 8
584 #define NV_MSI_X_VECTORS_MASK 0x000f
585 #define NV_MSI_CAPABLE 0x0010
586 #define NV_MSI_X_CAPABLE 0x0020
587 #define NV_MSI_ENABLED 0x0040
588 #define NV_MSI_X_ENABLED 0x0080
589
590 #define NV_MSI_X_VECTOR_ALL 0x0
591 #define NV_MSI_X_VECTOR_RX 0x0
592 #define NV_MSI_X_VECTOR_TX 0x1
593 #define NV_MSI_X_VECTOR_OTHER 0x2
594
595 #define NV_MSI_PRIV_OFFSET 0x68
596 #define NV_MSI_PRIV_VALUE 0xffffffff
597
598 #define NV_RESTART_TX 0x1
599 #define NV_RESTART_RX 0x2
600
601 #define NV_TX_LIMIT_COUNT 16
602
603 #define NV_DYNAMIC_THRESHOLD 4
604 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
605
606 /* statistics */
607 struct nv_ethtool_str {
608 char name[ETH_GSTRING_LEN];
609 };
610
611 static const struct nv_ethtool_str nv_estats_str[] = {
612 { "tx_bytes" },
613 { "tx_zero_rexmt" },
614 { "tx_one_rexmt" },
615 { "tx_many_rexmt" },
616 { "tx_late_collision" },
617 { "tx_fifo_errors" },
618 { "tx_carrier_errors" },
619 { "tx_excess_deferral" },
620 { "tx_retry_error" },
621 { "rx_frame_error" },
622 { "rx_extra_byte" },
623 { "rx_late_collision" },
624 { "rx_runt" },
625 { "rx_frame_too_long" },
626 { "rx_over_errors" },
627 { "rx_crc_errors" },
628 { "rx_frame_align_error" },
629 { "rx_length_error" },
630 { "rx_unicast" },
631 { "rx_multicast" },
632 { "rx_broadcast" },
633 { "rx_packets" },
634 { "rx_errors_total" },
635 { "tx_errors_total" },
636
637 /* version 2 stats */
638 { "tx_deferral" },
639 { "tx_packets" },
640 { "rx_bytes" },
641 { "tx_pause" },
642 { "rx_pause" },
643 { "rx_drop_frame" },
644
645 /* version 3 stats */
646 { "tx_unicast" },
647 { "tx_multicast" },
648 { "tx_broadcast" }
649 };
650
651 struct nv_ethtool_stats {
652 u64 tx_bytes;
653 u64 tx_zero_rexmt;
654 u64 tx_one_rexmt;
655 u64 tx_many_rexmt;
656 u64 tx_late_collision;
657 u64 tx_fifo_errors;
658 u64 tx_carrier_errors;
659 u64 tx_excess_deferral;
660 u64 tx_retry_error;
661 u64 rx_frame_error;
662 u64 rx_extra_byte;
663 u64 rx_late_collision;
664 u64 rx_runt;
665 u64 rx_frame_too_long;
666 u64 rx_over_errors;
667 u64 rx_crc_errors;
668 u64 rx_frame_align_error;
669 u64 rx_length_error;
670 u64 rx_unicast;
671 u64 rx_multicast;
672 u64 rx_broadcast;
673 u64 rx_packets;
674 u64 rx_errors_total;
675 u64 tx_errors_total;
676
677 /* version 2 stats */
678 u64 tx_deferral;
679 u64 tx_packets;
680 u64 rx_bytes;
681 u64 tx_pause;
682 u64 rx_pause;
683 u64 rx_drop_frame;
684
685 /* version 3 stats */
686 u64 tx_unicast;
687 u64 tx_multicast;
688 u64 tx_broadcast;
689 };
690
691 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
692 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
693 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
694
695 /* diagnostics */
696 #define NV_TEST_COUNT_BASE 3
697 #define NV_TEST_COUNT_EXTENDED 4
698
699 static const struct nv_ethtool_str nv_etests_str[] = {
700 { "link (online/offline)" },
701 { "register (offline) " },
702 { "interrupt (offline) " },
703 { "loopback (offline) " }
704 };
705
706 struct register_test {
707 __u32 reg;
708 __u32 mask;
709 };
710
711 static const struct register_test nv_registers_test[] = {
712 { NvRegUnknownSetupReg6, 0x01 },
713 { NvRegMisc1, 0x03c },
714 { NvRegOffloadConfig, 0x03ff },
715 { NvRegMulticastAddrA, 0xffffffff },
716 { NvRegTxWatermark, 0x0ff },
717 { NvRegWakeUpFlags, 0x07777 },
718 { 0,0 }
719 };
720
721 struct nv_skb_map {
722 struct sk_buff *skb;
723 dma_addr_t dma;
724 unsigned int dma_len:31;
725 unsigned int dma_single:1;
726 struct ring_desc_ex *first_tx_desc;
727 struct nv_skb_map *next_tx_ctx;
728 };
729
730 /*
731 * SMP locking:
732 * All hardware access under netdev_priv(dev)->lock, except the performance
733 * critical parts:
734 * - rx is (pseudo-) lockless: it relies on the single-threading provided
735 * by the arch code for interrupts.
736 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
737 * needs netdev_priv(dev)->lock :-(
738 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
739 */
740
741 /* in dev: base, irq */
742 struct fe_priv {
743 spinlock_t lock;
744
745 struct net_device *dev;
746 struct napi_struct napi;
747
748 /* General data:
749 * Locking: spin_lock(&np->lock); */
750 struct nv_ethtool_stats estats;
751 int in_shutdown;
752 u32 linkspeed;
753 int duplex;
754 int autoneg;
755 int fixed_mode;
756 int phyaddr;
757 int wolenabled;
758 unsigned int phy_oui;
759 unsigned int phy_model;
760 unsigned int phy_rev;
761 u16 gigabit;
762 int intr_test;
763 int recover_error;
764 int quiet_count;
765
766 /* General data: RO fields */
767 dma_addr_t ring_addr;
768 struct pci_dev *pci_dev;
769 u32 orig_mac[2];
770 u32 events;
771 u32 irqmask;
772 u32 desc_ver;
773 u32 txrxctl_bits;
774 u32 vlanctl_bits;
775 u32 driver_data;
776 u32 device_id;
777 u32 register_size;
778 int rx_csum;
779 u32 mac_in_use;
780 int mgmt_version;
781 int mgmt_sema;
782
783 void __iomem *base;
784
785 /* rx specific fields.
786 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
787 */
788 union ring_type get_rx, put_rx, first_rx, last_rx;
789 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
790 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
791 struct nv_skb_map *rx_skb;
792
793 union ring_type rx_ring;
794 unsigned int rx_buf_sz;
795 unsigned int pkt_limit;
796 struct timer_list oom_kick;
797 struct timer_list nic_poll;
798 struct timer_list stats_poll;
799 u32 nic_poll_irq;
800 int rx_ring_size;
801
802 /* media detection workaround.
803 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
804 */
805 int need_linktimer;
806 unsigned long link_timeout;
807 /*
808 * tx specific fields.
809 */
810 union ring_type get_tx, put_tx, first_tx, last_tx;
811 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
812 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
813 struct nv_skb_map *tx_skb;
814
815 union ring_type tx_ring;
816 u32 tx_flags;
817 int tx_ring_size;
818 int tx_limit;
819 u32 tx_pkts_in_progress;
820 struct nv_skb_map *tx_change_owner;
821 struct nv_skb_map *tx_end_flip;
822 int tx_stop;
823
824 /* vlan fields */
825 struct vlan_group *vlangrp;
826
827 /* msi/msi-x fields */
828 u32 msi_flags;
829 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
830
831 /* flow control */
832 u32 pause_flags;
833
834 /* power saved state */
835 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
836
837 /* for different msi-x irq type */
838 char name_rx[IFNAMSIZ + 3]; /* -rx */
839 char name_tx[IFNAMSIZ + 3]; /* -tx */
840 char name_other[IFNAMSIZ + 6]; /* -other */
841 };
842
843 /*
844 * Maximum number of loops until we assume that a bit in the irq mask
845 * is stuck. Overridable with module param.
846 */
847 static int max_interrupt_work = 4;
848
849 /*
850 * Optimization can be either throuput mode or cpu mode
851 *
852 * Throughput Mode: Every tx and rx packet will generate an interrupt.
853 * CPU Mode: Interrupts are controlled by a timer.
854 */
855 enum {
856 NV_OPTIMIZATION_MODE_THROUGHPUT,
857 NV_OPTIMIZATION_MODE_CPU,
858 NV_OPTIMIZATION_MODE_DYNAMIC
859 };
860 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
861
862 /*
863 * Poll interval for timer irq
864 *
865 * This interval determines how frequent an interrupt is generated.
866 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
867 * Min = 0, and Max = 65535
868 */
869 static int poll_interval = -1;
870
871 /*
872 * MSI interrupts
873 */
874 enum {
875 NV_MSI_INT_DISABLED,
876 NV_MSI_INT_ENABLED
877 };
878 static int msi = NV_MSI_INT_ENABLED;
879
880 /*
881 * MSIX interrupts
882 */
883 enum {
884 NV_MSIX_INT_DISABLED,
885 NV_MSIX_INT_ENABLED
886 };
887 static int msix = NV_MSIX_INT_ENABLED;
888
889 /*
890 * DMA 64bit
891 */
892 enum {
893 NV_DMA_64BIT_DISABLED,
894 NV_DMA_64BIT_ENABLED
895 };
896 static int dma_64bit = NV_DMA_64BIT_ENABLED;
897
898 /*
899 * Crossover Detection
900 * Realtek 8201 phy + some OEM boards do not work properly.
901 */
902 enum {
903 NV_CROSSOVER_DETECTION_DISABLED,
904 NV_CROSSOVER_DETECTION_ENABLED
905 };
906 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
907
908 /*
909 * Power down phy when interface is down (persists through reboot;
910 * older Linux and other OSes may not power it up again)
911 */
912 static int phy_power_down = 0;
913
914 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
915 {
916 return netdev_priv(dev);
917 }
918
919 static inline u8 __iomem *get_hwbase(struct net_device *dev)
920 {
921 return ((struct fe_priv *)netdev_priv(dev))->base;
922 }
923
924 static inline void pci_push(u8 __iomem *base)
925 {
926 /* force out pending posted writes */
927 readl(base);
928 }
929
930 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
931 {
932 return le32_to_cpu(prd->flaglen)
933 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
934 }
935
936 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
937 {
938 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
939 }
940
941 static bool nv_optimized(struct fe_priv *np)
942 {
943 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
944 return false;
945 return true;
946 }
947
948 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
949 int delay, int delaymax, const char *msg)
950 {
951 u8 __iomem *base = get_hwbase(dev);
952
953 pci_push(base);
954 do {
955 udelay(delay);
956 delaymax -= delay;
957 if (delaymax < 0) {
958 if (msg)
959 printk("%s", msg);
960 return 1;
961 }
962 } while ((readl(base + offset) & mask) != target);
963 return 0;
964 }
965
966 #define NV_SETUP_RX_RING 0x01
967 #define NV_SETUP_TX_RING 0x02
968
969 static inline u32 dma_low(dma_addr_t addr)
970 {
971 return addr;
972 }
973
974 static inline u32 dma_high(dma_addr_t addr)
975 {
976 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
977 }
978
979 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
980 {
981 struct fe_priv *np = get_nvpriv(dev);
982 u8 __iomem *base = get_hwbase(dev);
983
984 if (!nv_optimized(np)) {
985 if (rxtx_flags & NV_SETUP_RX_RING) {
986 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
987 }
988 if (rxtx_flags & NV_SETUP_TX_RING) {
989 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
990 }
991 } else {
992 if (rxtx_flags & NV_SETUP_RX_RING) {
993 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
994 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
995 }
996 if (rxtx_flags & NV_SETUP_TX_RING) {
997 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
998 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
999 }
1000 }
1001 }
1002
1003 static void free_rings(struct net_device *dev)
1004 {
1005 struct fe_priv *np = get_nvpriv(dev);
1006
1007 if (!nv_optimized(np)) {
1008 if (np->rx_ring.orig)
1009 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1010 np->rx_ring.orig, np->ring_addr);
1011 } else {
1012 if (np->rx_ring.ex)
1013 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1014 np->rx_ring.ex, np->ring_addr);
1015 }
1016 if (np->rx_skb)
1017 kfree(np->rx_skb);
1018 if (np->tx_skb)
1019 kfree(np->tx_skb);
1020 }
1021
1022 static int using_multi_irqs(struct net_device *dev)
1023 {
1024 struct fe_priv *np = get_nvpriv(dev);
1025
1026 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1027 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1028 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1029 return 0;
1030 else
1031 return 1;
1032 }
1033
1034 static void nv_txrx_gate(struct net_device *dev, bool gate)
1035 {
1036 struct fe_priv *np = get_nvpriv(dev);
1037 u8 __iomem *base = get_hwbase(dev);
1038 u32 powerstate;
1039
1040 if (!np->mac_in_use &&
1041 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1042 powerstate = readl(base + NvRegPowerState2);
1043 if (gate)
1044 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1045 else
1046 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1047 writel(powerstate, base + NvRegPowerState2);
1048 }
1049 }
1050
1051 static void nv_enable_irq(struct net_device *dev)
1052 {
1053 struct fe_priv *np = get_nvpriv(dev);
1054
1055 if (!using_multi_irqs(dev)) {
1056 if (np->msi_flags & NV_MSI_X_ENABLED)
1057 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1058 else
1059 enable_irq(np->pci_dev->irq);
1060 } else {
1061 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1062 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1063 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1064 }
1065 }
1066
1067 static void nv_disable_irq(struct net_device *dev)
1068 {
1069 struct fe_priv *np = get_nvpriv(dev);
1070
1071 if (!using_multi_irqs(dev)) {
1072 if (np->msi_flags & NV_MSI_X_ENABLED)
1073 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1074 else
1075 disable_irq(np->pci_dev->irq);
1076 } else {
1077 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1078 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1079 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1080 }
1081 }
1082
1083 /* In MSIX mode, a write to irqmask behaves as XOR */
1084 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1085 {
1086 u8 __iomem *base = get_hwbase(dev);
1087
1088 writel(mask, base + NvRegIrqMask);
1089 }
1090
1091 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1092 {
1093 struct fe_priv *np = get_nvpriv(dev);
1094 u8 __iomem *base = get_hwbase(dev);
1095
1096 if (np->msi_flags & NV_MSI_X_ENABLED) {
1097 writel(mask, base + NvRegIrqMask);
1098 } else {
1099 if (np->msi_flags & NV_MSI_ENABLED)
1100 writel(0, base + NvRegMSIIrqMask);
1101 writel(0, base + NvRegIrqMask);
1102 }
1103 }
1104
1105 static void nv_napi_enable(struct net_device *dev)
1106 {
1107 struct fe_priv *np = get_nvpriv(dev);
1108
1109 napi_enable(&np->napi);
1110 }
1111
1112 static void nv_napi_disable(struct net_device *dev)
1113 {
1114 struct fe_priv *np = get_nvpriv(dev);
1115
1116 napi_disable(&np->napi);
1117 }
1118
1119 #define MII_READ (-1)
1120 /* mii_rw: read/write a register on the PHY.
1121 *
1122 * Caller must guarantee serialization
1123 */
1124 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1125 {
1126 u8 __iomem *base = get_hwbase(dev);
1127 u32 reg;
1128 int retval;
1129
1130 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1131
1132 reg = readl(base + NvRegMIIControl);
1133 if (reg & NVREG_MIICTL_INUSE) {
1134 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1135 udelay(NV_MIIBUSY_DELAY);
1136 }
1137
1138 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1139 if (value != MII_READ) {
1140 writel(value, base + NvRegMIIData);
1141 reg |= NVREG_MIICTL_WRITE;
1142 }
1143 writel(reg, base + NvRegMIIControl);
1144
1145 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1146 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1147 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1148 dev->name, miireg, addr);
1149 retval = -1;
1150 } else if (value != MII_READ) {
1151 /* it was a write operation - fewer failures are detectable */
1152 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1153 dev->name, value, miireg, addr);
1154 retval = 0;
1155 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1156 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1157 dev->name, miireg, addr);
1158 retval = -1;
1159 } else {
1160 retval = readl(base + NvRegMIIData);
1161 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1162 dev->name, miireg, addr, retval);
1163 }
1164
1165 return retval;
1166 }
1167
1168 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1169 {
1170 struct fe_priv *np = netdev_priv(dev);
1171 u32 miicontrol;
1172 unsigned int tries = 0;
1173
1174 miicontrol = BMCR_RESET | bmcr_setup;
1175 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1176 return -1;
1177 }
1178
1179 /* wait for 500ms */
1180 msleep(500);
1181
1182 /* must wait till reset is deasserted */
1183 while (miicontrol & BMCR_RESET) {
1184 msleep(10);
1185 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1186 /* FIXME: 100 tries seem excessive */
1187 if (tries++ > 100)
1188 return -1;
1189 }
1190 return 0;
1191 }
1192
1193 static int phy_init(struct net_device *dev)
1194 {
1195 struct fe_priv *np = get_nvpriv(dev);
1196 u8 __iomem *base = get_hwbase(dev);
1197 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1198
1199 /* phy errata for E3016 phy */
1200 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1201 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1202 reg &= ~PHY_MARVELL_E3016_INITMASK;
1203 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1204 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1205 return PHY_ERROR;
1206 }
1207 }
1208 if (np->phy_oui == PHY_OUI_REALTEK) {
1209 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1210 np->phy_rev == PHY_REV_REALTEK_8211B) {
1211 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1212 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1213 return PHY_ERROR;
1214 }
1215 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1216 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1217 return PHY_ERROR;
1218 }
1219 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1220 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1221 return PHY_ERROR;
1222 }
1223 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1224 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1225 return PHY_ERROR;
1226 }
1227 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1228 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1229 return PHY_ERROR;
1230 }
1231 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1232 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1233 return PHY_ERROR;
1234 }
1235 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1236 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1237 return PHY_ERROR;
1238 }
1239 }
1240 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1241 np->phy_rev == PHY_REV_REALTEK_8211C) {
1242 u32 powerstate = readl(base + NvRegPowerState2);
1243
1244 /* need to perform hw phy reset */
1245 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1246 writel(powerstate, base + NvRegPowerState2);
1247 msleep(25);
1248
1249 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1250 writel(powerstate, base + NvRegPowerState2);
1251 msleep(25);
1252
1253 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1254 reg |= PHY_REALTEK_INIT9;
1255 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1256 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1257 return PHY_ERROR;
1258 }
1259 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1260 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1261 return PHY_ERROR;
1262 }
1263 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1264 if (!(reg & PHY_REALTEK_INIT11)) {
1265 reg |= PHY_REALTEK_INIT11;
1266 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1267 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1268 return PHY_ERROR;
1269 }
1270 }
1271 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1272 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1273 return PHY_ERROR;
1274 }
1275 }
1276 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1277 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1278 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1279 phy_reserved |= PHY_REALTEK_INIT7;
1280 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1281 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1282 return PHY_ERROR;
1283 }
1284 }
1285 }
1286 }
1287
1288 /* set advertise register */
1289 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1290 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1291 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1292 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1293 return PHY_ERROR;
1294 }
1295
1296 /* get phy interface type */
1297 phyinterface = readl(base + NvRegPhyInterface);
1298
1299 /* see if gigabit phy */
1300 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1301 if (mii_status & PHY_GIGABIT) {
1302 np->gigabit = PHY_GIGABIT;
1303 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1304 mii_control_1000 &= ~ADVERTISE_1000HALF;
1305 if (phyinterface & PHY_RGMII)
1306 mii_control_1000 |= ADVERTISE_1000FULL;
1307 else
1308 mii_control_1000 &= ~ADVERTISE_1000FULL;
1309
1310 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1311 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1312 return PHY_ERROR;
1313 }
1314 }
1315 else
1316 np->gigabit = 0;
1317
1318 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1319 mii_control |= BMCR_ANENABLE;
1320
1321 if (np->phy_oui == PHY_OUI_REALTEK &&
1322 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1323 np->phy_rev == PHY_REV_REALTEK_8211C) {
1324 /* start autoneg since we already performed hw reset above */
1325 mii_control |= BMCR_ANRESTART;
1326 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1327 printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1328 return PHY_ERROR;
1329 }
1330 } else {
1331 /* reset the phy
1332 * (certain phys need bmcr to be setup with reset)
1333 */
1334 if (phy_reset(dev, mii_control)) {
1335 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1336 return PHY_ERROR;
1337 }
1338 }
1339
1340 /* phy vendor specific configuration */
1341 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1342 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1343 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1344 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1345 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1346 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1347 return PHY_ERROR;
1348 }
1349 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1350 phy_reserved |= PHY_CICADA_INIT5;
1351 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1352 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1353 return PHY_ERROR;
1354 }
1355 }
1356 if (np->phy_oui == PHY_OUI_CICADA) {
1357 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1358 phy_reserved |= PHY_CICADA_INIT6;
1359 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1360 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1361 return PHY_ERROR;
1362 }
1363 }
1364 if (np->phy_oui == PHY_OUI_VITESSE) {
1365 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1366 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1367 return PHY_ERROR;
1368 }
1369 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1370 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1371 return PHY_ERROR;
1372 }
1373 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1374 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1375 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1376 return PHY_ERROR;
1377 }
1378 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1379 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1380 phy_reserved |= PHY_VITESSE_INIT3;
1381 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1382 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1383 return PHY_ERROR;
1384 }
1385 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1386 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1387 return PHY_ERROR;
1388 }
1389 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1390 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1391 return PHY_ERROR;
1392 }
1393 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1394 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1395 phy_reserved |= PHY_VITESSE_INIT3;
1396 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1397 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1398 return PHY_ERROR;
1399 }
1400 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1401 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1402 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1403 return PHY_ERROR;
1404 }
1405 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1406 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1407 return PHY_ERROR;
1408 }
1409 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1410 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1411 return PHY_ERROR;
1412 }
1413 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1414 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1415 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1416 return PHY_ERROR;
1417 }
1418 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1419 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1420 phy_reserved |= PHY_VITESSE_INIT8;
1421 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1422 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1423 return PHY_ERROR;
1424 }
1425 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1426 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1427 return PHY_ERROR;
1428 }
1429 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1430 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1431 return PHY_ERROR;
1432 }
1433 }
1434 if (np->phy_oui == PHY_OUI_REALTEK) {
1435 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1436 np->phy_rev == PHY_REV_REALTEK_8211B) {
1437 /* reset could have cleared these out, set them back */
1438 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1439 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1440 return PHY_ERROR;
1441 }
1442 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1443 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1444 return PHY_ERROR;
1445 }
1446 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1447 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1448 return PHY_ERROR;
1449 }
1450 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1451 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1452 return PHY_ERROR;
1453 }
1454 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1455 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1456 return PHY_ERROR;
1457 }
1458 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1459 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1460 return PHY_ERROR;
1461 }
1462 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1463 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1464 return PHY_ERROR;
1465 }
1466 }
1467 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1468 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1469 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1470 phy_reserved |= PHY_REALTEK_INIT7;
1471 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1472 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1473 return PHY_ERROR;
1474 }
1475 }
1476 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1477 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1478 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1479 return PHY_ERROR;
1480 }
1481 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1482 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1483 phy_reserved |= PHY_REALTEK_INIT3;
1484 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1485 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1486 return PHY_ERROR;
1487 }
1488 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1489 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1490 return PHY_ERROR;
1491 }
1492 }
1493 }
1494 }
1495
1496 /* some phys clear out pause advertisment on reset, set it back */
1497 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1498
1499 /* restart auto negotiation, power down phy */
1500 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1501 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1502 if (phy_power_down) {
1503 mii_control |= BMCR_PDOWN;
1504 }
1505 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1506 return PHY_ERROR;
1507 }
1508
1509 return 0;
1510 }
1511
1512 static void nv_start_rx(struct net_device *dev)
1513 {
1514 struct fe_priv *np = netdev_priv(dev);
1515 u8 __iomem *base = get_hwbase(dev);
1516 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1517
1518 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1519 /* Already running? Stop it. */
1520 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1521 rx_ctrl &= ~NVREG_RCVCTL_START;
1522 writel(rx_ctrl, base + NvRegReceiverControl);
1523 pci_push(base);
1524 }
1525 writel(np->linkspeed, base + NvRegLinkSpeed);
1526 pci_push(base);
1527 rx_ctrl |= NVREG_RCVCTL_START;
1528 if (np->mac_in_use)
1529 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1530 writel(rx_ctrl, base + NvRegReceiverControl);
1531 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1532 dev->name, np->duplex, np->linkspeed);
1533 pci_push(base);
1534 }
1535
1536 static void nv_stop_rx(struct net_device *dev)
1537 {
1538 struct fe_priv *np = netdev_priv(dev);
1539 u8 __iomem *base = get_hwbase(dev);
1540 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1541
1542 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1543 if (!np->mac_in_use)
1544 rx_ctrl &= ~NVREG_RCVCTL_START;
1545 else
1546 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1547 writel(rx_ctrl, base + NvRegReceiverControl);
1548 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1549 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1550 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1551
1552 udelay(NV_RXSTOP_DELAY2);
1553 if (!np->mac_in_use)
1554 writel(0, base + NvRegLinkSpeed);
1555 }
1556
1557 static void nv_start_tx(struct net_device *dev)
1558 {
1559 struct fe_priv *np = netdev_priv(dev);
1560 u8 __iomem *base = get_hwbase(dev);
1561 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1562
1563 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1564 tx_ctrl |= NVREG_XMITCTL_START;
1565 if (np->mac_in_use)
1566 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1567 writel(tx_ctrl, base + NvRegTransmitterControl);
1568 pci_push(base);
1569 }
1570
1571 static void nv_stop_tx(struct net_device *dev)
1572 {
1573 struct fe_priv *np = netdev_priv(dev);
1574 u8 __iomem *base = get_hwbase(dev);
1575 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1576
1577 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1578 if (!np->mac_in_use)
1579 tx_ctrl &= ~NVREG_XMITCTL_START;
1580 else
1581 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1582 writel(tx_ctrl, base + NvRegTransmitterControl);
1583 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1584 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1585 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1586
1587 udelay(NV_TXSTOP_DELAY2);
1588 if (!np->mac_in_use)
1589 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1590 base + NvRegTransmitPoll);
1591 }
1592
1593 static void nv_start_rxtx(struct net_device *dev)
1594 {
1595 nv_start_rx(dev);
1596 nv_start_tx(dev);
1597 }
1598
1599 static void nv_stop_rxtx(struct net_device *dev)
1600 {
1601 nv_stop_rx(dev);
1602 nv_stop_tx(dev);
1603 }
1604
1605 static void nv_txrx_reset(struct net_device *dev)
1606 {
1607 struct fe_priv *np = netdev_priv(dev);
1608 u8 __iomem *base = get_hwbase(dev);
1609
1610 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1611 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1612 pci_push(base);
1613 udelay(NV_TXRX_RESET_DELAY);
1614 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1615 pci_push(base);
1616 }
1617
1618 static void nv_mac_reset(struct net_device *dev)
1619 {
1620 struct fe_priv *np = netdev_priv(dev);
1621 u8 __iomem *base = get_hwbase(dev);
1622 u32 temp1, temp2, temp3;
1623
1624 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1625
1626 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1627 pci_push(base);
1628
1629 /* save registers since they will be cleared on reset */
1630 temp1 = readl(base + NvRegMacAddrA);
1631 temp2 = readl(base + NvRegMacAddrB);
1632 temp3 = readl(base + NvRegTransmitPoll);
1633
1634 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1635 pci_push(base);
1636 udelay(NV_MAC_RESET_DELAY);
1637 writel(0, base + NvRegMacReset);
1638 pci_push(base);
1639 udelay(NV_MAC_RESET_DELAY);
1640
1641 /* restore saved registers */
1642 writel(temp1, base + NvRegMacAddrA);
1643 writel(temp2, base + NvRegMacAddrB);
1644 writel(temp3, base + NvRegTransmitPoll);
1645
1646 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1647 pci_push(base);
1648 }
1649
1650 static void nv_get_hw_stats(struct net_device *dev)
1651 {
1652 struct fe_priv *np = netdev_priv(dev);
1653 u8 __iomem *base = get_hwbase(dev);
1654
1655 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1656 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1657 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1658 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1659 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1660 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1661 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1662 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1663 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1664 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1665 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1666 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1667 np->estats.rx_runt += readl(base + NvRegRxRunt);
1668 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1669 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1670 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1671 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1672 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1673 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1674 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1675 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1676 np->estats.rx_packets =
1677 np->estats.rx_unicast +
1678 np->estats.rx_multicast +
1679 np->estats.rx_broadcast;
1680 np->estats.rx_errors_total =
1681 np->estats.rx_crc_errors +
1682 np->estats.rx_over_errors +
1683 np->estats.rx_frame_error +
1684 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1685 np->estats.rx_late_collision +
1686 np->estats.rx_runt +
1687 np->estats.rx_frame_too_long;
1688 np->estats.tx_errors_total =
1689 np->estats.tx_late_collision +
1690 np->estats.tx_fifo_errors +
1691 np->estats.tx_carrier_errors +
1692 np->estats.tx_excess_deferral +
1693 np->estats.tx_retry_error;
1694
1695 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1696 np->estats.tx_deferral += readl(base + NvRegTxDef);
1697 np->estats.tx_packets += readl(base + NvRegTxFrame);
1698 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1699 np->estats.tx_pause += readl(base + NvRegTxPause);
1700 np->estats.rx_pause += readl(base + NvRegRxPause);
1701 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1702 }
1703
1704 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1705 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1706 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1707 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1708 }
1709 }
1710
1711 /*
1712 * nv_get_stats: dev->get_stats function
1713 * Get latest stats value from the nic.
1714 * Called with read_lock(&dev_base_lock) held for read -
1715 * only synchronized against unregister_netdevice.
1716 */
1717 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1718 {
1719 struct fe_priv *np = netdev_priv(dev);
1720
1721 /* If the nic supports hw counters then retrieve latest values */
1722 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1723 nv_get_hw_stats(dev);
1724
1725 /* copy to net_device stats */
1726 dev->stats.tx_bytes = np->estats.tx_bytes;
1727 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1728 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1729 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1730 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1731 dev->stats.rx_errors = np->estats.rx_errors_total;
1732 dev->stats.tx_errors = np->estats.tx_errors_total;
1733 }
1734
1735 return &dev->stats;
1736 }
1737
1738 /*
1739 * nv_alloc_rx: fill rx ring entries.
1740 * Return 1 if the allocations for the skbs failed and the
1741 * rx engine is without Available descriptors
1742 */
1743 static int nv_alloc_rx(struct net_device *dev)
1744 {
1745 struct fe_priv *np = netdev_priv(dev);
1746 struct ring_desc* less_rx;
1747
1748 less_rx = np->get_rx.orig;
1749 if (less_rx-- == np->first_rx.orig)
1750 less_rx = np->last_rx.orig;
1751
1752 while (np->put_rx.orig != less_rx) {
1753 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1754 if (skb) {
1755 np->put_rx_ctx->skb = skb;
1756 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1757 skb->data,
1758 skb_tailroom(skb),
1759 PCI_DMA_FROMDEVICE);
1760 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1761 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1762 wmb();
1763 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1764 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1765 np->put_rx.orig = np->first_rx.orig;
1766 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1767 np->put_rx_ctx = np->first_rx_ctx;
1768 } else {
1769 return 1;
1770 }
1771 }
1772 return 0;
1773 }
1774
1775 static int nv_alloc_rx_optimized(struct net_device *dev)
1776 {
1777 struct fe_priv *np = netdev_priv(dev);
1778 struct ring_desc_ex* less_rx;
1779
1780 less_rx = np->get_rx.ex;
1781 if (less_rx-- == np->first_rx.ex)
1782 less_rx = np->last_rx.ex;
1783
1784 while (np->put_rx.ex != less_rx) {
1785 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1786 if (skb) {
1787 np->put_rx_ctx->skb = skb;
1788 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1789 skb->data,
1790 skb_tailroom(skb),
1791 PCI_DMA_FROMDEVICE);
1792 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1793 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1794 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1795 wmb();
1796 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1797 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1798 np->put_rx.ex = np->first_rx.ex;
1799 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1800 np->put_rx_ctx = np->first_rx_ctx;
1801 } else {
1802 return 1;
1803 }
1804 }
1805 return 0;
1806 }
1807
1808 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1809 static void nv_do_rx_refill(unsigned long data)
1810 {
1811 struct net_device *dev = (struct net_device *) data;
1812 struct fe_priv *np = netdev_priv(dev);
1813
1814 /* Just reschedule NAPI rx processing */
1815 napi_schedule(&np->napi);
1816 }
1817
1818 static void nv_init_rx(struct net_device *dev)
1819 {
1820 struct fe_priv *np = netdev_priv(dev);
1821 int i;
1822
1823 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1824
1825 if (!nv_optimized(np))
1826 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1827 else
1828 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1829 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1830 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1831
1832 for (i = 0; i < np->rx_ring_size; i++) {
1833 if (!nv_optimized(np)) {
1834 np->rx_ring.orig[i].flaglen = 0;
1835 np->rx_ring.orig[i].buf = 0;
1836 } else {
1837 np->rx_ring.ex[i].flaglen = 0;
1838 np->rx_ring.ex[i].txvlan = 0;
1839 np->rx_ring.ex[i].bufhigh = 0;
1840 np->rx_ring.ex[i].buflow = 0;
1841 }
1842 np->rx_skb[i].skb = NULL;
1843 np->rx_skb[i].dma = 0;
1844 }
1845 }
1846
1847 static void nv_init_tx(struct net_device *dev)
1848 {
1849 struct fe_priv *np = netdev_priv(dev);
1850 int i;
1851
1852 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1853
1854 if (!nv_optimized(np))
1855 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1856 else
1857 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1858 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1859 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1860 np->tx_pkts_in_progress = 0;
1861 np->tx_change_owner = NULL;
1862 np->tx_end_flip = NULL;
1863 np->tx_stop = 0;
1864
1865 for (i = 0; i < np->tx_ring_size; i++) {
1866 if (!nv_optimized(np)) {
1867 np->tx_ring.orig[i].flaglen = 0;
1868 np->tx_ring.orig[i].buf = 0;
1869 } else {
1870 np->tx_ring.ex[i].flaglen = 0;
1871 np->tx_ring.ex[i].txvlan = 0;
1872 np->tx_ring.ex[i].bufhigh = 0;
1873 np->tx_ring.ex[i].buflow = 0;
1874 }
1875 np->tx_skb[i].skb = NULL;
1876 np->tx_skb[i].dma = 0;
1877 np->tx_skb[i].dma_len = 0;
1878 np->tx_skb[i].dma_single = 0;
1879 np->tx_skb[i].first_tx_desc = NULL;
1880 np->tx_skb[i].next_tx_ctx = NULL;
1881 }
1882 }
1883
1884 static int nv_init_ring(struct net_device *dev)
1885 {
1886 struct fe_priv *np = netdev_priv(dev);
1887
1888 nv_init_tx(dev);
1889 nv_init_rx(dev);
1890
1891 if (!nv_optimized(np))
1892 return nv_alloc_rx(dev);
1893 else
1894 return nv_alloc_rx_optimized(dev);
1895 }
1896
1897 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1898 {
1899 if (tx_skb->dma) {
1900 if (tx_skb->dma_single)
1901 pci_unmap_single(np->pci_dev, tx_skb->dma,
1902 tx_skb->dma_len,
1903 PCI_DMA_TODEVICE);
1904 else
1905 pci_unmap_page(np->pci_dev, tx_skb->dma,
1906 tx_skb->dma_len,
1907 PCI_DMA_TODEVICE);
1908 tx_skb->dma = 0;
1909 }
1910 }
1911
1912 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1913 {
1914 nv_unmap_txskb(np, tx_skb);
1915 if (tx_skb->skb) {
1916 dev_kfree_skb_any(tx_skb->skb);
1917 tx_skb->skb = NULL;
1918 return 1;
1919 }
1920 return 0;
1921 }
1922
1923 static void nv_drain_tx(struct net_device *dev)
1924 {
1925 struct fe_priv *np = netdev_priv(dev);
1926 unsigned int i;
1927
1928 for (i = 0; i < np->tx_ring_size; i++) {
1929 if (!nv_optimized(np)) {
1930 np->tx_ring.orig[i].flaglen = 0;
1931 np->tx_ring.orig[i].buf = 0;
1932 } else {
1933 np->tx_ring.ex[i].flaglen = 0;
1934 np->tx_ring.ex[i].txvlan = 0;
1935 np->tx_ring.ex[i].bufhigh = 0;
1936 np->tx_ring.ex[i].buflow = 0;
1937 }
1938 if (nv_release_txskb(np, &np->tx_skb[i]))
1939 dev->stats.tx_dropped++;
1940 np->tx_skb[i].dma = 0;
1941 np->tx_skb[i].dma_len = 0;
1942 np->tx_skb[i].dma_single = 0;
1943 np->tx_skb[i].first_tx_desc = NULL;
1944 np->tx_skb[i].next_tx_ctx = NULL;
1945 }
1946 np->tx_pkts_in_progress = 0;
1947 np->tx_change_owner = NULL;
1948 np->tx_end_flip = NULL;
1949 }
1950
1951 static void nv_drain_rx(struct net_device *dev)
1952 {
1953 struct fe_priv *np = netdev_priv(dev);
1954 int i;
1955
1956 for (i = 0; i < np->rx_ring_size; i++) {
1957 if (!nv_optimized(np)) {
1958 np->rx_ring.orig[i].flaglen = 0;
1959 np->rx_ring.orig[i].buf = 0;
1960 } else {
1961 np->rx_ring.ex[i].flaglen = 0;
1962 np->rx_ring.ex[i].txvlan = 0;
1963 np->rx_ring.ex[i].bufhigh = 0;
1964 np->rx_ring.ex[i].buflow = 0;
1965 }
1966 wmb();
1967 if (np->rx_skb[i].skb) {
1968 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1969 (skb_end_pointer(np->rx_skb[i].skb) -
1970 np->rx_skb[i].skb->data),
1971 PCI_DMA_FROMDEVICE);
1972 dev_kfree_skb(np->rx_skb[i].skb);
1973 np->rx_skb[i].skb = NULL;
1974 }
1975 }
1976 }
1977
1978 static void nv_drain_rxtx(struct net_device *dev)
1979 {
1980 nv_drain_tx(dev);
1981 nv_drain_rx(dev);
1982 }
1983
1984 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1985 {
1986 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1987 }
1988
1989 static void nv_legacybackoff_reseed(struct net_device *dev)
1990 {
1991 u8 __iomem *base = get_hwbase(dev);
1992 u32 reg;
1993 u32 low;
1994 int tx_status = 0;
1995
1996 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1997 get_random_bytes(&low, sizeof(low));
1998 reg |= low & NVREG_SLOTTIME_MASK;
1999
2000 /* Need to stop tx before change takes effect.
2001 * Caller has already gained np->lock.
2002 */
2003 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2004 if (tx_status)
2005 nv_stop_tx(dev);
2006 nv_stop_rx(dev);
2007 writel(reg, base + NvRegSlotTime);
2008 if (tx_status)
2009 nv_start_tx(dev);
2010 nv_start_rx(dev);
2011 }
2012
2013 /* Gear Backoff Seeds */
2014 #define BACKOFF_SEEDSET_ROWS 8
2015 #define BACKOFF_SEEDSET_LFSRS 15
2016
2017 /* Known Good seed sets */
2018 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2019 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2020 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2021 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2022 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2023 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2024 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2025 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2026 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2027
2028 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2029 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2030 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2031 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2032 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2033 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2034 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2035 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2036 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2037
2038 static void nv_gear_backoff_reseed(struct net_device *dev)
2039 {
2040 u8 __iomem *base = get_hwbase(dev);
2041 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2042 u32 temp, seedset, combinedSeed;
2043 int i;
2044
2045 /* Setup seed for free running LFSR */
2046 /* We are going to read the time stamp counter 3 times
2047 and swizzle bits around to increase randomness */
2048 get_random_bytes(&miniseed1, sizeof(miniseed1));
2049 miniseed1 &= 0x0fff;
2050 if (miniseed1 == 0)
2051 miniseed1 = 0xabc;
2052
2053 get_random_bytes(&miniseed2, sizeof(miniseed2));
2054 miniseed2 &= 0x0fff;
2055 if (miniseed2 == 0)
2056 miniseed2 = 0xabc;
2057 miniseed2_reversed =
2058 ((miniseed2 & 0xF00) >> 8) |
2059 (miniseed2 & 0x0F0) |
2060 ((miniseed2 & 0x00F) << 8);
2061
2062 get_random_bytes(&miniseed3, sizeof(miniseed3));
2063 miniseed3 &= 0x0fff;
2064 if (miniseed3 == 0)
2065 miniseed3 = 0xabc;
2066 miniseed3_reversed =
2067 ((miniseed3 & 0xF00) >> 8) |
2068 (miniseed3 & 0x0F0) |
2069 ((miniseed3 & 0x00F) << 8);
2070
2071 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2072 (miniseed2 ^ miniseed3_reversed);
2073
2074 /* Seeds can not be zero */
2075 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2076 combinedSeed |= 0x08;
2077 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2078 combinedSeed |= 0x8000;
2079
2080 /* No need to disable tx here */
2081 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2082 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2083 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2084 writel(temp,base + NvRegBackOffControl);
2085
2086 /* Setup seeds for all gear LFSRs. */
2087 get_random_bytes(&seedset, sizeof(seedset));
2088 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2089 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
2090 {
2091 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2092 temp |= main_seedset[seedset][i-1] & 0x3ff;
2093 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2094 writel(temp, base + NvRegBackOffControl);
2095 }
2096 }
2097
2098 /*
2099 * nv_start_xmit: dev->hard_start_xmit function
2100 * Called with netif_tx_lock held.
2101 */
2102 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2103 {
2104 struct fe_priv *np = netdev_priv(dev);
2105 u32 tx_flags = 0;
2106 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2107 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2108 unsigned int i;
2109 u32 offset = 0;
2110 u32 bcnt;
2111 u32 size = skb_headlen(skb);
2112 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2113 u32 empty_slots;
2114 struct ring_desc* put_tx;
2115 struct ring_desc* start_tx;
2116 struct ring_desc* prev_tx;
2117 struct nv_skb_map* prev_tx_ctx;
2118 unsigned long flags;
2119
2120 /* add fragments to entries count */
2121 for (i = 0; i < fragments; i++) {
2122 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2123 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2124 }
2125
2126 spin_lock_irqsave(&np->lock, flags);
2127 empty_slots = nv_get_empty_tx_slots(np);
2128 if (unlikely(empty_slots <= entries)) {
2129 netif_stop_queue(dev);
2130 np->tx_stop = 1;
2131 spin_unlock_irqrestore(&np->lock, flags);
2132 return NETDEV_TX_BUSY;
2133 }
2134 spin_unlock_irqrestore(&np->lock, flags);
2135
2136 start_tx = put_tx = np->put_tx.orig;
2137
2138 /* setup the header buffer */
2139 do {
2140 prev_tx = put_tx;
2141 prev_tx_ctx = np->put_tx_ctx;
2142 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2143 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2144 PCI_DMA_TODEVICE);
2145 np->put_tx_ctx->dma_len = bcnt;
2146 np->put_tx_ctx->dma_single = 1;
2147 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2148 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2149
2150 tx_flags = np->tx_flags;
2151 offset += bcnt;
2152 size -= bcnt;
2153 if (unlikely(put_tx++ == np->last_tx.orig))
2154 put_tx = np->first_tx.orig;
2155 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2156 np->put_tx_ctx = np->first_tx_ctx;
2157 } while (size);
2158
2159 /* setup the fragments */
2160 for (i = 0; i < fragments; i++) {
2161 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2162 u32 size = frag->size;
2163 offset = 0;
2164
2165 do {
2166 prev_tx = put_tx;
2167 prev_tx_ctx = np->put_tx_ctx;
2168 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2169 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2170 PCI_DMA_TODEVICE);
2171 np->put_tx_ctx->dma_len = bcnt;
2172 np->put_tx_ctx->dma_single = 0;
2173 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2174 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2175
2176 offset += bcnt;
2177 size -= bcnt;
2178 if (unlikely(put_tx++ == np->last_tx.orig))
2179 put_tx = np->first_tx.orig;
2180 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2181 np->put_tx_ctx = np->first_tx_ctx;
2182 } while (size);
2183 }
2184
2185 /* set last fragment flag */
2186 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2187
2188 /* save skb in this slot's context area */
2189 prev_tx_ctx->skb = skb;
2190
2191 if (skb_is_gso(skb))
2192 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2193 else
2194 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2195 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2196
2197 spin_lock_irqsave(&np->lock, flags);
2198
2199 /* set tx flags */
2200 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2201 np->put_tx.orig = put_tx;
2202
2203 spin_unlock_irqrestore(&np->lock, flags);
2204
2205 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2206 dev->name, entries, tx_flags_extra);
2207 {
2208 int j;
2209 for (j=0; j<64; j++) {
2210 if ((j%16) == 0)
2211 dprintk("\n%03x:", j);
2212 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2213 }
2214 dprintk("\n");
2215 }
2216
2217 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2218 return NETDEV_TX_OK;
2219 }
2220
2221 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2222 struct net_device *dev)
2223 {
2224 struct fe_priv *np = netdev_priv(dev);
2225 u32 tx_flags = 0;
2226 u32 tx_flags_extra;
2227 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2228 unsigned int i;
2229 u32 offset = 0;
2230 u32 bcnt;
2231 u32 size = skb_headlen(skb);
2232 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2233 u32 empty_slots;
2234 struct ring_desc_ex* put_tx;
2235 struct ring_desc_ex* start_tx;
2236 struct ring_desc_ex* prev_tx;
2237 struct nv_skb_map* prev_tx_ctx;
2238 struct nv_skb_map* start_tx_ctx;
2239 unsigned long flags;
2240
2241 /* add fragments to entries count */
2242 for (i = 0; i < fragments; i++) {
2243 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
2244 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2245 }
2246
2247 spin_lock_irqsave(&np->lock, flags);
2248 empty_slots = nv_get_empty_tx_slots(np);
2249 if (unlikely(empty_slots <= entries)) {
2250 netif_stop_queue(dev);
2251 np->tx_stop = 1;
2252 spin_unlock_irqrestore(&np->lock, flags);
2253 return NETDEV_TX_BUSY;
2254 }
2255 spin_unlock_irqrestore(&np->lock, flags);
2256
2257 start_tx = put_tx = np->put_tx.ex;
2258 start_tx_ctx = np->put_tx_ctx;
2259
2260 /* setup the header buffer */
2261 do {
2262 prev_tx = put_tx;
2263 prev_tx_ctx = np->put_tx_ctx;
2264 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2265 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2266 PCI_DMA_TODEVICE);
2267 np->put_tx_ctx->dma_len = bcnt;
2268 np->put_tx_ctx->dma_single = 1;
2269 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2270 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2271 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2272
2273 tx_flags = NV_TX2_VALID;
2274 offset += bcnt;
2275 size -= bcnt;
2276 if (unlikely(put_tx++ == np->last_tx.ex))
2277 put_tx = np->first_tx.ex;
2278 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2279 np->put_tx_ctx = np->first_tx_ctx;
2280 } while (size);
2281
2282 /* setup the fragments */
2283 for (i = 0; i < fragments; i++) {
2284 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2285 u32 size = frag->size;
2286 offset = 0;
2287
2288 do {
2289 prev_tx = put_tx;
2290 prev_tx_ctx = np->put_tx_ctx;
2291 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2292 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2293 PCI_DMA_TODEVICE);
2294 np->put_tx_ctx->dma_len = bcnt;
2295 np->put_tx_ctx->dma_single = 0;
2296 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2297 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2298 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2299
2300 offset += bcnt;
2301 size -= bcnt;
2302 if (unlikely(put_tx++ == np->last_tx.ex))
2303 put_tx = np->first_tx.ex;
2304 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2305 np->put_tx_ctx = np->first_tx_ctx;
2306 } while (size);
2307 }
2308
2309 /* set last fragment flag */
2310 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2311
2312 /* save skb in this slot's context area */
2313 prev_tx_ctx->skb = skb;
2314
2315 if (skb_is_gso(skb))
2316 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2317 else
2318 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2319 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2320
2321 /* vlan tag */
2322 if (likely(!np->vlangrp)) {
2323 start_tx->txvlan = 0;
2324 } else {
2325 if (vlan_tx_tag_present(skb))
2326 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2327 else
2328 start_tx->txvlan = 0;
2329 }
2330
2331 spin_lock_irqsave(&np->lock, flags);
2332
2333 if (np->tx_limit) {
2334 /* Limit the number of outstanding tx. Setup all fragments, but
2335 * do not set the VALID bit on the first descriptor. Save a pointer
2336 * to that descriptor and also for next skb_map element.
2337 */
2338
2339 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2340 if (!np->tx_change_owner)
2341 np->tx_change_owner = start_tx_ctx;
2342
2343 /* remove VALID bit */
2344 tx_flags &= ~NV_TX2_VALID;
2345 start_tx_ctx->first_tx_desc = start_tx;
2346 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2347 np->tx_end_flip = np->put_tx_ctx;
2348 } else {
2349 np->tx_pkts_in_progress++;
2350 }
2351 }
2352
2353 /* set tx flags */
2354 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2355 np->put_tx.ex = put_tx;
2356
2357 spin_unlock_irqrestore(&np->lock, flags);
2358
2359 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2360 dev->name, entries, tx_flags_extra);
2361 {
2362 int j;
2363 for (j=0; j<64; j++) {
2364 if ((j%16) == 0)
2365 dprintk("\n%03x:", j);
2366 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2367 }
2368 dprintk("\n");
2369 }
2370
2371 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2372 return NETDEV_TX_OK;
2373 }
2374
2375 static inline void nv_tx_flip_ownership(struct net_device *dev)
2376 {
2377 struct fe_priv *np = netdev_priv(dev);
2378
2379 np->tx_pkts_in_progress--;
2380 if (np->tx_change_owner) {
2381 np->tx_change_owner->first_tx_desc->flaglen |=
2382 cpu_to_le32(NV_TX2_VALID);
2383 np->tx_pkts_in_progress++;
2384
2385 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2386 if (np->tx_change_owner == np->tx_end_flip)
2387 np->tx_change_owner = NULL;
2388
2389 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2390 }
2391 }
2392
2393 /*
2394 * nv_tx_done: check for completed packets, release the skbs.
2395 *
2396 * Caller must own np->lock.
2397 */
2398 static int nv_tx_done(struct net_device *dev, int limit)
2399 {
2400 struct fe_priv *np = netdev_priv(dev);
2401 u32 flags;
2402 int tx_work = 0;
2403 struct ring_desc* orig_get_tx = np->get_tx.orig;
2404
2405 while ((np->get_tx.orig != np->put_tx.orig) &&
2406 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2407 (tx_work < limit)) {
2408
2409 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2410 dev->name, flags);
2411
2412 nv_unmap_txskb(np, np->get_tx_ctx);
2413
2414 if (np->desc_ver == DESC_VER_1) {
2415 if (flags & NV_TX_LASTPACKET) {
2416 if (flags & NV_TX_ERROR) {
2417 if (flags & NV_TX_UNDERFLOW)
2418 dev->stats.tx_fifo_errors++;
2419 if (flags & NV_TX_CARRIERLOST)
2420 dev->stats.tx_carrier_errors++;
2421 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2422 nv_legacybackoff_reseed(dev);
2423 dev->stats.tx_errors++;
2424 } else {
2425 dev->stats.tx_packets++;
2426 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2427 }
2428 dev_kfree_skb_any(np->get_tx_ctx->skb);
2429 np->get_tx_ctx->skb = NULL;
2430 tx_work++;
2431 }
2432 } else {
2433 if (flags & NV_TX2_LASTPACKET) {
2434 if (flags & NV_TX2_ERROR) {
2435 if (flags & NV_TX2_UNDERFLOW)
2436 dev->stats.tx_fifo_errors++;
2437 if (flags & NV_TX2_CARRIERLOST)
2438 dev->stats.tx_carrier_errors++;
2439 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2440 nv_legacybackoff_reseed(dev);
2441 dev->stats.tx_errors++;
2442 } else {
2443 dev->stats.tx_packets++;
2444 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2445 }
2446 dev_kfree_skb_any(np->get_tx_ctx->skb);
2447 np->get_tx_ctx->skb = NULL;
2448 tx_work++;
2449 }
2450 }
2451 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2452 np->get_tx.orig = np->first_tx.orig;
2453 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2454 np->get_tx_ctx = np->first_tx_ctx;
2455 }
2456 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2457 np->tx_stop = 0;
2458 netif_wake_queue(dev);
2459 }
2460 return tx_work;
2461 }
2462
2463 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2464 {
2465 struct fe_priv *np = netdev_priv(dev);
2466 u32 flags;
2467 int tx_work = 0;
2468 struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2469
2470 while ((np->get_tx.ex != np->put_tx.ex) &&
2471 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2472 (tx_work < limit)) {
2473
2474 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2475 dev->name, flags);
2476
2477 nv_unmap_txskb(np, np->get_tx_ctx);
2478
2479 if (flags & NV_TX2_LASTPACKET) {
2480 if (!(flags & NV_TX2_ERROR))
2481 dev->stats.tx_packets++;
2482 else {
2483 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2484 if (np->driver_data & DEV_HAS_GEAR_MODE)
2485 nv_gear_backoff_reseed(dev);
2486 else
2487 nv_legacybackoff_reseed(dev);
2488 }
2489 }
2490
2491 dev_kfree_skb_any(np->get_tx_ctx->skb);
2492 np->get_tx_ctx->skb = NULL;
2493 tx_work++;
2494
2495 if (np->tx_limit) {
2496 nv_tx_flip_ownership(dev);
2497 }
2498 }
2499 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2500 np->get_tx.ex = np->first_tx.ex;
2501 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2502 np->get_tx_ctx = np->first_tx_ctx;
2503 }
2504 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2505 np->tx_stop = 0;
2506 netif_wake_queue(dev);
2507 }
2508 return tx_work;
2509 }
2510
2511 /*
2512 * nv_tx_timeout: dev->tx_timeout function
2513 * Called with netif_tx_lock held.
2514 */
2515 static void nv_tx_timeout(struct net_device *dev)
2516 {
2517 struct fe_priv *np = netdev_priv(dev);
2518 u8 __iomem *base = get_hwbase(dev);
2519 u32 status;
2520 union ring_type put_tx;
2521 int saved_tx_limit;
2522
2523 if (np->msi_flags & NV_MSI_X_ENABLED)
2524 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2525 else
2526 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2527
2528 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2529
2530 {
2531 int i;
2532
2533 printk(KERN_INFO "%s: Ring at %lx\n",
2534 dev->name, (unsigned long)np->ring_addr);
2535 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2536 for (i=0;i<=np->register_size;i+= 32) {
2537 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2538 i,
2539 readl(base + i + 0), readl(base + i + 4),
2540 readl(base + i + 8), readl(base + i + 12),
2541 readl(base + i + 16), readl(base + i + 20),
2542 readl(base + i + 24), readl(base + i + 28));
2543 }
2544 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2545 for (i=0;i<np->tx_ring_size;i+= 4) {
2546 if (!nv_optimized(np)) {
2547 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2548 i,
2549 le32_to_cpu(np->tx_ring.orig[i].buf),
2550 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2551 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2552 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2553 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2554 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2555 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2556 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2557 } else {
2558 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2559 i,
2560 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2561 le32_to_cpu(np->tx_ring.ex[i].buflow),
2562 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2563 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2564 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2565 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2566 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2567 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2568 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2569 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2570 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2571 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2572 }
2573 }
2574 }
2575
2576 spin_lock_irq(&np->lock);
2577
2578 /* 1) stop tx engine */
2579 nv_stop_tx(dev);
2580
2581 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2582 saved_tx_limit = np->tx_limit;
2583 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2584 np->tx_stop = 0; /* prevent waking tx queue */
2585 if (!nv_optimized(np))
2586 nv_tx_done(dev, np->tx_ring_size);
2587 else
2588 nv_tx_done_optimized(dev, np->tx_ring_size);
2589
2590 /* save current HW postion */
2591 if (np->tx_change_owner)
2592 put_tx.ex = np->tx_change_owner->first_tx_desc;
2593 else
2594 put_tx = np->put_tx;
2595
2596 /* 3) clear all tx state */
2597 nv_drain_tx(dev);
2598 nv_init_tx(dev);
2599
2600 /* 4) restore state to current HW position */
2601 np->get_tx = np->put_tx = put_tx;
2602 np->tx_limit = saved_tx_limit;
2603
2604 /* 5) restart tx engine */
2605 nv_start_tx(dev);
2606 netif_wake_queue(dev);
2607 spin_unlock_irq(&np->lock);
2608 }
2609
2610 /*
2611 * Called when the nic notices a mismatch between the actual data len on the
2612 * wire and the len indicated in the 802 header
2613 */
2614 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2615 {
2616 int hdrlen; /* length of the 802 header */
2617 int protolen; /* length as stored in the proto field */
2618
2619 /* 1) calculate len according to header */
2620 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2621 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2622 hdrlen = VLAN_HLEN;
2623 } else {
2624 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2625 hdrlen = ETH_HLEN;
2626 }
2627 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2628 dev->name, datalen, protolen, hdrlen);
2629 if (protolen > ETH_DATA_LEN)
2630 return datalen; /* Value in proto field not a len, no checks possible */
2631
2632 protolen += hdrlen;
2633 /* consistency checks: */
2634 if (datalen > ETH_ZLEN) {
2635 if (datalen >= protolen) {
2636 /* more data on wire than in 802 header, trim of
2637 * additional data.
2638 */
2639 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2640 dev->name, protolen);
2641 return protolen;
2642 } else {
2643 /* less data on wire than mentioned in header.
2644 * Discard the packet.
2645 */
2646 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2647 dev->name);
2648 return -1;
2649 }
2650 } else {
2651 /* short packet. Accept only if 802 values are also short */
2652 if (protolen > ETH_ZLEN) {
2653 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2654 dev->name);
2655 return -1;
2656 }
2657 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2658 dev->name, datalen);
2659 return datalen;
2660 }
2661 }
2662
2663 static int nv_rx_process(struct net_device *dev, int limit)
2664 {
2665 struct fe_priv *np = netdev_priv(dev);
2666 u32 flags;
2667 int rx_work = 0;
2668 struct sk_buff *skb;
2669 int len;
2670
2671 while((np->get_rx.orig != np->put_rx.orig) &&
2672 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2673 (rx_work < limit)) {
2674
2675 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2676 dev->name, flags);
2677
2678 /*
2679 * the packet is for us - immediately tear down the pci mapping.
2680 * TODO: check if a prefetch of the first cacheline improves
2681 * the performance.
2682 */
2683 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2684 np->get_rx_ctx->dma_len,
2685 PCI_DMA_FROMDEVICE);
2686 skb = np->get_rx_ctx->skb;
2687 np->get_rx_ctx->skb = NULL;
2688
2689 {
2690 int j;
2691 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2692 for (j=0; j<64; j++) {
2693 if ((j%16) == 0)
2694 dprintk("\n%03x:", j);
2695 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2696 }
2697 dprintk("\n");
2698 }
2699 /* look at what we actually got: */
2700 if (np->desc_ver == DESC_VER_1) {
2701 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2702 len = flags & LEN_MASK_V1;
2703 if (unlikely(flags & NV_RX_ERROR)) {
2704 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2705 len = nv_getlen(dev, skb->data, len);
2706 if (len < 0) {
2707 dev->stats.rx_errors++;
2708 dev_kfree_skb(skb);
2709 goto next_pkt;
2710 }
2711 }
2712 /* framing errors are soft errors */
2713 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2714 if (flags & NV_RX_SUBSTRACT1) {
2715 len--;
2716 }
2717 }
2718 /* the rest are hard errors */
2719 else {
2720 if (flags & NV_RX_MISSEDFRAME)
2721 dev->stats.rx_missed_errors++;
2722 if (flags & NV_RX_CRCERR)
2723 dev->stats.rx_crc_errors++;
2724 if (flags & NV_RX_OVERFLOW)
2725 dev->stats.rx_over_errors++;
2726 dev->stats.rx_errors++;
2727 dev_kfree_skb(skb);
2728 goto next_pkt;
2729 }
2730 }
2731 } else {
2732 dev_kfree_skb(skb);
2733 goto next_pkt;
2734 }
2735 } else {
2736 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2737 len = flags & LEN_MASK_V2;
2738 if (unlikely(flags & NV_RX2_ERROR)) {
2739 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2740 len = nv_getlen(dev, skb->data, len);
2741 if (len < 0) {
2742 dev->stats.rx_errors++;
2743 dev_kfree_skb(skb);
2744 goto next_pkt;
2745 }
2746 }
2747 /* framing errors are soft errors */
2748 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2749 if (flags & NV_RX2_SUBSTRACT1) {
2750 len--;
2751 }
2752 }
2753 /* the rest are hard errors */
2754 else {
2755 if (flags & NV_RX2_CRCERR)
2756 dev->stats.rx_crc_errors++;
2757 if (flags & NV_RX2_OVERFLOW)
2758 dev->stats.rx_over_errors++;
2759 dev->stats.rx_errors++;
2760 dev_kfree_skb(skb);
2761 goto next_pkt;
2762 }
2763 }
2764 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2765 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2766 skb->ip_summed = CHECKSUM_UNNECESSARY;
2767 } else {
2768 dev_kfree_skb(skb);
2769 goto next_pkt;
2770 }
2771 }
2772 /* got a valid packet - forward it to the network core */
2773 skb_put(skb, len);
2774 skb->protocol = eth_type_trans(skb, dev);
2775 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2776 dev->name, len, skb->protocol);
2777 napi_gro_receive(&np->napi, skb);
2778 dev->stats.rx_packets++;
2779 dev->stats.rx_bytes += len;
2780 next_pkt:
2781 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2782 np->get_rx.orig = np->first_rx.orig;
2783 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2784 np->get_rx_ctx = np->first_rx_ctx;
2785
2786 rx_work++;
2787 }
2788
2789 return rx_work;
2790 }
2791
2792 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2793 {
2794 struct fe_priv *np = netdev_priv(dev);
2795 u32 flags;
2796 u32 vlanflags = 0;
2797 int rx_work = 0;
2798 struct sk_buff *skb;
2799 int len;
2800
2801 while((np->get_rx.ex != np->put_rx.ex) &&
2802 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2803 (rx_work < limit)) {
2804
2805 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2806 dev->name, flags);
2807
2808 /*
2809 * the packet is for us - immediately tear down the pci mapping.
2810 * TODO: check if a prefetch of the first cacheline improves
2811 * the performance.
2812 */
2813 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2814 np->get_rx_ctx->dma_len,
2815 PCI_DMA_FROMDEVICE);
2816 skb = np->get_rx_ctx->skb;
2817 np->get_rx_ctx->skb = NULL;
2818
2819 {
2820 int j;
2821 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2822 for (j=0; j<64; j++) {
2823 if ((j%16) == 0)
2824 dprintk("\n%03x:", j);
2825 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2826 }
2827 dprintk("\n");
2828 }
2829 /* look at what we actually got: */
2830 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2831 len = flags & LEN_MASK_V2;
2832 if (unlikely(flags & NV_RX2_ERROR)) {
2833 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2834 len = nv_getlen(dev, skb->data, len);
2835 if (len < 0) {
2836 dev_kfree_skb(skb);
2837 goto next_pkt;
2838 }
2839 }
2840 /* framing errors are soft errors */
2841 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2842 if (flags & NV_RX2_SUBSTRACT1) {
2843 len--;
2844 }
2845 }
2846 /* the rest are hard errors */
2847 else {
2848 dev_kfree_skb(skb);
2849 goto next_pkt;
2850 }
2851 }
2852
2853 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2854 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2855 skb->ip_summed = CHECKSUM_UNNECESSARY;
2856
2857 /* got a valid packet - forward it to the network core */
2858 skb_put(skb, len);
2859 skb->protocol = eth_type_trans(skb, dev);
2860 prefetch(skb->data);
2861
2862 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2863 dev->name, len, skb->protocol);
2864
2865 if (likely(!np->vlangrp)) {
2866 napi_gro_receive(&np->napi, skb);
2867 } else {
2868 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2869 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2870 vlan_gro_receive(&np->napi, np->vlangrp,
2871 vlanflags & NV_RX3_VLAN_TAG_MASK, skb);
2872 } else {
2873 napi_gro_receive(&np->napi, skb);
2874 }
2875 }
2876
2877 dev->stats.rx_packets++;
2878 dev->stats.rx_bytes += len;
2879 } else {
2880 dev_kfree_skb(skb);
2881 }
2882 next_pkt:
2883 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2884 np->get_rx.ex = np->first_rx.ex;
2885 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2886 np->get_rx_ctx = np->first_rx_ctx;
2887
2888 rx_work++;
2889 }
2890
2891 return rx_work;
2892 }
2893
2894 static void set_bufsize(struct net_device *dev)
2895 {
2896 struct fe_priv *np = netdev_priv(dev);
2897
2898 if (dev->mtu <= ETH_DATA_LEN)
2899 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2900 else
2901 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2902 }
2903
2904 /*
2905 * nv_change_mtu: dev->change_mtu function
2906 * Called with dev_base_lock held for read.
2907 */
2908 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2909 {
2910 struct fe_priv *np = netdev_priv(dev);
2911 int old_mtu;
2912
2913 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2914 return -EINVAL;
2915
2916 old_mtu = dev->mtu;
2917 dev->mtu = new_mtu;
2918
2919 /* return early if the buffer sizes will not change */
2920 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2921 return 0;
2922 if (old_mtu == new_mtu)
2923 return 0;
2924
2925 /* synchronized against open : rtnl_lock() held by caller */
2926 if (netif_running(dev)) {
2927 u8 __iomem *base = get_hwbase(dev);
2928 /*
2929 * It seems that the nic preloads valid ring entries into an
2930 * internal buffer. The procedure for flushing everything is
2931 * guessed, there is probably a simpler approach.
2932 * Changing the MTU is a rare event, it shouldn't matter.
2933 */
2934 nv_disable_irq(dev);
2935 nv_napi_disable(dev);
2936 netif_tx_lock_bh(dev);
2937 netif_addr_lock(dev);
2938 spin_lock(&np->lock);
2939 /* stop engines */
2940 nv_stop_rxtx(dev);
2941 nv_txrx_reset(dev);
2942 /* drain rx queue */
2943 nv_drain_rxtx(dev);
2944 /* reinit driver view of the rx queue */
2945 set_bufsize(dev);
2946 if (nv_init_ring(dev)) {
2947 if (!np->in_shutdown)
2948 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2949 }
2950 /* reinit nic view of the rx queue */
2951 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2952 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2953 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2954 base + NvRegRingSizes);
2955 pci_push(base);
2956 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2957 pci_push(base);
2958
2959 /* restart rx engine */
2960 nv_start_rxtx(dev);
2961 spin_unlock(&np->lock);
2962 netif_addr_unlock(dev);
2963 netif_tx_unlock_bh(dev);
2964 nv_napi_enable(dev);
2965 nv_enable_irq(dev);
2966 }
2967 return 0;
2968 }
2969
2970 static void nv_copy_mac_to_hw(struct net_device *dev)
2971 {
2972 u8 __iomem *base = get_hwbase(dev);
2973 u32 mac[2];
2974
2975 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2976 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2977 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2978
2979 writel(mac[0], base + NvRegMacAddrA);
2980 writel(mac[1], base + NvRegMacAddrB);
2981 }
2982
2983 /*
2984 * nv_set_mac_address: dev->set_mac_address function
2985 * Called with rtnl_lock() held.
2986 */
2987 static int nv_set_mac_address(struct net_device *dev, void *addr)
2988 {
2989 struct fe_priv *np = netdev_priv(dev);
2990 struct sockaddr *macaddr = (struct sockaddr*)addr;
2991
2992 if (!is_valid_ether_addr(macaddr->sa_data))
2993 return -EADDRNOTAVAIL;
2994
2995 /* synchronized against open : rtnl_lock() held by caller */
2996 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2997
2998 if (netif_running(dev)) {
2999 netif_tx_lock_bh(dev);
3000 netif_addr_lock(dev);
3001 spin_lock_irq(&np->lock);
3002
3003 /* stop rx engine */
3004 nv_stop_rx(dev);
3005
3006 /* set mac address */
3007 nv_copy_mac_to_hw(dev);
3008
3009 /* restart rx engine */
3010 nv_start_rx(dev);
3011 spin_unlock_irq(&np->lock);
3012 netif_addr_unlock(dev);
3013 netif_tx_unlock_bh(dev);
3014 } else {
3015 nv_copy_mac_to_hw(dev);
3016 }
3017 return 0;
3018 }
3019
3020 /*
3021 * nv_set_multicast: dev->set_multicast function
3022 * Called with netif_tx_lock held.
3023 */
3024 static void nv_set_multicast(struct net_device *dev)
3025 {
3026 struct fe_priv *np = netdev_priv(dev);
3027 u8 __iomem *base = get_hwbase(dev);
3028 u32 addr[2];
3029 u32 mask[2];
3030 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3031
3032 memset(addr, 0, sizeof(addr));
3033 memset(mask, 0, sizeof(mask));
3034
3035 if (dev->flags & IFF_PROMISC) {
3036 pff |= NVREG_PFF_PROMISC;
3037 } else {
3038 pff |= NVREG_PFF_MYADDR;
3039
3040 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3041 u32 alwaysOff[2];
3042 u32 alwaysOn[2];
3043
3044 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3045 if (dev->flags & IFF_ALLMULTI) {
3046 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3047 } else {
3048 struct netdev_hw_addr *ha;
3049
3050 netdev_for_each_mc_addr(ha, dev) {
3051 unsigned char *addr = ha->addr;
3052 u32 a, b;
3053
3054 a = le32_to_cpu(*(__le32 *) addr);
3055 b = le16_to_cpu(*(__le16 *) (&addr[4]));
3056 alwaysOn[0] &= a;
3057 alwaysOff[0] &= ~a;
3058 alwaysOn[1] &= b;
3059 alwaysOff[1] &= ~b;
3060 }
3061 }
3062 addr[0] = alwaysOn[0];
3063 addr[1] = alwaysOn[1];
3064 mask[0] = alwaysOn[0] | alwaysOff[0];
3065 mask[1] = alwaysOn[1] | alwaysOff[1];
3066 } else {
3067 mask[0] = NVREG_MCASTMASKA_NONE;
3068 mask[1] = NVREG_MCASTMASKB_NONE;
3069 }
3070 }
3071 addr[0] |= NVREG_MCASTADDRA_FORCE;
3072 pff |= NVREG_PFF_ALWAYS;
3073 spin_lock_irq(&np->lock);
3074 nv_stop_rx(dev);
3075 writel(addr[0], base + NvRegMulticastAddrA);
3076 writel(addr[1], base + NvRegMulticastAddrB);
3077 writel(mask[0], base + NvRegMulticastMaskA);
3078 writel(mask[1], base + NvRegMulticastMaskB);
3079 writel(pff, base + NvRegPacketFilterFlags);
3080 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
3081 dev->name);
3082 nv_start_rx(dev);
3083 spin_unlock_irq(&np->lock);
3084 }
3085
3086 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3087 {
3088 struct fe_priv *np = netdev_priv(dev);
3089 u8 __iomem *base = get_hwbase(dev);
3090
3091 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3092
3093 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3094 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3095 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3096 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3097 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3098 } else {
3099 writel(pff, base + NvRegPacketFilterFlags);
3100 }
3101 }
3102 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3103 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3104 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3105 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3106 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3107 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3108 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3109 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3110 /* limit the number of tx pause frames to a default of 8 */
3111 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3112 }
3113 writel(pause_enable, base + NvRegTxPauseFrame);
3114 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3115 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3116 } else {
3117 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3118 writel(regmisc, base + NvRegMisc1);
3119 }
3120 }
3121 }
3122
3123 /**
3124 * nv_update_linkspeed: Setup the MAC according to the link partner
3125 * @dev: Network device to be configured
3126 *
3127 * The function queries the PHY and checks if there is a link partner.
3128 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3129 * set to 10 MBit HD.
3130 *
3131 * The function returns 0 if there is no link partner and 1 if there is
3132 * a good link partner.
3133 */
3134 static int nv_update_linkspeed(struct net_device *dev)
3135 {
3136 struct fe_priv *np = netdev_priv(dev);
3137 u8 __iomem *base = get_hwbase(dev);
3138 int adv = 0;
3139 int lpa = 0;
3140 int adv_lpa, adv_pause, lpa_pause;
3141 int newls = np->linkspeed;
3142 int newdup = np->duplex;
3143 int mii_status;
3144 int retval = 0;
3145 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3146 u32 txrxFlags = 0;
3147 u32 phy_exp;
3148
3149 /* BMSR_LSTATUS is latched, read it twice:
3150 * we want the current value.
3151 */
3152 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3153 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3154
3155 if (!(mii_status & BMSR_LSTATUS)) {
3156 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
3157 dev->name);
3158 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3159 newdup = 0;
3160 retval = 0;
3161 goto set_speed;
3162 }
3163
3164 if (np->autoneg == 0) {
3165 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3166 dev->name, np->fixed_mode);
3167 if (np->fixed_mode & LPA_100FULL) {
3168 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3169 newdup = 1;
3170 } else if (np->fixed_mode & LPA_100HALF) {
3171 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3172 newdup = 0;
3173 } else if (np->fixed_mode & LPA_10FULL) {
3174 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3175 newdup = 1;
3176 } else {
3177 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3178 newdup = 0;
3179 }
3180 retval = 1;
3181 goto set_speed;
3182 }
3183 /* check auto negotiation is complete */
3184 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3185 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3186 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3187 newdup = 0;
3188 retval = 0;
3189 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
3190 goto set_speed;
3191 }
3192
3193 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3194 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3195 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3196 dev->name, adv, lpa);
3197
3198 retval = 1;
3199 if (np->gigabit == PHY_GIGABIT) {
3200 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3201 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3202
3203 if ((control_1000 & ADVERTISE_1000FULL) &&
3204 (status_1000 & LPA_1000FULL)) {
3205 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
3206 dev->name);
3207 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3208 newdup = 1;
3209 goto set_speed;
3210 }
3211 }
3212
3213 /* FIXME: handle parallel detection properly */
3214 adv_lpa = lpa & adv;
3215 if (adv_lpa & LPA_100FULL) {
3216 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3217 newdup = 1;
3218 } else if (adv_lpa & LPA_100HALF) {
3219 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3220 newdup = 0;
3221 } else if (adv_lpa & LPA_10FULL) {
3222 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3223 newdup = 1;
3224 } else if (adv_lpa & LPA_10HALF) {
3225 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3226 newdup = 0;
3227 } else {
3228 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
3229 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3230 newdup = 0;
3231 }
3232
3233 set_speed:
3234 if (np->duplex == newdup && np->linkspeed == newls)
3235 return retval;
3236
3237 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
3238 dev->name, np->linkspeed, np->duplex, newls, newdup);
3239
3240 np->duplex = newdup;
3241 np->linkspeed = newls;
3242
3243 /* The transmitter and receiver must be restarted for safe update */
3244 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3245 txrxFlags |= NV_RESTART_TX;
3246 nv_stop_tx(dev);
3247 }
3248 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3249 txrxFlags |= NV_RESTART_RX;
3250 nv_stop_rx(dev);
3251 }
3252
3253 if (np->gigabit == PHY_GIGABIT) {
3254 phyreg = readl(base + NvRegSlotTime);
3255 phyreg &= ~(0x3FF00);
3256 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3257 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3258 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3259 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3260 phyreg |= NVREG_SLOTTIME_1000_FULL;
3261 writel(phyreg, base + NvRegSlotTime);
3262 }
3263
3264 phyreg = readl(base + NvRegPhyInterface);
3265 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3266 if (np->duplex == 0)
3267 phyreg |= PHY_HALF;
3268 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3269 phyreg |= PHY_100;
3270 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3271 phyreg |= PHY_1000;
3272 writel(phyreg, base + NvRegPhyInterface);
3273
3274 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3275 if (phyreg & PHY_RGMII) {
3276 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3277 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3278 } else {
3279 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3280 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3281 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3282 else
3283 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3284 } else {
3285 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3286 }
3287 }
3288 } else {
3289 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3290 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3291 else
3292 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3293 }
3294 writel(txreg, base + NvRegTxDeferral);
3295
3296 if (np->desc_ver == DESC_VER_1) {
3297 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3298 } else {
3299 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3300 txreg = NVREG_TX_WM_DESC2_3_1000;
3301 else
3302 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3303 }
3304 writel(txreg, base + NvRegTxWatermark);
3305
3306 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3307 base + NvRegMisc1);
3308 pci_push(base);
3309 writel(np->linkspeed, base + NvRegLinkSpeed);
3310 pci_push(base);
3311
3312 pause_flags = 0;
3313 /* setup pause frame */
3314 if (np->duplex != 0) {
3315 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3316 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3317 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3318
3319 switch (adv_pause) {
3320 case ADVERTISE_PAUSE_CAP:
3321 if (lpa_pause & LPA_PAUSE_CAP) {
3322 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3323 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3324 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3325 }
3326 break;
3327 case ADVERTISE_PAUSE_ASYM:
3328 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3329 {
3330 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3331 }
3332 break;
3333 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3334 if (lpa_pause & LPA_PAUSE_CAP)
3335 {
3336 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3337 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3338 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3339 }
3340 if (lpa_pause == LPA_PAUSE_ASYM)
3341 {
3342 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3343 }
3344 break;
3345 }
3346 } else {
3347 pause_flags = np->pause_flags;
3348 }
3349 }
3350 nv_update_pause(dev, pause_flags);
3351
3352 if (txrxFlags & NV_RESTART_TX)
3353 nv_start_tx(dev);
3354 if (txrxFlags & NV_RESTART_RX)
3355 nv_start_rx(dev);
3356
3357 return retval;
3358 }
3359
3360 static void nv_linkchange(struct net_device *dev)
3361 {
3362 if (nv_update_linkspeed(dev)) {
3363 if (!netif_carrier_ok(dev)) {
3364 netif_carrier_on(dev);
3365 printk(KERN_INFO "%s: link up.\n", dev->name);
3366 nv_txrx_gate(dev, false);
3367 nv_start_rx(dev);
3368 }
3369 } else {
3370 if (netif_carrier_ok(dev)) {
3371 netif_carrier_off(dev);
3372 printk(KERN_INFO "%s: link down.\n", dev->name);
3373 nv_txrx_gate(dev, true);
3374 nv_stop_rx(dev);
3375 }
3376 }
3377 }
3378
3379 static void nv_link_irq(struct net_device *dev)
3380 {
3381 u8 __iomem *base = get_hwbase(dev);
3382 u32 miistat;
3383
3384 miistat = readl(base + NvRegMIIStatus);
3385 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3386 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3387
3388 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3389 nv_linkchange(dev);
3390 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3391 }
3392
3393 static void nv_msi_workaround(struct fe_priv *np)
3394 {
3395
3396 /* Need to toggle the msi irq mask within the ethernet device,
3397 * otherwise, future interrupts will not be detected.
3398 */
3399 if (np->msi_flags & NV_MSI_ENABLED) {
3400 u8 __iomem *base = np->base;
3401
3402 writel(0, base + NvRegMSIIrqMask);
3403 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3404 }
3405 }
3406
3407 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3408 {
3409 struct fe_priv *np = netdev_priv(dev);
3410
3411 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3412 if (total_work > NV_DYNAMIC_THRESHOLD) {
3413 /* transition to poll based interrupts */
3414 np->quiet_count = 0;
3415 if (np->irqmask != NVREG_IRQMASK_CPU) {
3416 np->irqmask = NVREG_IRQMASK_CPU;
3417 return 1;
3418 }
3419 } else {
3420 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3421 np->quiet_count++;
3422 } else {
3423 /* reached a period of low activity, switch
3424 to per tx/rx packet interrupts */
3425 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3426 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3427 return 1;
3428 }
3429 }
3430 }
3431 }
3432 return 0;
3433 }
3434
3435 static irqreturn_t nv_nic_irq(int foo, void *data)
3436 {
3437 struct net_device *dev = (struct net_device *) data;
3438 struct fe_priv *np = netdev_priv(dev);
3439 u8 __iomem *base = get_hwbase(dev);
3440
3441 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3442
3443 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3444 np->events = readl(base + NvRegIrqStatus);
3445 writel(np->events, base + NvRegIrqStatus);
3446 } else {
3447 np->events = readl(base + NvRegMSIXIrqStatus);
3448 writel(np->events, base + NvRegMSIXIrqStatus);
3449 }
3450 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3451 if (!(np->events & np->irqmask))
3452 return IRQ_NONE;
3453
3454 nv_msi_workaround(np);
3455
3456 if (napi_schedule_prep(&np->napi)) {
3457 /*
3458 * Disable further irq's (msix not enabled with napi)
3459 */
3460 writel(0, base + NvRegIrqMask);
3461 __napi_schedule(&np->napi);
3462 }
3463
3464 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3465
3466 return IRQ_HANDLED;
3467 }
3468
3469 /**
3470 * All _optimized functions are used to help increase performance
3471 * (reduce CPU and increase throughput). They use descripter version 3,
3472 * compiler directives, and reduce memory accesses.
3473 */
3474 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3475 {
3476 struct net_device *dev = (struct net_device *) data;
3477 struct fe_priv *np = netdev_priv(dev);
3478 u8 __iomem *base = get_hwbase(dev);
3479
3480 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3481
3482 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3483 np->events = readl(base + NvRegIrqStatus);
3484 writel(np->events, base + NvRegIrqStatus);
3485 } else {
3486 np->events = readl(base + NvRegMSIXIrqStatus);
3487 writel(np->events, base + NvRegMSIXIrqStatus);
3488 }
3489 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
3490 if (!(np->events & np->irqmask))
3491 return IRQ_NONE;
3492
3493 nv_msi_workaround(np);
3494
3495 if (napi_schedule_prep(&np->napi)) {
3496 /*
3497 * Disable further irq's (msix not enabled with napi)
3498 */
3499 writel(0, base + NvRegIrqMask);
3500 __napi_schedule(&np->napi);
3501 }
3502 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3503
3504 return IRQ_HANDLED;
3505 }
3506
3507 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3508 {
3509 struct net_device *dev = (struct net_device *) data;
3510 struct fe_priv *np = netdev_priv(dev);
3511 u8 __iomem *base = get_hwbase(dev);
3512 u32 events;
3513 int i;
3514 unsigned long flags;
3515
3516 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3517
3518 for (i=0; ; i++) {
3519 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3520 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3521 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3522 if (!(events & np->irqmask))
3523 break;
3524
3525 spin_lock_irqsave(&np->lock, flags);
3526 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3527 spin_unlock_irqrestore(&np->lock, flags);
3528
3529 if (unlikely(i > max_interrupt_work)) {
3530 spin_lock_irqsave(&np->lock, flags);
3531 /* disable interrupts on the nic */
3532 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3533 pci_push(base);
3534
3535 if (!np->in_shutdown) {
3536 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3537 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3538 }
3539 spin_unlock_irqrestore(&np->lock, flags);
3540 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3541 break;
3542 }
3543
3544 }
3545 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3546
3547 return IRQ_RETVAL(i);
3548 }
3549
3550 static int nv_napi_poll(struct napi_struct *napi, int budget)
3551 {
3552 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3553 struct net_device *dev = np->dev;
3554 u8 __iomem *base = get_hwbase(dev);
3555 unsigned long flags;
3556 int retcode;
3557 int rx_count, tx_work=0, rx_work=0;
3558
3559 do {
3560 if (!nv_optimized(np)) {
3561 spin_lock_irqsave(&np->lock, flags);
3562 tx_work += nv_tx_done(dev, np->tx_ring_size);
3563 spin_unlock_irqrestore(&np->lock, flags);
3564
3565 rx_count = nv_rx_process(dev, budget - rx_work);
3566 retcode = nv_alloc_rx(dev);
3567 } else {
3568 spin_lock_irqsave(&np->lock, flags);
3569 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3570 spin_unlock_irqrestore(&np->lock, flags);
3571
3572 rx_count = nv_rx_process_optimized(dev,
3573 budget - rx_work);
3574 retcode = nv_alloc_rx_optimized(dev);
3575 }
3576 } while (retcode == 0 &&
3577 rx_count > 0 && (rx_work += rx_count) < budget);
3578
3579 if (retcode) {
3580 spin_lock_irqsave(&np->lock, flags);
3581 if (!np->in_shutdown)
3582 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3583 spin_unlock_irqrestore(&np->lock, flags);
3584 }
3585
3586 nv_change_interrupt_mode(dev, tx_work + rx_work);
3587
3588 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3589 spin_lock_irqsave(&np->lock, flags);
3590 nv_link_irq(dev);
3591 spin_unlock_irqrestore(&np->lock, flags);
3592 }
3593 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3594 spin_lock_irqsave(&np->lock, flags);
3595 nv_linkchange(dev);
3596 spin_unlock_irqrestore(&np->lock, flags);
3597 np->link_timeout = jiffies + LINK_TIMEOUT;
3598 }
3599 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3600 spin_lock_irqsave(&np->lock, flags);
3601 if (!np->in_shutdown) {
3602 np->nic_poll_irq = np->irqmask;
3603 np->recover_error = 1;
3604 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3605 }
3606 spin_unlock_irqrestore(&np->lock, flags);
3607 napi_complete(napi);
3608 return rx_work;
3609 }
3610
3611 if (rx_work < budget) {
3612 /* re-enable interrupts
3613 (msix not enabled in napi) */
3614 napi_complete(napi);
3615
3616 writel(np->irqmask, base + NvRegIrqMask);
3617 }
3618 return rx_work;
3619 }
3620
3621 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3622 {
3623 struct net_device *dev = (struct net_device *) data;
3624 struct fe_priv *np = netdev_priv(dev);
3625 u8 __iomem *base = get_hwbase(dev);
3626 u32 events;
3627 int i;
3628 unsigned long flags;
3629
3630 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3631
3632 for (i=0; ; i++) {
3633 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3634 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3635 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3636 if (!(events & np->irqmask))
3637 break;
3638
3639 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3640 if (unlikely(nv_alloc_rx_optimized(dev))) {
3641 spin_lock_irqsave(&np->lock, flags);
3642 if (!np->in_shutdown)
3643 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3644 spin_unlock_irqrestore(&np->lock, flags);
3645 }
3646 }
3647
3648 if (unlikely(i > max_interrupt_work)) {
3649 spin_lock_irqsave(&np->lock, flags);
3650 /* disable interrupts on the nic */
3651 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3652 pci_push(base);
3653
3654 if (!np->in_shutdown) {
3655 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3656 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3657 }
3658 spin_unlock_irqrestore(&np->lock, flags);
3659 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3660 break;
3661 }
3662 }
3663 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3664
3665 return IRQ_RETVAL(i);
3666 }
3667
3668 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3669 {
3670 struct net_device *dev = (struct net_device *) data;
3671 struct fe_priv *np = netdev_priv(dev);
3672 u8 __iomem *base = get_hwbase(dev);
3673 u32 events;
3674 int i;
3675 unsigned long flags;
3676
3677 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3678
3679 for (i=0; ; i++) {
3680 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3681 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3682 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3683 if (!(events & np->irqmask))
3684 break;
3685
3686 /* check tx in case we reached max loop limit in tx isr */
3687 spin_lock_irqsave(&np->lock, flags);
3688 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3689 spin_unlock_irqrestore(&np->lock, flags);
3690
3691 if (events & NVREG_IRQ_LINK) {
3692 spin_lock_irqsave(&np->lock, flags);
3693 nv_link_irq(dev);
3694 spin_unlock_irqrestore(&np->lock, flags);
3695 }
3696 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3697 spin_lock_irqsave(&np->lock, flags);
3698 nv_linkchange(dev);
3699 spin_unlock_irqrestore(&np->lock, flags);
3700 np->link_timeout = jiffies + LINK_TIMEOUT;
3701 }
3702 if (events & NVREG_IRQ_RECOVER_ERROR) {
3703 spin_lock_irq(&np->lock);
3704 /* disable interrupts on the nic */
3705 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3706 pci_push(base);
3707
3708 if (!np->in_shutdown) {
3709 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3710 np->recover_error = 1;
3711 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3712 }
3713 spin_unlock_irq(&np->lock);
3714 break;
3715 }
3716 if (unlikely(i > max_interrupt_work)) {
3717 spin_lock_irqsave(&np->lock, flags);
3718 /* disable interrupts on the nic */
3719 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3720 pci_push(base);
3721
3722 if (!np->in_shutdown) {
3723 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3724 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3725 }
3726 spin_unlock_irqrestore(&np->lock, flags);
3727 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3728 break;
3729 }
3730
3731 }
3732 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3733
3734 return IRQ_RETVAL(i);
3735 }
3736
3737 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3738 {
3739 struct net_device *dev = (struct net_device *) data;
3740 struct fe_priv *np = netdev_priv(dev);
3741 u8 __iomem *base = get_hwbase(dev);
3742 u32 events;
3743
3744 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3745
3746 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3747 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3748 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3749 } else {
3750 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3751 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3752 }
3753 pci_push(base);
3754 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3755 if (!(events & NVREG_IRQ_TIMER))
3756 return IRQ_RETVAL(0);
3757
3758 nv_msi_workaround(np);
3759
3760 spin_lock(&np->lock);
3761 np->intr_test = 1;
3762 spin_unlock(&np->lock);
3763
3764 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3765
3766 return IRQ_RETVAL(1);
3767 }
3768
3769 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3770 {
3771 u8 __iomem *base = get_hwbase(dev);
3772 int i;
3773 u32 msixmap = 0;
3774
3775 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3776 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3777 * the remaining 8 interrupts.
3778 */
3779 for (i = 0; i < 8; i++) {
3780 if ((irqmask >> i) & 0x1) {
3781 msixmap |= vector << (i << 2);
3782 }
3783 }
3784 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3785
3786 msixmap = 0;
3787 for (i = 0; i < 8; i++) {
3788 if ((irqmask >> (i + 8)) & 0x1) {
3789 msixmap |= vector << (i << 2);
3790 }
3791 }
3792 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3793 }
3794
3795 static int nv_request_irq(struct net_device *dev, int intr_test)
3796 {
3797 struct fe_priv *np = get_nvpriv(dev);
3798 u8 __iomem *base = get_hwbase(dev);
3799 int ret = 1;
3800 int i;
3801 irqreturn_t (*handler)(int foo, void *data);
3802
3803 if (intr_test) {
3804 handler = nv_nic_irq_test;
3805 } else {
3806 if (nv_optimized(np))
3807 handler = nv_nic_irq_optimized;
3808 else
3809 handler = nv_nic_irq;
3810 }
3811
3812 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3813 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3814 np->msi_x_entry[i].entry = i;
3815 }
3816 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3817 np->msi_flags |= NV_MSI_X_ENABLED;
3818 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3819 /* Request irq for rx handling */
3820 sprintf(np->name_rx, "%s-rx", dev->name);
3821 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3822 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3823 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3824 pci_disable_msix(np->pci_dev);
3825 np->msi_flags &= ~NV_MSI_X_ENABLED;
3826 goto out_err;
3827 }
3828 /* Request irq for tx handling */
3829 sprintf(np->name_tx, "%s-tx", dev->name);
3830 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3831 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3832 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3833 pci_disable_msix(np->pci_dev);
3834 np->msi_flags &= ~NV_MSI_X_ENABLED;
3835 goto out_free_rx;
3836 }
3837 /* Request irq for link and timer handling */
3838 sprintf(np->name_other, "%s-other", dev->name);
3839 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3840 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3841 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3842 pci_disable_msix(np->pci_dev);
3843 np->msi_flags &= ~NV_MSI_X_ENABLED;
3844 goto out_free_tx;
3845 }
3846 /* map interrupts to their respective vector */
3847 writel(0, base + NvRegMSIXMap0);
3848 writel(0, base + NvRegMSIXMap1);
3849 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3850 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3851 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3852 } else {
3853 /* Request irq for all interrupts */
3854 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3855 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3856 pci_disable_msix(np->pci_dev);
3857 np->msi_flags &= ~NV_MSI_X_ENABLED;
3858 goto out_err;
3859 }
3860
3861 /* map interrupts to vector 0 */
3862 writel(0, base + NvRegMSIXMap0);
3863 writel(0, base + NvRegMSIXMap1);
3864 }
3865 }
3866 }
3867 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3868 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3869 np->msi_flags |= NV_MSI_ENABLED;
3870 dev->irq = np->pci_dev->irq;
3871 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3872 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3873 pci_disable_msi(np->pci_dev);
3874 np->msi_flags &= ~NV_MSI_ENABLED;
3875 dev->irq = np->pci_dev->irq;
3876 goto out_err;
3877 }
3878
3879 /* map interrupts to vector 0 */
3880 writel(0, base + NvRegMSIMap0);
3881 writel(0, base + NvRegMSIMap1);
3882 /* enable msi vector 0 */
3883 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3884 }
3885 }
3886 if (ret != 0) {
3887 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3888 goto out_err;
3889
3890 }
3891
3892 return 0;
3893 out_free_tx:
3894 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3895 out_free_rx:
3896 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3897 out_err:
3898 return 1;
3899 }
3900
3901 static void nv_free_irq(struct net_device *dev)
3902 {
3903 struct fe_priv *np = get_nvpriv(dev);
3904 int i;
3905
3906 if (np->msi_flags & NV_MSI_X_ENABLED) {
3907 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3908 free_irq(np->msi_x_entry[i].vector, dev);
3909 }
3910 pci_disable_msix(np->pci_dev);
3911 np->msi_flags &= ~NV_MSI_X_ENABLED;
3912 } else {
3913 free_irq(np->pci_dev->irq, dev);
3914 if (np->msi_flags & NV_MSI_ENABLED) {
3915 pci_disable_msi(np->pci_dev);
3916 np->msi_flags &= ~NV_MSI_ENABLED;
3917 }
3918 }
3919 }
3920
3921 static void nv_do_nic_poll(unsigned long data)
3922 {
3923 struct net_device *dev = (struct net_device *) data;
3924 struct fe_priv *np = netdev_priv(dev);
3925 u8 __iomem *base = get_hwbase(dev);
3926 u32 mask = 0;
3927
3928 /*
3929 * First disable irq(s) and then
3930 * reenable interrupts on the nic, we have to do this before calling
3931 * nv_nic_irq because that may decide to do otherwise
3932 */
3933
3934 if (!using_multi_irqs(dev)) {
3935 if (np->msi_flags & NV_MSI_X_ENABLED)
3936 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3937 else
3938 disable_irq_lockdep(np->pci_dev->irq);
3939 mask = np->irqmask;
3940 } else {
3941 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3942 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3943 mask |= NVREG_IRQ_RX_ALL;
3944 }
3945 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3946 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3947 mask |= NVREG_IRQ_TX_ALL;
3948 }
3949 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3950 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3951 mask |= NVREG_IRQ_OTHER;
3952 }
3953 }
3954 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3955
3956 if (np->recover_error) {
3957 np->recover_error = 0;
3958 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
3959 if (netif_running(dev)) {
3960 netif_tx_lock_bh(dev);
3961 netif_addr_lock(dev);
3962 spin_lock(&np->lock);
3963 /* stop engines */
3964 nv_stop_rxtx(dev);
3965 if (np->driver_data & DEV_HAS_POWER_CNTRL)
3966 nv_mac_reset(dev);
3967 nv_txrx_reset(dev);
3968 /* drain rx queue */
3969 nv_drain_rxtx(dev);
3970 /* reinit driver view of the rx queue */
3971 set_bufsize(dev);
3972 if (nv_init_ring(dev)) {
3973 if (!np->in_shutdown)
3974 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3975 }
3976 /* reinit nic view of the rx queue */
3977 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3978 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3979 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3980 base + NvRegRingSizes);
3981 pci_push(base);
3982 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3983 pci_push(base);
3984 /* clear interrupts */
3985 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3986 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3987 else
3988 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3989
3990 /* restart rx engine */
3991 nv_start_rxtx(dev);
3992 spin_unlock(&np->lock);
3993 netif_addr_unlock(dev);
3994 netif_tx_unlock_bh(dev);
3995 }
3996 }
3997
3998 writel(mask, base + NvRegIrqMask);
3999 pci_push(base);
4000
4001 if (!using_multi_irqs(dev)) {
4002 np->nic_poll_irq = 0;
4003 if (nv_optimized(np))
4004 nv_nic_irq_optimized(0, dev);
4005 else
4006 nv_nic_irq(0, dev);
4007 if (np->msi_flags & NV_MSI_X_ENABLED)
4008 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4009 else
4010 enable_irq_lockdep(np->pci_dev->irq);
4011 } else {
4012 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4013 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4014 nv_nic_irq_rx(0, dev);
4015 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4016 }
4017 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4018 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4019 nv_nic_irq_tx(0, dev);
4020 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4021 }
4022 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4023 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4024 nv_nic_irq_other(0, dev);
4025 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4026 }
4027 }
4028
4029 }
4030
4031 #ifdef CONFIG_NET_POLL_CONTROLLER
4032 static void nv_poll_controller(struct net_device *dev)
4033 {
4034 nv_do_nic_poll((unsigned long) dev);
4035 }
4036 #endif
4037
4038 static void nv_do_stats_poll(unsigned long data)
4039 {
4040 struct net_device *dev = (struct net_device *) data;
4041 struct fe_priv *np = netdev_priv(dev);
4042
4043 nv_get_hw_stats(dev);
4044
4045 if (!np->in_shutdown)
4046 mod_timer(&np->stats_poll,
4047 round_jiffies(jiffies + STATS_INTERVAL));
4048 }
4049
4050 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4051 {
4052 struct fe_priv *np = netdev_priv(dev);
4053 strcpy(info->driver, DRV_NAME);
4054 strcpy(info->version, FORCEDETH_VERSION);
4055 strcpy(info->bus_info, pci_name(np->pci_dev));
4056 }
4057
4058 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4059 {
4060 struct fe_priv *np = netdev_priv(dev);
4061 wolinfo->supported = WAKE_MAGIC;
4062
4063 spin_lock_irq(&np->lock);
4064 if (np->wolenabled)
4065 wolinfo->wolopts = WAKE_MAGIC;
4066 spin_unlock_irq(&np->lock);
4067 }
4068
4069 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4070 {
4071 struct fe_priv *np = netdev_priv(dev);
4072 u8 __iomem *base = get_hwbase(dev);
4073 u32 flags = 0;
4074
4075 if (wolinfo->wolopts == 0) {
4076 np->wolenabled = 0;
4077 } else if (wolinfo->wolopts & WAKE_MAGIC) {
4078 np->wolenabled = 1;
4079 flags = NVREG_WAKEUPFLAGS_ENABLE;
4080 }
4081 if (netif_running(dev)) {
4082 spin_lock_irq(&np->lock);
4083 writel(flags, base + NvRegWakeUpFlags);
4084 spin_unlock_irq(&np->lock);
4085 }
4086 return 0;
4087 }
4088
4089 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4090 {
4091 struct fe_priv *np = netdev_priv(dev);
4092 int adv;
4093
4094 spin_lock_irq(&np->lock);
4095 ecmd->port = PORT_MII;
4096 if (!netif_running(dev)) {
4097 /* We do not track link speed / duplex setting if the
4098 * interface is disabled. Force a link check */
4099 if (nv_update_linkspeed(dev)) {
4100 if (!netif_carrier_ok(dev))
4101 netif_carrier_on(dev);
4102 } else {
4103 if (netif_carrier_ok(dev))
4104 netif_carrier_off(dev);
4105 }
4106 }
4107
4108 if (netif_carrier_ok(dev)) {
4109 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4110 case NVREG_LINKSPEED_10:
4111 ecmd->speed = SPEED_10;
4112 break;
4113 case NVREG_LINKSPEED_100:
4114 ecmd->speed = SPEED_100;
4115 break;
4116 case NVREG_LINKSPEED_1000:
4117 ecmd->speed = SPEED_1000;
4118 break;
4119 }
4120 ecmd->duplex = DUPLEX_HALF;
4121 if (np->duplex)
4122 ecmd->duplex = DUPLEX_FULL;
4123 } else {
4124 ecmd->speed = -1;
4125 ecmd->duplex = -1;
4126 }
4127
4128 ecmd->autoneg = np->autoneg;
4129
4130 ecmd->advertising = ADVERTISED_MII;
4131 if (np->autoneg) {
4132 ecmd->advertising |= ADVERTISED_Autoneg;
4133 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4134 if (adv & ADVERTISE_10HALF)
4135 ecmd->advertising |= ADVERTISED_10baseT_Half;
4136 if (adv & ADVERTISE_10FULL)
4137 ecmd->advertising |= ADVERTISED_10baseT_Full;
4138 if (adv & ADVERTISE_100HALF)
4139 ecmd->advertising |= ADVERTISED_100baseT_Half;
4140 if (adv & ADVERTISE_100FULL)
4141 ecmd->advertising |= ADVERTISED_100baseT_Full;
4142 if (np->gigabit == PHY_GIGABIT) {
4143 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4144 if (adv & ADVERTISE_1000FULL)
4145 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4146 }
4147 }
4148 ecmd->supported = (SUPPORTED_Autoneg |
4149 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4150 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4151 SUPPORTED_MII);
4152 if (np->gigabit == PHY_GIGABIT)
4153 ecmd->supported |= SUPPORTED_1000baseT_Full;
4154
4155 ecmd->phy_address = np->phyaddr;
4156 ecmd->transceiver = XCVR_EXTERNAL;
4157
4158 /* ignore maxtxpkt, maxrxpkt for now */
4159 spin_unlock_irq(&np->lock);
4160 return 0;
4161 }
4162
4163 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4164 {
4165 struct fe_priv *np = netdev_priv(dev);
4166
4167 if (ecmd->port != PORT_MII)
4168 return -EINVAL;
4169 if (ecmd->transceiver != XCVR_EXTERNAL)
4170 return -EINVAL;
4171 if (ecmd->phy_address != np->phyaddr) {
4172 /* TODO: support switching between multiple phys. Should be
4173 * trivial, but not enabled due to lack of test hardware. */
4174 return -EINVAL;
4175 }
4176 if (ecmd->autoneg == AUTONEG_ENABLE) {
4177 u32 mask;
4178
4179 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4180 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4181 if (np->gigabit == PHY_GIGABIT)
4182 mask |= ADVERTISED_1000baseT_Full;
4183
4184 if ((ecmd->advertising & mask) == 0)
4185 return -EINVAL;
4186
4187 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4188 /* Note: autonegotiation disable, speed 1000 intentionally
4189 * forbidden - noone should need that. */
4190
4191 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4192 return -EINVAL;
4193 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4194 return -EINVAL;
4195 } else {
4196 return -EINVAL;
4197 }
4198
4199 netif_carrier_off(dev);
4200 if (netif_running(dev)) {
4201 unsigned long flags;
4202
4203 nv_disable_irq(dev);
4204 netif_tx_lock_bh(dev);
4205 netif_addr_lock(dev);
4206 /* with plain spinlock lockdep complains */
4207 spin_lock_irqsave(&np->lock, flags);
4208 /* stop engines */
4209 /* FIXME:
4210 * this can take some time, and interrupts are disabled
4211 * due to spin_lock_irqsave, but let's hope no daemon
4212 * is going to change the settings very often...
4213 * Worst case:
4214 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4215 * + some minor delays, which is up to a second approximately
4216 */
4217 nv_stop_rxtx(dev);
4218 spin_unlock_irqrestore(&np->lock, flags);
4219 netif_addr_unlock(dev);
4220 netif_tx_unlock_bh(dev);
4221 }
4222
4223 if (ecmd->autoneg == AUTONEG_ENABLE) {
4224 int adv, bmcr;
4225
4226 np->autoneg = 1;
4227
4228 /* advertise only what has been requested */
4229 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4230 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4231 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4232 adv |= ADVERTISE_10HALF;
4233 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4234 adv |= ADVERTISE_10FULL;
4235 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4236 adv |= ADVERTISE_100HALF;
4237 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4238 adv |= ADVERTISE_100FULL;
4239 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4240 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4241 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4242 adv |= ADVERTISE_PAUSE_ASYM;
4243 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4244
4245 if (np->gigabit == PHY_GIGABIT) {
4246 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4247 adv &= ~ADVERTISE_1000FULL;
4248 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4249 adv |= ADVERTISE_1000FULL;
4250 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4251 }
4252
4253 if (netif_running(dev))
4254 printk(KERN_INFO "%s: link down.\n", dev->name);
4255 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4256 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4257 bmcr |= BMCR_ANENABLE;
4258 /* reset the phy in order for settings to stick,
4259 * and cause autoneg to start */
4260 if (phy_reset(dev, bmcr)) {
4261 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4262 return -EINVAL;
4263 }
4264 } else {
4265 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4266 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4267 }
4268 } else {
4269 int adv, bmcr;
4270
4271 np->autoneg = 0;
4272
4273 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4274 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4275 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4276 adv |= ADVERTISE_10HALF;
4277 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4278 adv |= ADVERTISE_10FULL;
4279 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4280 adv |= ADVERTISE_100HALF;
4281 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4282 adv |= ADVERTISE_100FULL;
4283 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4284 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4285 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4286 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4287 }
4288 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4289 adv |= ADVERTISE_PAUSE_ASYM;
4290 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4291 }
4292 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4293 np->fixed_mode = adv;
4294
4295 if (np->gigabit == PHY_GIGABIT) {
4296 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4297 adv &= ~ADVERTISE_1000FULL;
4298 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4299 }
4300
4301 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4302 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4303 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4304 bmcr |= BMCR_FULLDPLX;
4305 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4306 bmcr |= BMCR_SPEED100;
4307 if (np->phy_oui == PHY_OUI_MARVELL) {
4308 /* reset the phy in order for forced mode settings to stick */
4309 if (phy_reset(dev, bmcr)) {
4310 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4311 return -EINVAL;
4312 }
4313 } else {
4314 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4315 if (netif_running(dev)) {
4316 /* Wait a bit and then reconfigure the nic. */
4317 udelay(10);
4318 nv_linkchange(dev);
4319 }
4320 }
4321 }
4322
4323 if (netif_running(dev)) {
4324 nv_start_rxtx(dev);
4325 nv_enable_irq(dev);
4326 }
4327
4328 return 0;
4329 }
4330
4331 #define FORCEDETH_REGS_VER 1
4332
4333 static int nv_get_regs_len(struct net_device *dev)
4334 {
4335 struct fe_priv *np = netdev_priv(dev);
4336 return np->register_size;
4337 }
4338
4339 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4340 {
4341 struct fe_priv *np = netdev_priv(dev);
4342 u8 __iomem *base = get_hwbase(dev);
4343 u32 *rbuf = buf;
4344 int i;
4345
4346 regs->version = FORCEDETH_REGS_VER;
4347 spin_lock_irq(&np->lock);
4348 for (i = 0;i <= np->register_size/sizeof(u32); i++)
4349 rbuf[i] = readl(base + i*sizeof(u32));
4350 spin_unlock_irq(&np->lock);
4351 }
4352
4353 static int nv_nway_reset(struct net_device *dev)
4354 {
4355 struct fe_priv *np = netdev_priv(dev);
4356 int ret;
4357
4358 if (np->autoneg) {
4359 int bmcr;
4360
4361 netif_carrier_off(dev);
4362 if (netif_running(dev)) {
4363 nv_disable_irq(dev);
4364 netif_tx_lock_bh(dev);
4365 netif_addr_lock(dev);
4366 spin_lock(&np->lock);
4367 /* stop engines */
4368 nv_stop_rxtx(dev);
4369 spin_unlock(&np->lock);
4370 netif_addr_unlock(dev);
4371 netif_tx_unlock_bh(dev);
4372 printk(KERN_INFO "%s: link down.\n", dev->name);
4373 }
4374
4375 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4376 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4377 bmcr |= BMCR_ANENABLE;
4378 /* reset the phy in order for settings to stick*/
4379 if (phy_reset(dev, bmcr)) {
4380 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4381 return -EINVAL;
4382 }
4383 } else {
4384 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4385 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4386 }
4387
4388 if (netif_running(dev)) {
4389 nv_start_rxtx(dev);
4390 nv_enable_irq(dev);
4391 }
4392 ret = 0;
4393 } else {
4394 ret = -EINVAL;
4395 }
4396
4397 return ret;
4398 }
4399
4400 static int nv_set_tso(struct net_device *dev, u32 value)
4401 {
4402 struct fe_priv *np = netdev_priv(dev);
4403
4404 if ((np->driver_data & DEV_HAS_CHECKSUM))
4405 return ethtool_op_set_tso(dev, value);
4406 else
4407 return -EOPNOTSUPP;
4408 }
4409
4410 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4411 {
4412 struct fe_priv *np = netdev_priv(dev);
4413
4414 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4415 ring->rx_mini_max_pending = 0;
4416 ring->rx_jumbo_max_pending = 0;
4417 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4418
4419 ring->rx_pending = np->rx_ring_size;
4420 ring->rx_mini_pending = 0;
4421 ring->rx_jumbo_pending = 0;
4422 ring->tx_pending = np->tx_ring_size;
4423 }
4424
4425 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4426 {
4427 struct fe_priv *np = netdev_priv(dev);
4428 u8 __iomem *base = get_hwbase(dev);
4429 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4430 dma_addr_t ring_addr;
4431
4432 if (ring->rx_pending < RX_RING_MIN ||
4433 ring->tx_pending < TX_RING_MIN ||
4434 ring->rx_mini_pending != 0 ||
4435 ring->rx_jumbo_pending != 0 ||
4436 (np->desc_ver == DESC_VER_1 &&
4437 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4438 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4439 (np->desc_ver != DESC_VER_1 &&
4440 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4441 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4442 return -EINVAL;
4443 }
4444
4445 /* allocate new rings */
4446 if (!nv_optimized(np)) {
4447 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4448 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4449 &ring_addr);
4450 } else {
4451 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4452 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4453 &ring_addr);
4454 }
4455 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4456 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4457 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4458 /* fall back to old rings */
4459 if (!nv_optimized(np)) {
4460 if (rxtx_ring)
4461 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4462 rxtx_ring, ring_addr);
4463 } else {
4464 if (rxtx_ring)
4465 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4466 rxtx_ring, ring_addr);
4467 }
4468 if (rx_skbuff)
4469 kfree(rx_skbuff);
4470 if (tx_skbuff)
4471 kfree(tx_skbuff);
4472 goto exit;
4473 }
4474
4475 if (netif_running(dev)) {
4476 nv_disable_irq(dev);
4477 nv_napi_disable(dev);
4478 netif_tx_lock_bh(dev);
4479 netif_addr_lock(dev);
4480 spin_lock(&np->lock);
4481 /* stop engines */
4482 nv_stop_rxtx(dev);
4483 nv_txrx_reset(dev);
4484 /* drain queues */
4485 nv_drain_rxtx(dev);
4486 /* delete queues */
4487 free_rings(dev);
4488 }
4489
4490 /* set new values */
4491 np->rx_ring_size = ring->rx_pending;
4492 np->tx_ring_size = ring->tx_pending;
4493
4494 if (!nv_optimized(np)) {
4495 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4496 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4497 } else {
4498 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4499 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4500 }
4501 np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4502 np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4503 np->ring_addr = ring_addr;
4504
4505 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4506 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4507
4508 if (netif_running(dev)) {
4509 /* reinit driver view of the queues */
4510 set_bufsize(dev);
4511 if (nv_init_ring(dev)) {
4512 if (!np->in_shutdown)
4513 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4514 }
4515
4516 /* reinit nic view of the queues */
4517 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4518 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4519 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4520 base + NvRegRingSizes);
4521 pci_push(base);
4522 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4523 pci_push(base);
4524
4525 /* restart engines */
4526 nv_start_rxtx(dev);
4527 spin_unlock(&np->lock);
4528 netif_addr_unlock(dev);
4529 netif_tx_unlock_bh(dev);
4530 nv_napi_enable(dev);
4531 nv_enable_irq(dev);
4532 }
4533 return 0;
4534 exit:
4535 return -ENOMEM;
4536 }
4537
4538 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4539 {
4540 struct fe_priv *np = netdev_priv(dev);
4541
4542 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4543 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4544 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4545 }
4546
4547 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4548 {
4549 struct fe_priv *np = netdev_priv(dev);
4550 int adv, bmcr;
4551
4552 if ((!np->autoneg && np->duplex == 0) ||
4553 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4554 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4555 dev->name);
4556 return -EINVAL;
4557 }
4558 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4559 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4560 return -EINVAL;
4561 }
4562
4563 netif_carrier_off(dev);
4564 if (netif_running(dev)) {
4565 nv_disable_irq(dev);
4566 netif_tx_lock_bh(dev);
4567 netif_addr_lock(dev);
4568 spin_lock(&np->lock);
4569 /* stop engines */
4570 nv_stop_rxtx(dev);
4571 spin_unlock(&np->lock);
4572 netif_addr_unlock(dev);
4573 netif_tx_unlock_bh(dev);
4574 }
4575
4576 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4577 if (pause->rx_pause)
4578 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4579 if (pause->tx_pause)
4580 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4581
4582 if (np->autoneg && pause->autoneg) {
4583 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4584
4585 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4586 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4587 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4588 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4589 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4590 adv |= ADVERTISE_PAUSE_ASYM;
4591 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4592
4593 if (netif_running(dev))
4594 printk(KERN_INFO "%s: link down.\n", dev->name);
4595 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4596 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4597 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4598 } else {
4599 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4600 if (pause->rx_pause)
4601 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4602 if (pause->tx_pause)
4603 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4604
4605 if (!netif_running(dev))
4606 nv_update_linkspeed(dev);
4607 else
4608 nv_update_pause(dev, np->pause_flags);
4609 }
4610
4611 if (netif_running(dev)) {
4612 nv_start_rxtx(dev);
4613 nv_enable_irq(dev);
4614 }
4615 return 0;
4616 }
4617
4618 static u32 nv_get_rx_csum(struct net_device *dev)
4619 {
4620 struct fe_priv *np = netdev_priv(dev);
4621 return (np->rx_csum) != 0;
4622 }
4623
4624 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4625 {
4626 struct fe_priv *np = netdev_priv(dev);
4627 u8 __iomem *base = get_hwbase(dev);
4628 int retcode = 0;
4629
4630 if (np->driver_data & DEV_HAS_CHECKSUM) {
4631 if (data) {
4632 np->rx_csum = 1;
4633 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4634 } else {
4635 np->rx_csum = 0;
4636 /* vlan is dependent on rx checksum offload */
4637 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4638 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4639 }
4640 if (netif_running(dev)) {
4641 spin_lock_irq(&np->lock);
4642 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4643 spin_unlock_irq(&np->lock);
4644 }
4645 } else {
4646 return -EINVAL;
4647 }
4648
4649 return retcode;
4650 }
4651
4652 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4653 {
4654 struct fe_priv *np = netdev_priv(dev);
4655
4656 if (np->driver_data & DEV_HAS_CHECKSUM)
4657 return ethtool_op_set_tx_csum(dev, data);
4658 else
4659 return -EOPNOTSUPP;
4660 }
4661
4662 static int nv_set_sg(struct net_device *dev, u32 data)
4663 {
4664 struct fe_priv *np = netdev_priv(dev);
4665
4666 if (np->driver_data & DEV_HAS_CHECKSUM)
4667 return ethtool_op_set_sg(dev, data);
4668 else
4669 return -EOPNOTSUPP;
4670 }
4671
4672 static int nv_get_sset_count(struct net_device *dev, int sset)
4673 {
4674 struct fe_priv *np = netdev_priv(dev);
4675
4676 switch (sset) {
4677 case ETH_SS_TEST:
4678 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4679 return NV_TEST_COUNT_EXTENDED;
4680 else
4681 return NV_TEST_COUNT_BASE;
4682 case ETH_SS_STATS:
4683 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4684 return NV_DEV_STATISTICS_V3_COUNT;
4685 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4686 return NV_DEV_STATISTICS_V2_COUNT;
4687 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4688 return NV_DEV_STATISTICS_V1_COUNT;
4689 else
4690 return 0;
4691 default:
4692 return -EOPNOTSUPP;
4693 }
4694 }
4695
4696 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4697 {
4698 struct fe_priv *np = netdev_priv(dev);
4699
4700 /* update stats */
4701 nv_do_stats_poll((unsigned long)dev);
4702
4703 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4704 }
4705
4706 static int nv_link_test(struct net_device *dev)
4707 {
4708 struct fe_priv *np = netdev_priv(dev);
4709 int mii_status;
4710
4711 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4712 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4713
4714 /* check phy link status */
4715 if (!(mii_status & BMSR_LSTATUS))
4716 return 0;
4717 else
4718 return 1;
4719 }
4720
4721 static int nv_register_test(struct net_device *dev)
4722 {
4723 u8 __iomem *base = get_hwbase(dev);
4724 int i = 0;
4725 u32 orig_read, new_read;
4726
4727 do {
4728 orig_read = readl(base + nv_registers_test[i].reg);
4729
4730 /* xor with mask to toggle bits */
4731 orig_read ^= nv_registers_test[i].mask;
4732
4733 writel(orig_read, base + nv_registers_test[i].reg);
4734
4735 new_read = readl(base + nv_registers_test[i].reg);
4736
4737 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4738 return 0;
4739
4740 /* restore original value */
4741 orig_read ^= nv_registers_test[i].mask;
4742 writel(orig_read, base + nv_registers_test[i].reg);
4743
4744 } while (nv_registers_test[++i].reg != 0);
4745
4746 return 1;
4747 }
4748
4749 static int nv_interrupt_test(struct net_device *dev)
4750 {
4751 struct fe_priv *np = netdev_priv(dev);
4752 u8 __iomem *base = get_hwbase(dev);
4753 int ret = 1;
4754 int testcnt;
4755 u32 save_msi_flags, save_poll_interval = 0;
4756
4757 if (netif_running(dev)) {
4758 /* free current irq */
4759 nv_free_irq(dev);
4760 save_poll_interval = readl(base+NvRegPollingInterval);
4761 }
4762
4763 /* flag to test interrupt handler */
4764 np->intr_test = 0;
4765
4766 /* setup test irq */
4767 save_msi_flags = np->msi_flags;
4768 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4769 np->msi_flags |= 0x001; /* setup 1 vector */
4770 if (nv_request_irq(dev, 1))
4771 return 0;
4772
4773 /* setup timer interrupt */
4774 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4775 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4776
4777 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4778
4779 /* wait for at least one interrupt */
4780 msleep(100);
4781
4782 spin_lock_irq(&np->lock);
4783
4784 /* flag should be set within ISR */
4785 testcnt = np->intr_test;
4786 if (!testcnt)
4787 ret = 2;
4788
4789 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4790 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4791 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4792 else
4793 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4794
4795 spin_unlock_irq(&np->lock);
4796
4797 nv_free_irq(dev);
4798
4799 np->msi_flags = save_msi_flags;
4800
4801 if (netif_running(dev)) {
4802 writel(save_poll_interval, base + NvRegPollingInterval);
4803 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4804 /* restore original irq */
4805 if (nv_request_irq(dev, 0))
4806 return 0;
4807 }
4808
4809 return ret;
4810 }
4811
4812 static int nv_loopback_test(struct net_device *dev)
4813 {
4814 struct fe_priv *np = netdev_priv(dev);
4815 u8 __iomem *base = get_hwbase(dev);
4816 struct sk_buff *tx_skb, *rx_skb;
4817 dma_addr_t test_dma_addr;
4818 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4819 u32 flags;
4820 int len, i, pkt_len;
4821 u8 *pkt_data;
4822 u32 filter_flags = 0;
4823 u32 misc1_flags = 0;
4824 int ret = 1;
4825
4826 if (netif_running(dev)) {
4827 nv_disable_irq(dev);
4828 filter_flags = readl(base + NvRegPacketFilterFlags);
4829 misc1_flags = readl(base + NvRegMisc1);
4830 } else {
4831 nv_txrx_reset(dev);
4832 }
4833
4834 /* reinit driver view of the rx queue */
4835 set_bufsize(dev);
4836 nv_init_ring(dev);
4837
4838 /* setup hardware for loopback */
4839 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4840 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4841
4842 /* reinit nic view of the rx queue */
4843 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4844 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4845 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4846 base + NvRegRingSizes);
4847 pci_push(base);
4848
4849 /* restart rx engine */
4850 nv_start_rxtx(dev);
4851
4852 /* setup packet for tx */
4853 pkt_len = ETH_DATA_LEN;
4854 tx_skb = dev_alloc_skb(pkt_len);
4855 if (!tx_skb) {
4856 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4857 " of %s\n", dev->name);
4858 ret = 0;
4859 goto out;
4860 }
4861 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4862 skb_tailroom(tx_skb),
4863 PCI_DMA_FROMDEVICE);
4864 pkt_data = skb_put(tx_skb, pkt_len);
4865 for (i = 0; i < pkt_len; i++)
4866 pkt_data[i] = (u8)(i & 0xff);
4867
4868 if (!nv_optimized(np)) {
4869 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4870 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4871 } else {
4872 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4873 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4874 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4875 }
4876 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4877 pci_push(get_hwbase(dev));
4878
4879 msleep(500);
4880
4881 /* check for rx of the packet */
4882 if (!nv_optimized(np)) {
4883 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4884 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4885
4886 } else {
4887 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4888 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4889 }
4890
4891 if (flags & NV_RX_AVAIL) {
4892 ret = 0;
4893 } else if (np->desc_ver == DESC_VER_1) {
4894 if (flags & NV_RX_ERROR)
4895 ret = 0;
4896 } else {
4897 if (flags & NV_RX2_ERROR) {
4898 ret = 0;
4899 }
4900 }
4901
4902 if (ret) {
4903 if (len != pkt_len) {
4904 ret = 0;
4905 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4906 dev->name, len, pkt_len);
4907 } else {
4908 rx_skb = np->rx_skb[0].skb;
4909 for (i = 0; i < pkt_len; i++) {
4910 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4911 ret = 0;
4912 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4913 dev->name, i);
4914 break;
4915 }
4916 }
4917 }
4918 } else {
4919 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4920 }
4921
4922 pci_unmap_single(np->pci_dev, test_dma_addr,
4923 (skb_end_pointer(tx_skb) - tx_skb->data),
4924 PCI_DMA_TODEVICE);
4925 dev_kfree_skb_any(tx_skb);
4926 out:
4927 /* stop engines */
4928 nv_stop_rxtx(dev);
4929 nv_txrx_reset(dev);
4930 /* drain rx queue */
4931 nv_drain_rxtx(dev);
4932
4933 if (netif_running(dev)) {
4934 writel(misc1_flags, base + NvRegMisc1);
4935 writel(filter_flags, base + NvRegPacketFilterFlags);
4936 nv_enable_irq(dev);
4937 }
4938
4939 return ret;
4940 }
4941
4942 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4943 {
4944 struct fe_priv *np = netdev_priv(dev);
4945 u8 __iomem *base = get_hwbase(dev);
4946 int result;
4947 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4948
4949 if (!nv_link_test(dev)) {
4950 test->flags |= ETH_TEST_FL_FAILED;
4951 buffer[0] = 1;
4952 }
4953
4954 if (test->flags & ETH_TEST_FL_OFFLINE) {
4955 if (netif_running(dev)) {
4956 netif_stop_queue(dev);
4957 nv_napi_disable(dev);
4958 netif_tx_lock_bh(dev);
4959 netif_addr_lock(dev);
4960 spin_lock_irq(&np->lock);
4961 nv_disable_hw_interrupts(dev, np->irqmask);
4962 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4963 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4964 } else {
4965 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4966 }
4967 /* stop engines */
4968 nv_stop_rxtx(dev);
4969 nv_txrx_reset(dev);
4970 /* drain rx queue */
4971 nv_drain_rxtx(dev);
4972 spin_unlock_irq(&np->lock);
4973 netif_addr_unlock(dev);
4974 netif_tx_unlock_bh(dev);
4975 }
4976
4977 if (!nv_register_test(dev)) {
4978 test->flags |= ETH_TEST_FL_FAILED;
4979 buffer[1] = 1;
4980 }
4981
4982 result = nv_interrupt_test(dev);
4983 if (result != 1) {
4984 test->flags |= ETH_TEST_FL_FAILED;
4985 buffer[2] = 1;
4986 }
4987 if (result == 0) {
4988 /* bail out */
4989 return;
4990 }
4991
4992 if (!nv_loopback_test(dev)) {
4993 test->flags |= ETH_TEST_FL_FAILED;
4994 buffer[3] = 1;
4995 }
4996
4997 if (netif_running(dev)) {
4998 /* reinit driver view of the rx queue */
4999 set_bufsize(dev);
5000 if (nv_init_ring(dev)) {
5001 if (!np->in_shutdown)
5002 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5003 }
5004 /* reinit nic view of the rx queue */
5005 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5006 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5007 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5008 base + NvRegRingSizes);
5009 pci_push(base);
5010 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5011 pci_push(base);
5012 /* restart rx engine */
5013 nv_start_rxtx(dev);
5014 netif_start_queue(dev);
5015 nv_napi_enable(dev);
5016 nv_enable_hw_interrupts(dev, np->irqmask);
5017 }
5018 }
5019 }
5020
5021 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5022 {
5023 switch (stringset) {
5024 case ETH_SS_STATS:
5025 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5026 break;
5027 case ETH_SS_TEST:
5028 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5029 break;
5030 }
5031 }
5032
5033 static const struct ethtool_ops ops = {
5034 .get_drvinfo = nv_get_drvinfo,
5035 .get_link = ethtool_op_get_link,
5036 .get_wol = nv_get_wol,
5037 .set_wol = nv_set_wol,
5038 .get_settings = nv_get_settings,
5039 .set_settings = nv_set_settings,
5040 .get_regs_len = nv_get_regs_len,
5041 .get_regs = nv_get_regs,
5042 .nway_reset = nv_nway_reset,
5043 .set_tso = nv_set_tso,
5044 .get_ringparam = nv_get_ringparam,
5045 .set_ringparam = nv_set_ringparam,
5046 .get_pauseparam = nv_get_pauseparam,
5047 .set_pauseparam = nv_set_pauseparam,
5048 .get_rx_csum = nv_get_rx_csum,
5049 .set_rx_csum = nv_set_rx_csum,
5050 .set_tx_csum = nv_set_tx_csum,
5051 .set_sg = nv_set_sg,
5052 .get_strings = nv_get_strings,
5053 .get_ethtool_stats = nv_get_ethtool_stats,
5054 .get_sset_count = nv_get_sset_count,
5055 .self_test = nv_self_test,
5056 };
5057
5058 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
5059 {
5060 struct fe_priv *np = get_nvpriv(dev);
5061
5062 spin_lock_irq(&np->lock);
5063
5064 /* save vlan group */
5065 np->vlangrp = grp;
5066
5067 if (grp) {
5068 /* enable vlan on MAC */
5069 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
5070 } else {
5071 /* disable vlan on MAC */
5072 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
5073 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
5074 }
5075
5076 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5077
5078 spin_unlock_irq(&np->lock);
5079 }
5080
5081 /* The mgmt unit and driver use a semaphore to access the phy during init */
5082 static int nv_mgmt_acquire_sema(struct net_device *dev)
5083 {
5084 struct fe_priv *np = netdev_priv(dev);
5085 u8 __iomem *base = get_hwbase(dev);
5086 int i;
5087 u32 tx_ctrl, mgmt_sema;
5088
5089 for (i = 0; i < 10; i++) {
5090 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5091 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5092 break;
5093 msleep(500);
5094 }
5095
5096 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5097 return 0;
5098
5099 for (i = 0; i < 2; i++) {
5100 tx_ctrl = readl(base + NvRegTransmitterControl);
5101 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5102 writel(tx_ctrl, base + NvRegTransmitterControl);
5103
5104 /* verify that semaphore was acquired */
5105 tx_ctrl = readl(base + NvRegTransmitterControl);
5106 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5107 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5108 np->mgmt_sema = 1;
5109 return 1;
5110 }
5111 else
5112 udelay(50);
5113 }
5114
5115 return 0;
5116 }
5117
5118 static void nv_mgmt_release_sema(struct net_device *dev)
5119 {
5120 struct fe_priv *np = netdev_priv(dev);
5121 u8 __iomem *base = get_hwbase(dev);
5122 u32 tx_ctrl;
5123
5124 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5125 if (np->mgmt_sema) {
5126 tx_ctrl = readl(base + NvRegTransmitterControl);
5127 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5128 writel(tx_ctrl, base + NvRegTransmitterControl);
5129 }
5130 }
5131 }
5132
5133
5134 static int nv_mgmt_get_version(struct net_device *dev)
5135 {
5136 struct fe_priv *np = netdev_priv(dev);
5137 u8 __iomem *base = get_hwbase(dev);
5138 u32 data_ready = readl(base + NvRegTransmitterControl);
5139 u32 data_ready2 = 0;
5140 unsigned long start;
5141 int ready = 0;
5142
5143 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5144 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5145 start = jiffies;
5146 while (time_before(jiffies, start + 5*HZ)) {
5147 data_ready2 = readl(base + NvRegTransmitterControl);
5148 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5149 ready = 1;
5150 break;
5151 }
5152 schedule_timeout_uninterruptible(1);
5153 }
5154
5155 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5156 return 0;
5157
5158 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5159
5160 return 1;
5161 }
5162
5163 static int nv_open(struct net_device *dev)
5164 {
5165 struct fe_priv *np = netdev_priv(dev);
5166 u8 __iomem *base = get_hwbase(dev);
5167 int ret = 1;
5168 int oom, i;
5169 u32 low;
5170
5171 dprintk(KERN_DEBUG "nv_open: begin\n");
5172
5173 /* power up phy */
5174 mii_rw(dev, np->phyaddr, MII_BMCR,
5175 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5176
5177 nv_txrx_gate(dev, false);
5178 /* erase previous misconfiguration */
5179 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5180 nv_mac_reset(dev);
5181 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5182 writel(0, base + NvRegMulticastAddrB);
5183 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5184 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5185 writel(0, base + NvRegPacketFilterFlags);
5186
5187 writel(0, base + NvRegTransmitterControl);
5188 writel(0, base + NvRegReceiverControl);
5189
5190 writel(0, base + NvRegAdapterControl);
5191
5192 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5193 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5194
5195 /* initialize descriptor rings */
5196 set_bufsize(dev);
5197 oom = nv_init_ring(dev);
5198
5199 writel(0, base + NvRegLinkSpeed);
5200 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5201 nv_txrx_reset(dev);
5202 writel(0, base + NvRegUnknownSetupReg6);
5203
5204 np->in_shutdown = 0;
5205
5206 /* give hw rings */
5207 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5208 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5209 base + NvRegRingSizes);
5210
5211 writel(np->linkspeed, base + NvRegLinkSpeed);
5212 if (np->desc_ver == DESC_VER_1)
5213 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5214 else
5215 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5216 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5217 writel(np->vlanctl_bits, base + NvRegVlanControl);
5218 pci_push(base);
5219 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5220 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5221 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
5222 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
5223
5224 writel(0, base + NvRegMIIMask);
5225 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5226 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5227
5228 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5229 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5230 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5231 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5232
5233 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5234
5235 get_random_bytes(&low, sizeof(low));
5236 low &= NVREG_SLOTTIME_MASK;
5237 if (np->desc_ver == DESC_VER_1) {
5238 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5239 } else {
5240 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5241 /* setup legacy backoff */
5242 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5243 } else {
5244 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5245 nv_gear_backoff_reseed(dev);
5246 }
5247 }
5248 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5249 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5250 if (poll_interval == -1) {
5251 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5252 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5253 else
5254 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5255 }
5256 else
5257 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5258 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5259 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5260 base + NvRegAdapterControl);
5261 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5262 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5263 if (np->wolenabled)
5264 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5265
5266 i = readl(base + NvRegPowerState);
5267 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5268 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5269
5270 pci_push(base);
5271 udelay(10);
5272 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5273
5274 nv_disable_hw_interrupts(dev, np->irqmask);
5275 pci_push(base);
5276 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5277 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5278 pci_push(base);
5279
5280 if (nv_request_irq(dev, 0)) {
5281 goto out_drain;
5282 }
5283
5284 /* ask for interrupts */
5285 nv_enable_hw_interrupts(dev, np->irqmask);
5286
5287 spin_lock_irq(&np->lock);
5288 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5289 writel(0, base + NvRegMulticastAddrB);
5290 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5291 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5292 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5293 /* One manual link speed update: Interrupts are enabled, future link
5294 * speed changes cause interrupts and are handled by nv_link_irq().
5295 */
5296 {
5297 u32 miistat;
5298 miistat = readl(base + NvRegMIIStatus);
5299 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5300 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5301 }
5302 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5303 * to init hw */
5304 np->linkspeed = 0;
5305 ret = nv_update_linkspeed(dev);
5306 nv_start_rxtx(dev);
5307 netif_start_queue(dev);
5308 nv_napi_enable(dev);
5309
5310 if (ret) {
5311 netif_carrier_on(dev);
5312 } else {
5313 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5314 netif_carrier_off(dev);
5315 }
5316 if (oom)
5317 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5318
5319 /* start statistics timer */
5320 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5321 mod_timer(&np->stats_poll,
5322 round_jiffies(jiffies + STATS_INTERVAL));
5323
5324 spin_unlock_irq(&np->lock);
5325
5326 return 0;
5327 out_drain:
5328 nv_drain_rxtx(dev);
5329 return ret;
5330 }
5331
5332 static int nv_close(struct net_device *dev)
5333 {
5334 struct fe_priv *np = netdev_priv(dev);
5335 u8 __iomem *base;
5336
5337 spin_lock_irq(&np->lock);
5338 np->in_shutdown = 1;
5339 spin_unlock_irq(&np->lock);
5340 nv_napi_disable(dev);
5341 synchronize_irq(np->pci_dev->irq);
5342
5343 del_timer_sync(&np->oom_kick);
5344 del_timer_sync(&np->nic_poll);
5345 del_timer_sync(&np->stats_poll);
5346
5347 netif_stop_queue(dev);
5348 spin_lock_irq(&np->lock);
5349 nv_stop_rxtx(dev);
5350 nv_txrx_reset(dev);
5351
5352 /* disable interrupts on the nic or we will lock up */
5353 base = get_hwbase(dev);
5354 nv_disable_hw_interrupts(dev, np->irqmask);
5355 pci_push(base);
5356 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5357
5358 spin_unlock_irq(&np->lock);
5359
5360 nv_free_irq(dev);
5361
5362 nv_drain_rxtx(dev);
5363
5364 if (np->wolenabled || !phy_power_down) {
5365 nv_txrx_gate(dev, false);
5366 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5367 nv_start_rx(dev);
5368 } else {
5369 /* power down phy */
5370 mii_rw(dev, np->phyaddr, MII_BMCR,
5371 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5372 nv_txrx_gate(dev, true);
5373 }
5374
5375 /* FIXME: power down nic */
5376
5377 return 0;
5378 }
5379
5380 static const struct net_device_ops nv_netdev_ops = {
5381 .ndo_open = nv_open,
5382 .ndo_stop = nv_close,
5383 .ndo_get_stats = nv_get_stats,
5384 .ndo_start_xmit = nv_start_xmit,
5385 .ndo_tx_timeout = nv_tx_timeout,
5386 .ndo_change_mtu = nv_change_mtu,
5387 .ndo_validate_addr = eth_validate_addr,
5388 .ndo_set_mac_address = nv_set_mac_address,
5389 .ndo_set_multicast_list = nv_set_multicast,
5390 .ndo_vlan_rx_register = nv_vlan_rx_register,
5391 #ifdef CONFIG_NET_POLL_CONTROLLER
5392 .ndo_poll_controller = nv_poll_controller,
5393 #endif
5394 };
5395
5396 static const struct net_device_ops nv_netdev_ops_optimized = {
5397 .ndo_open = nv_open,
5398 .ndo_stop = nv_close,
5399 .ndo_get_stats = nv_get_stats,
5400 .ndo_start_xmit = nv_start_xmit_optimized,
5401 .ndo_tx_timeout = nv_tx_timeout,
5402 .ndo_change_mtu = nv_change_mtu,
5403 .ndo_validate_addr = eth_validate_addr,
5404 .ndo_set_mac_address = nv_set_mac_address,
5405 .ndo_set_multicast_list = nv_set_multicast,
5406 .ndo_vlan_rx_register = nv_vlan_rx_register,
5407 #ifdef CONFIG_NET_POLL_CONTROLLER
5408 .ndo_poll_controller = nv_poll_controller,
5409 #endif
5410 };
5411
5412 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5413 {
5414 struct net_device *dev;
5415 struct fe_priv *np;
5416 unsigned long addr;
5417 u8 __iomem *base;
5418 int err, i;
5419 u32 powerstate, txreg;
5420 u32 phystate_orig = 0, phystate;
5421 int phyinitialized = 0;
5422 static int printed_version;
5423
5424 if (!printed_version++)
5425 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5426 " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5427
5428 dev = alloc_etherdev(sizeof(struct fe_priv));
5429 err = -ENOMEM;
5430 if (!dev)
5431 goto out;
5432
5433 np = netdev_priv(dev);
5434 np->dev = dev;
5435 np->pci_dev = pci_dev;
5436 spin_lock_init(&np->lock);
5437 SET_NETDEV_DEV(dev, &pci_dev->dev);
5438
5439 init_timer(&np->oom_kick);
5440 np->oom_kick.data = (unsigned long) dev;
5441 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
5442 init_timer(&np->nic_poll);
5443 np->nic_poll.data = (unsigned long) dev;
5444 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
5445 init_timer(&np->stats_poll);
5446 np->stats_poll.data = (unsigned long) dev;
5447 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
5448
5449 err = pci_enable_device(pci_dev);
5450 if (err)
5451 goto out_free;
5452
5453 pci_set_master(pci_dev);
5454
5455 err = pci_request_regions(pci_dev, DRV_NAME);
5456 if (err < 0)
5457 goto out_disable;
5458
5459 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5460 np->register_size = NV_PCI_REGSZ_VER3;
5461 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5462 np->register_size = NV_PCI_REGSZ_VER2;
5463 else
5464 np->register_size = NV_PCI_REGSZ_VER1;
5465
5466 err = -EINVAL;
5467 addr = 0;
5468 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5469 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5470 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5471 pci_resource_len(pci_dev, i),
5472 pci_resource_flags(pci_dev, i));
5473 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5474 pci_resource_len(pci_dev, i) >= np->register_size) {
5475 addr = pci_resource_start(pci_dev, i);
5476 break;
5477 }
5478 }
5479 if (i == DEVICE_COUNT_RESOURCE) {
5480 dev_printk(KERN_INFO, &pci_dev->dev,
5481 "Couldn't find register window\n");
5482 goto out_relreg;
5483 }
5484
5485 /* copy of driver data */
5486 np->driver_data = id->driver_data;
5487 /* copy of device id */
5488 np->device_id = id->device;
5489
5490 /* handle different descriptor versions */
5491 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5492 /* packet format 3: supports 40-bit addressing */
5493 np->desc_ver = DESC_VER_3;
5494 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5495 if (dma_64bit) {
5496 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5497 dev_printk(KERN_INFO, &pci_dev->dev,
5498 "64-bit DMA failed, using 32-bit addressing\n");
5499 else
5500 dev->features |= NETIF_F_HIGHDMA;
5501 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5502 dev_printk(KERN_INFO, &pci_dev->dev,
5503 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5504 }
5505 }
5506 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5507 /* packet format 2: supports jumbo frames */
5508 np->desc_ver = DESC_VER_2;
5509 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5510 } else {
5511 /* original packet format */
5512 np->desc_ver = DESC_VER_1;
5513 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5514 }
5515
5516 np->pkt_limit = NV_PKTLIMIT_1;
5517 if (id->driver_data & DEV_HAS_LARGEDESC)
5518 np->pkt_limit = NV_PKTLIMIT_2;
5519
5520 if (id->driver_data & DEV_HAS_CHECKSUM) {
5521 np->rx_csum = 1;
5522 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5523 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
5524 dev->features |= NETIF_F_TSO;
5525 dev->features |= NETIF_F_GRO;
5526 }
5527
5528 np->vlanctl_bits = 0;
5529 if (id->driver_data & DEV_HAS_VLAN) {
5530 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5531 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5532 }
5533
5534 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5535 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5536 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5537 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5538 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5539 }
5540
5541
5542 err = -ENOMEM;
5543 np->base = ioremap(addr, np->register_size);
5544 if (!np->base)
5545 goto out_relreg;
5546 dev->base_addr = (unsigned long)np->base;
5547
5548 dev->irq = pci_dev->irq;
5549
5550 np->rx_ring_size = RX_RING_DEFAULT;
5551 np->tx_ring_size = TX_RING_DEFAULT;
5552
5553 if (!nv_optimized(np)) {
5554 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5555 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5556 &np->ring_addr);
5557 if (!np->rx_ring.orig)
5558 goto out_unmap;
5559 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5560 } else {
5561 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5562 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5563 &np->ring_addr);
5564 if (!np->rx_ring.ex)
5565 goto out_unmap;
5566 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5567 }
5568 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5569 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5570 if (!np->rx_skb || !np->tx_skb)
5571 goto out_freering;
5572
5573 if (!nv_optimized(np))
5574 dev->netdev_ops = &nv_netdev_ops;
5575 else
5576 dev->netdev_ops = &nv_netdev_ops_optimized;
5577
5578 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5579 SET_ETHTOOL_OPS(dev, &ops);
5580 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5581
5582 pci_set_drvdata(pci_dev, dev);
5583
5584 /* read the mac address */
5585 base = get_hwbase(dev);
5586 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5587 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5588
5589 /* check the workaround bit for correct mac address order */
5590 txreg = readl(base + NvRegTransmitPoll);
5591 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5592 /* mac address is already in correct order */
5593 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5594 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5595 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5596 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5597 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5598 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5599 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5600 /* mac address is already in correct order */
5601 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5602 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5603 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5604 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5605 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5606 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5607 /*
5608 * Set orig mac address back to the reversed version.
5609 * This flag will be cleared during low power transition.
5610 * Therefore, we should always put back the reversed address.
5611 */
5612 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5613 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5614 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5615 } else {
5616 /* need to reverse mac address to correct order */
5617 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5618 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5619 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5620 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5621 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5622 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5623 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5624 printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
5625 }
5626 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5627
5628 if (!is_valid_ether_addr(dev->perm_addr)) {
5629 /*
5630 * Bad mac address. At least one bios sets the mac address
5631 * to 01:23:45:67:89:ab
5632 */
5633 dev_printk(KERN_ERR, &pci_dev->dev,
5634 "Invalid Mac address detected: %pM\n",
5635 dev->dev_addr);
5636 dev_printk(KERN_ERR, &pci_dev->dev,
5637 "Please complain to your hardware vendor. Switching to a random MAC.\n");
5638 random_ether_addr(dev->dev_addr);
5639 }
5640
5641 dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
5642 pci_name(pci_dev), dev->dev_addr);
5643
5644 /* set mac address */
5645 nv_copy_mac_to_hw(dev);
5646
5647 /* Workaround current PCI init glitch: wakeup bits aren't
5648 * being set from PCI PM capability.
5649 */
5650 device_init_wakeup(&pci_dev->dev, 1);
5651
5652 /* disable WOL */
5653 writel(0, base + NvRegWakeUpFlags);
5654 np->wolenabled = 0;
5655
5656 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5657
5658 /* take phy and nic out of low power mode */
5659 powerstate = readl(base + NvRegPowerState2);
5660 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5661 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5662 pci_dev->revision >= 0xA3)
5663 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5664 writel(powerstate, base + NvRegPowerState2);
5665 }
5666
5667 if (np->desc_ver == DESC_VER_1) {
5668 np->tx_flags = NV_TX_VALID;
5669 } else {
5670 np->tx_flags = NV_TX2_VALID;
5671 }
5672
5673 np->msi_flags = 0;
5674 if ((id->driver_data & DEV_HAS_MSI) && msi) {
5675 np->msi_flags |= NV_MSI_CAPABLE;
5676 }
5677 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5678 /* msix has had reported issues when modifying irqmask
5679 as in the case of napi, therefore, disable for now
5680 */
5681 #if 0
5682 np->msi_flags |= NV_MSI_X_CAPABLE;
5683 #endif
5684 }
5685
5686 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5687 np->irqmask = NVREG_IRQMASK_CPU;
5688 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5689 np->msi_flags |= 0x0001;
5690 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5691 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5692 /* start off in throughput mode */
5693 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5694 /* remove support for msix mode */
5695 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5696 } else {
5697 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5698 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5699 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5700 np->msi_flags |= 0x0003;
5701 }
5702
5703 if (id->driver_data & DEV_NEED_TIMERIRQ)
5704 np->irqmask |= NVREG_IRQ_TIMER;
5705 if (id->driver_data & DEV_NEED_LINKTIMER) {
5706 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5707 np->need_linktimer = 1;
5708 np->link_timeout = jiffies + LINK_TIMEOUT;
5709 } else {
5710 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5711 np->need_linktimer = 0;
5712 }
5713
5714 /* Limit the number of tx's outstanding for hw bug */
5715 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5716 np->tx_limit = 1;
5717 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5718 pci_dev->revision >= 0xA2)
5719 np->tx_limit = 0;
5720 }
5721
5722 /* clear phy state and temporarily halt phy interrupts */
5723 writel(0, base + NvRegMIIMask);
5724 phystate = readl(base + NvRegAdapterControl);
5725 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5726 phystate_orig = 1;
5727 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5728 writel(phystate, base + NvRegAdapterControl);
5729 }
5730 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5731
5732 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5733 /* management unit running on the mac? */
5734 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5735 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5736 nv_mgmt_acquire_sema(dev) &&
5737 nv_mgmt_get_version(dev)) {
5738 np->mac_in_use = 1;
5739 if (np->mgmt_version > 0) {
5740 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5741 }
5742 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
5743 pci_name(pci_dev), np->mac_in_use);
5744 /* management unit setup the phy already? */
5745 if (np->mac_in_use &&
5746 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5747 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5748 /* phy is inited by mgmt unit */
5749 phyinitialized = 1;
5750 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
5751 pci_name(pci_dev));
5752 } else {
5753 /* we need to init the phy */
5754 }
5755 }
5756 }
5757
5758 /* find a suitable phy */
5759 for (i = 1; i <= 32; i++) {
5760 int id1, id2;
5761 int phyaddr = i & 0x1F;
5762
5763 spin_lock_irq(&np->lock);
5764 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5765 spin_unlock_irq(&np->lock);
5766 if (id1 < 0 || id1 == 0xffff)
5767 continue;
5768 spin_lock_irq(&np->lock);
5769 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5770 spin_unlock_irq(&np->lock);
5771 if (id2 < 0 || id2 == 0xffff)
5772 continue;
5773
5774 np->phy_model = id2 & PHYID2_MODEL_MASK;
5775 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5776 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5777 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5778 pci_name(pci_dev), id1, id2, phyaddr);
5779 np->phyaddr = phyaddr;
5780 np->phy_oui = id1 | id2;
5781
5782 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5783 if (np->phy_oui == PHY_OUI_REALTEK2)
5784 np->phy_oui = PHY_OUI_REALTEK;
5785 /* Setup phy revision for Realtek */
5786 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5787 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5788
5789 break;
5790 }
5791 if (i == 33) {
5792 dev_printk(KERN_INFO, &pci_dev->dev,
5793 "open: Could not find a valid PHY.\n");
5794 goto out_error;
5795 }
5796
5797 if (!phyinitialized) {
5798 /* reset it */
5799 phy_init(dev);
5800 } else {
5801 /* see if it is a gigabit phy */
5802 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5803 if (mii_status & PHY_GIGABIT) {
5804 np->gigabit = PHY_GIGABIT;
5805 }
5806 }
5807
5808 /* set default link speed settings */
5809 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5810 np->duplex = 0;
5811 np->autoneg = 1;
5812
5813 err = register_netdev(dev);
5814 if (err) {
5815 dev_printk(KERN_INFO, &pci_dev->dev,
5816 "unable to register netdev: %d\n", err);
5817 goto out_error;
5818 }
5819
5820 dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5821 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5822 dev->name,
5823 np->phy_oui,
5824 np->phyaddr,
5825 dev->dev_addr[0],
5826 dev->dev_addr[1],
5827 dev->dev_addr[2],
5828 dev->dev_addr[3],
5829 dev->dev_addr[4],
5830 dev->dev_addr[5]);
5831
5832 dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5833 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5834 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5835 "csum " : "",
5836 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5837 "vlan " : "",
5838 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5839 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5840 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5841 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5842 np->need_linktimer ? "lnktim " : "",
5843 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5844 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5845 np->desc_ver);
5846
5847 return 0;
5848
5849 out_error:
5850 if (phystate_orig)
5851 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5852 pci_set_drvdata(pci_dev, NULL);
5853 out_freering:
5854 free_rings(dev);
5855 out_unmap:
5856 iounmap(get_hwbase(dev));
5857 out_relreg:
5858 pci_release_regions(pci_dev);
5859 out_disable:
5860 pci_disable_device(pci_dev);
5861 out_free:
5862 free_netdev(dev);
5863 out:
5864 return err;
5865 }
5866
5867 static void nv_restore_phy(struct net_device *dev)
5868 {
5869 struct fe_priv *np = netdev_priv(dev);
5870 u16 phy_reserved, mii_control;
5871
5872 if (np->phy_oui == PHY_OUI_REALTEK &&
5873 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5874 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5875 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5876 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5877 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5878 phy_reserved |= PHY_REALTEK_INIT8;
5879 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5880 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5881
5882 /* restart auto negotiation */
5883 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5884 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5885 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5886 }
5887 }
5888
5889 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5890 {
5891 struct net_device *dev = pci_get_drvdata(pci_dev);
5892 struct fe_priv *np = netdev_priv(dev);
5893 u8 __iomem *base = get_hwbase(dev);
5894
5895 /* special op: write back the misordered MAC address - otherwise
5896 * the next nv_probe would see a wrong address.
5897 */
5898 writel(np->orig_mac[0], base + NvRegMacAddrA);
5899 writel(np->orig_mac[1], base + NvRegMacAddrB);
5900 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5901 base + NvRegTransmitPoll);
5902 }
5903
5904 static void __devexit nv_remove(struct pci_dev *pci_dev)
5905 {
5906 struct net_device *dev = pci_get_drvdata(pci_dev);
5907
5908 unregister_netdev(dev);
5909
5910 nv_restore_mac_addr(pci_dev);
5911
5912 /* restore any phy related changes */
5913 nv_restore_phy(dev);
5914
5915 nv_mgmt_release_sema(dev);
5916
5917 /* free all structures */
5918 free_rings(dev);
5919 iounmap(get_hwbase(dev));
5920 pci_release_regions(pci_dev);
5921 pci_disable_device(pci_dev);
5922 free_netdev(dev);
5923 pci_set_drvdata(pci_dev, NULL);
5924 }
5925
5926 #ifdef CONFIG_PM
5927 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5928 {
5929 struct net_device *dev = pci_get_drvdata(pdev);
5930 struct fe_priv *np = netdev_priv(dev);
5931 u8 __iomem *base = get_hwbase(dev);
5932 int i;
5933
5934 if (netif_running(dev)) {
5935 // Gross.
5936 nv_close(dev);
5937 }
5938 netif_device_detach(dev);
5939
5940 /* save non-pci configuration space */
5941 for (i = 0;i <= np->register_size/sizeof(u32); i++)
5942 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5943
5944 pci_save_state(pdev);
5945 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5946 pci_disable_device(pdev);
5947 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5948 return 0;
5949 }
5950
5951 static int nv_resume(struct pci_dev *pdev)
5952 {
5953 struct net_device *dev = pci_get_drvdata(pdev);
5954 struct fe_priv *np = netdev_priv(dev);
5955 u8 __iomem *base = get_hwbase(dev);
5956 int i, rc = 0;
5957
5958 pci_set_power_state(pdev, PCI_D0);
5959 pci_restore_state(pdev);
5960 /* ack any pending wake events, disable PME */
5961 pci_enable_wake(pdev, PCI_D0, 0);
5962
5963 /* restore non-pci configuration space */
5964 for (i = 0;i <= np->register_size/sizeof(u32); i++)
5965 writel(np->saved_config_space[i], base+i*sizeof(u32));
5966
5967 if (np->driver_data & DEV_NEED_MSI_FIX)
5968 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
5969
5970 /* restore phy state, including autoneg */
5971 phy_init(dev);
5972
5973 netif_device_attach(dev);
5974 if (netif_running(dev)) {
5975 rc = nv_open(dev);
5976 nv_set_multicast(dev);
5977 }
5978 return rc;
5979 }
5980
5981 static void nv_shutdown(struct pci_dev *pdev)
5982 {
5983 struct net_device *dev = pci_get_drvdata(pdev);
5984 struct fe_priv *np = netdev_priv(dev);
5985
5986 if (netif_running(dev))
5987 nv_close(dev);
5988
5989 /*
5990 * Restore the MAC so a kernel started by kexec won't get confused.
5991 * If we really go for poweroff, we must not restore the MAC,
5992 * otherwise the MAC for WOL will be reversed at least on some boards.
5993 */
5994 if (system_state != SYSTEM_POWER_OFF) {
5995 nv_restore_mac_addr(pdev);
5996 }
5997
5998 pci_disable_device(pdev);
5999 /*
6000 * Apparently it is not possible to reinitialise from D3 hot,
6001 * only put the device into D3 if we really go for poweroff.
6002 */
6003 if (system_state == SYSTEM_POWER_OFF) {
6004 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
6005 pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
6006 pci_set_power_state(pdev, PCI_D3hot);
6007 }
6008 }
6009 #else
6010 #define nv_suspend NULL
6011 #define nv_shutdown NULL
6012 #define nv_resume NULL
6013 #endif /* CONFIG_PM */
6014
6015 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
6016 { /* nForce Ethernet Controller */
6017 PCI_DEVICE(0x10DE, 0x01C3),
6018 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6019 },
6020 { /* nForce2 Ethernet Controller */
6021 PCI_DEVICE(0x10DE, 0x0066),
6022 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6023 },
6024 { /* nForce3 Ethernet Controller */
6025 PCI_DEVICE(0x10DE, 0x00D6),
6026 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6027 },
6028 { /* nForce3 Ethernet Controller */
6029 PCI_DEVICE(0x10DE, 0x0086),
6030 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6031 },
6032 { /* nForce3 Ethernet Controller */
6033 PCI_DEVICE(0x10DE, 0x008C),
6034 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6035 },
6036 { /* nForce3 Ethernet Controller */
6037 PCI_DEVICE(0x10DE, 0x00E6),
6038 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6039 },
6040 { /* nForce3 Ethernet Controller */
6041 PCI_DEVICE(0x10DE, 0x00DF),
6042 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6043 },
6044 { /* CK804 Ethernet Controller */
6045 PCI_DEVICE(0x10DE, 0x0056),
6046 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6047 },
6048 { /* CK804 Ethernet Controller */
6049 PCI_DEVICE(0x10DE, 0x0057),
6050 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6051 },
6052 { /* MCP04 Ethernet Controller */
6053 PCI_DEVICE(0x10DE, 0x0037),
6054 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6055 },
6056 { /* MCP04 Ethernet Controller */
6057 PCI_DEVICE(0x10DE, 0x0038),
6058 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6059 },
6060 { /* MCP51 Ethernet Controller */
6061 PCI_DEVICE(0x10DE, 0x0268),
6062 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6063 },
6064 { /* MCP51 Ethernet Controller */
6065 PCI_DEVICE(0x10DE, 0x0269),
6066 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6067 },
6068 { /* MCP55 Ethernet Controller */
6069 PCI_DEVICE(0x10DE, 0x0372),
6070 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6071 },
6072 { /* MCP55 Ethernet Controller */
6073 PCI_DEVICE(0x10DE, 0x0373),
6074 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6075 },
6076 { /* MCP61 Ethernet Controller */
6077 PCI_DEVICE(0x10DE, 0x03E5),
6078 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6079 },
6080 { /* MCP61 Ethernet Controller */
6081 PCI_DEVICE(0x10DE, 0x03E6),
6082 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6083 },
6084 { /* MCP61 Ethernet Controller */
6085 PCI_DEVICE(0x10DE, 0x03EE),
6086 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6087 },
6088 { /* MCP61 Ethernet Controller */
6089 PCI_DEVICE(0x10DE, 0x03EF),
6090 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6091 },
6092 { /* MCP65 Ethernet Controller */
6093 PCI_DEVICE(0x10DE, 0x0450),
6094 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6095 },
6096 { /* MCP65 Ethernet Controller */
6097 PCI_DEVICE(0x10DE, 0x0451),
6098 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6099 },
6100 { /* MCP65 Ethernet Controller */
6101 PCI_DEVICE(0x10DE, 0x0452),
6102 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6103 },
6104 { /* MCP65 Ethernet Controller */
6105 PCI_DEVICE(0x10DE, 0x0453),
6106 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6107 },
6108 { /* MCP67 Ethernet Controller */
6109 PCI_DEVICE(0x10DE, 0x054C),
6110 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6111 },
6112 { /* MCP67 Ethernet Controller */
6113 PCI_DEVICE(0x10DE, 0x054D),
6114 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6115 },
6116 { /* MCP67 Ethernet Controller */
6117 PCI_DEVICE(0x10DE, 0x054E),
6118 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6119 },
6120 { /* MCP67 Ethernet Controller */
6121 PCI_DEVICE(0x10DE, 0x054F),
6122 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6123 },
6124 { /* MCP73 Ethernet Controller */
6125 PCI_DEVICE(0x10DE, 0x07DC),
6126 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6127 },
6128 { /* MCP73 Ethernet Controller */
6129 PCI_DEVICE(0x10DE, 0x07DD),
6130 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6131 },
6132 { /* MCP73 Ethernet Controller */
6133 PCI_DEVICE(0x10DE, 0x07DE),
6134 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6135 },
6136 { /* MCP73 Ethernet Controller */
6137 PCI_DEVICE(0x10DE, 0x07DF),
6138 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6139 },
6140 { /* MCP77 Ethernet Controller */
6141 PCI_DEVICE(0x10DE, 0x0760),
6142 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6143 },
6144 { /* MCP77 Ethernet Controller */
6145 PCI_DEVICE(0x10DE, 0x0761),
6146 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6147 },
6148 { /* MCP77 Ethernet Controller */
6149 PCI_DEVICE(0x10DE, 0x0762),
6150 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6151 },
6152 { /* MCP77 Ethernet Controller */
6153 PCI_DEVICE(0x10DE, 0x0763),
6154 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6155 },
6156 { /* MCP79 Ethernet Controller */
6157 PCI_DEVICE(0x10DE, 0x0AB0),
6158 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6159 },
6160 { /* MCP79 Ethernet Controller */
6161 PCI_DEVICE(0x10DE, 0x0AB1),
6162 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6163 },
6164 { /* MCP79 Ethernet Controller */
6165 PCI_DEVICE(0x10DE, 0x0AB2),
6166 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6167 },
6168 { /* MCP79 Ethernet Controller */
6169 PCI_DEVICE(0x10DE, 0x0AB3),
6170 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6171 },
6172 { /* MCP89 Ethernet Controller */
6173 PCI_DEVICE(0x10DE, 0x0D7D),
6174 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6175 },
6176 {0,},
6177 };
6178
6179 static struct pci_driver driver = {
6180 .name = DRV_NAME,
6181 .id_table = pci_tbl,
6182 .probe = nv_probe,
6183 .remove = __devexit_p(nv_remove),
6184 .suspend = nv_suspend,
6185 .resume = nv_resume,
6186 .shutdown = nv_shutdown,
6187 };
6188
6189 static int __init init_nic(void)
6190 {
6191 return pci_register_driver(&driver);
6192 }
6193
6194 static void __exit exit_nic(void)
6195 {
6196 pci_unregister_driver(&driver);
6197 }
6198
6199 module_param(max_interrupt_work, int, 0);
6200 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6201 module_param(optimization_mode, int, 0);
6202 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6203 module_param(poll_interval, int, 0);
6204 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6205 module_param(msi, int, 0);
6206 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6207 module_param(msix, int, 0);
6208 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6209 module_param(dma_64bit, int, 0);
6210 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6211 module_param(phy_cross, int, 0);
6212 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6213 module_param(phy_power_down, int, 0);
6214 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6215
6216 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6217 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6218 MODULE_LICENSE("GPL");
6219
6220 MODULE_DEVICE_TABLE(pci, pci_tbl);
6221
6222 module_init(init_nic);
6223 module_exit(exit_nic);
AMDTP streaming driver for the Linux FireWire stack (Juju)