raid5: refactor handle_stripe5 and handle_stripe6 (v3)
[firewire-audio.git] / include / asm-mips / serial.h
blobce51213d84f989f8eafb3df63cd46dba941861fb
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 1999 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9 #ifndef _ASM_SERIAL_H
10 #define _ASM_SERIAL_H
14 * This assumes you have a 1.8432 MHz clock for your UART.
16 * It'd be nice if someone built a serial card with a 24.576 MHz
17 * clock, since the 16550A is capable of handling a top speed of 1.5
18 * megabits/second; but this requires the faster clock.
20 #define BASE_BAUD (1843200 / 16)
22 /* Standard COM flags (except for COM4, because of the 8514 problem) */
23 #ifdef CONFIG_SERIAL_DETECT_IRQ
24 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
25 #define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
26 #else
27 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
28 #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
29 #endif
31 #ifdef CONFIG_MACH_JAZZ
32 #include <asm/jazz.h>
34 #ifndef CONFIG_OLIVETTI_M700
35 /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
36 exactly which ones ... XXX */
37 #define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
38 #else
39 /* but the M700 isn't such a strange beast */
40 #define JAZZ_BASE_BAUD BASE_BAUD
41 #endif
43 #define _JAZZ_SERIAL_INIT(int, base) \
44 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
45 .iomem_base = (u8 *) base, .iomem_reg_shift = 0, \
46 .io_type = SERIAL_IO_MEM }
47 #define JAZZ_SERIAL_PORT_DEFNS \
48 _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \
49 _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
50 #else
51 #define JAZZ_SERIAL_PORT_DEFNS
52 #endif
55 * Galileo EV64120 evaluation board
57 #ifdef CONFIG_MIPS_EV64120
58 #include <mach-gt64120.h>
59 #define EV64120_SERIAL_PORT_DEFNS \
60 { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
61 .flags = STD_COM_FLAGS, \
62 .iomem_base = EV64120_UART0_REGS_BASE, .iomem_reg_shift = 2, \
63 .io_type = SERIAL_IO_MEM }, \
64 { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
65 .flags = STD_COM_FLAGS, \
66 .iomem_base = EV64120_UART1_REGS_BASE, .iomem_reg_shift = 2, \
67 .io_type = SERIAL_IO_MEM },
68 #else
69 #define EV64120_SERIAL_PORT_DEFNS
70 #endif
72 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
73 #define STD_SERIAL_PORT_DEFNS \
74 /* UART CLK PORT IRQ FLAGS */ \
75 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
76 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
77 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
78 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
80 #else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
81 #define STD_SERIAL_PORT_DEFNS
82 #endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
84 #ifdef CONFIG_MOMENCO_OCELOT_3
85 #define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
86 #define OCELOT_3_SERIAL_IRQ 6
87 #define OCELOT_3_SERIAL_BASE (signed)0xfd000020
89 #define _OCELOT_3_SERIAL_INIT(int, base) \
90 { .baud_base = OCELOT_3_BASE_BAUD, irq: int, \
91 .flags = STD_COM_FLAGS, \
92 .iomem_base = (u8 *) base, iomem_reg_shift: 2, \
93 io_type: SERIAL_IO_MEM }
95 #define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
96 _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
97 #else
98 #define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
99 #endif
101 #ifdef CONFIG_MOMENCO_OCELOT
102 /* Ordinary NS16552 duart with a 20MHz crystal. */
103 #define OCELOT_BASE_BAUD ( 20000000 / 16 )
105 #define OCELOT_SERIAL1_IRQ 4
106 #define OCELOT_SERIAL1_BASE 0xe0001020
108 #define _OCELOT_SERIAL_INIT(int, base) \
109 { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
110 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
111 .io_type = SERIAL_IO_MEM }
112 #define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
113 _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
114 #else
115 #define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
116 #endif
118 #ifdef CONFIG_MOMENCO_OCELOT_C
119 /* Ordinary NS16552 duart with a 20MHz crystal. */
120 #define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
122 #define OCELOT_C_SERIAL1_IRQ 80
123 #define OCELOT_C_SERIAL1_BASE 0xfd000020
125 #define OCELOT_C_SERIAL2_IRQ 81
126 #define OCELOT_C_SERIAL2_BASE 0xfd000000
128 #define _OCELOT_C_SERIAL_INIT(int, base) \
129 { .baud_base = OCELOT_C_BASE_BAUD, \
130 .irq = (int), \
131 .flags = STD_COM_FLAGS, \
132 .iomem_base = (u8 *) base, \
133 .iomem_reg_shift = 2, \
134 .io_type = SERIAL_IO_MEM \
136 #define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
137 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
138 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
139 #else
140 #define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
141 #endif
143 #ifdef CONFIG_DDB5477
144 #include <asm/ddb5xxx/ddb5477.h>
145 #define DDB5477_SERIAL_PORT_DEFNS \
146 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \
147 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \
148 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \
149 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \
150 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \
151 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
152 #else
153 #define DDB5477_SERIAL_PORT_DEFNS
154 #endif
156 #ifdef CONFIG_SGI_IP32
158 * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
159 * They are initialized in ip32_setup
161 #define IP32_SERIAL_PORT_DEFNS \
162 {},{},
163 #else
164 #define IP32_SERIAL_PORT_DEFNS
165 #endif /* CONFIG_SGI_IP32 */
167 #define SERIAL_PORT_DFNS \
168 DDB5477_SERIAL_PORT_DEFNS \
169 EV64120_SERIAL_PORT_DEFNS \
170 IP32_SERIAL_PORT_DEFNS \
171 JAZZ_SERIAL_PORT_DEFNS \
172 STD_SERIAL_PORT_DEFNS \
173 MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
174 MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
175 MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
177 #endif /* _ASM_SERIAL_H */