2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
6 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License (GPL) Version 2 as
10 * published by the Free Software Foundation
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
18 #include "bfa_modules.h"
19 #include "bfi_cbreg.h"
22 bfa_hwcb_reginit(struct bfa_s
*bfa
)
24 struct bfa_iocfc_regs_s
*bfa_regs
= &bfa
->iocfc
.bfa_regs
;
25 void __iomem
*kva
= bfa_ioc_bar0(&bfa
->ioc
);
26 int i
, q
, fn
= bfa_ioc_pcifn(&bfa
->ioc
);
29 bfa_regs
->intr_status
= (kva
+ HOSTFN0_INT_STATUS
);
30 bfa_regs
->intr_mask
= (kva
+ HOSTFN0_INT_MSK
);
32 bfa_regs
->intr_status
= (kva
+ HOSTFN1_INT_STATUS
);
33 bfa_regs
->intr_mask
= (kva
+ HOSTFN1_INT_MSK
);
36 for (i
= 0; i
< BFI_IOC_MAX_CQS
; i
++) {
41 bfa_regs
->cpe_q_pi
[i
] = (kva
+ CPE_Q_PI(q
));
42 bfa_regs
->cpe_q_ci
[i
] = (kva
+ CPE_Q_CI(q
));
43 bfa_regs
->cpe_q_depth
[i
] = (kva
+ CPE_Q_DEPTH(q
));
49 bfa_regs
->rme_q_pi
[i
] = (kva
+ RME_Q_PI(q
));
50 bfa_regs
->rme_q_ci
[i
] = (kva
+ RME_Q_CI(q
));
51 bfa_regs
->rme_q_depth
[i
] = (kva
+ RME_Q_DEPTH(q
));
56 bfa_hwcb_reqq_ack(struct bfa_s
*bfa
, int reqq
)
61 bfa_hwcb_reqq_ack_msix(struct bfa_s
*bfa
, int reqq
)
63 writel(__HFN_INT_CPE_Q0
<< CPE_Q_NUM(bfa_ioc_pcifn(&bfa
->ioc
), reqq
),
64 bfa
->iocfc
.bfa_regs
.intr_status
);
68 bfa_hwcb_rspq_ack(struct bfa_s
*bfa
, int rspq
)
73 bfa_hwcb_rspq_ack_msix(struct bfa_s
*bfa
, int rspq
)
75 writel(__HFN_INT_RME_Q0
<< RME_Q_NUM(bfa_ioc_pcifn(&bfa
->ioc
), rspq
),
76 bfa
->iocfc
.bfa_regs
.intr_status
);
80 bfa_hwcb_msix_getvecs(struct bfa_s
*bfa
, u32
*msix_vecs_bmap
,
81 u32
*num_vecs
, u32
*max_vec_bit
)
83 #define __HFN_NUMINTS 13
84 if (bfa_ioc_pcifn(&bfa
->ioc
) == 0) {
85 *msix_vecs_bmap
= (__HFN_INT_CPE_Q0
| __HFN_INT_CPE_Q1
|
86 __HFN_INT_CPE_Q2
| __HFN_INT_CPE_Q3
|
87 __HFN_INT_RME_Q0
| __HFN_INT_RME_Q1
|
88 __HFN_INT_RME_Q2
| __HFN_INT_RME_Q3
|
90 *max_vec_bit
= __HFN_INT_MBOX_LPU0
;
92 *msix_vecs_bmap
= (__HFN_INT_CPE_Q4
| __HFN_INT_CPE_Q5
|
93 __HFN_INT_CPE_Q6
| __HFN_INT_CPE_Q7
|
94 __HFN_INT_RME_Q4
| __HFN_INT_RME_Q5
|
95 __HFN_INT_RME_Q6
| __HFN_INT_RME_Q7
|
97 *max_vec_bit
= __HFN_INT_MBOX_LPU1
;
100 *msix_vecs_bmap
|= (__HFN_INT_ERR_EMC
| __HFN_INT_ERR_LPU0
|
101 __HFN_INT_ERR_LPU1
| __HFN_INT_ERR_PSS
);
102 *num_vecs
= __HFN_NUMINTS
;
106 * No special setup required for crossbow -- vector assignments are implicit.
109 bfa_hwcb_msix_init(struct bfa_s
*bfa
, int nvecs
)
113 bfa_assert((nvecs
== 1) || (nvecs
== __HFN_NUMINTS
));
115 bfa
->msix
.nvecs
= nvecs
;
117 for (i
= 0; i
< BFA_MSIX_CB_MAX
; i
++)
118 bfa
->msix
.handler
[i
] = bfa_msix_all
;
122 for (i
= BFA_MSIX_CPE_Q0
; i
<= BFA_MSIX_CPE_Q7
; i
++)
123 bfa
->msix
.handler
[i
] = bfa_msix_reqq
;
125 for (i
= BFA_MSIX_RME_Q0
; i
<= BFA_MSIX_RME_Q7
; i
++)
126 bfa
->msix
.handler
[i
] = bfa_msix_rspq
;
128 for (; i
< BFA_MSIX_CB_MAX
; i
++)
129 bfa
->msix
.handler
[i
] = bfa_msix_lpu_err
;
133 * Crossbow -- dummy, interrupts are masked
136 bfa_hwcb_msix_install(struct bfa_s
*bfa
)
141 bfa_hwcb_msix_uninstall(struct bfa_s
*bfa
)
146 * No special enable/disable -- vector assignments are implicit.
149 bfa_hwcb_isr_mode_set(struct bfa_s
*bfa
, bfa_boolean_t msix
)
151 bfa
->iocfc
.hwif
.hw_reqq_ack
= bfa_hwcb_reqq_ack_msix
;
152 bfa
->iocfc
.hwif
.hw_rspq_ack
= bfa_hwcb_rspq_ack_msix
;
156 bfa_hwcb_msix_get_rme_range(struct bfa_s
*bfa
, u32
*start
, u32
*end
)
158 *start
= BFA_MSIX_RME_Q0
;
159 *end
= BFA_MSIX_RME_Q7
;