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[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
[firewire-audio.git] / drivers / serial / imx.c
blob6a29f9330a73c72d7799a83ce66a8ecd9a7e5588
1 /*
2 * linux/drivers/serial/imx.c
3 *
4 * Driver for Motorola IMX serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * [29-Mar-2005] Mike Lee
26 * Added hardware handshake
27 */
28
29 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30 #define SUPPORT_SYSRQ
31 #endif
32
33 #include <linux/module.h>
34 #include <linux/ioport.h>
35 #include <linux/init.h>
36 #include <linux/console.h>
37 #include <linux/sysrq.h>
38 #include <linux/platform_device.h>
39 #include <linux/tty.h>
40 #include <linux/tty_flip.h>
41 #include <linux/serial_core.h>
42 #include <linux/serial.h>
43 #include <linux/clk.h>
44
45 #include <asm/io.h>
46 #include <asm/irq.h>
47 #include <mach/hardware.h>
48 #include <mach/imx-uart.h>
49
50 /* Register definitions */
51 #define URXD0 0x0 /* Receiver Register */
52 #define URTX0 0x40 /* Transmitter Register */
53 #define UCR1 0x80 /* Control Register 1 */
54 #define UCR2 0x84 /* Control Register 2 */
55 #define UCR3 0x88 /* Control Register 3 */
56 #define UCR4 0x8c /* Control Register 4 */
57 #define UFCR 0x90 /* FIFO Control Register */
58 #define USR1 0x94 /* Status Register 1 */
59 #define USR2 0x98 /* Status Register 2 */
60 #define UESC 0x9c /* Escape Character Register */
61 #define UTIM 0xa0 /* Escape Timer Register */
62 #define UBIR 0xa4 /* BRM Incremental Register */
63 #define UBMR 0xa8 /* BRM Modulator Register */
64 #define UBRC 0xac /* Baud Rate Count Register */
65 #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
66 #define ONEMS 0xb0 /* One Millisecond register */
67 #define UTS 0xb4 /* UART Test Register */
68 #endif
69 #ifdef CONFIG_ARCH_IMX
70 #define BIPR1 0xb0 /* Incremental Preset Register 1 */
71 #define BIPR2 0xb4 /* Incremental Preset Register 2 */
72 #define BIPR3 0xb8 /* Incremental Preset Register 3 */
73 #define BIPR4 0xbc /* Incremental Preset Register 4 */
74 #define BMPR1 0xc0 /* BRM Modulator Register 1 */
75 #define BMPR2 0xc4 /* BRM Modulator Register 2 */
76 #define BMPR3 0xc8 /* BRM Modulator Register 3 */
77 #define BMPR4 0xcc /* BRM Modulator Register 4 */
78 #define UTS 0xd0 /* UART Test Register */
79 #endif
80
81 /* UART Control Register Bit Fields.*/
82 #define URXD_CHARRDY (1<<15)
83 #define URXD_ERR (1<<14)
84 #define URXD_OVRRUN (1<<13)
85 #define URXD_FRMERR (1<<12)
86 #define URXD_BRK (1<<11)
87 #define URXD_PRERR (1<<10)
88 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
89 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
90 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
91 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
92 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
93 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
94 #define UCR1_IREN (1<<7) /* Infrared interface enable */
95 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
96 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
97 #define UCR1_SNDBRK (1<<4) /* Send break */
98 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
99 #ifdef CONFIG_ARCH_IMX
100 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
101 #endif
102 #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
103 #define UCR1_UARTCLKEN (0) /* not present on mx2/mx3 */
104 #endif
105 #define UCR1_DOZE (1<<1) /* Doze */
106 #define UCR1_UARTEN (1<<0) /* UART enabled */
107 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
108 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
109 #define UCR2_CTSC (1<<13) /* CTS pin control */
110 #define UCR2_CTS (1<<12) /* Clear to send */
111 #define UCR2_ESCEN (1<<11) /* Escape enable */
112 #define UCR2_PREN (1<<8) /* Parity enable */
113 #define UCR2_PROE (1<<7) /* Parity odd/even */
114 #define UCR2_STPB (1<<6) /* Stop */
115 #define UCR2_WS (1<<5) /* Word size */
116 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
117 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
118 #define UCR2_RXEN (1<<1) /* Receiver enabled */
119 #define UCR2_SRST (1<<0) /* SW reset */
120 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
121 #define UCR3_PARERREN (1<<12) /* Parity enable */
122 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
123 #define UCR3_DSR (1<<10) /* Data set ready */
124 #define UCR3_DCD (1<<9) /* Data carrier detect */
125 #define UCR3_RI (1<<8) /* Ring indicator */
126 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
127 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
128 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
129 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
130 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
131 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
132 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
133 #define UCR3_BPEN (1<<0) /* Preset registers enable */
134 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
135 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
136 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
137 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
138 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
139 #define UCR4_IRSC (1<<5) /* IR special case */
140 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
141 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
142 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
143 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
144 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
145 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
146 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
147 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
148 #define USR1_RTSS (1<<14) /* RTS pin status */
149 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
150 #define USR1_RTSD (1<<12) /* RTS delta */
151 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
152 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
153 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
154 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
155 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
156 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
157 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
158 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
159 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
160 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
161 #define USR2_IDLE (1<<12) /* Idle condition */
162 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
163 #define USR2_WAKE (1<<7) /* Wake */
164 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
165 #define USR2_TXDC (1<<3) /* Transmitter complete */
166 #define USR2_BRCD (1<<2) /* Break condition */
167 #define USR2_ORE (1<<1) /* Overrun error */
168 #define USR2_RDR (1<<0) /* Recv data ready */
169 #define UTS_FRCPERR (1<<13) /* Force parity error */
170 #define UTS_LOOP (1<<12) /* Loop tx and rx */
171 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
172 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
173 #define UTS_TXFULL (1<<4) /* TxFIFO full */
174 #define UTS_RXFULL (1<<3) /* RxFIFO full */
175 #define UTS_SOFTRST (1<<0) /* Software reset */
176
177 /* We've been assigned a range on the "Low-density serial ports" major */
178 #ifdef CONFIG_ARCH_IMX
179 #define SERIAL_IMX_MAJOR 204
180 #define MINOR_START 41
181 #define DEV_NAME "ttySMX"
182 #define MAX_INTERNAL_IRQ IMX_IRQS
183 #endif
184
185 #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
186 #define SERIAL_IMX_MAJOR 207
187 #define MINOR_START 16
188 #define DEV_NAME "ttymxc"
189 #define MAX_INTERNAL_IRQ MXC_MAX_INT_LINES
190 #endif
191
192 /*
193 * This determines how often we check the modem status signals
194 * for any change. They generally aren't connected to an IRQ
195 * so we have to poll them. We also check immediately before
196 * filling the TX fifo incase CTS has been dropped.
197 */
198 #define MCTRL_TIMEOUT (250*HZ/1000)
199
200 #define DRIVER_NAME "IMX-uart"
201
202 #define UART_NR 8
203
204 struct imx_port {
205 struct uart_port port;
206 struct timer_list timer;
207 unsigned int old_status;
208 int txirq,rxirq,rtsirq;
209 int have_rtscts:1;
210 struct clk *clk;
211 };
212
213 /*
214 * Handle any change of modem status signal since we were last called.
215 */
216 static void imx_mctrl_check(struct imx_port *sport)
217 {
218 unsigned int status, changed;
219
220 status = sport->port.ops->get_mctrl(&sport->port);
221 changed = status ^ sport->old_status;
222
223 if (changed == 0)
224 return;
225
226 sport->old_status = status;
227
228 if (changed & TIOCM_RI)
229 sport->port.icount.rng++;
230 if (changed & TIOCM_DSR)
231 sport->port.icount.dsr++;
232 if (changed & TIOCM_CAR)
233 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
234 if (changed & TIOCM_CTS)
235 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
236
237 wake_up_interruptible(&sport->port.info->delta_msr_wait);
238 }
239
240 /*
241 * This is our per-port timeout handler, for checking the
242 * modem status signals.
243 */
244 static void imx_timeout(unsigned long data)
245 {
246 struct imx_port *sport = (struct imx_port *)data;
247 unsigned long flags;
248
249 if (sport->port.info) {
250 spin_lock_irqsave(&sport->port.lock, flags);
251 imx_mctrl_check(sport);
252 spin_unlock_irqrestore(&sport->port.lock, flags);
253
254 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
255 }
256 }
257
258 /*
259 * interrupts disabled on entry
260 */
261 static void imx_stop_tx(struct uart_port *port)
262 {
263 struct imx_port *sport = (struct imx_port *)port;
264 unsigned long temp;
265
266 temp = readl(sport->port.membase + UCR1);
267 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
268 }
269
270 /*
271 * interrupts disabled on entry
272 */
273 static void imx_stop_rx(struct uart_port *port)
274 {
275 struct imx_port *sport = (struct imx_port *)port;
276 unsigned long temp;
277
278 temp = readl(sport->port.membase + UCR2);
279 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
280 }
281
282 /*
283 * Set the modem control timer to fire immediately.
284 */
285 static void imx_enable_ms(struct uart_port *port)
286 {
287 struct imx_port *sport = (struct imx_port *)port;
288
289 mod_timer(&sport->timer, jiffies);
290 }
291
292 static inline void imx_transmit_buffer(struct imx_port *sport)
293 {
294 struct circ_buf *xmit = &sport->port.info->xmit;
295
296 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
297 /* send xmit->buf[xmit->tail]
298 * out the port here */
299 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
300 xmit->tail = (xmit->tail + 1) &
301 (UART_XMIT_SIZE - 1);
302 sport->port.icount.tx++;
303 if (uart_circ_empty(xmit))
304 break;
305 }
306
307 if (uart_circ_empty(xmit))
308 imx_stop_tx(&sport->port);
309 }
310
311 /*
312 * interrupts disabled on entry
313 */
314 static void imx_start_tx(struct uart_port *port)
315 {
316 struct imx_port *sport = (struct imx_port *)port;
317 unsigned long temp;
318
319 temp = readl(sport->port.membase + UCR1);
320 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
321
322 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
323 imx_transmit_buffer(sport);
324 }
325
326 static irqreturn_t imx_rtsint(int irq, void *dev_id)
327 {
328 struct imx_port *sport = dev_id;
329 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
330 unsigned long flags;
331
332 spin_lock_irqsave(&sport->port.lock, flags);
333
334 writel(USR1_RTSD, sport->port.membase + USR1);
335 uart_handle_cts_change(&sport->port, !!val);
336 wake_up_interruptible(&sport->port.info->delta_msr_wait);
337
338 spin_unlock_irqrestore(&sport->port.lock, flags);
339 return IRQ_HANDLED;
340 }
341
342 static irqreturn_t imx_txint(int irq, void *dev_id)
343 {
344 struct imx_port *sport = dev_id;
345 struct circ_buf *xmit = &sport->port.info->xmit;
346 unsigned long flags;
347
348 spin_lock_irqsave(&sport->port.lock,flags);
349 if (sport->port.x_char)
350 {
351 /* Send next char */
352 writel(sport->port.x_char, sport->port.membase + URTX0);
353 goto out;
354 }
355
356 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
357 imx_stop_tx(&sport->port);
358 goto out;
359 }
360
361 imx_transmit_buffer(sport);
362
363 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
364 uart_write_wakeup(&sport->port);
365
366 out:
367 spin_unlock_irqrestore(&sport->port.lock,flags);
368 return IRQ_HANDLED;
369 }
370
371 static irqreturn_t imx_rxint(int irq, void *dev_id)
372 {
373 struct imx_port *sport = dev_id;
374 unsigned int rx,flg,ignored = 0;
375 struct tty_struct *tty = sport->port.info->port.tty;
376 unsigned long flags, temp;
377
378 spin_lock_irqsave(&sport->port.lock,flags);
379
380 while (readl(sport->port.membase + USR2) & USR2_RDR) {
381 flg = TTY_NORMAL;
382 sport->port.icount.rx++;
383
384 rx = readl(sport->port.membase + URXD0);
385
386 temp = readl(sport->port.membase + USR2);
387 if (temp & USR2_BRCD) {
388 writel(temp | USR2_BRCD, sport->port.membase + USR2);
389 if (uart_handle_break(&sport->port))
390 continue;
391 }
392
393 if (uart_handle_sysrq_char
394 (&sport->port, (unsigned char)rx))
395 continue;
396
397 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
398 if (rx & URXD_PRERR)
399 sport->port.icount.parity++;
400 else if (rx & URXD_FRMERR)
401 sport->port.icount.frame++;
402 if (rx & URXD_OVRRUN)
403 sport->port.icount.overrun++;
404
405 if (rx & sport->port.ignore_status_mask) {
406 if (++ignored > 100)
407 goto out;
408 continue;
409 }
410
411 rx &= sport->port.read_status_mask;
412
413 if (rx & URXD_PRERR)
414 flg = TTY_PARITY;
415 else if (rx & URXD_FRMERR)
416 flg = TTY_FRAME;
417 if (rx & URXD_OVRRUN)
418 flg = TTY_OVERRUN;
419
420 #ifdef SUPPORT_SYSRQ
421 sport->port.sysrq = 0;
422 #endif
423 }
424
425 tty_insert_flip_char(tty, rx, flg);
426 }
427
428 out:
429 spin_unlock_irqrestore(&sport->port.lock,flags);
430 tty_flip_buffer_push(tty);
431 return IRQ_HANDLED;
432 }
433
434 static irqreturn_t imx_int(int irq, void *dev_id)
435 {
436 struct imx_port *sport = dev_id;
437 unsigned int sts;
438
439 sts = readl(sport->port.membase + USR1);
440
441 if (sts & USR1_RRDY)
442 imx_rxint(irq, dev_id);
443
444 if (sts & USR1_TRDY &&
445 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
446 imx_txint(irq, dev_id);
447
448 if (sts & USR1_RTSS)
449 imx_rtsint(irq, dev_id);
450
451 return IRQ_HANDLED;
452 }
453
454 /*
455 * Return TIOCSER_TEMT when transmitter is not busy.
456 */
457 static unsigned int imx_tx_empty(struct uart_port *port)
458 {
459 struct imx_port *sport = (struct imx_port *)port;
460
461 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
462 }
463
464 /*
465 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
466 */
467 static unsigned int imx_get_mctrl(struct uart_port *port)
468 {
469 struct imx_port *sport = (struct imx_port *)port;
470 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
471
472 if (readl(sport->port.membase + USR1) & USR1_RTSS)
473 tmp |= TIOCM_CTS;
474
475 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
476 tmp |= TIOCM_RTS;
477
478 return tmp;
479 }
480
481 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
482 {
483 struct imx_port *sport = (struct imx_port *)port;
484 unsigned long temp;
485
486 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
487
488 if (mctrl & TIOCM_RTS)
489 temp |= UCR2_CTS;
490
491 writel(temp, sport->port.membase + UCR2);
492 }
493
494 /*
495 * Interrupts always disabled.
496 */
497 static void imx_break_ctl(struct uart_port *port, int break_state)
498 {
499 struct imx_port *sport = (struct imx_port *)port;
500 unsigned long flags, temp;
501
502 spin_lock_irqsave(&sport->port.lock, flags);
503
504 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
505
506 if ( break_state != 0 )
507 temp |= UCR1_SNDBRK;
508
509 writel(temp, sport->port.membase + UCR1);
510
511 spin_unlock_irqrestore(&sport->port.lock, flags);
512 }
513
514 #define TXTL 2 /* reset default */
515 #define RXTL 1 /* reset default */
516
517 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
518 {
519 unsigned int val;
520 unsigned int ufcr_rfdiv;
521
522 /* set receiver / transmitter trigger level.
523 * RFDIV is set such way to satisfy requested uartclk value
524 */
525 val = TXTL << 10 | RXTL;
526 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
527 / sport->port.uartclk;
528
529 if(!ufcr_rfdiv)
530 ufcr_rfdiv = 1;
531
532 if(ufcr_rfdiv >= 7)
533 ufcr_rfdiv = 6;
534 else
535 ufcr_rfdiv = 6 - ufcr_rfdiv;
536
537 val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
538
539 writel(val, sport->port.membase + UFCR);
540
541 return 0;
542 }
543
544 static int imx_startup(struct uart_port *port)
545 {
546 struct imx_port *sport = (struct imx_port *)port;
547 int retval;
548 unsigned long flags, temp;
549
550 imx_setup_ufcr(sport, 0);
551
552 /* disable the DREN bit (Data Ready interrupt enable) before
553 * requesting IRQs
554 */
555 temp = readl(sport->port.membase + UCR4);
556 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
557
558 /*
559 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
560 * chips only have one interrupt.
561 */
562 if (sport->txirq > 0) {
563 retval = request_irq(sport->rxirq, imx_rxint, 0,
564 DRIVER_NAME, sport);
565 if (retval)
566 goto error_out1;
567
568 retval = request_irq(sport->txirq, imx_txint, 0,
569 DRIVER_NAME, sport);
570 if (retval)
571 goto error_out2;
572
573 retval = request_irq(sport->rtsirq, imx_rtsint,
574 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
575 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
576 DRIVER_NAME, sport);
577 if (retval)
578 goto error_out3;
579 } else {
580 retval = request_irq(sport->port.irq, imx_int, 0,
581 DRIVER_NAME, sport);
582 if (retval) {
583 free_irq(sport->port.irq, sport);
584 goto error_out1;
585 }
586 }
587
588 /*
589 * Finally, clear and enable interrupts
590 */
591 writel(USR1_RTSD, sport->port.membase + USR1);
592
593 temp = readl(sport->port.membase + UCR1);
594 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
595 writel(temp, sport->port.membase + UCR1);
596
597 temp = readl(sport->port.membase + UCR2);
598 temp |= (UCR2_RXEN | UCR2_TXEN);
599 writel(temp, sport->port.membase + UCR2);
600
601 /*
602 * Enable modem status interrupts
603 */
604 spin_lock_irqsave(&sport->port.lock,flags);
605 imx_enable_ms(&sport->port);
606 spin_unlock_irqrestore(&sport->port.lock,flags);
607
608 return 0;
609
610 error_out3:
611 if (sport->txirq)
612 free_irq(sport->txirq, sport);
613 error_out2:
614 if (sport->rxirq)
615 free_irq(sport->rxirq, sport);
616 error_out1:
617 return retval;
618 }
619
620 static void imx_shutdown(struct uart_port *port)
621 {
622 struct imx_port *sport = (struct imx_port *)port;
623 unsigned long temp;
624
625 /*
626 * Stop our timer.
627 */
628 del_timer_sync(&sport->timer);
629
630 /*
631 * Free the interrupts
632 */
633 if (sport->txirq > 0) {
634 free_irq(sport->rtsirq, sport);
635 free_irq(sport->txirq, sport);
636 free_irq(sport->rxirq, sport);
637 } else
638 free_irq(sport->port.irq, sport);
639
640 /*
641 * Disable all interrupts, port and break condition.
642 */
643
644 temp = readl(sport->port.membase + UCR1);
645 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
646 writel(temp, sport->port.membase + UCR1);
647 }
648
649 static void
650 imx_set_termios(struct uart_port *port, struct ktermios *termios,
651 struct ktermios *old)
652 {
653 struct imx_port *sport = (struct imx_port *)port;
654 unsigned long flags;
655 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
656 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
657 unsigned int div, num, denom, ufcr;
658
659 /*
660 * If we don't support modem control lines, don't allow
661 * these to be set.
662 */
663 if (0) {
664 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
665 termios->c_cflag |= CLOCAL;
666 }
667
668 /*
669 * We only support CS7 and CS8.
670 */
671 while ((termios->c_cflag & CSIZE) != CS7 &&
672 (termios->c_cflag & CSIZE) != CS8) {
673 termios->c_cflag &= ~CSIZE;
674 termios->c_cflag |= old_csize;
675 old_csize = CS8;
676 }
677
678 if ((termios->c_cflag & CSIZE) == CS8)
679 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
680 else
681 ucr2 = UCR2_SRST | UCR2_IRTS;
682
683 if (termios->c_cflag & CRTSCTS) {
684 if( sport->have_rtscts ) {
685 ucr2 &= ~UCR2_IRTS;
686 ucr2 |= UCR2_CTSC;
687 } else {
688 termios->c_cflag &= ~CRTSCTS;
689 }
690 }
691
692 if (termios->c_cflag & CSTOPB)
693 ucr2 |= UCR2_STPB;
694 if (termios->c_cflag & PARENB) {
695 ucr2 |= UCR2_PREN;
696 if (termios->c_cflag & PARODD)
697 ucr2 |= UCR2_PROE;
698 }
699
700 /*
701 * Ask the core to calculate the divisor for us.
702 */
703 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
704 quot = uart_get_divisor(port, baud);
705
706 spin_lock_irqsave(&sport->port.lock, flags);
707
708 sport->port.read_status_mask = 0;
709 if (termios->c_iflag & INPCK)
710 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
711 if (termios->c_iflag & (BRKINT | PARMRK))
712 sport->port.read_status_mask |= URXD_BRK;
713
714 /*
715 * Characters to ignore
716 */
717 sport->port.ignore_status_mask = 0;
718 if (termios->c_iflag & IGNPAR)
719 sport->port.ignore_status_mask |= URXD_PRERR;
720 if (termios->c_iflag & IGNBRK) {
721 sport->port.ignore_status_mask |= URXD_BRK;
722 /*
723 * If we're ignoring parity and break indicators,
724 * ignore overruns too (for real raw support).
725 */
726 if (termios->c_iflag & IGNPAR)
727 sport->port.ignore_status_mask |= URXD_OVRRUN;
728 }
729
730 del_timer_sync(&sport->timer);
731
732 /*
733 * Update the per-port timeout.
734 */
735 uart_update_timeout(port, termios->c_cflag, baud);
736
737 /*
738 * disable interrupts and drain transmitter
739 */
740 old_ucr1 = readl(sport->port.membase + UCR1);
741 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
742 sport->port.membase + UCR1);
743
744 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
745 barrier();
746
747 /* then, disable everything */
748 old_txrxen = readl(sport->port.membase + UCR2);
749 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
750 sport->port.membase + UCR2);
751 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
752
753 div = sport->port.uartclk / (baud * 16);
754 if (div > 7)
755 div = 7;
756 if (!div)
757 div = 1;
758
759 num = baud;
760 denom = port->uartclk / div / 16;
761
762 /* shift num and denom right until they fit into 16 bits */
763 while (num > 0x10000 || denom > 0x10000) {
764 num >>= 1;
765 denom >>= 1;
766 }
767 if (num > 0)
768 num -= 1;
769 if (denom > 0)
770 denom -= 1;
771
772 writel(num, sport->port.membase + UBIR);
773 writel(denom, sport->port.membase + UBMR);
774
775 if (div == 7)
776 div = 6; /* 6 in RFDIV means divide by 7 */
777 else
778 div = 6 - div;
779
780 ufcr = readl(sport->port.membase + UFCR);
781 ufcr = (ufcr & (~UFCR_RFDIV)) |
782 (div << 7);
783 writel(ufcr, sport->port.membase + UFCR);
784
785 #ifdef ONEMS
786 writel(sport->port.uartclk / div / 1000, sport->port.membase + ONEMS);
787 #endif
788
789 writel(old_ucr1, sport->port.membase + UCR1);
790
791 /* set the parity, stop bits and data size */
792 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
793
794 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
795 imx_enable_ms(&sport->port);
796
797 spin_unlock_irqrestore(&sport->port.lock, flags);
798 }
799
800 static const char *imx_type(struct uart_port *port)
801 {
802 struct imx_port *sport = (struct imx_port *)port;
803
804 return sport->port.type == PORT_IMX ? "IMX" : NULL;
805 }
806
807 /*
808 * Release the memory region(s) being used by 'port'.
809 */
810 static void imx_release_port(struct uart_port *port)
811 {
812 struct platform_device *pdev = to_platform_device(port->dev);
813 struct resource *mmres;
814
815 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
816 release_mem_region(mmres->start, mmres->end - mmres->start + 1);
817 }
818
819 /*
820 * Request the memory region(s) being used by 'port'.
821 */
822 static int imx_request_port(struct uart_port *port)
823 {
824 struct platform_device *pdev = to_platform_device(port->dev);
825 struct resource *mmres;
826 void *ret;
827
828 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
829 if (!mmres)
830 return -ENODEV;
831
832 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
833 "imx-uart");
834
835 return ret ? 0 : -EBUSY;
836 }
837
838 /*
839 * Configure/autoconfigure the port.
840 */
841 static void imx_config_port(struct uart_port *port, int flags)
842 {
843 struct imx_port *sport = (struct imx_port *)port;
844
845 if (flags & UART_CONFIG_TYPE &&
846 imx_request_port(&sport->port) == 0)
847 sport->port.type = PORT_IMX;
848 }
849
850 /*
851 * Verify the new serial_struct (for TIOCSSERIAL).
852 * The only change we allow are to the flags and type, and
853 * even then only between PORT_IMX and PORT_UNKNOWN
854 */
855 static int
856 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
857 {
858 struct imx_port *sport = (struct imx_port *)port;
859 int ret = 0;
860
861 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
862 ret = -EINVAL;
863 if (sport->port.irq != ser->irq)
864 ret = -EINVAL;
865 if (ser->io_type != UPIO_MEM)
866 ret = -EINVAL;
867 if (sport->port.uartclk / 16 != ser->baud_base)
868 ret = -EINVAL;
869 if ((void *)sport->port.mapbase != ser->iomem_base)
870 ret = -EINVAL;
871 if (sport->port.iobase != ser->port)
872 ret = -EINVAL;
873 if (ser->hub6 != 0)
874 ret = -EINVAL;
875 return ret;
876 }
877
878 static struct uart_ops imx_pops = {
879 .tx_empty = imx_tx_empty,
880 .set_mctrl = imx_set_mctrl,
881 .get_mctrl = imx_get_mctrl,
882 .stop_tx = imx_stop_tx,
883 .start_tx = imx_start_tx,
884 .stop_rx = imx_stop_rx,
885 .enable_ms = imx_enable_ms,
886 .break_ctl = imx_break_ctl,
887 .startup = imx_startup,
888 .shutdown = imx_shutdown,
889 .set_termios = imx_set_termios,
890 .type = imx_type,
891 .release_port = imx_release_port,
892 .request_port = imx_request_port,
893 .config_port = imx_config_port,
894 .verify_port = imx_verify_port,
895 };
896
897 static struct imx_port *imx_ports[UART_NR];
898
899 #ifdef CONFIG_SERIAL_IMX_CONSOLE
900 static void imx_console_putchar(struct uart_port *port, int ch)
901 {
902 struct imx_port *sport = (struct imx_port *)port;
903
904 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
905 barrier();
906
907 writel(ch, sport->port.membase + URTX0);
908 }
909
910 /*
911 * Interrupts are disabled on entering
912 */
913 static void
914 imx_console_write(struct console *co, const char *s, unsigned int count)
915 {
916 struct imx_port *sport = imx_ports[co->index];
917 unsigned int old_ucr1, old_ucr2;
918
919 /*
920 * First, save UCR1/2 and then disable interrupts
921 */
922 old_ucr1 = readl(sport->port.membase + UCR1);
923 old_ucr2 = readl(sport->port.membase + UCR2);
924
925 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
926 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
927 sport->port.membase + UCR1);
928
929 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
930
931 uart_console_write(&sport->port, s, count, imx_console_putchar);
932
933 /*
934 * Finally, wait for transmitter to become empty
935 * and restore UCR1/2
936 */
937 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
938
939 writel(old_ucr1, sport->port.membase + UCR1);
940 writel(old_ucr2, sport->port.membase + UCR2);
941 }
942
943 /*
944 * If the port was already initialised (eg, by a boot loader),
945 * try to determine the current setup.
946 */
947 static void __init
948 imx_console_get_options(struct imx_port *sport, int *baud,
949 int *parity, int *bits)
950 {
951
952 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
953 /* ok, the port was enabled */
954 unsigned int ucr2, ubir,ubmr, uartclk;
955 unsigned int baud_raw;
956 unsigned int ucfr_rfdiv;
957
958 ucr2 = readl(sport->port.membase + UCR2);
959
960 *parity = 'n';
961 if (ucr2 & UCR2_PREN) {
962 if (ucr2 & UCR2_PROE)
963 *parity = 'o';
964 else
965 *parity = 'e';
966 }
967
968 if (ucr2 & UCR2_WS)
969 *bits = 8;
970 else
971 *bits = 7;
972
973 ubir = readl(sport->port.membase + UBIR) & 0xffff;
974 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
975
976 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
977 if (ucfr_rfdiv == 6)
978 ucfr_rfdiv = 7;
979 else
980 ucfr_rfdiv = 6 - ucfr_rfdiv;
981
982 uartclk = clk_get_rate(sport->clk);
983 uartclk /= ucfr_rfdiv;
984
985 { /*
986 * The next code provides exact computation of
987 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
988 * without need of float support or long long division,
989 * which would be required to prevent 32bit arithmetic overflow
990 */
991 unsigned int mul = ubir + 1;
992 unsigned int div = 16 * (ubmr + 1);
993 unsigned int rem = uartclk % div;
994
995 baud_raw = (uartclk / div) * mul;
996 baud_raw += (rem * mul + div / 2) / div;
997 *baud = (baud_raw + 50) / 100 * 100;
998 }
999
1000 if(*baud != baud_raw)
1001 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1002 baud_raw, *baud);
1003 }
1004 }
1005
1006 static int __init
1007 imx_console_setup(struct console *co, char *options)
1008 {
1009 struct imx_port *sport;
1010 int baud = 9600;
1011 int bits = 8;
1012 int parity = 'n';
1013 int flow = 'n';
1014
1015 /*
1016 * Check whether an invalid uart number has been specified, and
1017 * if so, search for the first available port that does have
1018 * console support.
1019 */
1020 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1021 co->index = 0;
1022 sport = imx_ports[co->index];
1023
1024 if (options)
1025 uart_parse_options(options, &baud, &parity, &bits, &flow);
1026 else
1027 imx_console_get_options(sport, &baud, &parity, &bits);
1028
1029 imx_setup_ufcr(sport, 0);
1030
1031 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1032 }
1033
1034 static struct uart_driver imx_reg;
1035 static struct console imx_console = {
1036 .name = DEV_NAME,
1037 .write = imx_console_write,
1038 .device = uart_console_device,
1039 .setup = imx_console_setup,
1040 .flags = CON_PRINTBUFFER,
1041 .index = -1,
1042 .data = &imx_reg,
1043 };
1044
1045 #define IMX_CONSOLE &imx_console
1046 #else
1047 #define IMX_CONSOLE NULL
1048 #endif
1049
1050 static struct uart_driver imx_reg = {
1051 .owner = THIS_MODULE,
1052 .driver_name = DRIVER_NAME,
1053 .dev_name = DEV_NAME,
1054 .major = SERIAL_IMX_MAJOR,
1055 .minor = MINOR_START,
1056 .nr = ARRAY_SIZE(imx_ports),
1057 .cons = IMX_CONSOLE,
1058 };
1059
1060 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1061 {
1062 struct imx_port *sport = platform_get_drvdata(dev);
1063
1064 if (sport)
1065 uart_suspend_port(&imx_reg, &sport->port);
1066
1067 return 0;
1068 }
1069
1070 static int serial_imx_resume(struct platform_device *dev)
1071 {
1072 struct imx_port *sport = platform_get_drvdata(dev);
1073
1074 if (sport)
1075 uart_resume_port(&imx_reg, &sport->port);
1076
1077 return 0;
1078 }
1079
1080 static int serial_imx_probe(struct platform_device *pdev)
1081 {
1082 struct imx_port *sport;
1083 struct imxuart_platform_data *pdata;
1084 void __iomem *base;
1085 int ret = 0;
1086 struct resource *res;
1087
1088 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1089 if (!sport)
1090 return -ENOMEM;
1091
1092 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1093 if (!res) {
1094 ret = -ENODEV;
1095 goto free;
1096 }
1097
1098 base = ioremap(res->start, PAGE_SIZE);
1099 if (!base) {
1100 ret = -ENOMEM;
1101 goto free;
1102 }
1103
1104 sport->port.dev = &pdev->dev;
1105 sport->port.mapbase = res->start;
1106 sport->port.membase = base;
1107 sport->port.type = PORT_IMX,
1108 sport->port.iotype = UPIO_MEM;
1109 sport->port.irq = platform_get_irq(pdev, 0);
1110 sport->rxirq = platform_get_irq(pdev, 0);
1111 sport->txirq = platform_get_irq(pdev, 1);
1112 sport->rtsirq = platform_get_irq(pdev, 2);
1113 sport->port.fifosize = 32;
1114 sport->port.ops = &imx_pops;
1115 sport->port.flags = UPF_BOOT_AUTOCONF;
1116 sport->port.line = pdev->id;
1117 init_timer(&sport->timer);
1118 sport->timer.function = imx_timeout;
1119 sport->timer.data = (unsigned long)sport;
1120
1121 sport->clk = clk_get(&pdev->dev, "uart_clk");
1122 if (IS_ERR(sport->clk)) {
1123 ret = PTR_ERR(sport->clk);
1124 goto unmap;
1125 }
1126 clk_enable(sport->clk);
1127
1128 sport->port.uartclk = clk_get_rate(sport->clk);
1129
1130 imx_ports[pdev->id] = sport;
1131
1132 pdata = pdev->dev.platform_data;
1133 if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1134 sport->have_rtscts = 1;
1135
1136 if (pdata->init)
1137 pdata->init(pdev);
1138
1139 uart_add_one_port(&imx_reg, &sport->port);
1140 platform_set_drvdata(pdev, &sport->port);
1141
1142 return 0;
1143 unmap:
1144 iounmap(sport->port.membase);
1145 free:
1146 kfree(sport);
1147
1148 return ret;
1149 }
1150
1151 static int serial_imx_remove(struct platform_device *pdev)
1152 {
1153 struct imxuart_platform_data *pdata;
1154 struct imx_port *sport = platform_get_drvdata(pdev);
1155
1156 pdata = pdev->dev.platform_data;
1157
1158 platform_set_drvdata(pdev, NULL);
1159
1160 if (sport) {
1161 uart_remove_one_port(&imx_reg, &sport->port);
1162 clk_put(sport->clk);
1163 }
1164
1165 clk_disable(sport->clk);
1166
1167 if (pdata->exit)
1168 pdata->exit(pdev);
1169
1170 iounmap(sport->port.membase);
1171 kfree(sport);
1172
1173 return 0;
1174 }
1175
1176 static struct platform_driver serial_imx_driver = {
1177 .probe = serial_imx_probe,
1178 .remove = serial_imx_remove,
1179
1180 .suspend = serial_imx_suspend,
1181 .resume = serial_imx_resume,
1182 .driver = {
1183 .name = "imx-uart",
1184 .owner = THIS_MODULE,
1185 },
1186 };
1187
1188 static int __init imx_serial_init(void)
1189 {
1190 int ret;
1191
1192 printk(KERN_INFO "Serial: IMX driver\n");
1193
1194 ret = uart_register_driver(&imx_reg);
1195 if (ret)
1196 return ret;
1197
1198 ret = platform_driver_register(&serial_imx_driver);
1199 if (ret != 0)
1200 uart_unregister_driver(&imx_reg);
1201
1202 return 0;
1203 }
1204
1205 static void __exit imx_serial_exit(void)
1206 {
1207 platform_driver_unregister(&serial_imx_driver);
1208 uart_unregister_driver(&imx_reg);
1209 }
1210
1211 module_init(imx_serial_init);
1212 module_exit(imx_serial_exit);
1213
1214 MODULE_AUTHOR("Sascha Hauer");
1215 MODULE_DESCRIPTION("IMX generic serial port driver");
1216 MODULE_LICENSE("GPL");
1217 MODULE_ALIAS("platform:imx-uart");
AMDTP streaming driver for the Linux FireWire stack (Juju)