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[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
[firewire-audio.git] / arch / arm / mach-s3c2412 / clock.c
blobaf4b2ce516f99777340f5fe70afd91692bac6a93
1 /* linux/arch/arm/mach-s3c2412/clock.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412,S3C2413 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/errno.h>
28 #include <linux/err.h>
29 #include <linux/sysdev.h>
30 #include <linux/clk.h>
31 #include <linux/mutex.h>
32 #include <linux/delay.h>
33 #include <linux/serial_core.h>
34
35 #include <asm/mach/map.h>
36
37 #include <mach/hardware.h>
38 #include <asm/io.h>
39
40 #include <asm/plat-s3c/regs-serial.h>
41 #include <mach/regs-clock.h>
42 #include <mach/regs-gpio.h>
43
44 #include <asm/plat-s3c24xx/s3c2412.h>
45 #include <asm/plat-s3c24xx/clock.h>
46 #include <asm/plat-s3c24xx/cpu.h>
47
48 /* We currently have to assume that the system is running
49 * from the XTPll input, and that all ***REFCLKs are being
50 * fed from it, as we cannot read the state of OM[4] from
51 * software.
52 *
53 * It would be possible for each board initialisation to
54 * set the correct muxing at initialisation
55 */
56
57 static int s3c2412_clkcon_enable(struct clk *clk, int enable)
58 {
59 unsigned int clocks = clk->ctrlbit;
60 unsigned long clkcon;
61
62 clkcon = __raw_readl(S3C2410_CLKCON);
63
64 if (enable)
65 clkcon |= clocks;
66 else
67 clkcon &= ~clocks;
68
69 __raw_writel(clkcon, S3C2410_CLKCON);
70
71 return 0;
72 }
73
74 static int s3c2412_upll_enable(struct clk *clk, int enable)
75 {
76 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
77 unsigned long orig = upllcon;
78
79 if (!enable)
80 upllcon |= S3C2412_PLLCON_OFF;
81 else
82 upllcon &= ~S3C2412_PLLCON_OFF;
83
84 __raw_writel(upllcon, S3C2410_UPLLCON);
85
86 /* allow ~150uS for the PLL to settle and lock */
87
88 if (enable && (orig & S3C2412_PLLCON_OFF))
89 udelay(150);
90
91 return 0;
92 }
93
94 /* clock selections */
95
96 /* CPU EXTCLK input */
97 static struct clk clk_ext = {
98 .name = "extclk",
99 .id = -1,
100 };
101
102 static struct clk clk_erefclk = {
103 .name = "erefclk",
104 .id = -1,
105 };
106
107 static struct clk clk_urefclk = {
108 .name = "urefclk",
109 .id = -1,
110 };
111
112 static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
113 {
114 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
115
116 if (parent == &clk_urefclk)
117 clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
118 else if (parent == &clk_upll)
119 clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
120 else
121 return -EINVAL;
122
123 clk->parent = parent;
124
125 __raw_writel(clksrc, S3C2412_CLKSRC);
126 return 0;
127 }
128
129 static struct clk clk_usysclk = {
130 .name = "usysclk",
131 .id = -1,
132 .parent = &clk_xtal,
133 .set_parent = s3c2412_setparent_usysclk,
134 };
135
136 static struct clk clk_mrefclk = {
137 .name = "mrefclk",
138 .parent = &clk_xtal,
139 .id = -1,
140 };
141
142 static struct clk clk_mdivclk = {
143 .name = "mdivclk",
144 .parent = &clk_xtal,
145 .id = -1,
146 };
147
148 static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
149 {
150 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
151
152 if (parent == &clk_usysclk)
153 clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
154 else if (parent == &clk_h)
155 clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
156 else
157 return -EINVAL;
158
159 clk->parent = parent;
160
161 __raw_writel(clksrc, S3C2412_CLKSRC);
162 return 0;
163 }
164
165 static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
166 unsigned long rate)
167 {
168 unsigned long parent_rate = clk_get_rate(clk->parent);
169 int div;
170
171 if (rate > parent_rate)
172 return parent_rate;
173
174 div = parent_rate / rate;
175 if (div > 2)
176 div = 2;
177
178 return parent_rate / div;
179 }
180
181 static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
182 {
183 unsigned long parent_rate = clk_get_rate(clk->parent);
184 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
185
186 return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
187 }
188
189 static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
190 {
191 unsigned long parent_rate = clk_get_rate(clk->parent);
192 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
193
194 rate = s3c2412_roundrate_usbsrc(clk, rate);
195
196 if ((parent_rate / rate) == 2)
197 clkdivn |= S3C2412_CLKDIVN_USB48DIV;
198 else
199 clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
200
201 __raw_writel(clkdivn, S3C2410_CLKDIVN);
202 return 0;
203 }
204
205 static struct clk clk_usbsrc = {
206 .name = "usbsrc",
207 .id = -1,
208 .get_rate = s3c2412_getrate_usbsrc,
209 .set_rate = s3c2412_setrate_usbsrc,
210 .round_rate = s3c2412_roundrate_usbsrc,
211 .set_parent = s3c2412_setparent_usbsrc,
212 };
213
214 static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
215 {
216 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
217
218 if (parent == &clk_mdivclk)
219 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
220 else if (parent == &clk_mpll)
221 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
222 else
223 return -EINVAL;
224
225 clk->parent = parent;
226
227 __raw_writel(clksrc, S3C2412_CLKSRC);
228 return 0;
229 }
230
231 static struct clk clk_msysclk = {
232 .name = "msysclk",
233 .id = -1,
234 .set_parent = s3c2412_setparent_msysclk,
235 };
236
237 static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
238 {
239 unsigned long flags;
240 unsigned long clkdiv;
241 unsigned long dvs;
242
243 /* Note, we current equate fclk andf msysclk for S3C2412 */
244
245 if (parent == &clk_msysclk || parent == &clk_f)
246 dvs = 0;
247 else if (parent == &clk_h)
248 dvs = S3C2412_CLKDIVN_DVSEN;
249 else
250 return -EINVAL;
251
252 clk->parent = parent;
253
254 /* update this under irq lockdown, clkdivn is not protected
255 * by the clock system. */
256
257 local_irq_save(flags);
258
259 clkdiv = __raw_readl(S3C2410_CLKDIVN);
260 clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
261 clkdiv |= dvs;
262 __raw_writel(clkdiv, S3C2410_CLKDIVN);
263
264 local_irq_restore(flags);
265
266 return 0;
267 }
268
269 static struct clk clk_armclk = {
270 .name = "armclk",
271 .id = -1,
272 .parent = &clk_msysclk,
273 .set_parent = s3c2412_setparent_armclk,
274 };
275
276 /* these next clocks have an divider immediately after them,
277 * so we can register them with their divider and leave out the
278 * intermediate clock stage
279 */
280 static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
281 unsigned long rate)
282 {
283 unsigned long parent_rate = clk_get_rate(clk->parent);
284 int div;
285
286 if (rate > parent_rate)
287 return parent_rate;
288
289 /* note, we remove the +/- 1 calculations as they cancel out */
290
291 div = (rate / parent_rate);
292
293 if (div < 1)
294 div = 1;
295 else if (div > 16)
296 div = 16;
297
298 return parent_rate / div;
299 }
300
301 static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
302 {
303 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
304
305 if (parent == &clk_erefclk)
306 clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
307 else if (parent == &clk_mpll)
308 clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
309 else
310 return -EINVAL;
311
312 clk->parent = parent;
313
314 __raw_writel(clksrc, S3C2412_CLKSRC);
315 return 0;
316 }
317
318 static unsigned long s3c2412_getrate_uart(struct clk *clk)
319 {
320 unsigned long parent_rate = clk_get_rate(clk->parent);
321 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
322
323 div &= S3C2412_CLKDIVN_UARTDIV_MASK;
324 div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
325
326 return parent_rate / (div + 1);
327 }
328
329 static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
330 {
331 unsigned long parent_rate = clk_get_rate(clk->parent);
332 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
333
334 rate = s3c2412_roundrate_clksrc(clk, rate);
335
336 clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
337 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
338
339 __raw_writel(clkdivn, S3C2410_CLKDIVN);
340 return 0;
341 }
342
343 static struct clk clk_uart = {
344 .name = "uartclk",
345 .id = -1,
346 .get_rate = s3c2412_getrate_uart,
347 .set_rate = s3c2412_setrate_uart,
348 .set_parent = s3c2412_setparent_uart,
349 .round_rate = s3c2412_roundrate_clksrc,
350 };
351
352 static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
353 {
354 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
355
356 if (parent == &clk_erefclk)
357 clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
358 else if (parent == &clk_mpll)
359 clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
360 else
361 return -EINVAL;
362
363 clk->parent = parent;
364
365 __raw_writel(clksrc, S3C2412_CLKSRC);
366 return 0;
367 }
368
369 static unsigned long s3c2412_getrate_i2s(struct clk *clk)
370 {
371 unsigned long parent_rate = clk_get_rate(clk->parent);
372 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
373
374 div &= S3C2412_CLKDIVN_I2SDIV_MASK;
375 div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
376
377 return parent_rate / (div + 1);
378 }
379
380 static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
381 {
382 unsigned long parent_rate = clk_get_rate(clk->parent);
383 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
384
385 rate = s3c2412_roundrate_clksrc(clk, rate);
386
387 clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
388 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
389
390 __raw_writel(clkdivn, S3C2410_CLKDIVN);
391 return 0;
392 }
393
394 static struct clk clk_i2s = {
395 .name = "i2sclk",
396 .id = -1,
397 .get_rate = s3c2412_getrate_i2s,
398 .set_rate = s3c2412_setrate_i2s,
399 .set_parent = s3c2412_setparent_i2s,
400 .round_rate = s3c2412_roundrate_clksrc,
401 };
402
403 static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
404 {
405 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
406
407 if (parent == &clk_usysclk)
408 clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
409 else if (parent == &clk_h)
410 clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
411 else
412 return -EINVAL;
413
414 clk->parent = parent;
415
416 __raw_writel(clksrc, S3C2412_CLKSRC);
417 return 0;
418 }
419 static unsigned long s3c2412_getrate_cam(struct clk *clk)
420 {
421 unsigned long parent_rate = clk_get_rate(clk->parent);
422 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
423
424 div &= S3C2412_CLKDIVN_CAMDIV_MASK;
425 div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
426
427 return parent_rate / (div + 1);
428 }
429
430 static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
431 {
432 unsigned long parent_rate = clk_get_rate(clk->parent);
433 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
434
435 rate = s3c2412_roundrate_clksrc(clk, rate);
436
437 clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
438 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
439
440 __raw_writel(clkdivn, S3C2410_CLKDIVN);
441 return 0;
442 }
443
444 static struct clk clk_cam = {
445 .name = "camif-upll", /* same as 2440 name */
446 .id = -1,
447 .get_rate = s3c2412_getrate_cam,
448 .set_rate = s3c2412_setrate_cam,
449 .set_parent = s3c2412_setparent_cam,
450 .round_rate = s3c2412_roundrate_clksrc,
451 };
452
453 /* standard clock definitions */
454
455 static struct clk init_clocks_disable[] = {
456 {
457 .name = "nand",
458 .id = -1,
459 .parent = &clk_h,
460 .enable = s3c2412_clkcon_enable,
461 .ctrlbit = S3C2412_CLKCON_NAND,
462 }, {
463 .name = "sdi",
464 .id = -1,
465 .parent = &clk_p,
466 .enable = s3c2412_clkcon_enable,
467 .ctrlbit = S3C2412_CLKCON_SDI,
468 }, {
469 .name = "adc",
470 .id = -1,
471 .parent = &clk_p,
472 .enable = s3c2412_clkcon_enable,
473 .ctrlbit = S3C2412_CLKCON_ADC,
474 }, {
475 .name = "i2c",
476 .id = -1,
477 .parent = &clk_p,
478 .enable = s3c2412_clkcon_enable,
479 .ctrlbit = S3C2412_CLKCON_IIC,
480 }, {
481 .name = "iis",
482 .id = -1,
483 .parent = &clk_p,
484 .enable = s3c2412_clkcon_enable,
485 .ctrlbit = S3C2412_CLKCON_IIS,
486 }, {
487 .name = "spi",
488 .id = -1,
489 .parent = &clk_p,
490 .enable = s3c2412_clkcon_enable,
491 .ctrlbit = S3C2412_CLKCON_SPI,
492 }
493 };
494
495 static struct clk init_clocks[] = {
496 {
497 .name = "dma",
498 .id = 0,
499 .parent = &clk_h,
500 .enable = s3c2412_clkcon_enable,
501 .ctrlbit = S3C2412_CLKCON_DMA0,
502 }, {
503 .name = "dma",
504 .id = 1,
505 .parent = &clk_h,
506 .enable = s3c2412_clkcon_enable,
507 .ctrlbit = S3C2412_CLKCON_DMA1,
508 }, {
509 .name = "dma",
510 .id = 2,
511 .parent = &clk_h,
512 .enable = s3c2412_clkcon_enable,
513 .ctrlbit = S3C2412_CLKCON_DMA2,
514 }, {
515 .name = "dma",
516 .id = 3,
517 .parent = &clk_h,
518 .enable = s3c2412_clkcon_enable,
519 .ctrlbit = S3C2412_CLKCON_DMA3,
520 }, {
521 .name = "lcd",
522 .id = -1,
523 .parent = &clk_h,
524 .enable = s3c2412_clkcon_enable,
525 .ctrlbit = S3C2412_CLKCON_LCDC,
526 }, {
527 .name = "gpio",
528 .id = -1,
529 .parent = &clk_p,
530 .enable = s3c2412_clkcon_enable,
531 .ctrlbit = S3C2412_CLKCON_GPIO,
532 }, {
533 .name = "usb-host",
534 .id = -1,
535 .parent = &clk_h,
536 .enable = s3c2412_clkcon_enable,
537 .ctrlbit = S3C2412_CLKCON_USBH,
538 }, {
539 .name = "usb-device",
540 .id = -1,
541 .parent = &clk_h,
542 .enable = s3c2412_clkcon_enable,
543 .ctrlbit = S3C2412_CLKCON_USBD,
544 }, {
545 .name = "timers",
546 .id = -1,
547 .parent = &clk_p,
548 .enable = s3c2412_clkcon_enable,
549 .ctrlbit = S3C2412_CLKCON_PWMT,
550 }, {
551 .name = "uart",
552 .id = 0,
553 .parent = &clk_p,
554 .enable = s3c2412_clkcon_enable,
555 .ctrlbit = S3C2412_CLKCON_UART0,
556 }, {
557 .name = "uart",
558 .id = 1,
559 .parent = &clk_p,
560 .enable = s3c2412_clkcon_enable,
561 .ctrlbit = S3C2412_CLKCON_UART1,
562 }, {
563 .name = "uart",
564 .id = 2,
565 .parent = &clk_p,
566 .enable = s3c2412_clkcon_enable,
567 .ctrlbit = S3C2412_CLKCON_UART2,
568 }, {
569 .name = "rtc",
570 .id = -1,
571 .parent = &clk_p,
572 .enable = s3c2412_clkcon_enable,
573 .ctrlbit = S3C2412_CLKCON_RTC,
574 }, {
575 .name = "watchdog",
576 .id = -1,
577 .parent = &clk_p,
578 .ctrlbit = 0,
579 }, {
580 .name = "usb-bus-gadget",
581 .id = -1,
582 .parent = &clk_usb_bus,
583 .enable = s3c2412_clkcon_enable,
584 .ctrlbit = S3C2412_CLKCON_USB_DEV48,
585 }, {
586 .name = "usb-bus-host",
587 .id = -1,
588 .parent = &clk_usb_bus,
589 .enable = s3c2412_clkcon_enable,
590 .ctrlbit = S3C2412_CLKCON_USB_HOST48,
591 }
592 };
593
594 /* clocks to add where we need to check their parentage */
595
596 struct clk_init {
597 struct clk *clk;
598 unsigned int bit;
599 struct clk *src_0;
600 struct clk *src_1;
601 };
602
603 static struct clk_init clks_src[] __initdata = {
604 {
605 .clk = &clk_usysclk,
606 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
607 .src_0 = &clk_urefclk,
608 .src_1 = &clk_upll,
609 }, {
610 .clk = &clk_i2s,
611 .bit = S3C2412_CLKSRC_I2SCLK_MPLL,
612 .src_0 = &clk_erefclk,
613 .src_1 = &clk_mpll,
614 }, {
615 .clk = &clk_cam,
616 .bit = S3C2412_CLKSRC_CAMCLK_HCLK,
617 .src_0 = &clk_usysclk,
618 .src_1 = &clk_h,
619 }, {
620 .clk = &clk_msysclk,
621 .bit = S3C2412_CLKSRC_MSYSCLK_MPLL,
622 .src_0 = &clk_mdivclk,
623 .src_1 = &clk_mpll,
624 }, {
625 .clk = &clk_uart,
626 .bit = S3C2412_CLKSRC_UARTCLK_MPLL,
627 .src_0 = &clk_erefclk,
628 .src_1 = &clk_mpll,
629 }, {
630 .clk = &clk_usbsrc,
631 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
632 .src_0 = &clk_usysclk,
633 .src_1 = &clk_h,
634 /* here we assume OM[4] select xtal */
635 }, {
636 .clk = &clk_erefclk,
637 .bit = S3C2412_CLKSRC_EREFCLK_EXTCLK,
638 .src_0 = &clk_xtal,
639 .src_1 = &clk_ext,
640 }, {
641 .clk = &clk_urefclk,
642 .bit = S3C2412_CLKSRC_UREFCLK_EXTCLK,
643 .src_0 = &clk_xtal,
644 .src_1 = &clk_ext,
645 },
646 };
647
648 /* s3c2412_clk_initparents
649 *
650 * Initialise the parents for the clocks that we get at start-time
651 */
652
653 static void __init s3c2412_clk_initparents(void)
654 {
655 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
656 struct clk_init *cip = clks_src;
657 struct clk *src;
658 int ptr;
659 int ret;
660
661 for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
662 ret = s3c24xx_register_clock(cip->clk);
663 if (ret < 0) {
664 printk(KERN_ERR "Failed to register clock %s (%d)\n",
665 cip->clk->name, ret);
666 }
667
668 src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
669
670 printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
671 clk_set_parent(cip->clk, src);
672 }
673 }
674
675 /* clocks to add straight away */
676
677 static struct clk *clks[] __initdata = {
678 &clk_ext,
679 &clk_usb_bus,
680 &clk_mrefclk,
681 &clk_armclk,
682 };
683
684 int __init s3c2412_baseclk_add(void)
685 {
686 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
687 unsigned int dvs;
688 struct clk *clkp;
689 int ret;
690 int ptr;
691
692 clk_upll.enable = s3c2412_upll_enable;
693 clk_usb_bus.parent = &clk_usbsrc;
694 clk_usb_bus.rate = 0x0;
695
696 clk_f.parent = &clk_msysclk;
697
698 s3c2412_clk_initparents();
699
700 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
701 clkp = clks[ptr];
702
703 ret = s3c24xx_register_clock(clkp);
704 if (ret < 0) {
705 printk(KERN_ERR "Failed to register clock %s (%d)\n",
706 clkp->name, ret);
707 }
708 }
709
710 /* set the dvs state according to what we got at boot time */
711
712 dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
713
714 if (dvs)
715 clk_armclk.parent = &clk_h;
716
717 printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
718
719 /* ensure usb bus clock is within correct rate of 48MHz */
720
721 if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
722 printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
723
724 /* for the moment, let's use the UPLL, and see if we can
725 * get 48MHz */
726
727 clk_set_parent(&clk_usysclk, &clk_upll);
728 clk_set_parent(&clk_usbsrc, &clk_usysclk);
729 clk_set_rate(&clk_usbsrc, 48*1000*1000);
730 }
731
732 printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
733 (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
734 print_mhz(clk_get_rate(&clk_upll)),
735 print_mhz(clk_get_rate(&clk_usb_bus)));
736
737 /* register clocks from clock array */
738
739 clkp = init_clocks;
740 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
741 /* ensure that we note the clock state */
742
743 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
744
745 ret = s3c24xx_register_clock(clkp);
746 if (ret < 0) {
747 printk(KERN_ERR "Failed to register clock %s (%d)\n",
748 clkp->name, ret);
749 }
750 }
751
752 /* We must be careful disabling the clocks we are not intending to
753 * be using at boot time, as subsystems such as the LCD which do
754 * their own DMA requests to the bus can cause the system to lockup
755 * if they where in the middle of requesting bus access.
756 *
757 * Disabling the LCD clock if the LCD is active is very dangerous,
758 * and therefore the bootloader should be careful to not enable
759 * the LCD clock if it is not needed.
760 */
761
762 /* install (and disable) the clocks we do not need immediately */
763
764 clkp = init_clocks_disable;
765 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
766
767 ret = s3c24xx_register_clock(clkp);
768 if (ret < 0) {
769 printk(KERN_ERR "Failed to register clock %s (%d)\n",
770 clkp->name, ret);
771 }
772
773 s3c2412_clkcon_enable(clkp, 0);
774 }
775
776 return 0;
777 }
AMDTP streaming driver for the Linux FireWire stack (Juju)