arch/arm/mach-pxa/time.c

   1 /*
   2  * arch/arm/mach-pxa/time.c
   3  *
   4  * PXA clocksource, clockevents, and OST interrupt handlers.
   5  * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
   6  *
   7  * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
   8  * by MontaVista Software, Inc.  (Nico, your code rocks!)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/sched.h>
  20
  21 #include <asm/div64.h>
  22 #include <asm/cnt32_to_63.h>
  23 #include <asm/mach/irq.h>
  24 #include <asm/mach/time.h>
  25 #include <mach/pxa-regs.h>
  26 #include <asm/mach-types.h>
  27
  28 /*
  29  * This is PXA's sched_clock implementation. This has a resolution
  30  * of at least 308 ns and a maximum value of 208 days.
  31  *
  32  * The return value is guaranteed to be monotonic in that range as
  33  * long as there is always less than 582 seconds between successive
  34  * calls to sched_clock() which should always be the case in practice.
  35  */
  36
  37 #define OSCR2NS_SCALE_FACTOR 10
  38
  39 static unsigned long oscr2ns_scale;
  40
  41 static void __init set_oscr2ns_scale(unsigned long oscr_rate)
  42 {
  43         unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
  44         do_div(v, oscr_rate);
  45         oscr2ns_scale = v;
  46         /*
  47          * We want an even value to automatically clear the top bit
  48          * returned by cnt32_to_63() without an additional run time
  49          * instruction. So if the LSB is 1 then round it up.
  50          */
  51         if (oscr2ns_scale & 1)
  52                 oscr2ns_scale++;
  53 }
  54
  55 unsigned long long sched_clock(void)
  56 {
  57         unsigned long long v = cnt32_to_63(OSCR);
  58         return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
  59 }
  60
  61
  62 #define MIN_OSCR_DELTA 16
  63
  64 static irqreturn_t
  65 pxa_ost0_interrupt(int irq, void *dev_id)
  66 {
  67         struct clock_event_device *c = dev_id;
  68
  69         /* Disarm the compare/match, signal the event. */
  70         OIER &= ~OIER_E0;
  71         OSSR = OSSR_M0;
  72         c->event_handler(c);
  73
  74         return IRQ_HANDLED;
  75 }
  76
  77 static int
  78 pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
  79 {
  80         unsigned long flags, next, oscr;
  81
  82         raw_local_irq_save(flags);
  83         OIER |= OIER_E0;
  84         next = OSCR + delta;
  85         OSMR0 = next;
  86         oscr = OSCR;
  87         raw_local_irq_restore(flags);
  88
  89         return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
  90 }
  91
  92 static void
  93 pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
  94 {
  95         unsigned long irqflags;
  96
  97         switch (mode) {
  98         case CLOCK_EVT_MODE_ONESHOT:
  99                 raw_local_irq_save(irqflags);
 100                 OIER &= ~OIER_E0;
 101                 OSSR = OSSR_M0;
 102                 raw_local_irq_restore(irqflags);
 103                 break;
 104
 105         case CLOCK_EVT_MODE_UNUSED:
 106         case CLOCK_EVT_MODE_SHUTDOWN:
 107                 /* initializing, released, or preparing for suspend */
 108                 raw_local_irq_save(irqflags);
 109                 OIER &= ~OIER_E0;
 110                 OSSR = OSSR_M0;
 111                 raw_local_irq_restore(irqflags);
 112                 break;
 113
 114         case CLOCK_EVT_MODE_RESUME:
 115         case CLOCK_EVT_MODE_PERIODIC:
 116                 break;
 117         }
 118 }
 119
 120 static struct clock_event_device ckevt_pxa_osmr0 = {
 121         .name           = "osmr0",
 122         .features       = CLOCK_EVT_FEAT_ONESHOT,
 123         .shift          = 32,
 124         .rating         = 200,
 125         .cpumask        = CPU_MASK_CPU0,
 126         .set_next_event = pxa_osmr0_set_next_event,
 127         .set_mode       = pxa_osmr0_set_mode,
 128 };
 129
 130 static cycle_t pxa_read_oscr(void)
 131 {
 132         return OSCR;
 133 }
 134
 135 static struct clocksource cksrc_pxa_oscr0 = {
 136         .name           = "oscr0",
 137         .rating         = 200,
 138         .read           = pxa_read_oscr,
 139         .mask           = CLOCKSOURCE_MASK(32),
 140         .shift          = 20,
 141         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 142 };
 143
 144 static struct irqaction pxa_ost0_irq = {
 145         .name           = "ost0",
 146         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 147         .handler        = pxa_ost0_interrupt,
 148         .dev_id         = &ckevt_pxa_osmr0,
 149 };
 150
 151 static void __init pxa_timer_init(void)
 152 {
 153         unsigned long clock_tick_rate;
 154
 155         OIER = 0;
 156         OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
 157
 158         if (cpu_is_pxa21x() || cpu_is_pxa25x())
 159                 clock_tick_rate = 3686400;
 160         else if (machine_is_mainstone())
 161                 clock_tick_rate = 3249600;
 162         else
 163                 clock_tick_rate = 3250000;
 164
 165         set_oscr2ns_scale(clock_tick_rate);
 166
 167         ckevt_pxa_osmr0.mult =
 168                 div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
 169         ckevt_pxa_osmr0.max_delta_ns =
 170                 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
 171         ckevt_pxa_osmr0.min_delta_ns =
 172                 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
 173
 174         cksrc_pxa_oscr0.mult =
 175                 clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
 176
 177         setup_irq(IRQ_OST0, &pxa_ost0_irq);
 178
 179         clocksource_register(&cksrc_pxa_oscr0);
 180         clockevents_register_device(&ckevt_pxa_osmr0);
 181 }
 182
 183 #ifdef CONFIG_PM
 184 static unsigned long osmr[4], oier, oscr;
 185
 186 static void pxa_timer_suspend(void)
 187 {
 188         osmr[0] = OSMR0;
 189         osmr[1] = OSMR1;
 190         osmr[2] = OSMR2;
 191         osmr[3] = OSMR3;
 192         oier = OIER;
 193         oscr = OSCR;
 194 }
 195
 196 static void pxa_timer_resume(void)
 197 {
 198         /*
 199          * Ensure that we have at least MIN_OSCR_DELTA between match
 200          * register 0 and the OSCR, to guarantee that we will receive
 201          * the one-shot timer interrupt.  We adjust OSMR0 in preference
 202          * to OSCR to guarantee that OSCR is monotonically incrementing.
 203          */
 204         if (osmr[0] - oscr < MIN_OSCR_DELTA)
 205                 osmr[0] += MIN_OSCR_DELTA;
 206
 207         OSMR0 = osmr[0];
 208         OSMR1 = osmr[1];
 209         OSMR2 = osmr[2];
 210         OSMR3 = osmr[3];
 211         OIER = oier;
 212         OSCR = oscr;
 213 }
 214 #else
 215 #define pxa_timer_suspend NULL
 216 #define pxa_timer_resume NULL
 217 #endif
 218
 219 struct sys_timer pxa_timer = {
 220         .init           = pxa_timer_init,
 221         .suspend        = pxa_timer_suspend,
 222         .resume         = pxa_timer_resume,
 223 };