arch/arm/mach-omap1/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap1/pm.c
   3  *
   4  * OMAP Power Management Routines
   5  *
   6  * Original code for the SA11x0:
   7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   8  *
   9  * Modified for the PXA250 by Nicolas Pitre:
  10  * Copyright (c) 2002 Monta Vista Software, Inc.
  11  *
  12  * Modified for the OMAP1510 by David Singleton:
  13  * Copyright (c) 2002 Monta Vista Software, Inc.
  14  *
  15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the GNU General Public License along
  34  * with this program; if not, write to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/suspend.h>
  39 #include <linux/sched.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/sysfs.h>
  43 #include <linux/module.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/irq.h>
  47 #include <asm/atomic.h>
  48 #include <asm/mach/time.h>
  49 #include <asm/mach/irq.h>
  50
  51 #include <mach/cpu.h>
  52 #include <mach/irqs.h>
  53 #include <mach/clock.h>
  54 #include <mach/sram.h>
  55 #include <mach/tc.h>
  56 #include <mach/pm.h>
  57 #include <mach/mux.h>
  58 #include <mach/dma.h>
  59 #include <mach/dmtimer.h>
  60
  61 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  62 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
  63 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  64 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
  65 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  66 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  67
  68 #ifdef CONFIG_OMAP_32K_TIMER
  69
  70 static unsigned short enable_dyn_sleep = 1;
  71
  72 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
  73                          char *buf)
  74 {
  75         return sprintf(buf, "%hu\n", enable_dyn_sleep);
  76 }
  77
  78 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
  79                           const char * buf, size_t n)
  80 {
  81         unsigned short value;
  82         if (sscanf(buf, "%hu", &value) != 1 ||
  83             (value != 0 && value != 1)) {
  84                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  85                 return -EINVAL;
  86         }
  87         enable_dyn_sleep = value;
  88         return n;
  89 }
  90
  91 static struct kobj_attribute sleep_while_idle_attr =
  92         __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
  93
  94 #endif
  95
  96 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
  97
  98 /*
  99  * Let's power down on idle, but only if we are really
 100  * idle, because once we start down the path of
 101  * going idle we continue to do idle even if we get
 102  * a clock tick interrupt . .
 103  */
 104 void omap_pm_idle(void)
 105 {
 106         extern __u32 arm_idlect1_mask;
 107         __u32 use_idlect1 = arm_idlect1_mask;
 108         int do_sleep = 0;
 109
 110         local_irq_disable();
 111         local_fiq_disable();
 112         if (need_resched()) {
 113                 local_fiq_enable();
 114                 local_irq_enable();
 115                 return;
 116         }
 117
 118 #ifdef CONFIG_OMAP_MPU_TIMER
 119 #warning Enable 32kHz OS timer in order to allow sleep states in idle
 120         use_idlect1 = use_idlect1 & ~(1 << 9);
 121 #else
 122
 123         while (enable_dyn_sleep) {
 124
 125 #ifdef CONFIG_CBUS_TAHVO_USB
 126                 extern int vbus_active;
 127                 /* Clock requirements? */
 128                 if (vbus_active)
 129                         break;
 130 #endif
 131                 do_sleep = 1;
 132                 break;
 133         }
 134
 135 #endif
 136
 137 #ifdef CONFIG_OMAP_DM_TIMER
 138         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
 139 #endif
 140
 141         if (omap_dma_running())
 142                 use_idlect1 &= ~(1 << 6);
 143
 144         /* We should be able to remove the do_sleep variable and multiple
 145          * tests above as soon as drivers, timer and DMA code have been fixed.
 146          * Even the sleep block count should become obsolete. */
 147         if ((use_idlect1 != ~0) || !do_sleep) {
 148
 149                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
 150                 if (cpu_is_omap15xx())
 151                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
 152                 else
 153                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
 154                 omap_writel(use_idlect1, ARM_IDLECT1);
 155                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
 156                 omap_writel(saved_idlect1, ARM_IDLECT1);
 157
 158                 local_fiq_enable();
 159                 local_irq_enable();
 160                 return;
 161         }
 162         omap_sram_suspend(omap_readl(ARM_IDLECT1),
 163                           omap_readl(ARM_IDLECT2));
 164
 165         local_fiq_enable();
 166         local_irq_enable();
 167 }
 168
 169 /*
 170  * Configuration of the wakeup event is board specific. For the
 171  * moment we put it into this helper function. Later it may move
 172  * to board specific files.
 173  */
 174 static void omap_pm_wakeup_setup(void)
 175 {
 176         u32 level1_wake = 0;
 177         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
 178
 179         /*
 180          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
 181          * and the L2 wakeup interrupts: keypad and UART2. Note that the
 182          * drivers must still separately call omap_set_gpio_wakeup() to
 183          * wake up to a GPIO interrupt.
 184          */
 185         if (cpu_is_omap730())
 186                 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
 187                         OMAP_IRQ_BIT(INT_730_IH2_IRQ);
 188         else if (cpu_is_omap15xx())
 189                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 190                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 191         else if (cpu_is_omap16xx())
 192                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 193                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
 194
 195         omap_writel(~level1_wake, OMAP_IH1_MIR);
 196
 197         if (cpu_is_omap730()) {
 198                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 199                 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
 200                                 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
 201                                 OMAP_IH2_1_MIR);
 202         } else if (cpu_is_omap15xx()) {
 203                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 204                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
 205         } else if (cpu_is_omap16xx()) {
 206                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 207                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 208
 209                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
 210                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
 211                             OMAP_IH2_1_MIR);
 212                 omap_writel(~0x0, OMAP_IH2_2_MIR);
 213                 omap_writel(~0x0, OMAP_IH2_3_MIR);
 214         }
 215
 216         /*  New IRQ agreement, recalculate in cascade order */
 217         omap_writel(1, OMAP_IH2_CONTROL);
 218         omap_writel(1, OMAP_IH1_CONTROL);
 219 }
 220
 221 #define EN_DSPCK        13      /* ARM_CKCTL */
 222 #define EN_APICK        6       /* ARM_IDLECT2 */
 223 #define DSP_EN          1       /* ARM_RSTCT1 */
 224
 225 void omap_pm_suspend(void)
 226 {
 227         unsigned long arg0 = 0, arg1 = 0;
 228
 229         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
 230
 231         omap_serial_wake_trigger(1);
 232
 233         if (!cpu_is_omap15xx())
 234                 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
 235
 236         /*
 237          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
 238          */
 239
 240         local_irq_disable();
 241         local_fiq_disable();
 242
 243         /*
 244          * Step 2: save registers
 245          *
 246          * The omap is a strange/beautiful device. The caches, memory
 247          * and register state are preserved across power saves.
 248          * We have to save and restore very little register state to
 249          * idle the omap.
 250          *
 251          * Save interrupt, MPUI, ARM and UPLD control registers.
 252          */
 253
 254         if (cpu_is_omap730()) {
 255                 MPUI730_SAVE(OMAP_IH1_MIR);
 256                 MPUI730_SAVE(OMAP_IH2_0_MIR);
 257                 MPUI730_SAVE(OMAP_IH2_1_MIR);
 258                 MPUI730_SAVE(MPUI_CTRL);
 259                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 260                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 261                 MPUI730_SAVE(EMIFS_CONFIG);
 262                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 263
 264         } else if (cpu_is_omap15xx()) {
 265                 MPUI1510_SAVE(OMAP_IH1_MIR);
 266                 MPUI1510_SAVE(OMAP_IH2_MIR);
 267                 MPUI1510_SAVE(MPUI_CTRL);
 268                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 269                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 270                 MPUI1510_SAVE(EMIFS_CONFIG);
 271                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 272         } else if (cpu_is_omap16xx()) {
 273                 MPUI1610_SAVE(OMAP_IH1_MIR);
 274                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
 275                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
 276                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
 277                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
 278                 MPUI1610_SAVE(MPUI_CTRL);
 279                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 280                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 281                 MPUI1610_SAVE(EMIFS_CONFIG);
 282                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 283         }
 284
 285         ARM_SAVE(ARM_CKCTL);
 286         ARM_SAVE(ARM_IDLECT1);
 287         ARM_SAVE(ARM_IDLECT2);
 288         if (!(cpu_is_omap15xx()))
 289                 ARM_SAVE(ARM_IDLECT3);
 290         ARM_SAVE(ARM_EWUPCT);
 291         ARM_SAVE(ARM_RSTCT1);
 292         ARM_SAVE(ARM_RSTCT2);
 293         ARM_SAVE(ARM_SYSST);
 294         ULPD_SAVE(ULPD_CLOCK_CTRL);
 295         ULPD_SAVE(ULPD_STATUS_REQ);
 296
 297         /* (Step 3 removed - we now allow deep sleep by default) */
 298
 299         /*
 300          * Step 4: OMAP DSP Shutdown
 301          */
 302
 303         /* stop DSP */
 304         omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
 305
 306                 /* shut down dsp_ck */
 307         if (!cpu_is_omap730())
 308                 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
 309
 310         /* temporarily enabling api_ck to access DSP registers */
 311         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 312
 313         /* save DSP registers */
 314         DSP_SAVE(DSP_IDLECT2);
 315
 316         /* Stop all DSP domain clocks */
 317         __raw_writew(0, DSP_IDLECT2);
 318
 319         /*
 320          * Step 5: Wakeup Event Setup
 321          */
 322
 323         omap_pm_wakeup_setup();
 324
 325         /*
 326          * Step 6: ARM and Traffic controller shutdown
 327          */
 328
 329         /* disable ARM watchdog */
 330         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
 331         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
 332
 333         /*
 334          * Step 6b: ARM and Traffic controller shutdown
 335          *
 336          * Step 6 continues here. Prepare jump to power management
 337          * assembly code in internal SRAM.
 338          *
 339          * Since the omap_cpu_suspend routine has been copied to
 340          * SRAM, we'll do an indirect procedure call to it and pass the
 341          * contents of arm_idlect1 and arm_idlect2 so it can restore
 342          * them when it wakes up and it will return.
 343          */
 344
 345         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
 346         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
 347
 348         /*
 349          * Step 6c: ARM and Traffic controller shutdown
 350          *
 351          * Jump to assembly code. The processor will stay there
 352          * until wake up.
 353          */
 354         omap_sram_suspend(arg0, arg1);
 355
 356         /*
 357          * If we are here, processor is woken up!
 358          */
 359
 360         /*
 361          * Restore DSP clocks
 362          */
 363
 364         /* again temporarily enabling api_ck to access DSP registers */
 365         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 366
 367         /* Restore DSP domain clocks */
 368         DSP_RESTORE(DSP_IDLECT2);
 369
 370         /*
 371          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
 372          */
 373
 374         if (!(cpu_is_omap15xx()))
 375                 ARM_RESTORE(ARM_IDLECT3);
 376         ARM_RESTORE(ARM_CKCTL);
 377         ARM_RESTORE(ARM_EWUPCT);
 378         ARM_RESTORE(ARM_RSTCT1);
 379         ARM_RESTORE(ARM_RSTCT2);
 380         ARM_RESTORE(ARM_SYSST);
 381         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 382         ULPD_RESTORE(ULPD_STATUS_REQ);
 383
 384         if (cpu_is_omap730()) {
 385                 MPUI730_RESTORE(EMIFS_CONFIG);
 386                 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
 387                 MPUI730_RESTORE(OMAP_IH1_MIR);
 388                 MPUI730_RESTORE(OMAP_IH2_0_MIR);
 389                 MPUI730_RESTORE(OMAP_IH2_1_MIR);
 390         } else if (cpu_is_omap15xx()) {
 391                 MPUI1510_RESTORE(MPUI_CTRL);
 392                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 393                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
 394                 MPUI1510_RESTORE(EMIFS_CONFIG);
 395                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
 396                 MPUI1510_RESTORE(OMAP_IH1_MIR);
 397                 MPUI1510_RESTORE(OMAP_IH2_MIR);
 398         } else if (cpu_is_omap16xx()) {
 399                 MPUI1610_RESTORE(MPUI_CTRL);
 400                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
 401                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
 402                 MPUI1610_RESTORE(EMIFS_CONFIG);
 403                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
 404
 405                 MPUI1610_RESTORE(OMAP_IH1_MIR);
 406                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
 407                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
 408                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
 409                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
 410         }
 411
 412         if (!cpu_is_omap15xx())
 413                 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
 414
 415         /*
 416          * Re-enable interrupts
 417          */
 418
 419         local_irq_enable();
 420         local_fiq_enable();
 421
 422         omap_serial_wake_trigger(0);
 423
 424         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
 425 }
 426
 427 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 428 static int g_read_completed;
 429
 430 /*
 431  * Read system PM registers for debugging
 432  */
 433 static int omap_pm_read_proc(
 434         char *page_buffer,
 435         char **my_first_byte,
 436         off_t virtual_start,
 437         int length,
 438         int *eof,
 439         void *data)
 440 {
 441         int my_buffer_offset = 0;
 442         char * const my_base = page_buffer;
 443
 444         ARM_SAVE(ARM_CKCTL);
 445         ARM_SAVE(ARM_IDLECT1);
 446         ARM_SAVE(ARM_IDLECT2);
 447         if (!(cpu_is_omap15xx()))
 448                 ARM_SAVE(ARM_IDLECT3);
 449         ARM_SAVE(ARM_EWUPCT);
 450         ARM_SAVE(ARM_RSTCT1);
 451         ARM_SAVE(ARM_RSTCT2);
 452         ARM_SAVE(ARM_SYSST);
 453
 454         ULPD_SAVE(ULPD_IT_STATUS);
 455         ULPD_SAVE(ULPD_CLOCK_CTRL);
 456         ULPD_SAVE(ULPD_SOFT_REQ);
 457         ULPD_SAVE(ULPD_STATUS_REQ);
 458         ULPD_SAVE(ULPD_DPLL_CTRL);
 459         ULPD_SAVE(ULPD_POWER_CTRL);
 460
 461         if (cpu_is_omap730()) {
 462                 MPUI730_SAVE(MPUI_CTRL);
 463                 MPUI730_SAVE(MPUI_DSP_STATUS);
 464                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 465                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 466                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 467                 MPUI730_SAVE(EMIFS_CONFIG);
 468         } else if (cpu_is_omap15xx()) {
 469                 MPUI1510_SAVE(MPUI_CTRL);
 470                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 471                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 472                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 473                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 474                 MPUI1510_SAVE(EMIFS_CONFIG);
 475         } else if (cpu_is_omap16xx()) {
 476                 MPUI1610_SAVE(MPUI_CTRL);
 477                 MPUI1610_SAVE(MPUI_DSP_STATUS);
 478                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 479                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 480                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 481                 MPUI1610_SAVE(EMIFS_CONFIG);
 482         }
 483
 484         if (virtual_start == 0) {
 485                 g_read_completed = 0;
 486
 487                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
 488                    "ARM_CKCTL_REG:            0x%-8x     \n"
 489                    "ARM_IDLECT1_REG:          0x%-8x     \n"
 490                    "ARM_IDLECT2_REG:          0x%-8x     \n"
 491                    "ARM_IDLECT3_REG:          0x%-8x     \n"
 492                    "ARM_EWUPCT_REG:           0x%-8x     \n"
 493                    "ARM_RSTCT1_REG:           0x%-8x     \n"
 494                    "ARM_RSTCT2_REG:           0x%-8x     \n"
 495                    "ARM_SYSST_REG:            0x%-8x     \n"
 496                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
 497                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
 498                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
 499                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
 500                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
 501                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
 502                    ARM_SHOW(ARM_CKCTL),
 503                    ARM_SHOW(ARM_IDLECT1),
 504                    ARM_SHOW(ARM_IDLECT2),
 505                    ARM_SHOW(ARM_IDLECT3),
 506                    ARM_SHOW(ARM_EWUPCT),
 507                    ARM_SHOW(ARM_RSTCT1),
 508                    ARM_SHOW(ARM_RSTCT2),
 509                    ARM_SHOW(ARM_SYSST),
 510                    ULPD_SHOW(ULPD_IT_STATUS),
 511                    ULPD_SHOW(ULPD_CLOCK_CTRL),
 512                    ULPD_SHOW(ULPD_SOFT_REQ),
 513                    ULPD_SHOW(ULPD_DPLL_CTRL),
 514                    ULPD_SHOW(ULPD_STATUS_REQ),
 515                    ULPD_SHOW(ULPD_POWER_CTRL));
 516
 517                 if (cpu_is_omap730()) {
 518                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 519                            "MPUI730_CTRL_REG         0x%-8x \n"
 520                            "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
 521                            "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 522                            "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
 523                            "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
 524                            "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
 525                            MPUI730_SHOW(MPUI_CTRL),
 526                            MPUI730_SHOW(MPUI_DSP_STATUS),
 527                            MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
 528                            MPUI730_SHOW(MPUI_DSP_API_CONFIG),
 529                            MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
 530                            MPUI730_SHOW(EMIFS_CONFIG));
 531                 } else if (cpu_is_omap15xx()) {
 532                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 533                            "MPUI1510_CTRL_REG             0x%-8x \n"
 534                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
 535                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 536                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
 537                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
 538                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
 539                            MPUI1510_SHOW(MPUI_CTRL),
 540                            MPUI1510_SHOW(MPUI_DSP_STATUS),
 541                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
 542                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
 543                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
 544                            MPUI1510_SHOW(EMIFS_CONFIG));
 545                 } else if (cpu_is_omap16xx()) {
 546                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 547                            "MPUI1610_CTRL_REG             0x%-8x \n"
 548                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
 549                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 550                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
 551                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
 552                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
 553                            MPUI1610_SHOW(MPUI_CTRL),
 554                            MPUI1610_SHOW(MPUI_DSP_STATUS),
 555                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
 556                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
 557                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
 558                            MPUI1610_SHOW(EMIFS_CONFIG));
 559                 }
 560
 561                 g_read_completed++;
 562         } else if (g_read_completed >= 1) {
 563                  *eof = 1;
 564                  return 0;
 565         }
 566         g_read_completed++;
 567
 568         *my_first_byte = page_buffer;
 569         return  my_buffer_offset;
 570 }
 571
 572 static void omap_pm_init_proc(void)
 573 {
 574         struct proc_dir_entry *entry;
 575
 576         entry = create_proc_read_entry("driver/omap_pm",
 577                                        S_IWUSR | S_IRUGO, NULL,
 578                                        omap_pm_read_proc, NULL);
 579 }
 580
 581 #endif /* DEBUG && CONFIG_PROC_FS */
 582
 583 static void (*saved_idle)(void) = NULL;
 584
 585 /*
 586  *      omap_pm_prepare - Do preliminary suspend work.
 587  *
 588  */
 589 static int omap_pm_prepare(void)
 590 {
 591         /* We cannot sleep in idle until we have resumed */
 592         saved_idle = pm_idle;
 593         pm_idle = NULL;
 594
 595         return 0;
 596 }
 597
 598
 599 /*
 600  *      omap_pm_enter - Actually enter a sleep state.
 601  *      @state:         State we're entering.
 602  *
 603  */
 604
 605 static int omap_pm_enter(suspend_state_t state)
 606 {
 607         switch (state)
 608         {
 609         case PM_SUSPEND_STANDBY:
 610         case PM_SUSPEND_MEM:
 611                 omap_pm_suspend();
 612                 break;
 613         default:
 614                 return -EINVAL;
 615         }
 616
 617         return 0;
 618 }
 619
 620
 621 /**
 622  *      omap_pm_finish - Finish up suspend sequence.
 623  *
 624  *      This is called after we wake back up (or if entering the sleep state
 625  *      failed).
 626  */
 627
 628 static void omap_pm_finish(void)
 629 {
 630         pm_idle = saved_idle;
 631 }
 632
 633
 634 static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
 635 {
 636         return IRQ_HANDLED;
 637 }
 638
 639 static struct irqaction omap_wakeup_irq = {
 640         .name           = "peripheral wakeup",
 641         .flags          = IRQF_DISABLED,
 642         .handler        = omap_wakeup_interrupt
 643 };
 644
 645
 646
 647 static struct platform_suspend_ops omap_pm_ops ={
 648         .prepare        = omap_pm_prepare,
 649         .enter          = omap_pm_enter,
 650         .finish         = omap_pm_finish,
 651         .valid          = suspend_valid_only_mem,
 652 };
 653
 654 static int __init omap_pm_init(void)
 655 {
 656
 657 #ifdef CONFIG_OMAP_32K_TIMER
 658         int error;
 659 #endif
 660
 661         printk("Power Management for TI OMAP.\n");
 662
 663         /*
 664          * We copy the assembler sleep/wakeup routines to SRAM.
 665          * These routines need to be in SRAM as that's the only
 666          * memory the MPU can see when it wakes up.
 667          */
 668         if (cpu_is_omap730()) {
 669                 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
 670                                                    omap730_cpu_suspend_sz);
 671         } else if (cpu_is_omap15xx()) {
 672                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 673                                                    omap1510_cpu_suspend_sz);
 674         } else if (cpu_is_omap16xx()) {
 675                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
 676                                                    omap1610_cpu_suspend_sz);
 677         }
 678
 679         if (omap_sram_suspend == NULL) {
 680                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
 681                 return -ENODEV;
 682         }
 683
 684         pm_idle = omap_pm_idle;
 685
 686         if (cpu_is_omap730())
 687                 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
 688         else if (cpu_is_omap16xx())
 689                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 690
 691         /* Program new power ramp-up time
 692          * (0 for most boards since we don't lower voltage when in deep sleep)
 693          */
 694         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
 695
 696         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
 697         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 698
 699         /* Configure IDLECT3 */
 700         if (cpu_is_omap730())
 701                 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
 702         else if (cpu_is_omap16xx())
 703                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 704
 705         suspend_set_ops(&omap_pm_ops);
 706
 707 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 708         omap_pm_init_proc();
 709 #endif
 710
 711 #ifdef CONFIG_OMAP_32K_TIMER
 712         error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
 713         if (error)
 714                 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
 715 #endif
 716
 717         if (cpu_is_omap16xx()) {
 718                 /* configure LOW_PWR pin */
 719                 omap_cfg_reg(T20_1610_LOW_PWR);
 720         }
 721
 722         return 0;
 723 }
 724 __initcall(omap_pm_init);