2 * Copyright (C) 1995 Linus Torvalds
3 * Copyright 2010 Tilera Corporation. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation, version 2.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for
16 #include <linux/module.h>
17 #include <linux/signal.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/string.h>
22 #include <linux/types.h>
23 #include <linux/ptrace.h>
24 #include <linux/mman.h>
26 #include <linux/hugetlb.h>
27 #include <linux/swap.h>
28 #include <linux/smp.h>
29 #include <linux/init.h>
30 #include <linux/highmem.h>
31 #include <linux/pagemap.h>
32 #include <linux/poison.h>
33 #include <linux/bootmem.h>
34 #include <linux/slab.h>
35 #include <linux/proc_fs.h>
36 #include <linux/efi.h>
37 #include <linux/memory_hotplug.h>
38 #include <linux/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/processor.h>
41 #include <asm/system.h>
42 #include <asm/pgtable.h>
43 #include <asm/pgalloc.h>
45 #include <asm/fixmap.h>
47 #include <asm/tlbflush.h>
48 #include <asm/sections.h>
49 #include <asm/setup.h>
50 #include <asm/homecache.h>
51 #include <hv/hypervisor.h>
52 #include <arch/chip.h>
57 * We could set FORCE_MAX_ZONEORDER to "(HPAGE_SHIFT - PAGE_SHIFT + 1)"
58 * in the Tile Kconfig, but this generates configure warnings.
59 * Do it here and force people to get it right to compile this file.
60 * The problem is that with 4KB small pages and 16MB huge pages,
61 * the default value doesn't allow us to group enough small pages
62 * together to make up a huge page.
64 #if CONFIG_FORCE_MAX_ZONEORDER < HPAGE_SHIFT - PAGE_SHIFT + 1
65 # error "Change FORCE_MAX_ZONEORDER in arch/tile/Kconfig to match page size"
68 #define clear_pgd(pmdptr) (*(pmdptr) = hv_pte(0))
71 unsigned long VMALLOC_RESERVE
= CONFIG_VMALLOC_RESERVE
;
74 DEFINE_PER_CPU(struct mmu_gather
, mmu_gathers
);
76 /* Create an L2 page table */
77 static pte_t
* __init
alloc_pte(void)
79 return __alloc_bootmem(L2_KERNEL_PGTABLE_SIZE
, HV_PAGE_TABLE_ALIGN
, 0);
83 * L2 page tables per controller. We allocate these all at once from
84 * the bootmem allocator and store them here. This saves on kernel L2
85 * page table memory, compared to allocating a full 64K page per L2
86 * page table, and also means that in cases where we use huge pages,
87 * we are guaranteed to later be able to shatter those huge pages and
88 * switch to using these page tables instead, without requiring
89 * further allocation. Each l2_ptes[] entry points to the first page
90 * table for the first hugepage-size piece of memory on the
91 * controller; other page tables are just indexed directly, i.e. the
92 * L2 page tables are contiguous in memory for each controller.
94 static pte_t
*l2_ptes
[MAX_NUMNODES
];
95 static int num_l2_ptes
[MAX_NUMNODES
];
97 static void init_prealloc_ptes(int node
, int pages
)
99 BUG_ON(pages
& (HV_L2_ENTRIES
-1));
101 num_l2_ptes
[node
] = pages
;
102 l2_ptes
[node
] = __alloc_bootmem(pages
* sizeof(pte_t
),
103 HV_PAGE_TABLE_ALIGN
, 0);
107 pte_t
*get_prealloc_pte(unsigned long pfn
)
109 int node
= pfn_to_nid(pfn
);
110 pfn
&= ~(-1UL << (NR_PA_HIGHBIT_SHIFT
- PAGE_SHIFT
));
111 BUG_ON(node
>= MAX_NUMNODES
);
112 BUG_ON(pfn
>= num_l2_ptes
[node
]);
113 return &l2_ptes
[node
][pfn
];
117 * What caching do we expect pages from the heap to have when
118 * they are allocated during bootup? (Once we've installed the
119 * "real" swapper_pg_dir.)
121 static int initial_heap_home(void)
123 #if CHIP_HAS_CBOX_HOME_MAP()
125 return PAGE_HOME_HASH
;
127 return smp_processor_id();
131 * Place a pointer to an L2 page table in a middle page
134 static void __init
assign_pte(pmd_t
*pmd
, pte_t
*page_table
)
136 phys_addr_t pa
= __pa(page_table
);
137 unsigned long l2_ptfn
= pa
>> HV_LOG2_PAGE_TABLE_ALIGN
;
138 pte_t pteval
= hv_pte_set_ptfn(__pgprot(_PAGE_TABLE
), l2_ptfn
);
139 BUG_ON((pa
& (HV_PAGE_TABLE_ALIGN
-1)) != 0);
140 pteval
= pte_set_home(pteval
, initial_heap_home());
141 *(pte_t
*)pmd
= pteval
;
142 if (page_table
!= (pte_t
*)pmd_page_vaddr(*pmd
))
148 #if HV_L1_SIZE != HV_L2_SIZE
149 # error Rework assumption that L1 and L2 page tables are same size.
152 /* Since pmd_t arrays and pte_t arrays are the same size, just use casts. */
153 static inline pmd_t
*alloc_pmd(void)
155 return (pmd_t
*)alloc_pte();
158 static inline void assign_pmd(pud_t
*pud
, pmd_t
*pmd
)
160 assign_pte((pmd_t
*)pud
, (pte_t
*)pmd
);
163 #endif /* __tilegx__ */
165 /* Replace the given pmd with a full PTE table. */
166 void __init
shatter_pmd(pmd_t
*pmd
)
168 pte_t
*pte
= get_prealloc_pte(pte_pfn(*(pte_t
*)pmd
));
169 assign_pte(pmd
, pte
);
172 #ifdef CONFIG_HIGHMEM
174 * This function initializes a certain range of kernel virtual memory
175 * with new bootmem page tables, everywhere page tables are missing in
180 * NOTE: The pagetables are allocated contiguous on the physical space
181 * so we can cache the place of the first one and move around without
182 * checking the pgd every time.
184 static void __init
page_table_range_init(unsigned long start
,
185 unsigned long end
, pgd_t
*pgd_base
)
192 pgd_idx
= pgd_index(vaddr
);
193 pgd
= pgd_base
+ pgd_idx
;
195 for ( ; (pgd_idx
< PTRS_PER_PGD
) && (vaddr
!= end
); pgd
++, pgd_idx
++) {
196 pmd_t
*pmd
= pmd_offset(pud_offset(pgd
, vaddr
), vaddr
);
198 assign_pte(pmd
, alloc_pte());
202 #endif /* CONFIG_HIGHMEM */
205 #if CHIP_HAS_CBOX_HOME_MAP()
207 static int __initdata ktext_hash
= 1; /* .text pages */
208 static int __initdata kdata_hash
= 1; /* .data and .bss pages */
209 int __write_once hash_default
= 1; /* kernel allocator pages */
210 EXPORT_SYMBOL(hash_default
);
211 int __write_once kstack_hash
= 1; /* if no homecaching, use h4h */
212 #endif /* CHIP_HAS_CBOX_HOME_MAP */
215 * CPUs to use to for striping the pages of kernel data. If hash-for-home
216 * is available, this is only relevant if kcache_hash sets up the
217 * .data and .bss to be page-homed, and we don't want the default mode
218 * of using the full set of kernel cpus for the striping.
220 static __initdata
struct cpumask kdata_mask
;
221 static __initdata
int kdata_arg_seen
;
223 int __write_once kdata_huge
; /* if no homecaching, small pages */
226 /* Combine a generic pgprot_t with cache home to get a cache-aware pgprot. */
227 static pgprot_t __init
construct_pgprot(pgprot_t prot
, int home
)
229 prot
= pte_set_home(prot
, home
);
230 #if CHIP_HAS_CBOX_HOME_MAP()
231 if (home
== PAGE_HOME_IMMUTABLE
) {
233 prot
= hv_pte_set_mode(prot
, HV_PTE_MODE_CACHE_HASH_L3
);
235 prot
= hv_pte_set_mode(prot
, HV_PTE_MODE_CACHE_NO_L3
);
242 * For a given kernel data VA, how should it be cached?
243 * We return the complete pgprot_t with caching bits set.
245 static pgprot_t __init
init_pgprot(ulong address
)
249 enum { CODE_DELTA
= MEM_SV_INTRPT
- PAGE_OFFSET
};
251 #if CHIP_HAS_CBOX_HOME_MAP()
252 /* For kdata=huge, everything is just hash-for-home. */
254 return construct_pgprot(PAGE_KERNEL
, PAGE_HOME_HASH
);
257 /* We map the aliased pages of permanent text inaccessible. */
258 if (address
< (ulong
) _sinittext
- CODE_DELTA
)
262 * We map read-only data non-coherent for performance. We could
263 * use neighborhood caching on TILE64, but it's not clear it's a win.
265 if ((address
>= (ulong
) __start_rodata
&&
266 address
< (ulong
) __end_rodata
) ||
267 address
== (ulong
) empty_zero_page
) {
268 return construct_pgprot(PAGE_KERNEL_RO
, PAGE_HOME_IMMUTABLE
);
271 /* As a performance optimization, keep the boot init stack here. */
272 if (address
>= (ulong
)&init_thread_union
&&
273 address
< (ulong
)&init_thread_union
+ THREAD_SIZE
)
274 return construct_pgprot(PAGE_KERNEL
, smp_processor_id());
277 #if !ATOMIC_LOCKS_FOUND_VIA_TABLE()
278 /* Force the atomic_locks[] array page to be hash-for-home. */
279 if (address
== (ulong
) atomic_locks
)
280 return construct_pgprot(PAGE_KERNEL
, PAGE_HOME_HASH
);
285 * Everything else that isn't data or bss is heap, so mark it
286 * with the initial heap home (hash-for-home, or this cpu). This
287 * includes any addresses after the loaded image and any address before
288 * _einitdata, since we already captured the case of text before
289 * _sinittext, and __pa(einittext) is approximately __pa(sinitdata).
291 * All the LOWMEM pages that we mark this way will get their
292 * struct page homecache properly marked later, in set_page_homes().
293 * The HIGHMEM pages we leave with a default zero for their
294 * homes, but with a zero free_time we don't have to actually
295 * do a flush action the first time we use them, either.
297 if (address
>= (ulong
) _end
|| address
< (ulong
) _einitdata
)
298 return construct_pgprot(PAGE_KERNEL
, initial_heap_home());
300 #if CHIP_HAS_CBOX_HOME_MAP()
301 /* Use hash-for-home if requested for data/bss. */
303 return construct_pgprot(PAGE_KERNEL
, PAGE_HOME_HASH
);
307 * Make the w1data homed like heap to start with, to avoid
308 * making it part of the page-striped data area when we're just
309 * going to convert it to read-only soon anyway.
311 if (address
>= (ulong
)__w1data_begin
&& address
< (ulong
)__w1data_end
)
312 return construct_pgprot(PAGE_KERNEL
, initial_heap_home());
315 * Otherwise we just hand out consecutive cpus. To avoid
316 * requiring this function to hold state, we just walk forward from
317 * _sdata by PAGE_SIZE, skipping the readonly and init data, to reach
318 * the requested address, while walking cpu home around kdata_mask.
319 * This is typically no more than a dozen or so iterations.
321 page
= (((ulong
)__w1data_end
) + PAGE_SIZE
- 1) & PAGE_MASK
;
322 BUG_ON(address
< page
|| address
>= (ulong
)_end
);
323 cpu
= cpumask_first(&kdata_mask
);
324 for (; page
< address
; page
+= PAGE_SIZE
) {
325 if (page
>= (ulong
)&init_thread_union
&&
326 page
< (ulong
)&init_thread_union
+ THREAD_SIZE
)
328 if (page
== (ulong
)empty_zero_page
)
331 #if !ATOMIC_LOCKS_FOUND_VIA_TABLE()
332 if (page
== (ulong
)atomic_locks
)
336 cpu
= cpumask_next(cpu
, &kdata_mask
);
338 cpu
= cpumask_first(&kdata_mask
);
340 return construct_pgprot(PAGE_KERNEL
, cpu
);
344 * This function sets up how we cache the kernel text. If we have
345 * hash-for-home support, normally that is used instead (see the
346 * kcache_hash boot flag for more information). But if we end up
347 * using a page-based caching technique, this option sets up the
348 * details of that. In addition, the "ktext=nocache" option may
349 * always be used to disable local caching of text pages, if desired.
352 static int __initdata ktext_arg_seen
;
353 static int __initdata ktext_small
;
354 static int __initdata ktext_local
;
355 static int __initdata ktext_all
;
356 static int __initdata ktext_nondataplane
;
357 static int __initdata ktext_nocache
;
358 static struct cpumask __initdata ktext_mask
;
360 static int __init
setup_ktext(char *str
)
365 /* If you have a leading "nocache", turn off ktext caching */
366 if (strncmp(str
, "nocache", 7) == 0) {
368 pr_info("ktext: disabling local caching of kernel text\n");
378 /* Default setting on Tile64: use a huge page */
379 if (strcmp(str
, "huge") == 0)
380 pr_info("ktext: using one huge locally cached page\n");
382 /* Pay TLB cost but get no cache benefit: cache small pages locally */
383 else if (strcmp(str
, "local") == 0) {
386 pr_info("ktext: using small pages with local caching\n");
389 /* Neighborhood cache ktext pages on all cpus. */
390 else if (strcmp(str
, "all") == 0) {
393 pr_info("ktext: using maximal caching neighborhood\n");
397 /* Neighborhood ktext pages on specified mask */
398 else if (cpulist_parse(str
, &ktext_mask
) == 0) {
399 char buf
[NR_CPUS
* 5];
400 cpulist_scnprintf(buf
, sizeof(buf
), &ktext_mask
);
401 if (cpumask_weight(&ktext_mask
) > 1) {
403 pr_info("ktext: using caching neighborhood %s "
404 "with small pages\n", buf
);
406 pr_info("ktext: caching on cpu %s with one huge page\n",
417 early_param("ktext", setup_ktext
);
420 static inline pgprot_t
ktext_set_nocache(pgprot_t prot
)
423 prot
= hv_pte_set_nc(prot
);
424 #if CHIP_HAS_NC_AND_NOALLOC_BITS()
426 prot
= hv_pte_set_no_alloc_l2(prot
);
432 static pmd_t
*__init
get_pmd(pgd_t pgtables
[], unsigned long va
)
434 return pmd_offset(pud_offset(&pgtables
[pgd_index(va
)], va
), va
);
437 static pmd_t
*__init
get_pmd(pgd_t pgtables
[], unsigned long va
)
439 pud_t
*pud
= pud_offset(&pgtables
[pgd_index(va
)], va
);
441 assign_pmd(pud
, alloc_pmd());
442 return pmd_offset(pud
, va
);
446 /* Temporary page table we use for staging. */
447 static pgd_t pgtables
[PTRS_PER_PGD
]
448 __attribute__((section(".init.page")));
451 * This maps the physical memory to kernel virtual address space, a total
452 * of max_low_pfn pages, by creating page tables starting from address
455 * This routine transitions us from using a set of compiled-in large
456 * pages to using some more precise caching, including removing access
457 * to code pages mapped at PAGE_OFFSET (executed only at MEM_SV_START)
458 * marking read-only data as locally cacheable, striping the remaining
459 * .data and .bss across all the available tiles, and removing access
460 * to pages above the top of RAM (thus ensuring a page fault from a bad
461 * virtual address rather than a hypervisor shoot down for accessing
462 * memory outside the assigned limits).
464 static void __init
kernel_physical_mapping_init(pgd_t
*pgd_base
)
466 unsigned long address
, pfn
;
470 const struct cpumask
*my_cpu_mask
= cpumask_of(smp_processor_id());
471 struct cpumask kstripe_mask
;
474 #if CHIP_HAS_CBOX_HOME_MAP()
475 if (ktext_arg_seen
&& ktext_hash
) {
476 pr_warning("warning: \"ktext\" boot argument ignored"
477 " if \"kcache_hash\" sets up text hash-for-home\n");
481 if (kdata_arg_seen
&& kdata_hash
) {
482 pr_warning("warning: \"kdata\" boot argument ignored"
483 " if \"kcache_hash\" sets up data hash-for-home\n");
486 if (kdata_huge
&& !hash_default
) {
487 pr_warning("warning: disabling \"kdata=huge\"; requires"
488 " kcache_hash=all or =allbutstack\n");
494 * Set up a mask for cpus to use for kernel striping.
495 * This is normally all cpus, but minus dataplane cpus if any.
496 * If the dataplane covers the whole chip, we stripe over
497 * the whole chip too.
499 cpumask_copy(&kstripe_mask
, cpu_possible_mask
);
501 kdata_mask
= kstripe_mask
;
503 /* Allocate and fill in L2 page tables */
504 for (i
= 0; i
< MAX_NUMNODES
; ++i
) {
505 #ifdef CONFIG_HIGHMEM
506 unsigned long end_pfn
= node_lowmem_end_pfn
[i
];
508 unsigned long end_pfn
= node_end_pfn
[i
];
510 unsigned long end_huge_pfn
= 0;
512 /* Pre-shatter the last huge page to allow per-cpu pages. */
514 end_huge_pfn
= end_pfn
- (HPAGE_SIZE
>> PAGE_SHIFT
);
516 pfn
= node_start_pfn
[i
];
518 /* Allocate enough memory to hold L2 page tables for node. */
519 init_prealloc_ptes(i
, end_pfn
- pfn
);
521 address
= (unsigned long) pfn_to_kaddr(pfn
);
522 while (pfn
< end_pfn
) {
523 BUG_ON(address
& (HPAGE_SIZE
-1));
524 pmd
= get_pmd(pgtables
, address
);
525 pte
= get_prealloc_pte(pfn
);
526 if (pfn
< end_huge_pfn
) {
527 pgprot_t prot
= init_pgprot(address
);
528 *(pte_t
*)pmd
= pte_mkhuge(pfn_pte(pfn
, prot
));
529 for (pte_ofs
= 0; pte_ofs
< PTRS_PER_PTE
;
530 pfn
++, pte_ofs
++, address
+= PAGE_SIZE
)
531 pte
[pte_ofs
] = pfn_pte(pfn
, prot
);
534 printk(KERN_DEBUG
"pre-shattered huge"
535 " page at %#lx\n", address
);
536 for (pte_ofs
= 0; pte_ofs
< PTRS_PER_PTE
;
537 pfn
++, pte_ofs
++, address
+= PAGE_SIZE
) {
538 pgprot_t prot
= init_pgprot(address
);
539 pte
[pte_ofs
] = pfn_pte(pfn
, prot
);
541 assign_pte(pmd
, pte
);
547 * Set or check ktext_map now that we have cpu_possible_mask
548 * and kstripe_mask to work with.
551 cpumask_copy(&ktext_mask
, cpu_possible_mask
);
552 else if (ktext_nondataplane
)
553 ktext_mask
= kstripe_mask
;
554 else if (!cpumask_empty(&ktext_mask
)) {
555 /* Sanity-check any mask that was requested */
557 cpumask_andnot(&bad
, &ktext_mask
, cpu_possible_mask
);
558 cpumask_and(&ktext_mask
, &ktext_mask
, cpu_possible_mask
);
559 if (!cpumask_empty(&bad
)) {
560 char buf
[NR_CPUS
* 5];
561 cpulist_scnprintf(buf
, sizeof(buf
), &bad
);
562 pr_info("ktext: not using unavailable cpus %s\n", buf
);
564 if (cpumask_empty(&ktext_mask
)) {
565 pr_warning("ktext: no valid cpus; caching on %d.\n",
567 cpumask_copy(&ktext_mask
,
568 cpumask_of(smp_processor_id()));
572 address
= MEM_SV_INTRPT
;
573 pmd
= get_pmd(pgtables
, address
);
575 /* Allocate an L2 PTE for the kernel text */
577 pgprot_t prot
= construct_pgprot(PAGE_KERNEL_EXEC
,
578 PAGE_HOME_IMMUTABLE
);
582 prot
= hv_pte_set_mode(prot
,
583 HV_PTE_MODE_UNCACHED
);
585 prot
= hv_pte_set_mode(prot
,
586 HV_PTE_MODE_CACHE_NO_L3
);
588 prot
= hv_pte_set_mode(prot
,
589 HV_PTE_MODE_CACHE_TILE_L3
);
590 cpu
= cpumask_first(&ktext_mask
);
592 prot
= ktext_set_nocache(prot
);
595 BUG_ON(address
!= (unsigned long)_stext
);
596 pfn
= 0; /* code starts at PA 0 */
598 for (pte_ofs
= 0; address
< (unsigned long)_einittext
;
599 pfn
++, pte_ofs
++, address
+= PAGE_SIZE
) {
601 prot
= set_remote_cache_cpu(prot
, cpu
);
602 cpu
= cpumask_next(cpu
, &ktext_mask
);
604 cpu
= cpumask_first(&ktext_mask
);
606 pte
[pte_ofs
] = pfn_pte(pfn
, prot
);
608 assign_pte(pmd
, pte
);
610 pte_t pteval
= pfn_pte(0, PAGE_KERNEL_EXEC
);
611 pteval
= pte_mkhuge(pteval
);
612 #if CHIP_HAS_CBOX_HOME_MAP()
614 pteval
= hv_pte_set_mode(pteval
,
615 HV_PTE_MODE_CACHE_HASH_L3
);
616 pteval
= ktext_set_nocache(pteval
);
618 #endif /* CHIP_HAS_CBOX_HOME_MAP() */
619 if (cpumask_weight(&ktext_mask
) == 1) {
620 pteval
= set_remote_cache_cpu(pteval
,
621 cpumask_first(&ktext_mask
));
622 pteval
= hv_pte_set_mode(pteval
,
623 HV_PTE_MODE_CACHE_TILE_L3
);
624 pteval
= ktext_set_nocache(pteval
);
625 } else if (ktext_nocache
)
626 pteval
= hv_pte_set_mode(pteval
,
627 HV_PTE_MODE_UNCACHED
);
629 pteval
= hv_pte_set_mode(pteval
,
630 HV_PTE_MODE_CACHE_NO_L3
);
631 *(pte_t
*)pmd
= pteval
;
634 /* Set swapper_pgprot here so it is flushed to memory right away. */
635 swapper_pgprot
= init_pgprot((unsigned long)swapper_pg_dir
);
638 * Since we may be changing the caching of the stack and page
639 * table itself, we invoke an assembly helper to do the
642 * - flush the cache so we start with an empty slate
643 * - install pgtables[] as the real page table
644 * - flush the TLB so the new page table takes effect
646 rc
= flush_and_install_context(__pa(pgtables
),
647 init_pgprot((unsigned long)pgtables
),
648 __get_cpu_var(current_asid
),
649 cpumask_bits(my_cpu_mask
));
652 /* Copy the page table back to the normal swapper_pg_dir. */
653 memcpy(pgd_base
, pgtables
, sizeof(pgtables
));
654 __install_page_table(pgd_base
, __get_cpu_var(current_asid
),
659 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
660 * is valid. The argument is a physical page number.
662 * On Tile, the only valid things for which we can just hand out unchecked
663 * PTEs are the kernel code and data. Anything else might change its
664 * homing with time, and we wouldn't know to adjust the /dev/mem PTEs.
665 * Note that init_thread_union is released to heap soon after boot,
666 * so we include it in the init data.
668 * For TILE-Gx, we might want to consider allowing access to PA
669 * regions corresponding to PCI space, etc.
671 int devmem_is_allowed(unsigned long pagenr
)
673 return pagenr
< kaddr_to_pfn(_end
) &&
674 !(pagenr
>= kaddr_to_pfn(&init_thread_union
) ||
675 pagenr
< kaddr_to_pfn(_einitdata
)) &&
676 !(pagenr
>= kaddr_to_pfn(_sinittext
) ||
677 pagenr
<= kaddr_to_pfn(_einittext
-1));
680 #ifdef CONFIG_HIGHMEM
681 static void __init
permanent_kmaps_init(pgd_t
*pgd_base
)
690 page_table_range_init(vaddr
, vaddr
+ PAGE_SIZE
*LAST_PKMAP
, pgd_base
);
692 pgd
= swapper_pg_dir
+ pgd_index(vaddr
);
693 pud
= pud_offset(pgd
, vaddr
);
694 pmd
= pmd_offset(pud
, vaddr
);
695 pte
= pte_offset_kernel(pmd
, vaddr
);
696 pkmap_page_table
= pte
;
698 #endif /* CONFIG_HIGHMEM */
701 static void __init
init_free_pfn_range(unsigned long start
, unsigned long end
)
704 struct page
*page
= pfn_to_page(start
);
706 for (pfn
= start
; pfn
< end
; ) {
707 /* Optimize by freeing pages in large batches */
708 int order
= __ffs(pfn
);
712 if (order
>= MAX_ORDER
)
715 while (pfn
+ count
> end
) {
719 for (p
= page
, i
= 0; i
< count
; ++i
, ++p
) {
720 __ClearPageReserved(p
);
722 * Hacky direct set to avoid unnecessary
723 * lock take/release for EVERY page here.
725 p
->_count
.counter
= 0;
726 p
->_mapcount
.counter
= -1;
728 init_page_count(page
);
729 __free_pages(page
, order
);
730 totalram_pages
+= count
;
737 static void __init
set_non_bootmem_pages_init(void)
741 unsigned long start
, end
;
742 int nid
= z
->zone_pgdat
->node_id
;
743 int idx
= zone_idx(z
);
745 start
= z
->zone_start_pfn
;
747 continue; /* bootmem */
748 end
= start
+ z
->spanned_pages
;
749 if (idx
== ZONE_NORMAL
) {
750 BUG_ON(start
!= node_start_pfn
[nid
]);
751 start
= node_free_pfn
[nid
];
753 #ifdef CONFIG_HIGHMEM
754 if (idx
== ZONE_HIGHMEM
)
755 totalhigh_pages
+= z
->spanned_pages
;
758 unsigned long percpu_pfn
= node_percpu_pfn
[nid
];
759 if (start
< percpu_pfn
&& end
> percpu_pfn
)
763 if (start
<= pci_reserve_start_pfn
&&
764 end
> pci_reserve_start_pfn
) {
765 if (end
> pci_reserve_end_pfn
)
766 init_free_pfn_range(pci_reserve_end_pfn
, end
);
767 end
= pci_reserve_start_pfn
;
770 init_free_pfn_range(start
, end
);
775 * paging_init() sets up the page tables - note that all of lowmem is
776 * already mapped by head.S.
778 void __init
paging_init(void)
780 #ifdef CONFIG_HIGHMEM
781 unsigned long vaddr
, end
;
786 pgd_t
*pgd_base
= swapper_pg_dir
;
788 kernel_physical_mapping_init(pgd_base
);
790 #ifdef CONFIG_HIGHMEM
792 * Fixed mappings, only the page table structure has to be
793 * created - mappings will be set by set_fixmap():
795 vaddr
= __fix_to_virt(__end_of_fixed_addresses
- 1) & PMD_MASK
;
796 end
= (FIXADDR_TOP
+ PMD_SIZE
- 1) & PMD_MASK
;
797 page_table_range_init(vaddr
, end
, pgd_base
);
798 permanent_kmaps_init(pgd_base
);
803 * Since GX allocates just one pmd_t array worth of vmalloc space,
804 * we go ahead and allocate it statically here, then share it
805 * globally. As a result we don't have to worry about any task
806 * changing init_mm once we get up and running, and there's no
807 * need for e.g. vmalloc_sync_all().
809 BUILD_BUG_ON(pgd_index(VMALLOC_START
) != pgd_index(VMALLOC_END
));
810 pud
= pud_offset(pgd_base
+ pgd_index(VMALLOC_START
), VMALLOC_START
);
811 assign_pmd(pud
, alloc_pmd());
817 * Walk the kernel page tables and derive the page_home() from
818 * the PTEs, so that set_pte() can properly validate the caching
819 * of all PTEs it sees.
821 void __init
set_page_homes(void)
825 static void __init
set_max_mapnr_init(void)
827 #ifdef CONFIG_FLATMEM
828 max_mapnr
= max_low_pfn
;
832 void __init
mem_init(void)
834 int codesize
, datasize
, initsize
;
840 #ifdef CONFIG_FLATMEM
845 #ifdef CONFIG_HIGHMEM
846 /* check that fixmap and pkmap do not overlap */
847 if (PKMAP_ADDR(LAST_PKMAP
-1) >= FIXADDR_START
) {
848 pr_err("fixmap and kmap areas overlap"
849 " - this will crash\n");
850 pr_err("pkstart: %lxh pkend: %lxh fixstart %lxh\n",
851 PKMAP_BASE
, PKMAP_ADDR(LAST_PKMAP
-1),
857 set_max_mapnr_init();
859 /* this will put all bootmem onto the freelists */
860 totalram_pages
+= free_all_bootmem();
862 /* count all remaining LOWMEM and give all HIGHMEM to page allocator */
863 set_non_bootmem_pages_init();
865 codesize
= (unsigned long)&_etext
- (unsigned long)&_text
;
866 datasize
= (unsigned long)&_end
- (unsigned long)&_sdata
;
867 initsize
= (unsigned long)&_einittext
- (unsigned long)&_sinittext
;
868 initsize
+= (unsigned long)&_einitdata
- (unsigned long)&_sinitdata
;
870 pr_info("Memory: %luk/%luk available (%dk kernel code, %dk data, %dk init, %ldk highmem)\n",
871 (unsigned long) nr_free_pages() << (PAGE_SHIFT
-10),
872 num_physpages
<< (PAGE_SHIFT
-10),
876 (unsigned long) (totalhigh_pages
<< (PAGE_SHIFT
-10))
880 * In debug mode, dump some interesting memory mappings.
882 #ifdef CONFIG_HIGHMEM
883 printk(KERN_DEBUG
" KMAP %#lx - %#lx\n",
884 FIXADDR_START
, FIXADDR_TOP
+ PAGE_SIZE
- 1);
885 printk(KERN_DEBUG
" PKMAP %#lx - %#lx\n",
886 PKMAP_BASE
, PKMAP_ADDR(LAST_PKMAP
) - 1);
888 #ifdef CONFIG_HUGEVMAP
889 printk(KERN_DEBUG
" HUGEMAP %#lx - %#lx\n",
890 HUGE_VMAP_BASE
, HUGE_VMAP_END
- 1);
892 printk(KERN_DEBUG
" VMALLOC %#lx - %#lx\n",
893 _VMALLOC_START
, _VMALLOC_END
- 1);
895 for (i
= MAX_NUMNODES
-1; i
>= 0; --i
) {
896 struct pglist_data
*node
= &node_data
[i
];
897 if (node
->node_present_pages
) {
898 unsigned long start
= (unsigned long)
899 pfn_to_kaddr(node
->node_start_pfn
);
900 unsigned long end
= start
+
901 (node
->node_present_pages
<< PAGE_SHIFT
);
902 printk(KERN_DEBUG
" MEM%d %#lx - %#lx\n",
908 for (i
= MAX_NUMNODES
-1; i
>= 0; --i
) {
909 if ((unsigned long)vbase_map
[i
] != -1UL) {
910 printk(KERN_DEBUG
" LOWMEM%d %#lx - %#lx\n",
911 i
, (unsigned long) (vbase_map
[i
]),
912 (unsigned long) (last
-1));
920 * Convert from using one lock for all atomic operations to
923 __init_atomic_per_cpu();
928 * this is for the non-NUMA, single node SMP system case.
929 * Specifically, in the case of x86, we will always add
930 * memory to the highmem for now.
932 #ifndef CONFIG_NEED_MULTIPLE_NODES
933 int arch_add_memory(u64 start
, u64 size
)
935 struct pglist_data
*pgdata
= &contig_page_data
;
936 struct zone
*zone
= pgdata
->node_zones
+ MAX_NR_ZONES
-1;
937 unsigned long start_pfn
= start
>> PAGE_SHIFT
;
938 unsigned long nr_pages
= size
>> PAGE_SHIFT
;
940 return __add_pages(zone
, start_pfn
, nr_pages
);
943 int remove_memory(u64 start
, u64 size
)
949 struct kmem_cache
*pgd_cache
;
951 void __init
pgtable_cache_init(void)
953 pgd_cache
= kmem_cache_create("pgd",
954 PTRS_PER_PGD
*sizeof(pgd_t
),
955 PTRS_PER_PGD
*sizeof(pgd_t
),
959 panic("pgtable_cache_init(): Cannot create pgd cache");
962 #if !CHIP_HAS_COHERENT_LOCAL_CACHE()
964 * The __w1data area holds data that is only written during initialization,
965 * and is read-only and thus freely cacheable thereafter. Fix the page
966 * table entries that cover that region accordingly.
968 static void mark_w1data_ro(void)
970 /* Loop over page table entries */
971 unsigned long addr
= (unsigned long)__w1data_begin
;
972 BUG_ON((addr
& (PAGE_SIZE
-1)) != 0);
973 for (; addr
<= (unsigned long)__w1data_end
- 1; addr
+= PAGE_SIZE
) {
974 unsigned long pfn
= kaddr_to_pfn((void *)addr
);
975 pte_t
*ptep
= virt_to_pte(NULL
, addr
);
976 BUG_ON(pte_huge(*ptep
)); /* not relevant for kdata_huge */
977 set_pte_at(&init_mm
, addr
, ptep
, pfn_pte(pfn
, PAGE_KERNEL_RO
));
982 #ifdef CONFIG_DEBUG_PAGEALLOC
983 static long __write_once initfree
;
985 static long __write_once initfree
= 1;
988 /* Select whether to free (1) or mark unusable (0) the __init pages. */
989 static int __init
set_initfree(char *str
)
992 if (strict_strtol(str
, 0, &val
)) {
994 pr_info("initfree: %s free init pages\n",
995 initfree
? "will" : "won't");
999 __setup("initfree=", set_initfree
);
1001 static void free_init_pages(char *what
, unsigned long begin
, unsigned long end
)
1003 unsigned long addr
= (unsigned long) begin
;
1005 if (kdata_huge
&& !initfree
) {
1006 pr_warning("Warning: ignoring initfree=0:"
1007 " incompatible with kdata=huge\n");
1010 end
= (end
+ PAGE_SIZE
- 1) & PAGE_MASK
;
1011 local_flush_tlb_pages(NULL
, begin
, PAGE_SIZE
, end
- begin
);
1012 for (addr
= begin
; addr
< end
; addr
+= PAGE_SIZE
) {
1014 * Note we just reset the home here directly in the
1015 * page table. We know this is safe because our caller
1016 * just flushed the caches on all the other cpus,
1017 * and they won't be touching any of these pages.
1019 int pfn
= kaddr_to_pfn((void *)addr
);
1020 struct page
*page
= pfn_to_page(pfn
);
1021 pte_t
*ptep
= virt_to_pte(NULL
, addr
);
1024 * If debugging page accesses then do not free
1025 * this memory but mark them not present - any
1026 * buggy init-section access will create a
1027 * kernel page fault:
1029 pte_clear(&init_mm
, addr
, ptep
);
1032 __ClearPageReserved(page
);
1033 init_page_count(page
);
1034 if (pte_huge(*ptep
))
1035 BUG_ON(!kdata_huge
);
1037 set_pte_at(&init_mm
, addr
, ptep
,
1038 pfn_pte(pfn
, PAGE_KERNEL
));
1039 memset((void *)addr
, POISON_FREE_INITMEM
, PAGE_SIZE
);
1043 pr_info("Freeing %s: %ldk freed\n", what
, (end
- begin
) >> 10);
1046 void free_initmem(void)
1048 const unsigned long text_delta
= MEM_SV_INTRPT
- PAGE_OFFSET
;
1051 * Evict the dirty initdata on the boot cpu, evict the w1data
1052 * wherever it's homed, and evict all the init code everywhere.
1053 * We are guaranteed that no one will touch the init pages any
1054 * more, and although other cpus may be touching the w1data,
1055 * we only actually change the caching on tile64, which won't
1056 * be keeping local copies in the other tiles' caches anyway.
1058 homecache_evict(&cpu_cacheable_map
);
1060 /* Free the data pages that we won't use again after init. */
1061 free_init_pages("unused kernel data",
1062 (unsigned long)_sinitdata
,
1063 (unsigned long)_einitdata
);
1066 * Free the pages mapped from 0xc0000000 that correspond to code
1067 * pages from MEM_SV_INTRPT that we won't use again after init.
1069 free_init_pages("unused kernel text",
1070 (unsigned long)_sinittext
- text_delta
,
1071 (unsigned long)_einittext
- text_delta
);
1073 #if !CHIP_HAS_COHERENT_LOCAL_CACHE()
1075 * Upgrade the .w1data section to globally cached.
1076 * We don't do this on tilepro, since the cache architecture
1077 * pretty much makes it irrelevant, and in any case we end
1078 * up having racing issues with other tiles that may touch
1079 * the data after we flush the cache but before we update
1080 * the PTEs and flush the TLBs, causing sharer shootdowns
1081 * later. Even though this is to clean data, it seems like
1082 * an unnecessary complication.
1087 /* Do a global TLB flush so everyone sees the changes. */