1 /******************************************************************************
3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *****************************************************************************/
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/skbuff.h>
33 #include <linux/netdevice.h>
34 #include <linux/wireless.h>
35 #include <net/mac80211.h>
36 #include <linux/etherdevice.h>
37 #include <asm/unaligned.h>
39 #include "iwl-eeprom.h"
44 #include "iwl-helpers.h"
45 #include "iwl-5000-hw.h"
46 #include "iwl-6000-hw.h"
48 /* Highest firmware API version supported */
49 #define IWL5000_UCODE_API_MAX 2
50 #define IWL5150_UCODE_API_MAX 2
52 /* Lowest firmware API version supported */
53 #define IWL5000_UCODE_API_MIN 1
54 #define IWL5150_UCODE_API_MIN 1
56 #define IWL5000_FW_PRE "iwlwifi-5000-"
57 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
58 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
60 #define IWL5150_FW_PRE "iwlwifi-5150-"
61 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
62 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
64 static const u16 iwl5000_default_queue_to_tx_fifo
[] = {
74 /* FIXME: same implementation as 4965 */
75 static int iwl5000_apm_stop_master(struct iwl_priv
*priv
)
79 spin_lock_irqsave(&priv
->lock
, flags
);
81 /* set stop master bit */
82 iwl_set_bit(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
84 iwl_poll_direct_bit(priv
, CSR_RESET
,
85 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
87 spin_unlock_irqrestore(&priv
->lock
, flags
);
88 IWL_DEBUG_INFO(priv
, "stop master\n");
94 static int iwl5000_apm_init(struct iwl_priv
*priv
)
98 iwl_set_bit(priv
, CSR_GIO_CHICKEN_BITS
,
99 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
101 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
102 iwl_set_bit(priv
, CSR_GIO_CHICKEN_BITS
,
103 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
105 /* Set FH wait threshold to maximum (HW error during stress W/A) */
106 iwl_set_bit(priv
, CSR_DBG_HPET_MEM_REG
, CSR_DBG_HPET_MEM_REG_VAL
);
108 /* enable HAP INTA to move device L1a -> L0s */
109 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
110 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
);
112 if (priv
->cfg
->need_pll_cfg
)
113 iwl_set_bit(priv
, CSR_ANA_PLL_CFG
, CSR50_ANA_PLL_CFG_VAL
);
115 /* set "initialization complete" bit to move adapter
116 * D0U* --> D0A* state */
117 iwl_set_bit(priv
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
119 /* wait for clock stabilization */
120 ret
= iwl_poll_direct_bit(priv
, CSR_GP_CNTRL
,
121 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
123 IWL_DEBUG_INFO(priv
, "Failed to init the card\n");
128 iwl_write_prph(priv
, APMG_CLK_EN_REG
, APMG_CLK_VAL_DMA_CLK_RQT
);
132 /* disable L1-Active */
133 iwl_set_bits_prph(priv
, APMG_PCIDEV_STT_REG
,
134 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
139 /* FIXME: this is identical to 4965 */
140 static void iwl5000_apm_stop(struct iwl_priv
*priv
)
144 iwl5000_apm_stop_master(priv
);
146 spin_lock_irqsave(&priv
->lock
, flags
);
148 iwl_set_bit(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
152 /* clear "init complete" move adapter D0A* --> D0U state */
153 iwl_clear_bit(priv
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
155 spin_unlock_irqrestore(&priv
->lock
, flags
);
159 static int iwl5000_apm_reset(struct iwl_priv
*priv
)
163 iwl5000_apm_stop_master(priv
);
165 iwl_set_bit(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_SW_RESET
);
170 /* FIXME: put here L1A -L0S w/a */
172 if (priv
->cfg
->need_pll_cfg
)
173 iwl_set_bit(priv
, CSR_ANA_PLL_CFG
, CSR50_ANA_PLL_CFG_VAL
);
175 /* set "initialization complete" bit to move adapter
176 * D0U* --> D0A* state */
177 iwl_set_bit(priv
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
179 /* wait for clock stabilization */
180 ret
= iwl_poll_direct_bit(priv
, CSR_GP_CNTRL
,
181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
183 IWL_DEBUG_INFO(priv
, "Failed to init the card\n");
188 iwl_write_prph(priv
, APMG_CLK_EN_REG
, APMG_CLK_VAL_DMA_CLK_RQT
);
192 /* disable L1-Active */
193 iwl_set_bits_prph(priv
, APMG_PCIDEV_STT_REG
,
194 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
201 static void iwl5000_nic_config(struct iwl_priv
*priv
)
207 spin_lock_irqsave(&priv
->lock
, flags
);
209 lctl
= iwl_pcie_link_ctl(priv
);
212 /* L1-ASPM is enabled by BIOS */
213 if ((lctl
& PCI_CFG_LINK_CTRL_VAL_L1_EN
) == PCI_CFG_LINK_CTRL_VAL_L1_EN
)
214 /* L1-APSM enabled: disable L0S */
215 iwl_set_bit(priv
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
217 /* L1-ASPM disabled: enable L0S */
218 iwl_clear_bit(priv
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
220 radio_cfg
= iwl_eeprom_query16(priv
, EEPROM_RADIO_CONFIG
);
222 /* write radio config values to register */
223 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg
) < EEPROM_5000_RF_CFG_TYPE_MAX
)
224 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
225 EEPROM_RF_CFG_TYPE_MSK(radio_cfg
) |
226 EEPROM_RF_CFG_STEP_MSK(radio_cfg
) |
227 EEPROM_RF_CFG_DASH_MSK(radio_cfg
));
229 /* set CSR_HW_CONFIG_REG for uCode use */
230 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
231 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI
|
232 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI
);
234 /* W/A : NIC is stuck in a reset state after Early PCIe power off
235 * (PCIe power is lost before PERST# is asserted),
236 * causing ME FW to lose ownership and not being able to obtain it back.
238 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
239 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS
,
240 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS
);
242 spin_unlock_irqrestore(&priv
->lock
, flags
);
250 static u32
eeprom_indirect_address(const struct iwl_priv
*priv
, u32 address
)
254 if ((address
& INDIRECT_ADDRESS
) == 0)
257 switch (address
& INDIRECT_TYPE_MSK
) {
259 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_HOST
);
261 case INDIRECT_GENERAL
:
262 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_GENERAL
);
264 case INDIRECT_REGULATORY
:
265 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_REGULATORY
);
267 case INDIRECT_CALIBRATION
:
268 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_CALIBRATION
);
270 case INDIRECT_PROCESS_ADJST
:
271 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_PROCESS_ADJST
);
273 case INDIRECT_OTHERS
:
274 offset
= iwl_eeprom_query16(priv
, EEPROM_5000_LINK_OTHERS
);
277 IWL_ERR(priv
, "illegal indirect type: 0x%X\n",
278 address
& INDIRECT_TYPE_MSK
);
282 /* translate the offset from words to byte */
283 return (address
& ADDRESS_MSK
) + (offset
<< 1);
286 static u16
iwl5000_eeprom_calib_version(struct iwl_priv
*priv
)
288 struct iwl_eeprom_calib_hdr
{
294 hdr
= (struct iwl_eeprom_calib_hdr
*)iwl_eeprom_query_addr(priv
,
295 EEPROM_5000_CALIB_ALL
);
300 static void iwl5000_gain_computation(struct iwl_priv
*priv
,
301 u32 average_noise
[NUM_RX_CHAINS
],
302 u16 min_average_noise_antenna_i
,
303 u32 min_average_noise
)
307 struct iwl_chain_noise_data
*data
= &priv
->chain_noise_data
;
309 /* Find Gain Code for the antennas B and C */
310 for (i
= 1; i
< NUM_RX_CHAINS
; i
++) {
311 if ((data
->disconn_array
[i
])) {
312 data
->delta_gain_code
[i
] = 0;
315 delta_g
= (1000 * ((s32
)average_noise
[0] -
316 (s32
)average_noise
[i
])) / 1500;
317 /* bound gain by 2 bits value max, 3rd bit is sign */
318 data
->delta_gain_code
[i
] =
319 min(abs(delta_g
), CHAIN_NOISE_MAX_DELTA_GAIN_CODE
);
322 /* set negative sign */
323 data
->delta_gain_code
[i
] |= (1 << 2);
326 IWL_DEBUG_CALIB(priv
, "Delta gains: ANT_B = %d ANT_C = %d\n",
327 data
->delta_gain_code
[1], data
->delta_gain_code
[2]);
329 if (!data
->radio_write
) {
330 struct iwl_calib_chain_noise_gain_cmd cmd
;
332 memset(&cmd
, 0, sizeof(cmd
));
334 cmd
.hdr
.op_code
= IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD
;
335 cmd
.hdr
.first_group
= 0;
336 cmd
.hdr
.groups_num
= 1;
337 cmd
.hdr
.data_valid
= 1;
338 cmd
.delta_gain_1
= data
->delta_gain_code
[1];
339 cmd
.delta_gain_2
= data
->delta_gain_code
[2];
340 iwl_send_cmd_pdu_async(priv
, REPLY_PHY_CALIBRATION_CMD
,
341 sizeof(cmd
), &cmd
, NULL
);
343 data
->radio_write
= 1;
344 data
->state
= IWL_CHAIN_NOISE_CALIBRATED
;
347 data
->chain_noise_a
= 0;
348 data
->chain_noise_b
= 0;
349 data
->chain_noise_c
= 0;
350 data
->chain_signal_a
= 0;
351 data
->chain_signal_b
= 0;
352 data
->chain_signal_c
= 0;
353 data
->beacon_count
= 0;
356 static void iwl5000_chain_noise_reset(struct iwl_priv
*priv
)
358 struct iwl_chain_noise_data
*data
= &priv
->chain_noise_data
;
361 if ((data
->state
== IWL_CHAIN_NOISE_ALIVE
) && iwl_is_associated(priv
)) {
362 struct iwl_calib_chain_noise_reset_cmd cmd
;
363 memset(&cmd
, 0, sizeof(cmd
));
365 cmd
.hdr
.op_code
= IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD
;
366 cmd
.hdr
.first_group
= 0;
367 cmd
.hdr
.groups_num
= 1;
368 cmd
.hdr
.data_valid
= 1;
369 ret
= iwl_send_cmd_pdu(priv
, REPLY_PHY_CALIBRATION_CMD
,
373 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
374 data
->state
= IWL_CHAIN_NOISE_ACCUMULATE
;
375 IWL_DEBUG_CALIB(priv
, "Run chain_noise_calibrate\n");
379 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info
*info
,
382 if ((info
->control
.rates
[0].flags
& IEEE80211_TX_RC_USE_RTS_CTS
) ||
383 (info
->control
.rates
[0].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
))
384 *tx_flags
|= TX_CMD_FLG_RTS_CTS_MSK
;
386 *tx_flags
&= ~TX_CMD_FLG_RTS_CTS_MSK
;
389 static struct iwl_sensitivity_ranges iwl5000_sensitivity
= {
392 .auto_corr_min_ofdm
= 90,
393 .auto_corr_min_ofdm_mrc
= 170,
394 .auto_corr_min_ofdm_x1
= 120,
395 .auto_corr_min_ofdm_mrc_x1
= 240,
397 .auto_corr_max_ofdm
= 120,
398 .auto_corr_max_ofdm_mrc
= 210,
399 .auto_corr_max_ofdm_x1
= 155,
400 .auto_corr_max_ofdm_mrc_x1
= 290,
402 .auto_corr_min_cck
= 125,
403 .auto_corr_max_cck
= 200,
404 .auto_corr_min_cck_mrc
= 170,
405 .auto_corr_max_cck_mrc
= 400,
410 static struct iwl_sensitivity_ranges iwl5150_sensitivity
= {
412 .max_nrg_cck
= 0, /* not used, set to 0 */
413 .auto_corr_min_ofdm
= 90,
414 .auto_corr_min_ofdm_mrc
= 170,
415 .auto_corr_min_ofdm_x1
= 105,
416 .auto_corr_min_ofdm_mrc_x1
= 220,
418 .auto_corr_max_ofdm
= 120,
419 .auto_corr_max_ofdm_mrc
= 210,
420 /* max = min for performance bug in 5150 DSP */
421 .auto_corr_max_ofdm_x1
= 105,
422 .auto_corr_max_ofdm_mrc_x1
= 220,
424 .auto_corr_min_cck
= 125,
425 .auto_corr_max_cck
= 200,
426 .auto_corr_min_cck_mrc
= 170,
427 .auto_corr_max_cck_mrc
= 400,
432 static const u8
*iwl5000_eeprom_query_addr(const struct iwl_priv
*priv
,
435 u32 address
= eeprom_indirect_address(priv
, offset
);
436 BUG_ON(address
>= priv
->cfg
->eeprom_size
);
437 return &priv
->eeprom
[address
];
440 static void iwl5150_set_ct_threshold(struct iwl_priv
*priv
)
442 const s32 volt2temp_coef
= IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF
;
443 s32 threshold
= (s32
)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD
) -
444 iwl_temp_calib_to_offset(priv
);
446 priv
->hw_params
.ct_kill_threshold
= threshold
* volt2temp_coef
;
449 static void iwl5000_set_ct_threshold(struct iwl_priv
*priv
)
452 priv
->hw_params
.ct_kill_threshold
= CT_KILL_THRESHOLD
;
458 static int iwl5000_set_Xtal_calib(struct iwl_priv
*priv
)
460 struct iwl_calib_xtal_freq_cmd cmd
;
461 u16
*xtal_calib
= (u16
*)iwl_eeprom_query_addr(priv
, EEPROM_5000_XTAL
);
463 cmd
.hdr
.op_code
= IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD
;
464 cmd
.hdr
.first_group
= 0;
465 cmd
.hdr
.groups_num
= 1;
466 cmd
.hdr
.data_valid
= 1;
467 cmd
.cap_pin1
= (u8
)xtal_calib
[0];
468 cmd
.cap_pin2
= (u8
)xtal_calib
[1];
469 return iwl_calib_set(&priv
->calib_results
[IWL_CALIB_XTAL
],
470 (u8
*)&cmd
, sizeof(cmd
));
473 static int iwl5000_send_calib_cfg(struct iwl_priv
*priv
)
475 struct iwl_calib_cfg_cmd calib_cfg_cmd
;
476 struct iwl_host_cmd cmd
= {
477 .id
= CALIBRATION_CFG_CMD
,
478 .len
= sizeof(struct iwl_calib_cfg_cmd
),
479 .data
= &calib_cfg_cmd
,
482 memset(&calib_cfg_cmd
, 0, sizeof(calib_cfg_cmd
));
483 calib_cfg_cmd
.ucd_calib_cfg
.once
.is_enable
= IWL_CALIB_INIT_CFG_ALL
;
484 calib_cfg_cmd
.ucd_calib_cfg
.once
.start
= IWL_CALIB_INIT_CFG_ALL
;
485 calib_cfg_cmd
.ucd_calib_cfg
.once
.send_res
= IWL_CALIB_INIT_CFG_ALL
;
486 calib_cfg_cmd
.ucd_calib_cfg
.flags
= IWL_CALIB_INIT_CFG_ALL
;
488 return iwl_send_cmd(priv
, &cmd
);
491 static void iwl5000_rx_calib_result(struct iwl_priv
*priv
,
492 struct iwl_rx_mem_buffer
*rxb
)
494 struct iwl_rx_packet
*pkt
= (void *)rxb
->skb
->data
;
495 struct iwl_calib_hdr
*hdr
= (struct iwl_calib_hdr
*)pkt
->u
.raw
;
496 int len
= le32_to_cpu(pkt
->len
) & FH_RSCSR_FRAME_SIZE_MSK
;
499 /* reduce the size of the length field itself */
502 /* Define the order in which the results will be sent to the runtime
503 * uCode. iwl_send_calib_results sends them in a row according to their
504 * index. We sort them here */
505 switch (hdr
->op_code
) {
506 case IWL_PHY_CALIBRATE_DC_CMD
:
507 index
= IWL_CALIB_DC
;
509 case IWL_PHY_CALIBRATE_LO_CMD
:
510 index
= IWL_CALIB_LO
;
512 case IWL_PHY_CALIBRATE_TX_IQ_CMD
:
513 index
= IWL_CALIB_TX_IQ
;
515 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD
:
516 index
= IWL_CALIB_TX_IQ_PERD
;
518 case IWL_PHY_CALIBRATE_BASE_BAND_CMD
:
519 index
= IWL_CALIB_BASE_BAND
;
522 IWL_ERR(priv
, "Unknown calibration notification %d\n",
526 iwl_calib_set(&priv
->calib_results
[index
], pkt
->u
.raw
, len
);
529 static void iwl5000_rx_calib_complete(struct iwl_priv
*priv
,
530 struct iwl_rx_mem_buffer
*rxb
)
532 IWL_DEBUG_INFO(priv
, "Init. calibration is completed, restarting fw.\n");
533 queue_work(priv
->workqueue
, &priv
->restart
);
539 static int iwl5000_load_section(struct iwl_priv
*priv
,
540 struct fw_desc
*image
,
543 dma_addr_t phy_addr
= image
->p_addr
;
544 u32 byte_cnt
= image
->len
;
546 iwl_write_direct32(priv
,
547 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
548 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
550 iwl_write_direct32(priv
,
551 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
), dst_addr
);
553 iwl_write_direct32(priv
,
554 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
555 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
557 iwl_write_direct32(priv
,
558 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
559 (iwl_get_dma_hi_addr(phy_addr
)
560 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
562 iwl_write_direct32(priv
,
563 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
564 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
|
565 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
|
566 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
568 iwl_write_direct32(priv
,
569 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
570 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
571 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
572 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
577 static int iwl5000_load_given_ucode(struct iwl_priv
*priv
,
578 struct fw_desc
*inst_image
,
579 struct fw_desc
*data_image
)
583 ret
= iwl5000_load_section(priv
, inst_image
,
584 IWL50_RTC_INST_LOWER_BOUND
);
588 IWL_DEBUG_INFO(priv
, "INST uCode section being loaded...\n");
589 ret
= wait_event_interruptible_timeout(priv
->wait_command_queue
,
590 priv
->ucode_write_complete
, 5 * HZ
);
591 if (ret
== -ERESTARTSYS
) {
592 IWL_ERR(priv
, "Could not load the INST uCode section due "
597 IWL_ERR(priv
, "Could not load the INST uCode section\n");
601 priv
->ucode_write_complete
= 0;
603 ret
= iwl5000_load_section(
604 priv
, data_image
, IWL50_RTC_DATA_LOWER_BOUND
);
608 IWL_DEBUG_INFO(priv
, "DATA uCode section being loaded...\n");
610 ret
= wait_event_interruptible_timeout(priv
->wait_command_queue
,
611 priv
->ucode_write_complete
, 5 * HZ
);
612 if (ret
== -ERESTARTSYS
) {
613 IWL_ERR(priv
, "Could not load the INST uCode section due "
617 IWL_ERR(priv
, "Could not load the DATA uCode section\n");
622 priv
->ucode_write_complete
= 0;
627 static int iwl5000_load_ucode(struct iwl_priv
*priv
)
631 /* check whether init ucode should be loaded, or rather runtime ucode */
632 if (priv
->ucode_init
.len
&& (priv
->ucode_type
== UCODE_NONE
)) {
633 IWL_DEBUG_INFO(priv
, "Init ucode found. Loading init ucode...\n");
634 ret
= iwl5000_load_given_ucode(priv
,
635 &priv
->ucode_init
, &priv
->ucode_init_data
);
637 IWL_DEBUG_INFO(priv
, "Init ucode load complete.\n");
638 priv
->ucode_type
= UCODE_INIT
;
641 IWL_DEBUG_INFO(priv
, "Init ucode not found, or already loaded. "
642 "Loading runtime ucode...\n");
643 ret
= iwl5000_load_given_ucode(priv
,
644 &priv
->ucode_code
, &priv
->ucode_data
);
646 IWL_DEBUG_INFO(priv
, "Runtime ucode load complete.\n");
647 priv
->ucode_type
= UCODE_RT
;
654 static void iwl5000_init_alive_start(struct iwl_priv
*priv
)
658 /* Check alive response for "valid" sign from uCode */
659 if (priv
->card_alive_init
.is_valid
!= UCODE_VALID_OK
) {
660 /* We had an error bringing up the hardware, so take it
661 * all the way back down so we can try again */
662 IWL_DEBUG_INFO(priv
, "Initialize Alive failed.\n");
666 /* initialize uCode was loaded... verify inst image.
667 * This is a paranoid check, because we would not have gotten the
668 * "initialize" alive if code weren't properly loaded. */
669 if (iwl_verify_ucode(priv
)) {
670 /* Runtime instruction load was bad;
671 * take it all the way back down so we can try again */
672 IWL_DEBUG_INFO(priv
, "Bad \"initialize\" uCode load.\n");
676 iwl_clear_stations_table(priv
);
677 ret
= priv
->cfg
->ops
->lib
->alive_notify(priv
);
680 "Could not complete ALIVE transition: %d\n", ret
);
684 iwl5000_send_calib_cfg(priv
);
688 /* real restart (first load init_ucode) */
689 queue_work(priv
->workqueue
, &priv
->restart
);
692 static void iwl5000_set_wr_ptrs(struct iwl_priv
*priv
,
693 int txq_id
, u32 index
)
695 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
,
696 (index
& 0xff) | (txq_id
<< 8));
697 iwl_write_prph(priv
, IWL50_SCD_QUEUE_RDPTR(txq_id
), index
);
700 static void iwl5000_tx_queue_set_status(struct iwl_priv
*priv
,
701 struct iwl_tx_queue
*txq
,
702 int tx_fifo_id
, int scd_retry
)
704 int txq_id
= txq
->q
.id
;
705 int active
= test_bit(txq_id
, &priv
->txq_ctx_active_msk
) ? 1 : 0;
707 iwl_write_prph(priv
, IWL50_SCD_QUEUE_STATUS_BITS(txq_id
),
708 (active
<< IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE
) |
709 (tx_fifo_id
<< IWL50_SCD_QUEUE_STTS_REG_POS_TXF
) |
710 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL
) |
711 IWL50_SCD_QUEUE_STTS_REG_MSK
);
713 txq
->sched_retry
= scd_retry
;
715 IWL_DEBUG_INFO(priv
, "%s %s Queue %d on AC %d\n",
716 active
? "Activate" : "Deactivate",
717 scd_retry
? "BA" : "AC", txq_id
, tx_fifo_id
);
720 static int iwl5000_send_wimax_coex(struct iwl_priv
*priv
)
722 struct iwl_wimax_coex_cmd coex_cmd
;
724 memset(&coex_cmd
, 0, sizeof(coex_cmd
));
726 return iwl_send_cmd_pdu(priv
, COEX_PRIORITY_TABLE_CMD
,
727 sizeof(coex_cmd
), &coex_cmd
);
730 static int iwl5000_alive_notify(struct iwl_priv
*priv
)
737 spin_lock_irqsave(&priv
->lock
, flags
);
739 priv
->scd_base_addr
= iwl_read_prph(priv
, IWL50_SCD_SRAM_BASE_ADDR
);
740 a
= priv
->scd_base_addr
+ IWL50_SCD_CONTEXT_DATA_OFFSET
;
741 for (; a
< priv
->scd_base_addr
+ IWL50_SCD_TX_STTS_BITMAP_OFFSET
;
743 iwl_write_targ_mem(priv
, a
, 0);
744 for (; a
< priv
->scd_base_addr
+ IWL50_SCD_TRANSLATE_TBL_OFFSET
;
746 iwl_write_targ_mem(priv
, a
, 0);
747 for (; a
< sizeof(u16
) * priv
->hw_params
.max_txq_num
; a
+= 4)
748 iwl_write_targ_mem(priv
, a
, 0);
750 iwl_write_prph(priv
, IWL50_SCD_DRAM_BASE_ADDR
,
751 priv
->scd_bc_tbls
.dma
>> 10);
753 /* Enable DMA channel */
754 for (chan
= 0; chan
< FH50_TCSR_CHNL_NUM
; chan
++)
755 iwl_write_direct32(priv
, FH_TCSR_CHNL_TX_CONFIG_REG(chan
),
756 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
757 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
);
759 /* Update FH chicken bits */
760 reg_val
= iwl_read_direct32(priv
, FH_TX_CHICKEN_BITS_REG
);
761 iwl_write_direct32(priv
, FH_TX_CHICKEN_BITS_REG
,
762 reg_val
| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
);
764 iwl_write_prph(priv
, IWL50_SCD_QUEUECHAIN_SEL
,
765 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv
->hw_params
.max_txq_num
));
766 iwl_write_prph(priv
, IWL50_SCD_AGGR_SEL
, 0);
768 /* initiate the queues */
769 for (i
= 0; i
< priv
->hw_params
.max_txq_num
; i
++) {
770 iwl_write_prph(priv
, IWL50_SCD_QUEUE_RDPTR(i
), 0);
771 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
, 0 | (i
<< 8));
772 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
773 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i
), 0);
774 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
775 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i
) +
778 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
779 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
781 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
782 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
785 iwl_write_prph(priv
, IWL50_SCD_INTERRUPT_MASK
,
786 IWL_MASK(0, priv
->hw_params
.max_txq_num
));
788 /* Activate all Tx DMA/FIFO channels */
789 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, IWL_MASK(0, 7));
791 iwl5000_set_wr_ptrs(priv
, IWL_CMD_QUEUE_NUM
, 0);
793 /* map qos queues to fifos one-to-one */
794 for (i
= 0; i
< ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo
); i
++) {
795 int ac
= iwl5000_default_queue_to_tx_fifo
[i
];
796 iwl_txq_ctx_activate(priv
, i
);
797 iwl5000_tx_queue_set_status(priv
, &priv
->txq
[i
], ac
, 0);
799 /* TODO - need to initialize those FIFOs inside the loop above,
800 * not only mark them as active */
801 iwl_txq_ctx_activate(priv
, 4);
802 iwl_txq_ctx_activate(priv
, 7);
803 iwl_txq_ctx_activate(priv
, 8);
804 iwl_txq_ctx_activate(priv
, 9);
806 spin_unlock_irqrestore(&priv
->lock
, flags
);
809 iwl5000_send_wimax_coex(priv
);
811 iwl5000_set_Xtal_calib(priv
);
812 iwl_send_calib_results(priv
);
817 static int iwl5000_hw_set_hw_params(struct iwl_priv
*priv
)
819 if ((priv
->cfg
->mod_params
->num_of_queues
> IWL50_NUM_QUEUES
) ||
820 (priv
->cfg
->mod_params
->num_of_queues
< IWL_MIN_NUM_QUEUES
)) {
822 "invalid queues_num, should be between %d and %d\n",
823 IWL_MIN_NUM_QUEUES
, IWL50_NUM_QUEUES
);
827 priv
->hw_params
.max_txq_num
= priv
->cfg
->mod_params
->num_of_queues
;
828 priv
->hw_params
.dma_chnl_num
= FH50_TCSR_CHNL_NUM
;
829 priv
->hw_params
.scd_bc_tbls_size
=
830 IWL50_NUM_QUEUES
* sizeof(struct iwl5000_scd_bc_tbl
);
831 priv
->hw_params
.tfd_size
= sizeof(struct iwl_tfd
);
832 priv
->hw_params
.max_stations
= IWL5000_STATION_COUNT
;
833 priv
->hw_params
.bcast_sta_id
= IWL5000_BROADCAST_ID
;
835 switch (priv
->hw_rev
& CSR_HW_REV_TYPE_MSK
) {
836 case CSR_HW_REV_TYPE_6x00
:
837 case CSR_HW_REV_TYPE_6x50
:
838 priv
->hw_params
.max_data_size
= IWL60_RTC_DATA_SIZE
;
839 priv
->hw_params
.max_inst_size
= IWL60_RTC_INST_SIZE
;
842 priv
->hw_params
.max_data_size
= IWL50_RTC_DATA_SIZE
;
843 priv
->hw_params
.max_inst_size
= IWL50_RTC_INST_SIZE
;
846 priv
->hw_params
.max_bsm_size
= 0;
847 priv
->hw_params
.fat_channel
= BIT(IEEE80211_BAND_2GHZ
) |
848 BIT(IEEE80211_BAND_5GHZ
);
849 priv
->hw_params
.rx_wrt_ptr_reg
= FH_RSCSR_CHNL0_WPTR
;
851 priv
->hw_params
.tx_chains_num
= num_of_ant(priv
->cfg
->valid_tx_ant
);
852 priv
->hw_params
.rx_chains_num
= num_of_ant(priv
->cfg
->valid_rx_ant
);
853 priv
->hw_params
.valid_tx_ant
= priv
->cfg
->valid_tx_ant
;
854 priv
->hw_params
.valid_rx_ant
= priv
->cfg
->valid_rx_ant
;
856 if (priv
->cfg
->ops
->lib
->temp_ops
.set_ct_kill
)
857 priv
->cfg
->ops
->lib
->temp_ops
.set_ct_kill(priv
);
859 /* Set initial sensitivity parameters */
860 /* Set initial calibration set */
861 switch (priv
->hw_rev
& CSR_HW_REV_TYPE_MSK
) {
862 case CSR_HW_REV_TYPE_5150
:
863 priv
->hw_params
.sens
= &iwl5150_sensitivity
;
864 priv
->hw_params
.calib_init_cfg
=
867 BIT(IWL_CALIB_TX_IQ
) |
868 BIT(IWL_CALIB_BASE_BAND
);
872 priv
->hw_params
.sens
= &iwl5000_sensitivity
;
873 priv
->hw_params
.calib_init_cfg
=
874 BIT(IWL_CALIB_XTAL
) |
876 BIT(IWL_CALIB_TX_IQ
) |
877 BIT(IWL_CALIB_TX_IQ_PERD
) |
878 BIT(IWL_CALIB_BASE_BAND
);
886 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
888 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv
*priv
,
889 struct iwl_tx_queue
*txq
,
892 struct iwl5000_scd_bc_tbl
*scd_bc_tbl
= priv
->scd_bc_tbls
.addr
;
893 int write_ptr
= txq
->q
.write_ptr
;
894 int txq_id
= txq
->q
.id
;
897 u16 len
= byte_cnt
+ IWL_TX_CRC_SIZE
+ IWL_TX_DELIMITER_SIZE
;
900 WARN_ON(len
> 0xFFF || write_ptr
>= TFD_QUEUE_SIZE_MAX
);
902 if (txq_id
!= IWL_CMD_QUEUE_NUM
) {
903 sta_id
= txq
->cmd
[txq
->q
.write_ptr
]->cmd
.tx
.sta_id
;
904 sec_ctl
= txq
->cmd
[txq
->q
.write_ptr
]->cmd
.tx
.sec_ctl
;
906 switch (sec_ctl
& TX_CMD_SEC_MSK
) {
910 case TX_CMD_SEC_TKIP
:
914 len
+= WEP_IV_LEN
+ WEP_ICV_LEN
;
919 bc_ent
= cpu_to_le16((len
& 0xFFF) | (sta_id
<< 12));
921 scd_bc_tbl
[txq_id
].tfd_offset
[write_ptr
] = bc_ent
;
923 if (txq
->q
.write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
925 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ write_ptr
] = bc_ent
;
928 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv
*priv
,
929 struct iwl_tx_queue
*txq
)
931 struct iwl5000_scd_bc_tbl
*scd_bc_tbl
= priv
->scd_bc_tbls
.addr
;
932 int txq_id
= txq
->q
.id
;
933 int read_ptr
= txq
->q
.read_ptr
;
937 WARN_ON(read_ptr
>= TFD_QUEUE_SIZE_MAX
);
939 if (txq_id
!= IWL_CMD_QUEUE_NUM
)
940 sta_id
= txq
->cmd
[read_ptr
]->cmd
.tx
.sta_id
;
942 bc_ent
= cpu_to_le16(1 | (sta_id
<< 12));
943 scd_bc_tbl
[txq_id
].tfd_offset
[read_ptr
] = bc_ent
;
945 if (txq
->q
.write_ptr
< TFD_QUEUE_SIZE_BC_DUP
)
947 tfd_offset
[TFD_QUEUE_SIZE_MAX
+ read_ptr
] = bc_ent
;
950 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv
*priv
, u16 ra_tid
,
957 scd_q2ratid
= ra_tid
& IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK
;
959 tbl_dw_addr
= priv
->scd_base_addr
+
960 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id
);
962 tbl_dw
= iwl_read_targ_mem(priv
, tbl_dw_addr
);
965 tbl_dw
= (scd_q2ratid
<< 16) | (tbl_dw
& 0x0000FFFF);
967 tbl_dw
= scd_q2ratid
| (tbl_dw
& 0xFFFF0000);
969 iwl_write_targ_mem(priv
, tbl_dw_addr
, tbl_dw
);
973 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv
*priv
, u16 txq_id
)
975 /* Simply stop the queue, but don't change any configuration;
976 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
978 IWL50_SCD_QUEUE_STATUS_BITS(txq_id
),
979 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE
)|
980 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN
));
983 static int iwl5000_txq_agg_enable(struct iwl_priv
*priv
, int txq_id
,
984 int tx_fifo
, int sta_id
, int tid
, u16 ssn_idx
)
989 if ((IWL50_FIRST_AMPDU_QUEUE
> txq_id
) ||
990 (IWL50_FIRST_AMPDU_QUEUE
+ IWL50_NUM_AMPDU_QUEUES
<= txq_id
)) {
992 "queue number out of range: %d, must be %d to %d\n",
993 txq_id
, IWL50_FIRST_AMPDU_QUEUE
,
994 IWL50_FIRST_AMPDU_QUEUE
+ IWL50_NUM_AMPDU_QUEUES
- 1);
998 ra_tid
= BUILD_RAxTID(sta_id
, tid
);
1000 /* Modify device's station table to Tx this TID */
1001 iwl_sta_tx_modify_enable_tid(priv
, sta_id
, tid
);
1003 spin_lock_irqsave(&priv
->lock
, flags
);
1005 /* Stop this Tx queue before configuring it */
1006 iwl5000_tx_queue_stop_scheduler(priv
, txq_id
);
1008 /* Map receiver-address / traffic-ID to this queue */
1009 iwl5000_tx_queue_set_q2ratid(priv
, ra_tid
, txq_id
);
1011 /* Set this queue as a chain-building queue */
1012 iwl_set_bits_prph(priv
, IWL50_SCD_QUEUECHAIN_SEL
, (1<<txq_id
));
1014 /* enable aggregations for the queue */
1015 iwl_set_bits_prph(priv
, IWL50_SCD_AGGR_SEL
, (1<<txq_id
));
1017 /* Place first TFD at index corresponding to start sequence number.
1018 * Assumes that ssn_idx is valid (!= 0xFFF) */
1019 priv
->txq
[txq_id
].q
.read_ptr
= (ssn_idx
& 0xff);
1020 priv
->txq
[txq_id
].q
.write_ptr
= (ssn_idx
& 0xff);
1021 iwl5000_set_wr_ptrs(priv
, txq_id
, ssn_idx
);
1023 /* Set up Tx window size and frame limit for this queue */
1024 iwl_write_targ_mem(priv
, priv
->scd_base_addr
+
1025 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id
) +
1028 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS
) &
1029 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK
) |
1030 ((SCD_FRAME_LIMIT
<<
1031 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
) &
1032 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
));
1034 iwl_set_bits_prph(priv
, IWL50_SCD_INTERRUPT_MASK
, (1 << txq_id
));
1036 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1037 iwl5000_tx_queue_set_status(priv
, &priv
->txq
[txq_id
], tx_fifo
, 1);
1039 spin_unlock_irqrestore(&priv
->lock
, flags
);
1044 static int iwl5000_txq_agg_disable(struct iwl_priv
*priv
, u16 txq_id
,
1045 u16 ssn_idx
, u8 tx_fifo
)
1047 if ((IWL50_FIRST_AMPDU_QUEUE
> txq_id
) ||
1048 (IWL50_FIRST_AMPDU_QUEUE
+ IWL50_NUM_AMPDU_QUEUES
<= txq_id
)) {
1050 "queue number out of range: %d, must be %d to %d\n",
1051 txq_id
, IWL50_FIRST_AMPDU_QUEUE
,
1052 IWL50_FIRST_AMPDU_QUEUE
+ IWL50_NUM_AMPDU_QUEUES
- 1);
1056 iwl5000_tx_queue_stop_scheduler(priv
, txq_id
);
1058 iwl_clear_bits_prph(priv
, IWL50_SCD_AGGR_SEL
, (1 << txq_id
));
1060 priv
->txq
[txq_id
].q
.read_ptr
= (ssn_idx
& 0xff);
1061 priv
->txq
[txq_id
].q
.write_ptr
= (ssn_idx
& 0xff);
1062 /* supposes that ssn_idx is valid (!= 0xFFF) */
1063 iwl5000_set_wr_ptrs(priv
, txq_id
, ssn_idx
);
1065 iwl_clear_bits_prph(priv
, IWL50_SCD_INTERRUPT_MASK
, (1 << txq_id
));
1066 iwl_txq_ctx_deactivate(priv
, txq_id
);
1067 iwl5000_tx_queue_set_status(priv
, &priv
->txq
[txq_id
], tx_fifo
, 0);
1072 u16
iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd
*cmd
, u8
*data
)
1074 u16 size
= (u16
)sizeof(struct iwl_addsta_cmd
);
1075 struct iwl_addsta_cmd
*addsta
= (struct iwl_addsta_cmd
*)data
;
1076 memcpy(addsta
, cmd
, size
);
1077 /* resrved in 5000 */
1078 addsta
->rate_n_flags
= cpu_to_le16(0);
1084 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1085 * must be called under priv->lock and mac access
1087 static void iwl5000_txq_set_sched(struct iwl_priv
*priv
, u32 mask
)
1089 iwl_write_prph(priv
, IWL50_SCD_TXFACT
, mask
);
1093 static inline u32
iwl5000_get_scd_ssn(struct iwl5000_tx_resp
*tx_resp
)
1095 return le32_to_cpup((__le32
*)&tx_resp
->status
+
1096 tx_resp
->frame_count
) & MAX_SN
;
1099 static int iwl5000_tx_status_reply_tx(struct iwl_priv
*priv
,
1100 struct iwl_ht_agg
*agg
,
1101 struct iwl5000_tx_resp
*tx_resp
,
1102 int txq_id
, u16 start_idx
)
1105 struct agg_tx_status
*frame_status
= &tx_resp
->status
;
1106 struct ieee80211_tx_info
*info
= NULL
;
1107 struct ieee80211_hdr
*hdr
= NULL
;
1108 u32 rate_n_flags
= le32_to_cpu(tx_resp
->rate_n_flags
);
1112 if (agg
->wait_for_ba
)
1113 IWL_DEBUG_TX_REPLY(priv
, "got tx response w/o block-ack\n");
1115 agg
->frame_count
= tx_resp
->frame_count
;
1116 agg
->start_idx
= start_idx
;
1117 agg
->rate_n_flags
= rate_n_flags
;
1120 /* # frames attempted by Tx command */
1121 if (agg
->frame_count
== 1) {
1122 /* Only one frame was attempted; no block-ack will arrive */
1123 status
= le16_to_cpu(frame_status
[0].status
);
1126 /* FIXME: code repetition */
1127 IWL_DEBUG_TX_REPLY(priv
, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1128 agg
->frame_count
, agg
->start_idx
, idx
);
1130 info
= IEEE80211_SKB_CB(priv
->txq
[txq_id
].txb
[idx
].skb
[0]);
1131 info
->status
.rates
[0].count
= tx_resp
->failure_frame
+ 1;
1132 info
->flags
&= ~IEEE80211_TX_CTL_AMPDU
;
1133 info
->flags
|= iwl_is_tx_success(status
) ?
1134 IEEE80211_TX_STAT_ACK
: 0;
1135 iwl_hwrate_to_tx_control(priv
, rate_n_flags
, info
);
1137 /* FIXME: code repetition end */
1139 IWL_DEBUG_TX_REPLY(priv
, "1 Frame 0x%x failure :%d\n",
1140 status
& 0xff, tx_resp
->failure_frame
);
1141 IWL_DEBUG_TX_REPLY(priv
, "Rate Info rate_n_flags=%x\n", rate_n_flags
);
1143 agg
->wait_for_ba
= 0;
1145 /* Two or more frames were attempted; expect block-ack */
1147 int start
= agg
->start_idx
;
1149 /* Construct bit-map of pending frames within Tx window */
1150 for (i
= 0; i
< agg
->frame_count
; i
++) {
1152 status
= le16_to_cpu(frame_status
[i
].status
);
1153 seq
= le16_to_cpu(frame_status
[i
].sequence
);
1154 idx
= SEQ_TO_INDEX(seq
);
1155 txq_id
= SEQ_TO_QUEUE(seq
);
1157 if (status
& (AGG_TX_STATE_FEW_BYTES_MSK
|
1158 AGG_TX_STATE_ABORT_MSK
))
1161 IWL_DEBUG_TX_REPLY(priv
, "FrameCnt = %d, txq_id=%d idx=%d\n",
1162 agg
->frame_count
, txq_id
, idx
);
1164 hdr
= iwl_tx_queue_get_hdr(priv
, txq_id
, idx
);
1166 sc
= le16_to_cpu(hdr
->seq_ctrl
);
1167 if (idx
!= (SEQ_TO_SN(sc
) & 0xff)) {
1169 "BUG_ON idx doesn't match seq control"
1170 " idx=%d, seq_idx=%d, seq=%d\n",
1176 IWL_DEBUG_TX_REPLY(priv
, "AGG Frame i=%d idx %d seq=%d\n",
1177 i
, idx
, SEQ_TO_SN(sc
));
1181 sh
= (start
- idx
) + 0xff;
1182 bitmap
= bitmap
<< sh
;
1185 } else if (sh
< -64)
1186 sh
= 0xff - (start
- idx
);
1190 bitmap
= bitmap
<< sh
;
1193 bitmap
|= 1ULL << sh
;
1194 IWL_DEBUG_TX_REPLY(priv
, "start=%d bitmap=0x%llx\n",
1195 start
, (unsigned long long)bitmap
);
1198 agg
->bitmap
= bitmap
;
1199 agg
->start_idx
= start
;
1200 IWL_DEBUG_TX_REPLY(priv
, "Frames %d start_idx=%d bitmap=0x%llx\n",
1201 agg
->frame_count
, agg
->start_idx
,
1202 (unsigned long long)agg
->bitmap
);
1205 agg
->wait_for_ba
= 1;
1210 static void iwl5000_rx_reply_tx(struct iwl_priv
*priv
,
1211 struct iwl_rx_mem_buffer
*rxb
)
1213 struct iwl_rx_packet
*pkt
= (struct iwl_rx_packet
*)rxb
->skb
->data
;
1214 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1215 int txq_id
= SEQ_TO_QUEUE(sequence
);
1216 int index
= SEQ_TO_INDEX(sequence
);
1217 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1218 struct ieee80211_tx_info
*info
;
1219 struct iwl5000_tx_resp
*tx_resp
= (void *)&pkt
->u
.raw
[0];
1220 u32 status
= le16_to_cpu(tx_resp
->status
.status
);
1225 if ((index
>= txq
->q
.n_bd
) || (iwl_queue_used(&txq
->q
, index
) == 0)) {
1226 IWL_ERR(priv
, "Read index for DMA queue txq_id (%d) index %d "
1227 "is out of range [0-%d] %d %d\n", txq_id
,
1228 index
, txq
->q
.n_bd
, txq
->q
.write_ptr
,
1233 info
= IEEE80211_SKB_CB(txq
->txb
[txq
->q
.read_ptr
].skb
[0]);
1234 memset(&info
->status
, 0, sizeof(info
->status
));
1236 tid
= (tx_resp
->ra_tid
& IWL50_TX_RES_TID_MSK
) >> IWL50_TX_RES_TID_POS
;
1237 sta_id
= (tx_resp
->ra_tid
& IWL50_TX_RES_RA_MSK
) >> IWL50_TX_RES_RA_POS
;
1239 if (txq
->sched_retry
) {
1240 const u32 scd_ssn
= iwl5000_get_scd_ssn(tx_resp
);
1241 struct iwl_ht_agg
*agg
= NULL
;
1243 agg
= &priv
->stations
[sta_id
].tid
[tid
].agg
;
1245 iwl5000_tx_status_reply_tx(priv
, agg
, tx_resp
, txq_id
, index
);
1247 /* check if BAR is needed */
1248 if ((tx_resp
->frame_count
== 1) && !iwl_is_tx_success(status
))
1249 info
->flags
|= IEEE80211_TX_STAT_AMPDU_NO_BACK
;
1251 if (txq
->q
.read_ptr
!= (scd_ssn
& 0xff)) {
1252 index
= iwl_queue_dec_wrap(scd_ssn
& 0xff, txq
->q
.n_bd
);
1253 IWL_DEBUG_TX_REPLY(priv
, "Retry scheduler reclaim "
1254 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1255 scd_ssn
, index
, txq_id
, txq
->swq_id
);
1257 freed
= iwl_tx_queue_reclaim(priv
, txq_id
, index
);
1258 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
-= freed
;
1260 if (priv
->mac80211_registered
&&
1261 (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
) &&
1262 (agg
->state
!= IWL_EMPTYING_HW_QUEUE_DELBA
)) {
1263 if (agg
->state
== IWL_AGG_OFF
)
1264 iwl_wake_queue(priv
, txq_id
);
1266 iwl_wake_queue(priv
, txq
->swq_id
);
1270 BUG_ON(txq_id
!= txq
->swq_id
);
1272 info
->status
.rates
[0].count
= tx_resp
->failure_frame
+ 1;
1273 info
->flags
|= iwl_is_tx_success(status
) ?
1274 IEEE80211_TX_STAT_ACK
: 0;
1275 iwl_hwrate_to_tx_control(priv
,
1276 le32_to_cpu(tx_resp
->rate_n_flags
),
1279 IWL_DEBUG_TX_REPLY(priv
, "TXQ %d status %s (0x%08x) rate_n_flags "
1280 "0x%x retries %d\n",
1282 iwl_get_tx_fail_reason(status
), status
,
1283 le32_to_cpu(tx_resp
->rate_n_flags
),
1284 tx_resp
->failure_frame
);
1286 freed
= iwl_tx_queue_reclaim(priv
, txq_id
, index
);
1287 if (ieee80211_is_data_qos(tx_resp
->frame_ctrl
))
1288 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
-= freed
;
1290 if (priv
->mac80211_registered
&&
1291 (iwl_queue_space(&txq
->q
) > txq
->q
.low_mark
))
1292 iwl_wake_queue(priv
, txq_id
);
1295 if (ieee80211_is_data_qos(tx_resp
->frame_ctrl
))
1296 iwl_txq_check_empty(priv
, sta_id
, tid
, txq_id
);
1298 if (iwl_check_bits(status
, TX_ABORT_REQUIRED_MSK
))
1299 IWL_ERR(priv
, "TODO: Implement Tx ABORT REQUIRED!!!\n");
1302 /* Currently 5000 is the superset of everything */
1303 u16
iwl5000_get_hcmd_size(u8 cmd_id
, u16 len
)
1308 static void iwl5000_setup_deferred_work(struct iwl_priv
*priv
)
1310 /* in 5000 the tx power calibration is done in uCode */
1311 priv
->disable_tx_power_cal
= 1;
1314 static void iwl5000_rx_handler_setup(struct iwl_priv
*priv
)
1316 /* init calibration handlers */
1317 priv
->rx_handlers
[CALIBRATION_RES_NOTIFICATION
] =
1318 iwl5000_rx_calib_result
;
1319 priv
->rx_handlers
[CALIBRATION_COMPLETE_NOTIFICATION
] =
1320 iwl5000_rx_calib_complete
;
1321 priv
->rx_handlers
[REPLY_TX
] = iwl5000_rx_reply_tx
;
1325 static int iwl5000_hw_valid_rtc_data_addr(u32 addr
)
1327 return (addr
>= IWL50_RTC_DATA_LOWER_BOUND
) &&
1328 (addr
< IWL50_RTC_DATA_UPPER_BOUND
);
1331 static int iwl5000_send_rxon_assoc(struct iwl_priv
*priv
)
1334 struct iwl5000_rxon_assoc_cmd rxon_assoc
;
1335 const struct iwl_rxon_cmd
*rxon1
= &priv
->staging_rxon
;
1336 const struct iwl_rxon_cmd
*rxon2
= &priv
->active_rxon
;
1338 if ((rxon1
->flags
== rxon2
->flags
) &&
1339 (rxon1
->filter_flags
== rxon2
->filter_flags
) &&
1340 (rxon1
->cck_basic_rates
== rxon2
->cck_basic_rates
) &&
1341 (rxon1
->ofdm_ht_single_stream_basic_rates
==
1342 rxon2
->ofdm_ht_single_stream_basic_rates
) &&
1343 (rxon1
->ofdm_ht_dual_stream_basic_rates
==
1344 rxon2
->ofdm_ht_dual_stream_basic_rates
) &&
1345 (rxon1
->ofdm_ht_triple_stream_basic_rates
==
1346 rxon2
->ofdm_ht_triple_stream_basic_rates
) &&
1347 (rxon1
->acquisition_data
== rxon2
->acquisition_data
) &&
1348 (rxon1
->rx_chain
== rxon2
->rx_chain
) &&
1349 (rxon1
->ofdm_basic_rates
== rxon2
->ofdm_basic_rates
)) {
1350 IWL_DEBUG_INFO(priv
, "Using current RXON_ASSOC. Not resending.\n");
1354 rxon_assoc
.flags
= priv
->staging_rxon
.flags
;
1355 rxon_assoc
.filter_flags
= priv
->staging_rxon
.filter_flags
;
1356 rxon_assoc
.ofdm_basic_rates
= priv
->staging_rxon
.ofdm_basic_rates
;
1357 rxon_assoc
.cck_basic_rates
= priv
->staging_rxon
.cck_basic_rates
;
1358 rxon_assoc
.reserved1
= 0;
1359 rxon_assoc
.reserved2
= 0;
1360 rxon_assoc
.reserved3
= 0;
1361 rxon_assoc
.ofdm_ht_single_stream_basic_rates
=
1362 priv
->staging_rxon
.ofdm_ht_single_stream_basic_rates
;
1363 rxon_assoc
.ofdm_ht_dual_stream_basic_rates
=
1364 priv
->staging_rxon
.ofdm_ht_dual_stream_basic_rates
;
1365 rxon_assoc
.rx_chain_select_flags
= priv
->staging_rxon
.rx_chain
;
1366 rxon_assoc
.ofdm_ht_triple_stream_basic_rates
=
1367 priv
->staging_rxon
.ofdm_ht_triple_stream_basic_rates
;
1368 rxon_assoc
.acquisition_data
= priv
->staging_rxon
.acquisition_data
;
1370 ret
= iwl_send_cmd_pdu_async(priv
, REPLY_RXON_ASSOC
,
1371 sizeof(rxon_assoc
), &rxon_assoc
, NULL
);
1377 static int iwl5000_send_tx_power(struct iwl_priv
*priv
)
1379 struct iwl5000_tx_power_dbm_cmd tx_power_cmd
;
1382 /* half dBm need to multiply */
1383 tx_power_cmd
.global_lmt
= (s8
)(2 * priv
->tx_power_user_lmt
);
1384 tx_power_cmd
.flags
= IWL50_TX_POWER_NO_CLOSED
;
1385 tx_power_cmd
.srv_chan_lmt
= IWL50_TX_POWER_AUTO
;
1387 if (IWL_UCODE_API(priv
->ucode_ver
) == 1)
1388 tx_ant_cfg_cmd
= REPLY_TX_POWER_DBM_CMD_V1
;
1390 tx_ant_cfg_cmd
= REPLY_TX_POWER_DBM_CMD
;
1392 return iwl_send_cmd_pdu_async(priv
, tx_ant_cfg_cmd
,
1393 sizeof(tx_power_cmd
), &tx_power_cmd
,
1397 static void iwl5000_temperature(struct iwl_priv
*priv
)
1399 /* store temperature from statistics (in Celsius) */
1400 priv
->temperature
= le32_to_cpu(priv
->statistics
.general
.temperature
);
1403 static void iwl5150_temperature(struct iwl_priv
*priv
)
1406 s32 offset
= iwl_temp_calib_to_offset(priv
);
1408 vt
= le32_to_cpu(priv
->statistics
.general
.temperature
);
1409 vt
= vt
/ IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF
+ offset
;
1410 /* now vt hold the temperature in Kelvin */
1411 priv
->temperature
= KELVIN_TO_CELSIUS(vt
);
1414 /* Calc max signal level (dBm) among 3 possible receivers */
1415 int iwl5000_calc_rssi(struct iwl_priv
*priv
,
1416 struct iwl_rx_phy_res
*rx_resp
)
1418 /* data from PHY/DSP regarding signal strength, etc.,
1419 * contents are always there, not configurable by host
1421 struct iwl5000_non_cfg_phy
*ncphy
=
1422 (struct iwl5000_non_cfg_phy
*)rx_resp
->non_cfg_phy_buf
;
1423 u32 val
, rssi_a
, rssi_b
, rssi_c
, max_rssi
;
1426 val
= le32_to_cpu(ncphy
->non_cfg_phy
[IWL50_RX_RES_AGC_IDX
]);
1427 agc
= (val
& IWL50_OFDM_AGC_MSK
) >> IWL50_OFDM_AGC_BIT_POS
;
1429 /* Find max rssi among 3 possible receivers.
1430 * These values are measured by the digital signal processor (DSP).
1431 * They should stay fairly constant even as the signal strength varies,
1432 * if the radio's automatic gain control (AGC) is working right.
1433 * AGC value (see below) will provide the "interesting" info.
1435 val
= le32_to_cpu(ncphy
->non_cfg_phy
[IWL50_RX_RES_RSSI_AB_IDX
]);
1436 rssi_a
= (val
& IWL50_OFDM_RSSI_A_MSK
) >> IWL50_OFDM_RSSI_A_BIT_POS
;
1437 rssi_b
= (val
& IWL50_OFDM_RSSI_B_MSK
) >> IWL50_OFDM_RSSI_B_BIT_POS
;
1438 val
= le32_to_cpu(ncphy
->non_cfg_phy
[IWL50_RX_RES_RSSI_C_IDX
]);
1439 rssi_c
= (val
& IWL50_OFDM_RSSI_C_MSK
) >> IWL50_OFDM_RSSI_C_BIT_POS
;
1441 max_rssi
= max_t(u32
, rssi_a
, rssi_b
);
1442 max_rssi
= max_t(u32
, max_rssi
, rssi_c
);
1444 IWL_DEBUG_STATS(priv
, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1445 rssi_a
, rssi_b
, rssi_c
, max_rssi
, agc
);
1447 /* dBm = max_rssi dB - agc dB - constant.
1448 * Higher AGC (higher radio gain) means lower signal. */
1449 return max_rssi
- agc
- IWL49_RSSI_OFFSET
;
1452 struct iwl_hcmd_ops iwl5000_hcmd
= {
1453 .rxon_assoc
= iwl5000_send_rxon_assoc
,
1454 .commit_rxon
= iwl_commit_rxon
,
1455 .set_rxon_chain
= iwl_set_rxon_chain
,
1458 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils
= {
1459 .get_hcmd_size
= iwl5000_get_hcmd_size
,
1460 .build_addsta_hcmd
= iwl5000_build_addsta_hcmd
,
1461 .gain_computation
= iwl5000_gain_computation
,
1462 .chain_noise_reset
= iwl5000_chain_noise_reset
,
1463 .rts_tx_cmd_flag
= iwl5000_rts_tx_cmd_flag
,
1464 .calc_rssi
= iwl5000_calc_rssi
,
1467 struct iwl_lib_ops iwl5000_lib
= {
1468 .set_hw_params
= iwl5000_hw_set_hw_params
,
1469 .txq_update_byte_cnt_tbl
= iwl5000_txq_update_byte_cnt_tbl
,
1470 .txq_inval_byte_cnt_tbl
= iwl5000_txq_inval_byte_cnt_tbl
,
1471 .txq_set_sched
= iwl5000_txq_set_sched
,
1472 .txq_agg_enable
= iwl5000_txq_agg_enable
,
1473 .txq_agg_disable
= iwl5000_txq_agg_disable
,
1474 .txq_attach_buf_to_tfd
= iwl_hw_txq_attach_buf_to_tfd
,
1475 .txq_free_tfd
= iwl_hw_txq_free_tfd
,
1476 .txq_init
= iwl_hw_tx_queue_init
,
1477 .rx_handler_setup
= iwl5000_rx_handler_setup
,
1478 .setup_deferred_work
= iwl5000_setup_deferred_work
,
1479 .is_valid_rtc_data_addr
= iwl5000_hw_valid_rtc_data_addr
,
1480 .load_ucode
= iwl5000_load_ucode
,
1481 .init_alive_start
= iwl5000_init_alive_start
,
1482 .alive_notify
= iwl5000_alive_notify
,
1483 .send_tx_power
= iwl5000_send_tx_power
,
1484 .update_chain_flags
= iwl_update_chain_flags
,
1486 .init
= iwl5000_apm_init
,
1487 .reset
= iwl5000_apm_reset
,
1488 .stop
= iwl5000_apm_stop
,
1489 .config
= iwl5000_nic_config
,
1490 .set_pwr_src
= iwl_set_pwr_src
,
1493 .regulatory_bands
= {
1494 EEPROM_5000_REG_BAND_1_CHANNELS
,
1495 EEPROM_5000_REG_BAND_2_CHANNELS
,
1496 EEPROM_5000_REG_BAND_3_CHANNELS
,
1497 EEPROM_5000_REG_BAND_4_CHANNELS
,
1498 EEPROM_5000_REG_BAND_5_CHANNELS
,
1499 EEPROM_5000_REG_BAND_24_FAT_CHANNELS
,
1500 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1502 .verify_signature
= iwlcore_eeprom_verify_signature
,
1503 .acquire_semaphore
= iwlcore_eeprom_acquire_semaphore
,
1504 .release_semaphore
= iwlcore_eeprom_release_semaphore
,
1505 .calib_version
= iwl5000_eeprom_calib_version
,
1506 .query_addr
= iwl5000_eeprom_query_addr
,
1508 .post_associate
= iwl_post_associate
,
1510 .config_ap
= iwl_config_ap
,
1512 .temperature
= iwl5000_temperature
,
1513 .set_ct_kill
= iwl5000_set_ct_threshold
,
1517 static struct iwl_lib_ops iwl5150_lib
= {
1518 .set_hw_params
= iwl5000_hw_set_hw_params
,
1519 .txq_update_byte_cnt_tbl
= iwl5000_txq_update_byte_cnt_tbl
,
1520 .txq_inval_byte_cnt_tbl
= iwl5000_txq_inval_byte_cnt_tbl
,
1521 .txq_set_sched
= iwl5000_txq_set_sched
,
1522 .txq_agg_enable
= iwl5000_txq_agg_enable
,
1523 .txq_agg_disable
= iwl5000_txq_agg_disable
,
1524 .txq_attach_buf_to_tfd
= iwl_hw_txq_attach_buf_to_tfd
,
1525 .txq_free_tfd
= iwl_hw_txq_free_tfd
,
1526 .txq_init
= iwl_hw_tx_queue_init
,
1527 .rx_handler_setup
= iwl5000_rx_handler_setup
,
1528 .setup_deferred_work
= iwl5000_setup_deferred_work
,
1529 .is_valid_rtc_data_addr
= iwl5000_hw_valid_rtc_data_addr
,
1530 .load_ucode
= iwl5000_load_ucode
,
1531 .init_alive_start
= iwl5000_init_alive_start
,
1532 .alive_notify
= iwl5000_alive_notify
,
1533 .send_tx_power
= iwl5000_send_tx_power
,
1534 .update_chain_flags
= iwl_update_chain_flags
,
1536 .init
= iwl5000_apm_init
,
1537 .reset
= iwl5000_apm_reset
,
1538 .stop
= iwl5000_apm_stop
,
1539 .config
= iwl5000_nic_config
,
1540 .set_pwr_src
= iwl_set_pwr_src
,
1543 .regulatory_bands
= {
1544 EEPROM_5000_REG_BAND_1_CHANNELS
,
1545 EEPROM_5000_REG_BAND_2_CHANNELS
,
1546 EEPROM_5000_REG_BAND_3_CHANNELS
,
1547 EEPROM_5000_REG_BAND_4_CHANNELS
,
1548 EEPROM_5000_REG_BAND_5_CHANNELS
,
1549 EEPROM_5000_REG_BAND_24_FAT_CHANNELS
,
1550 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1552 .verify_signature
= iwlcore_eeprom_verify_signature
,
1553 .acquire_semaphore
= iwlcore_eeprom_acquire_semaphore
,
1554 .release_semaphore
= iwlcore_eeprom_release_semaphore
,
1555 .calib_version
= iwl5000_eeprom_calib_version
,
1556 .query_addr
= iwl5000_eeprom_query_addr
,
1558 .post_associate
= iwl_post_associate
,
1560 .config_ap
= iwl_config_ap
,
1562 .temperature
= iwl5150_temperature
,
1563 .set_ct_kill
= iwl5150_set_ct_threshold
,
1567 struct iwl_ops iwl5000_ops
= {
1568 .lib
= &iwl5000_lib
,
1569 .hcmd
= &iwl5000_hcmd
,
1570 .utils
= &iwl5000_hcmd_utils
,
1573 static struct iwl_ops iwl5150_ops
= {
1574 .lib
= &iwl5150_lib
,
1575 .hcmd
= &iwl5000_hcmd
,
1576 .utils
= &iwl5000_hcmd_utils
,
1579 struct iwl_mod_params iwl50_mod_params
= {
1580 .num_of_queues
= IWL50_NUM_QUEUES
,
1581 .num_of_ampdu_queues
= IWL50_NUM_AMPDU_QUEUES
,
1584 /* the rest are 0 by default */
1588 struct iwl_cfg iwl5300_agn_cfg
= {
1590 .fw_name_pre
= IWL5000_FW_PRE
,
1591 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1592 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1593 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1594 .ops
= &iwl5000_ops
,
1595 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1596 .eeprom_ver
= EEPROM_5000_EEPROM_VERSION
,
1597 .eeprom_calib_ver
= EEPROM_5000_TX_POWER_VERSION
,
1598 .mod_params
= &iwl50_mod_params
,
1599 .valid_tx_ant
= ANT_ABC
,
1600 .valid_rx_ant
= ANT_ABC
,
1601 .need_pll_cfg
= true,
1604 struct iwl_cfg iwl5100_bg_cfg
= {
1606 .fw_name_pre
= IWL5000_FW_PRE
,
1607 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1608 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1610 .ops
= &iwl5000_ops
,
1611 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1612 .eeprom_ver
= EEPROM_5000_EEPROM_VERSION
,
1613 .eeprom_calib_ver
= EEPROM_5000_TX_POWER_VERSION
,
1614 .mod_params
= &iwl50_mod_params
,
1615 .valid_tx_ant
= ANT_B
,
1616 .valid_rx_ant
= ANT_AB
,
1617 .need_pll_cfg
= true,
1620 struct iwl_cfg iwl5100_abg_cfg
= {
1622 .fw_name_pre
= IWL5000_FW_PRE
,
1623 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1624 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1625 .sku
= IWL_SKU_A
|IWL_SKU_G
,
1626 .ops
= &iwl5000_ops
,
1627 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1628 .eeprom_ver
= EEPROM_5000_EEPROM_VERSION
,
1629 .eeprom_calib_ver
= EEPROM_5000_TX_POWER_VERSION
,
1630 .mod_params
= &iwl50_mod_params
,
1631 .valid_tx_ant
= ANT_B
,
1632 .valid_rx_ant
= ANT_AB
,
1633 .need_pll_cfg
= true,
1636 struct iwl_cfg iwl5100_agn_cfg
= {
1638 .fw_name_pre
= IWL5000_FW_PRE
,
1639 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1640 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1641 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1642 .ops
= &iwl5000_ops
,
1643 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1644 .eeprom_ver
= EEPROM_5000_EEPROM_VERSION
,
1645 .eeprom_calib_ver
= EEPROM_5000_TX_POWER_VERSION
,
1646 .mod_params
= &iwl50_mod_params
,
1647 .valid_tx_ant
= ANT_B
,
1648 .valid_rx_ant
= ANT_AB
,
1649 .need_pll_cfg
= true,
1652 struct iwl_cfg iwl5350_agn_cfg
= {
1654 .fw_name_pre
= IWL5000_FW_PRE
,
1655 .ucode_api_max
= IWL5000_UCODE_API_MAX
,
1656 .ucode_api_min
= IWL5000_UCODE_API_MIN
,
1657 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1658 .ops
= &iwl5000_ops
,
1659 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1660 .eeprom_ver
= EEPROM_5050_EEPROM_VERSION
,
1661 .eeprom_calib_ver
= EEPROM_5050_TX_POWER_VERSION
,
1662 .mod_params
= &iwl50_mod_params
,
1663 .valid_tx_ant
= ANT_ABC
,
1664 .valid_rx_ant
= ANT_ABC
,
1665 .need_pll_cfg
= true,
1668 struct iwl_cfg iwl5150_agn_cfg
= {
1670 .fw_name_pre
= IWL5150_FW_PRE
,
1671 .ucode_api_max
= IWL5150_UCODE_API_MAX
,
1672 .ucode_api_min
= IWL5150_UCODE_API_MIN
,
1673 .sku
= IWL_SKU_A
|IWL_SKU_G
|IWL_SKU_N
,
1674 .ops
= &iwl5150_ops
,
1675 .eeprom_size
= IWL_5000_EEPROM_IMG_SIZE
,
1676 .eeprom_ver
= EEPROM_5050_EEPROM_VERSION
,
1677 .eeprom_calib_ver
= EEPROM_5050_TX_POWER_VERSION
,
1678 .mod_params
= &iwl50_mod_params
,
1679 .valid_tx_ant
= ANT_A
,
1680 .valid_rx_ant
= ANT_AB
,
1681 .need_pll_cfg
= true,
1684 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX
));
1685 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX
));
1687 module_param_named(swcrypto50
, iwl50_mod_params
.sw_crypto
, bool, 0444);
1688 MODULE_PARM_DESC(swcrypto50
,
1689 "using software crypto engine (default 0 [hardware])\n");
1690 module_param_named(debug50
, iwl50_mod_params
.debug
, uint
, 0444);
1691 MODULE_PARM_DESC(debug50
, "50XX debug output mask");
1692 module_param_named(queues_num50
, iwl50_mod_params
.num_of_queues
, int, 0444);
1693 MODULE_PARM_DESC(queues_num50
, "number of hw queues in 50xx series");
1694 module_param_named(11n_disable50
, iwl50_mod_params
.disable_11n
, int, 0444);
1695 MODULE_PARM_DESC(11n_disable50
, "disable 50XX 11n functionality");
1696 module_param_named(amsdu_size_8K50
, iwl50_mod_params
.amsdu_size_8K
, int, 0444);
1697 MODULE_PARM_DESC(amsdu_size_8K50
, "enable 8K amsdu size in 50XX series");
1698 module_param_named(fw_restart50
, iwl50_mod_params
.restart_fw
, int, 0444);
1699 MODULE_PARM_DESC(fw_restart50
, "restart firmware in case of error");