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Merge branch 'for-2.6.30' into for-2.6.31
[firewire-audio.git] / sound / soc / omap / omap-mcbsp.c
blob495192af8c2ea51d12f2b1a4f5f33679148ed7fa
1 /*
2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 *
6 * Contact: Jarkko Nikula <jhnikula@gmail.com>
7 * Peter Ujfalusi <peter.ujfalusi@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/initval.h>
32 #include <sound/soc.h>
33
34 #include <mach/control.h>
35 #include <mach/dma.h>
36 #include <mach/mcbsp.h>
37 #include "omap-mcbsp.h"
38 #include "omap-pcm.h"
39
40 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
41
42 struct omap_mcbsp_data {
43 unsigned int bus_id;
44 struct omap_mcbsp_reg_cfg regs;
45 unsigned int fmt;
46 /*
47 * Flags indicating is the bus already activated and configured by
48 * another substream
49 */
50 int active;
51 int configured;
52 };
53
54 #define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
55
56 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
57
58 /*
59 * Stream DMA parameters. DMA request line and port address are set runtime
60 * since they are different between OMAP1 and later OMAPs
61 */
62 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
63
64 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
65 static const int omap1_dma_reqs[][2] = {
66 { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
67 { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
68 { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
69 };
70 static const unsigned long omap1_mcbsp_port[][2] = {
71 { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
72 OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
73 { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
74 OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
75 { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
76 OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
77 };
78 #else
79 static const int omap1_dma_reqs[][2] = {};
80 static const unsigned long omap1_mcbsp_port[][2] = {};
81 #endif
82
83 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
84 static const int omap24xx_dma_reqs[][2] = {
85 { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
86 { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
87 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
88 { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
89 { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
90 { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
91 #endif
92 };
93 #else
94 static const int omap24xx_dma_reqs[][2] = {};
95 #endif
96
97 #if defined(CONFIG_ARCH_OMAP2420)
98 static const unsigned long omap2420_mcbsp_port[][2] = {
99 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
100 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
101 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
102 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
103 };
104 #else
105 static const unsigned long omap2420_mcbsp_port[][2] = {};
106 #endif
107
108 #if defined(CONFIG_ARCH_OMAP2430)
109 static const unsigned long omap2430_mcbsp_port[][2] = {
110 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
111 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
112 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
113 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
114 { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
115 OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
116 { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
117 OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
118 { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
119 OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
120 };
121 #else
122 static const unsigned long omap2430_mcbsp_port[][2] = {};
123 #endif
124
125 #if defined(CONFIG_ARCH_OMAP34XX)
126 static const unsigned long omap34xx_mcbsp_port[][2] = {
127 { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
128 OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
129 { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
130 OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
131 { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
132 OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
133 { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
134 OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
135 { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
136 OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
137 };
138 #else
139 static const unsigned long omap34xx_mcbsp_port[][2] = {};
140 #endif
141
142 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
143 struct snd_soc_dai *dai)
144 {
145 struct snd_soc_pcm_runtime *rtd = substream->private_data;
146 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
147 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
148 int err = 0;
149
150 if (cpu_is_omap343x() && mcbsp_data->bus_id == 1) {
151 /*
152 * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
153 * Set constraint for minimum buffer size to the same than FIFO
154 * size in order to avoid underruns in playback startup because
155 * HW is keeping the DMA request active until FIFO is filled.
156 */
157 snd_pcm_hw_constraint_minmax(substream->runtime,
158 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4096, UINT_MAX);
159 }
160
161 if (!cpu_dai->active)
162 err = omap_mcbsp_request(mcbsp_data->bus_id);
163
164 return err;
165 }
166
167 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
168 struct snd_soc_dai *dai)
169 {
170 struct snd_soc_pcm_runtime *rtd = substream->private_data;
171 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
172 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
173
174 if (!cpu_dai->active) {
175 omap_mcbsp_free(mcbsp_data->bus_id);
176 mcbsp_data->configured = 0;
177 }
178 }
179
180 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
181 struct snd_soc_dai *dai)
182 {
183 struct snd_soc_pcm_runtime *rtd = substream->private_data;
184 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
185 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
186 int err = 0;
187
188 switch (cmd) {
189 case SNDRV_PCM_TRIGGER_START:
190 case SNDRV_PCM_TRIGGER_RESUME:
191 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
192 if (!mcbsp_data->active++)
193 omap_mcbsp_start(mcbsp_data->bus_id);
194 break;
195
196 case SNDRV_PCM_TRIGGER_STOP:
197 case SNDRV_PCM_TRIGGER_SUSPEND:
198 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
199 if (!--mcbsp_data->active)
200 omap_mcbsp_stop(mcbsp_data->bus_id);
201 break;
202 default:
203 err = -EINVAL;
204 }
205
206 return err;
207 }
208
209 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
210 struct snd_pcm_hw_params *params,
211 struct snd_soc_dai *dai)
212 {
213 struct snd_soc_pcm_runtime *rtd = substream->private_data;
214 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
215 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
216 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
217 int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
218 int wlen, channels, wpf;
219 unsigned long port;
220 unsigned int format;
221
222 if (cpu_class_is_omap1()) {
223 dma = omap1_dma_reqs[bus_id][substream->stream];
224 port = omap1_mcbsp_port[bus_id][substream->stream];
225 } else if (cpu_is_omap2420()) {
226 dma = omap24xx_dma_reqs[bus_id][substream->stream];
227 port = omap2420_mcbsp_port[bus_id][substream->stream];
228 } else if (cpu_is_omap2430()) {
229 dma = omap24xx_dma_reqs[bus_id][substream->stream];
230 port = omap2430_mcbsp_port[bus_id][substream->stream];
231 } else if (cpu_is_omap343x()) {
232 dma = omap24xx_dma_reqs[bus_id][substream->stream];
233 port = omap34xx_mcbsp_port[bus_id][substream->stream];
234 } else {
235 return -ENODEV;
236 }
237 omap_mcbsp_dai_dma_params[id][substream->stream].name =
238 substream->stream ? "Audio Capture" : "Audio Playback";
239 omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
240 omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
241 cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
242
243 if (mcbsp_data->configured) {
244 /* McBSP already configured by another stream */
245 return 0;
246 }
247
248 format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
249 wpf = channels = params_channels(params);
250 switch (channels) {
251 case 2:
252 if (format == SND_SOC_DAIFMT_I2S) {
253 /* Use dual-phase frames */
254 regs->rcr2 |= RPHASE;
255 regs->xcr2 |= XPHASE;
256 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
257 wpf--;
258 regs->rcr2 |= RFRLEN2(wpf - 1);
259 regs->xcr2 |= XFRLEN2(wpf - 1);
260 }
261 case 1:
262 /* Set word per (McBSP) frame for phase1 */
263 regs->rcr1 |= RFRLEN1(wpf - 1);
264 regs->xcr1 |= XFRLEN1(wpf - 1);
265 break;
266 default:
267 /* Unsupported number of channels */
268 return -EINVAL;
269 }
270
271 switch (params_format(params)) {
272 case SNDRV_PCM_FORMAT_S16_LE:
273 /* Set word lengths */
274 wlen = 16;
275 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
276 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
277 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
278 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
279 break;
280 default:
281 /* Unsupported PCM format */
282 return -EINVAL;
283 }
284
285 /* Set FS period and length in terms of bit clock periods */
286 switch (format) {
287 case SND_SOC_DAIFMT_I2S:
288 regs->srgr2 |= FPER(wlen * channels - 1);
289 regs->srgr1 |= FWID(wlen - 1);
290 break;
291 case SND_SOC_DAIFMT_DSP_A:
292 case SND_SOC_DAIFMT_DSP_B:
293 regs->srgr2 |= FPER(wlen * channels - 1);
294 regs->srgr1 |= FWID(0);
295 break;
296 }
297
298 omap_mcbsp_config(bus_id, &mcbsp_data->regs);
299 mcbsp_data->configured = 1;
300
301 return 0;
302 }
303
304 /*
305 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
306 * cache is initialized here
307 */
308 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
309 unsigned int fmt)
310 {
311 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
312 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
313 unsigned int temp_fmt = fmt;
314
315 if (mcbsp_data->configured)
316 return 0;
317
318 mcbsp_data->fmt = fmt;
319 memset(regs, 0, sizeof(*regs));
320 /* Generic McBSP register settings */
321 regs->spcr2 |= XINTM(3) | FREE;
322 regs->spcr1 |= RINTM(3);
323 regs->rcr2 |= RFIG;
324 regs->xcr2 |= XFIG;
325 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
326 regs->xccr = DXENDLY(1) | XDMAEN;
327 regs->rccr = RFULL_CYCLE | RDMAEN;
328 }
329
330 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
331 case SND_SOC_DAIFMT_I2S:
332 /* 1-bit data delay */
333 regs->rcr2 |= RDATDLY(1);
334 regs->xcr2 |= XDATDLY(1);
335 break;
336 case SND_SOC_DAIFMT_DSP_A:
337 /* 1-bit data delay */
338 regs->rcr2 |= RDATDLY(1);
339 regs->xcr2 |= XDATDLY(1);
340 /* Invert FS polarity configuration */
341 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
342 break;
343 case SND_SOC_DAIFMT_DSP_B:
344 /* 0-bit data delay */
345 regs->rcr2 |= RDATDLY(0);
346 regs->xcr2 |= XDATDLY(0);
347 /* Invert FS polarity configuration */
348 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
349 break;
350 default:
351 /* Unsupported data format */
352 return -EINVAL;
353 }
354
355 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
356 case SND_SOC_DAIFMT_CBS_CFS:
357 /* McBSP master. Set FS and bit clocks as outputs */
358 regs->pcr0 |= FSXM | FSRM |
359 CLKXM | CLKRM;
360 /* Sample rate generator drives the FS */
361 regs->srgr2 |= FSGM;
362 break;
363 case SND_SOC_DAIFMT_CBM_CFM:
364 /* McBSP slave */
365 break;
366 default:
367 /* Unsupported master/slave configuration */
368 return -EINVAL;
369 }
370
371 /* Set bit clock (CLKX/CLKR) and FS polarities */
372 switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
373 case SND_SOC_DAIFMT_NB_NF:
374 /*
375 * Normal BCLK + FS.
376 * FS active low. TX data driven on falling edge of bit clock
377 * and RX data sampled on rising edge of bit clock.
378 */
379 regs->pcr0 |= FSXP | FSRP |
380 CLKXP | CLKRP;
381 break;
382 case SND_SOC_DAIFMT_NB_IF:
383 regs->pcr0 |= CLKXP | CLKRP;
384 break;
385 case SND_SOC_DAIFMT_IB_NF:
386 regs->pcr0 |= FSXP | FSRP;
387 break;
388 case SND_SOC_DAIFMT_IB_IF:
389 break;
390 default:
391 return -EINVAL;
392 }
393
394 return 0;
395 }
396
397 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
398 int div_id, int div)
399 {
400 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
401 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
402
403 if (div_id != OMAP_MCBSP_CLKGDV)
404 return -ENODEV;
405
406 regs->srgr1 |= CLKGDV(div - 1);
407
408 return 0;
409 }
410
411 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
412 int clk_id)
413 {
414 int sel_bit;
415 u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
416
417 if (cpu_class_is_omap1()) {
418 /* OMAP1's can use only external source clock */
419 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
420 return -EINVAL;
421 else
422 return 0;
423 }
424
425 if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
426 return -EINVAL;
427
428 if (cpu_is_omap343x())
429 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
430
431 switch (mcbsp_data->bus_id) {
432 case 0:
433 reg = OMAP2_CONTROL_DEVCONF0;
434 sel_bit = 2;
435 break;
436 case 1:
437 reg = OMAP2_CONTROL_DEVCONF0;
438 sel_bit = 6;
439 break;
440 case 2:
441 reg = reg_devconf1;
442 sel_bit = 0;
443 break;
444 case 3:
445 reg = reg_devconf1;
446 sel_bit = 2;
447 break;
448 case 4:
449 reg = reg_devconf1;
450 sel_bit = 4;
451 break;
452 default:
453 return -EINVAL;
454 }
455
456 if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
457 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
458 else
459 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
460
461 return 0;
462 }
463
464 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
465 int clk_id, unsigned int freq,
466 int dir)
467 {
468 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
469 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
470 int err = 0;
471
472 switch (clk_id) {
473 case OMAP_MCBSP_SYSCLK_CLK:
474 regs->srgr2 |= CLKSM;
475 break;
476 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
477 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
478 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
479 break;
480
481 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
482 regs->srgr2 |= CLKSM;
483 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
484 regs->pcr0 |= SCLKME;
485 break;
486 default:
487 err = -ENODEV;
488 }
489
490 return err;
491 }
492
493 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
494 .startup = omap_mcbsp_dai_startup,
495 .shutdown = omap_mcbsp_dai_shutdown,
496 .trigger = omap_mcbsp_dai_trigger,
497 .hw_params = omap_mcbsp_dai_hw_params,
498 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
499 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
500 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
501 };
502
503 #define OMAP_MCBSP_DAI_BUILDER(link_id) \
504 { \
505 .name = "omap-mcbsp-dai-"#link_id, \
506 .id = (link_id), \
507 .playback = { \
508 .channels_min = 1, \
509 .channels_max = 2, \
510 .rates = OMAP_MCBSP_RATES, \
511 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
512 }, \
513 .capture = { \
514 .channels_min = 1, \
515 .channels_max = 2, \
516 .rates = OMAP_MCBSP_RATES, \
517 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
518 }, \
519 .ops = &omap_mcbsp_dai_ops, \
520 .private_data = &mcbsp_data[(link_id)].bus_id, \
521 }
522
523 struct snd_soc_dai omap_mcbsp_dai[] = {
524 OMAP_MCBSP_DAI_BUILDER(0),
525 OMAP_MCBSP_DAI_BUILDER(1),
526 #if NUM_LINKS >= 3
527 OMAP_MCBSP_DAI_BUILDER(2),
528 #endif
529 #if NUM_LINKS == 5
530 OMAP_MCBSP_DAI_BUILDER(3),
531 OMAP_MCBSP_DAI_BUILDER(4),
532 #endif
533 };
534
535 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
536
537 static int __init snd_omap_mcbsp_init(void)
538 {
539 return snd_soc_register_dais(omap_mcbsp_dai,
540 ARRAY_SIZE(omap_mcbsp_dai));
541 }
542 module_init(snd_omap_mcbsp_init);
543
544 static void __exit snd_omap_mcbsp_exit(void)
545 {
546 snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
547 }
548 module_exit(snd_omap_mcbsp_exit);
549
550 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
551 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
552 MODULE_LICENSE("GPL");
AMDTP streaming driver for the Linux FireWire stack (Juju)