?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] sky2: yukon-ec-u chipset initialization
[firewire-audio.git] / drivers / net / sky2.c
blobce135b84a54c8640cfe7a48e8513934a9e3a8e4e
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/in.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "0.15"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
64 #define is_ec_a1(hw) \
65 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
66 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
67
68 #define RX_LE_SIZE 512
69 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
70 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
71 #define RX_DEF_PENDING RX_MAX_PENDING
72 #define RX_SKB_ALIGN 8
73
74 #define TX_RING_SIZE 512
75 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
76 #define TX_MIN_PENDING 64
77 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
78
79 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
80 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
81 #define ETH_JUMBO_MTU 9000
82 #define TX_WATCHDOG (5 * HZ)
83 #define NAPI_WEIGHT 64
84 #define PHY_RETRIES 1000
85
86 static const u32 default_msg =
87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90
91 static int debug = -1; /* defaults above */
92 module_param(debug, int, 0);
93 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94
95 static int copybreak __read_mostly = 256;
96 module_param(copybreak, int, 0);
97 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98
99 static int disable_msi = 0;
100 module_param(disable_msi, int, 0);
101 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
123 { 0 }
124 };
125
126 MODULE_DEVICE_TABLE(pci, sky2_id_table);
127
128 /* Avoid conditionals by using array */
129 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
131
132 /* This driver supports yukon2 chipset only */
133 static const char *yukon2_name[] = {
134 "XL", /* 0xb3 */
135 "EC Ultra", /* 0xb4 */
136 "UNKNOWN", /* 0xb5 */
137 "EC", /* 0xb6 */
138 "FE", /* 0xb7 */
139 };
140
141 /* Access to external PHY */
142 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
143 {
144 int i;
145
146 gma_write16(hw, port, GM_SMI_DATA, val);
147 gma_write16(hw, port, GM_SMI_CTRL,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
149
150 for (i = 0; i < PHY_RETRIES; i++) {
151 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
152 return 0;
153 udelay(1);
154 }
155
156 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
157 return -ETIMEDOUT;
158 }
159
160 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
161 {
162 int i;
163
164 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
165 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
166
167 for (i = 0; i < PHY_RETRIES; i++) {
168 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
169 *val = gma_read16(hw, port, GM_SMI_DATA);
170 return 0;
171 }
172
173 udelay(1);
174 }
175
176 return -ETIMEDOUT;
177 }
178
179 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
180 {
181 u16 v;
182
183 if (__gm_phy_read(hw, port, reg, &v) != 0)
184 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
185 return v;
186 }
187
188 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
189 {
190 u16 power_control;
191 u32 reg1;
192 int vaux;
193 int ret = 0;
194
195 pr_debug("sky2_set_power_state %d\n", state);
196 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
197
198 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
199 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
200 (power_control & PCI_PM_CAP_PME_D3cold);
201
202 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
203
204 power_control |= PCI_PM_CTRL_PME_STATUS;
205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
206
207 switch (state) {
208 case PCI_D0:
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
212
213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
215
216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
222 else
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224
225 /* Turn off phy power saving */
226 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
227 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
228
229 /* looks like this XL is back asswards .. */
230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
231 reg1 |= PCI_Y2_PHY1_COMA;
232 if (hw->ports > 1)
233 reg1 |= PCI_Y2_PHY2_COMA;
234 }
235
236 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
237 pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0);
238 pci_read_config_dword(hw->pdev, PCI_DEV_REG4, &reg1);
239 reg1 &= P_ASPM_CONTROL_MSK;
240 pci_write_config_dword(hw->pdev, PCI_DEV_REG4, reg1);
241 pci_write_config_dword(hw->pdev, PCI_DEV_REG5, 0);
242 }
243
244 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
245
246 break;
247
248 case PCI_D3hot:
249 case PCI_D3cold:
250 /* Turn on phy power saving */
251 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
254 else
255 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
256 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
257
258 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
259 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
260 else
261 /* enable bits are inverted */
262 sky2_write8(hw, B2_Y2_CLK_GATE,
263 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
264 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
265 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
266
267 /* switch power to VAUX */
268 if (vaux && state != PCI_D3cold)
269 sky2_write8(hw, B0_POWER_CTRL,
270 (PC_VAUX_ENA | PC_VCC_ENA |
271 PC_VAUX_ON | PC_VCC_OFF));
272 break;
273 default:
274 printk(KERN_ERR PFX "Unknown power state %d\n", state);
275 ret = -1;
276 }
277
278 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
279 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
280 return ret;
281 }
282
283 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
284 {
285 u16 reg;
286
287 /* disable all GMAC IRQ's */
288 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
289 /* disable PHY IRQs */
290 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
291
292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
296
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
300 }
301
302 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
303 {
304 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
305 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
306
307 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
308 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
309
310 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
311 PHY_M_EC_MAC_S_MSK);
312 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
313
314 if (hw->chip_id == CHIP_ID_YUKON_EC)
315 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
316 else
317 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
318
319 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
320 }
321
322 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
323 if (hw->copper) {
324 if (hw->chip_id == CHIP_ID_YUKON_FE) {
325 /* enable automatic crossover */
326 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
327 } else {
328 /* disable energy detect */
329 ctrl &= ~PHY_M_PC_EN_DET_MSK;
330
331 /* enable automatic crossover */
332 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
333
334 if (sky2->autoneg == AUTONEG_ENABLE &&
335 hw->chip_id == CHIP_ID_YUKON_XL) {
336 ctrl &= ~PHY_M_PC_DSC_MSK;
337 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
338 }
339 }
340 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
341 } else {
342 /* workaround for deviation #4.88 (CRC errors) */
343 /* disable Automatic Crossover */
344
345 ctrl &= ~PHY_M_PC_MDIX_MSK;
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347
348 if (hw->chip_id == CHIP_ID_YUKON_XL) {
349 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl &= ~PHY_M_MAC_MD_MSK;
353 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
354 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
355
356 /* select page 1 to access Fiber registers */
357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
358 }
359 }
360
361 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
362 if (sky2->autoneg == AUTONEG_DISABLE)
363 ctrl &= ~PHY_CT_ANE;
364 else
365 ctrl |= PHY_CT_ANE;
366
367 ctrl |= PHY_CT_RESET;
368 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
369
370 ctrl = 0;
371 ct1000 = 0;
372 adv = PHY_AN_CSMA;
373
374 if (sky2->autoneg == AUTONEG_ENABLE) {
375 if (hw->copper) {
376 if (sky2->advertising & ADVERTISED_1000baseT_Full)
377 ct1000 |= PHY_M_1000C_AFD;
378 if (sky2->advertising & ADVERTISED_1000baseT_Half)
379 ct1000 |= PHY_M_1000C_AHD;
380 if (sky2->advertising & ADVERTISED_100baseT_Full)
381 adv |= PHY_M_AN_100_FD;
382 if (sky2->advertising & ADVERTISED_100baseT_Half)
383 adv |= PHY_M_AN_100_HD;
384 if (sky2->advertising & ADVERTISED_10baseT_Full)
385 adv |= PHY_M_AN_10_FD;
386 if (sky2->advertising & ADVERTISED_10baseT_Half)
387 adv |= PHY_M_AN_10_HD;
388 } else /* special defines for FIBER (88E1011S only) */
389 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
390
391 /* Set Flow-control capabilities */
392 if (sky2->tx_pause && sky2->rx_pause)
393 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
394 else if (sky2->rx_pause && !sky2->tx_pause)
395 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
396 else if (!sky2->rx_pause && sky2->tx_pause)
397 adv |= PHY_AN_PAUSE_ASYM; /* local */
398
399 /* Restart Auto-negotiation */
400 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
401 } else {
402 /* forced speed/duplex settings */
403 ct1000 = PHY_M_1000C_MSE;
404
405 if (sky2->duplex == DUPLEX_FULL)
406 ctrl |= PHY_CT_DUP_MD;
407
408 switch (sky2->speed) {
409 case SPEED_1000:
410 ctrl |= PHY_CT_SP1000;
411 break;
412 case SPEED_100:
413 ctrl |= PHY_CT_SP100;
414 break;
415 }
416
417 ctrl |= PHY_CT_RESET;
418 }
419
420 if (hw->chip_id != CHIP_ID_YUKON_FE)
421 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
422
423 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
424 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
425
426 /* Setup Phy LED's */
427 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
428 ledover = 0;
429
430 switch (hw->chip_id) {
431 case CHIP_ID_YUKON_FE:
432 /* on 88E3082 these bits are at 11..9 (shifted left) */
433 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
434
435 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
436
437 /* delete ACT LED control bits */
438 ctrl &= ~PHY_M_FELP_LED1_MSK;
439 /* change ACT LED control to blink mode */
440 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
441 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
442 break;
443
444 case CHIP_ID_YUKON_XL:
445 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
446
447 /* select page 3 to access LED control register */
448 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
449
450 /* set LED Function Control register */
451 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
452 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
453 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
454 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
455
456 /* set Polarity Control register */
457 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
458 (PHY_M_POLC_LS1_P_MIX(4) |
459 PHY_M_POLC_IS0_P_MIX(4) |
460 PHY_M_POLC_LOS_CTRL(2) |
461 PHY_M_POLC_INIT_CTRL(2) |
462 PHY_M_POLC_STA1_CTRL(2) |
463 PHY_M_POLC_STA0_CTRL(2)));
464
465 /* restore page register */
466 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
467 break;
468
469 default:
470 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
471 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
472 /* turn off the Rx LED (LED_RX) */
473 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
474 }
475
476 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
477 /* apply fixes in PHY AFE */
478 gm_phy_write(hw, port, 22, 255);
479 /* increase differential signal amplitude in 10BASE-T */
480 gm_phy_write(hw, port, 24, 0xaa99);
481 gm_phy_write(hw, port, 23, 0x2011);
482
483 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
484 gm_phy_write(hw, port, 24, 0xa204);
485 gm_phy_write(hw, port, 23, 0x2002);
486
487 /* set page register to 0 */
488 gm_phy_write(hw, port, 22, 0);
489 } else {
490 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
491
492 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
493 /* turn on 100 Mbps LED (LED_LINK100) */
494 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
495 }
496
497 if (ledover)
498 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
499
500 }
501 /* Enable phy interrupt on auto-negotiation complete (or link up) */
502 if (sky2->autoneg == AUTONEG_ENABLE)
503 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
504 else
505 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
506 }
507
508 /* Force a renegotiation */
509 static void sky2_phy_reinit(struct sky2_port *sky2)
510 {
511 down(&sky2->phy_sema);
512 sky2_phy_init(sky2->hw, sky2->port);
513 up(&sky2->phy_sema);
514 }
515
516 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
517 {
518 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
519 u16 reg;
520 int i;
521 const u8 *addr = hw->dev[port]->dev_addr;
522
523 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
524 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
525
526 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
527
528 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
529 /* WA DEV_472 -- looks like crossed wires on port 2 */
530 /* clear GMAC 1 Control reset */
531 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
532 do {
533 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
534 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
535 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
536 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
537 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
538 }
539
540 if (sky2->autoneg == AUTONEG_DISABLE) {
541 reg = gma_read16(hw, port, GM_GP_CTRL);
542 reg |= GM_GPCR_AU_ALL_DIS;
543 gma_write16(hw, port, GM_GP_CTRL, reg);
544 gma_read16(hw, port, GM_GP_CTRL);
545
546 switch (sky2->speed) {
547 case SPEED_1000:
548 reg &= ~GM_GPCR_SPEED_100;
549 reg |= GM_GPCR_SPEED_1000;
550 break;
551 case SPEED_100:
552 reg &= ~GM_GPCR_SPEED_1000;
553 reg |= GM_GPCR_SPEED_100;
554 break;
555 case SPEED_10:
556 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
557 break;
558 }
559
560 if (sky2->duplex == DUPLEX_FULL)
561 reg |= GM_GPCR_DUP_FULL;
562 } else
563 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564
565 if (!sky2->tx_pause && !sky2->rx_pause) {
566 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
567 reg |=
568 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
569 } else if (sky2->tx_pause && !sky2->rx_pause) {
570 /* disable Rx flow-control */
571 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
572 }
573
574 gma_write16(hw, port, GM_GP_CTRL, reg);
575
576 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
577
578 down(&sky2->phy_sema);
579 sky2_phy_init(hw, port);
580 up(&sky2->phy_sema);
581
582 /* MIB clear */
583 reg = gma_read16(hw, port, GM_PHY_ADDR);
584 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
585
586 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
587 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
588 gma_write16(hw, port, GM_PHY_ADDR, reg);
589
590 /* transmit control */
591 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
592
593 /* receive control reg: unicast + multicast + no FCS */
594 gma_write16(hw, port, GM_RX_CTRL,
595 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
596
597 /* transmit flow control */
598 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
599
600 /* transmit parameter */
601 gma_write16(hw, port, GM_TX_PARAM,
602 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
603 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
604 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
605 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
606
607 /* serial mode register */
608 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
609 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
610
611 if (hw->dev[port]->mtu > ETH_DATA_LEN)
612 reg |= GM_SMOD_JUMBO_ENA;
613
614 gma_write16(hw, port, GM_SERIAL_MODE, reg);
615
616 /* virtual address for data */
617 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
618
619 /* physical address: used for pause frames */
620 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
621
622 /* ignore counter overflows */
623 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
624 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
625 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
626
627 /* Configure Rx MAC FIFO */
628 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
629 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
630 GMF_RX_CTRL_DEF);
631
632 /* Flush Rx MAC FIFO on any flow control or error */
633 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
634
635 /* Set threshold to 0xa (64 bytes)
636 * ASF disabled so no need to do WA dev #4.30
637 */
638 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
639
640 /* Configure Tx MAC FIFO */
641 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
642 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
643
644 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
645 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
646 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
647 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
648 /* set Tx GMAC FIFO Almost Empty Threshold */
649 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
650 /* Disable Store & Forward mode for TX */
651 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
652 }
653 }
654
655 }
656
657 /* Assign Ram Buffer allocation.
658 * start and end are in units of 4k bytes
659 * ram registers are in units of 64bit words
660 */
661 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
662 {
663 u32 start, end;
664
665 start = startk * 4096/8;
666 end = (endk * 4096/8) - 1;
667
668 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
669 sky2_write32(hw, RB_ADDR(q, RB_START), start);
670 sky2_write32(hw, RB_ADDR(q, RB_END), end);
671 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
672 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
673
674 if (q == Q_R1 || q == Q_R2) {
675 u32 space = (endk - startk) * 4096/8;
676 u32 tp = space - space/4;
677
678 /* On receive queue's set the thresholds
679 * give receiver priority when > 3/4 full
680 * send pause when down to 2K
681 */
682 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
683 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
684
685 tp = space - 2048/8;
686 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
687 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
688 } else {
689 /* Enable store & forward on Tx queue's because
690 * Tx FIFO is only 1K on Yukon
691 */
692 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
693 }
694
695 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
696 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
697 }
698
699 /* Setup Bus Memory Interface */
700 static void sky2_qset(struct sky2_hw *hw, u16 q)
701 {
702 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
703 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
704 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
705 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
706 }
707
708 /* Setup prefetch unit registers. This is the interface between
709 * hardware and driver list elements
710 */
711 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
712 u64 addr, u32 last)
713 {
714 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
715 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
716 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
717 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
718 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
719 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
720
721 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
722 }
723
724 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
725 {
726 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
727
728 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
729 return le;
730 }
731
732 /*
733 * This is a workaround code taken from SysKonnect sk98lin driver
734 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
735 */
736 static void sky2_put_idx(struct sky2_hw *hw, unsigned q,
737 u16 idx, u16 *last, u16 size)
738 {
739 wmb();
740 if (is_ec_a1(hw) && idx < *last) {
741 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
742
743 if (hwget == 0) {
744 /* Start prefetching again */
745 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
746 goto setnew;
747 }
748
749 if (hwget == size - 1) {
750 /* set watermark to one list element */
751 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
752
753 /* set put index to first list element */
754 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
755 } else /* have hardware go to end of list */
756 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
757 size - 1);
758 } else {
759 setnew:
760 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
761 }
762 *last = idx;
763 mmiowb();
764 }
765
766
767 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
768 {
769 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
770 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
771 return le;
772 }
773
774 /* Return high part of DMA address (could be 32 or 64 bit) */
775 static inline u32 high32(dma_addr_t a)
776 {
777 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
778 }
779
780 /* Build description to hardware about buffer */
781 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
782 {
783 struct sky2_rx_le *le;
784 u32 hi = high32(map);
785 u16 len = sky2->rx_bufsize;
786
787 if (sky2->rx_addr64 != hi) {
788 le = sky2_next_rx(sky2);
789 le->addr = cpu_to_le32(hi);
790 le->ctrl = 0;
791 le->opcode = OP_ADDR64 | HW_OWNER;
792 sky2->rx_addr64 = high32(map + len);
793 }
794
795 le = sky2_next_rx(sky2);
796 le->addr = cpu_to_le32((u32) map);
797 le->length = cpu_to_le16(len);
798 le->ctrl = 0;
799 le->opcode = OP_PACKET | HW_OWNER;
800 }
801
802
803 /* Tell chip where to start receive checksum.
804 * Actually has two checksums, but set both same to avoid possible byte
805 * order problems.
806 */
807 static void rx_set_checksum(struct sky2_port *sky2)
808 {
809 struct sky2_rx_le *le;
810
811 le = sky2_next_rx(sky2);
812 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
813 le->ctrl = 0;
814 le->opcode = OP_TCPSTART | HW_OWNER;
815
816 sky2_write32(sky2->hw,
817 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
818 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
819
820 }
821
822 /*
823 * The RX Stop command will not work for Yukon-2 if the BMU does not
824 * reach the end of packet and since we can't make sure that we have
825 * incoming data, we must reset the BMU while it is not doing a DMA
826 * transfer. Since it is possible that the RX path is still active,
827 * the RX RAM buffer will be stopped first, so any possible incoming
828 * data will not trigger a DMA. After the RAM buffer is stopped, the
829 * BMU is polled until any DMA in progress is ended and only then it
830 * will be reset.
831 */
832 static void sky2_rx_stop(struct sky2_port *sky2)
833 {
834 struct sky2_hw *hw = sky2->hw;
835 unsigned rxq = rxqaddr[sky2->port];
836 int i;
837
838 /* disable the RAM Buffer receive queue */
839 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
840
841 for (i = 0; i < 0xffff; i++)
842 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
843 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
844 goto stopped;
845
846 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
847 sky2->netdev->name);
848 stopped:
849 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
850
851 /* reset the Rx prefetch unit */
852 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
853 }
854
855 /* Clean out receive buffer area, assumes receiver hardware stopped */
856 static void sky2_rx_clean(struct sky2_port *sky2)
857 {
858 unsigned i;
859
860 memset(sky2->rx_le, 0, RX_LE_BYTES);
861 for (i = 0; i < sky2->rx_pending; i++) {
862 struct ring_info *re = sky2->rx_ring + i;
863
864 if (re->skb) {
865 pci_unmap_single(sky2->hw->pdev,
866 re->mapaddr, sky2->rx_bufsize,
867 PCI_DMA_FROMDEVICE);
868 kfree_skb(re->skb);
869 re->skb = NULL;
870 }
871 }
872 }
873
874 /* Basic MII support */
875 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
876 {
877 struct mii_ioctl_data *data = if_mii(ifr);
878 struct sky2_port *sky2 = netdev_priv(dev);
879 struct sky2_hw *hw = sky2->hw;
880 int err = -EOPNOTSUPP;
881
882 if (!netif_running(dev))
883 return -ENODEV; /* Phy still in reset */
884
885 switch(cmd) {
886 case SIOCGMIIPHY:
887 data->phy_id = PHY_ADDR_MARV;
888
889 /* fallthru */
890 case SIOCGMIIREG: {
891 u16 val = 0;
892
893 down(&sky2->phy_sema);
894 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
895 up(&sky2->phy_sema);
896
897 data->val_out = val;
898 break;
899 }
900
901 case SIOCSMIIREG:
902 if (!capable(CAP_NET_ADMIN))
903 return -EPERM;
904
905 down(&sky2->phy_sema);
906 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
907 data->val_in);
908 up(&sky2->phy_sema);
909 break;
910 }
911 return err;
912 }
913
914 #ifdef SKY2_VLAN_TAG_USED
915 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
916 {
917 struct sky2_port *sky2 = netdev_priv(dev);
918 struct sky2_hw *hw = sky2->hw;
919 u16 port = sky2->port;
920
921 spin_lock_bh(&sky2->tx_lock);
922
923 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
924 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
925 sky2->vlgrp = grp;
926
927 spin_unlock_bh(&sky2->tx_lock);
928 }
929
930 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
931 {
932 struct sky2_port *sky2 = netdev_priv(dev);
933 struct sky2_hw *hw = sky2->hw;
934 u16 port = sky2->port;
935
936 spin_lock_bh(&sky2->tx_lock);
937
938 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
939 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
940 if (sky2->vlgrp)
941 sky2->vlgrp->vlan_devices[vid] = NULL;
942
943 spin_unlock_bh(&sky2->tx_lock);
944 }
945 #endif
946
947 /*
948 * It appears the hardware has a bug in the FIFO logic that
949 * cause it to hang if the FIFO gets overrun and the receive buffer
950 * is not aligned. ALso alloc_skb() won't align properly if slab
951 * debugging is enabled.
952 */
953 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
954 {
955 struct sk_buff *skb;
956
957 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
958 if (likely(skb)) {
959 unsigned long p = (unsigned long) skb->data;
960 skb_reserve(skb,
961 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
962 }
963
964 return skb;
965 }
966
967 /*
968 * Allocate and setup receiver buffer pool.
969 * In case of 64 bit dma, there are 2X as many list elements
970 * available as ring entries
971 * and need to reserve one list element so we don't wrap around.
972 */
973 static int sky2_rx_start(struct sky2_port *sky2)
974 {
975 struct sky2_hw *hw = sky2->hw;
976 unsigned rxq = rxqaddr[sky2->port];
977 int i;
978
979 sky2->rx_put = sky2->rx_next = 0;
980 sky2_qset(hw, rxq);
981
982 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
983 /* MAC Rx RAM Read is controlled by hardware */
984 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
985 }
986
987 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
988
989 rx_set_checksum(sky2);
990 for (i = 0; i < sky2->rx_pending; i++) {
991 struct ring_info *re = sky2->rx_ring + i;
992
993 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
994 if (!re->skb)
995 goto nomem;
996
997 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
998 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
999 sky2_rx_add(sky2, re->mapaddr);
1000 }
1001
1002 /* Tell chip about available buffers */
1003 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1004 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
1005 return 0;
1006 nomem:
1007 sky2_rx_clean(sky2);
1008 return -ENOMEM;
1009 }
1010
1011 /* Bring up network interface. */
1012 static int sky2_up(struct net_device *dev)
1013 {
1014 struct sky2_port *sky2 = netdev_priv(dev);
1015 struct sky2_hw *hw = sky2->hw;
1016 unsigned port = sky2->port;
1017 u32 ramsize, rxspace;
1018 int err = -ENOMEM;
1019
1020 if (netif_msg_ifup(sky2))
1021 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1022
1023 /* must be power of 2 */
1024 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1025 TX_RING_SIZE *
1026 sizeof(struct sky2_tx_le),
1027 &sky2->tx_le_map);
1028 if (!sky2->tx_le)
1029 goto err_out;
1030
1031 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1032 GFP_KERNEL);
1033 if (!sky2->tx_ring)
1034 goto err_out;
1035 sky2->tx_prod = sky2->tx_cons = 0;
1036
1037 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1038 &sky2->rx_le_map);
1039 if (!sky2->rx_le)
1040 goto err_out;
1041 memset(sky2->rx_le, 0, RX_LE_BYTES);
1042
1043 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1044 GFP_KERNEL);
1045 if (!sky2->rx_ring)
1046 goto err_out;
1047
1048 sky2_mac_init(hw, port);
1049
1050 /* Determine available ram buffer space (in 4K blocks).
1051 * Note: not sure about the FE setting below yet
1052 */
1053 if (hw->chip_id == CHIP_ID_YUKON_FE)
1054 ramsize = 4;
1055 else
1056 ramsize = sky2_read8(hw, B2_E_0);
1057
1058 /* Give transmitter one third (rounded up) */
1059 rxspace = ramsize - (ramsize + 2) / 3;
1060
1061 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1062 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1063
1064 /* Make sure SyncQ is disabled */
1065 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1066 RB_RST_SET);
1067
1068 sky2_qset(hw, txqaddr[port]);
1069
1070 /* Set almost empty threshold */
1071 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1072 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1073
1074 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1075 TX_RING_SIZE - 1);
1076
1077 err = sky2_rx_start(sky2);
1078 if (err)
1079 goto err_out;
1080
1081 /* Enable interrupts from phy/mac for port */
1082 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1083 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1084 return 0;
1085
1086 err_out:
1087 if (sky2->rx_le) {
1088 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1089 sky2->rx_le, sky2->rx_le_map);
1090 sky2->rx_le = NULL;
1091 }
1092 if (sky2->tx_le) {
1093 pci_free_consistent(hw->pdev,
1094 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1095 sky2->tx_le, sky2->tx_le_map);
1096 sky2->tx_le = NULL;
1097 }
1098 kfree(sky2->tx_ring);
1099 kfree(sky2->rx_ring);
1100
1101 sky2->tx_ring = NULL;
1102 sky2->rx_ring = NULL;
1103 return err;
1104 }
1105
1106 /* Modular subtraction in ring */
1107 static inline int tx_dist(unsigned tail, unsigned head)
1108 {
1109 return (head - tail) % TX_RING_SIZE;
1110 }
1111
1112 /* Number of list elements available for next tx */
1113 static inline int tx_avail(const struct sky2_port *sky2)
1114 {
1115 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1116 }
1117
1118 /* Estimate of number of transmit list elements required */
1119 static unsigned tx_le_req(const struct sk_buff *skb)
1120 {
1121 unsigned count;
1122
1123 count = sizeof(dma_addr_t) / sizeof(u32);
1124 count += skb_shinfo(skb)->nr_frags * count;
1125
1126 if (skb_shinfo(skb)->tso_size)
1127 ++count;
1128
1129 if (skb->ip_summed == CHECKSUM_HW)
1130 ++count;
1131
1132 return count;
1133 }
1134
1135 /*
1136 * Put one packet in ring for transmit.
1137 * A single packet can generate multiple list elements, and
1138 * the number of ring elements will probably be less than the number
1139 * of list elements used.
1140 *
1141 * No BH disabling for tx_lock here (like tg3)
1142 */
1143 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1144 {
1145 struct sky2_port *sky2 = netdev_priv(dev);
1146 struct sky2_hw *hw = sky2->hw;
1147 struct sky2_tx_le *le = NULL;
1148 struct tx_ring_info *re;
1149 unsigned i, len;
1150 dma_addr_t mapping;
1151 u32 addr64;
1152 u16 mss;
1153 u8 ctrl;
1154
1155 /* No BH disabling for tx_lock here. We are running in BH disabled
1156 * context and TX reclaim runs via poll inside of a software
1157 * interrupt, and no related locks in IRQ processing.
1158 */
1159 if (!spin_trylock(&sky2->tx_lock))
1160 return NETDEV_TX_LOCKED;
1161
1162 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1163 /* There is a known but harmless race with lockless tx
1164 * and netif_stop_queue.
1165 */
1166 if (!netif_queue_stopped(dev)) {
1167 netif_stop_queue(dev);
1168 if (net_ratelimit())
1169 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1170 dev->name);
1171 }
1172 spin_unlock(&sky2->tx_lock);
1173
1174 return NETDEV_TX_BUSY;
1175 }
1176
1177 if (unlikely(netif_msg_tx_queued(sky2)))
1178 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1179 dev->name, sky2->tx_prod, skb->len);
1180
1181 len = skb_headlen(skb);
1182 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1183 addr64 = high32(mapping);
1184
1185 re = sky2->tx_ring + sky2->tx_prod;
1186
1187 /* Send high bits if changed or crosses boundary */
1188 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1189 le = get_tx_le(sky2);
1190 le->tx.addr = cpu_to_le32(addr64);
1191 le->ctrl = 0;
1192 le->opcode = OP_ADDR64 | HW_OWNER;
1193 sky2->tx_addr64 = high32(mapping + len);
1194 }
1195
1196 /* Check for TCP Segmentation Offload */
1197 mss = skb_shinfo(skb)->tso_size;
1198 if (mss != 0) {
1199 /* just drop the packet if non-linear expansion fails */
1200 if (skb_header_cloned(skb) &&
1201 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1202 dev_kfree_skb_any(skb);
1203 goto out_unlock;
1204 }
1205
1206 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1207 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1208 mss += ETH_HLEN;
1209 }
1210
1211 if (mss != sky2->tx_last_mss) {
1212 le = get_tx_le(sky2);
1213 le->tx.tso.size = cpu_to_le16(mss);
1214 le->tx.tso.rsvd = 0;
1215 le->opcode = OP_LRGLEN | HW_OWNER;
1216 le->ctrl = 0;
1217 sky2->tx_last_mss = mss;
1218 }
1219
1220 ctrl = 0;
1221 #ifdef SKY2_VLAN_TAG_USED
1222 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1223 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1224 if (!le) {
1225 le = get_tx_le(sky2);
1226 le->tx.addr = 0;
1227 le->opcode = OP_VLAN|HW_OWNER;
1228 le->ctrl = 0;
1229 } else
1230 le->opcode |= OP_VLAN;
1231 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1232 ctrl |= INS_VLAN;
1233 }
1234 #endif
1235
1236 /* Handle TCP checksum offload */
1237 if (skb->ip_summed == CHECKSUM_HW) {
1238 u16 hdr = skb->h.raw - skb->data;
1239 u16 offset = hdr + skb->csum;
1240
1241 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1242 if (skb->nh.iph->protocol == IPPROTO_UDP)
1243 ctrl |= UDPTCP;
1244
1245 le = get_tx_le(sky2);
1246 le->tx.csum.start = cpu_to_le16(hdr);
1247 le->tx.csum.offset = cpu_to_le16(offset);
1248 le->length = 0; /* initial checksum value */
1249 le->ctrl = 1; /* one packet */
1250 le->opcode = OP_TCPLISW | HW_OWNER;
1251 }
1252
1253 le = get_tx_le(sky2);
1254 le->tx.addr = cpu_to_le32((u32) mapping);
1255 le->length = cpu_to_le16(len);
1256 le->ctrl = ctrl;
1257 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1258
1259 /* Record the transmit mapping info */
1260 re->skb = skb;
1261 pci_unmap_addr_set(re, mapaddr, mapping);
1262
1263 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1264 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1265 struct tx_ring_info *fre;
1266
1267 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1268 frag->size, PCI_DMA_TODEVICE);
1269 addr64 = high32(mapping);
1270 if (addr64 != sky2->tx_addr64) {
1271 le = get_tx_le(sky2);
1272 le->tx.addr = cpu_to_le32(addr64);
1273 le->ctrl = 0;
1274 le->opcode = OP_ADDR64 | HW_OWNER;
1275 sky2->tx_addr64 = addr64;
1276 }
1277
1278 le = get_tx_le(sky2);
1279 le->tx.addr = cpu_to_le32((u32) mapping);
1280 le->length = cpu_to_le16(frag->size);
1281 le->ctrl = ctrl;
1282 le->opcode = OP_BUFFER | HW_OWNER;
1283
1284 fre = sky2->tx_ring
1285 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1286 pci_unmap_addr_set(fre, mapaddr, mapping);
1287 }
1288
1289 re->idx = sky2->tx_prod;
1290 le->ctrl |= EOP;
1291
1292 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1293 &sky2->tx_last_put, TX_RING_SIZE);
1294
1295 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1296 netif_stop_queue(dev);
1297
1298 out_unlock:
1299 spin_unlock(&sky2->tx_lock);
1300
1301 dev->trans_start = jiffies;
1302 return NETDEV_TX_OK;
1303 }
1304
1305 /*
1306 * Free ring elements from starting at tx_cons until "done"
1307 *
1308 * NB: the hardware will tell us about partial completion of multi-part
1309 * buffers; these are deferred until completion.
1310 */
1311 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1312 {
1313 struct net_device *dev = sky2->netdev;
1314 struct pci_dev *pdev = sky2->hw->pdev;
1315 u16 nxt, put;
1316 unsigned i;
1317
1318 BUG_ON(done >= TX_RING_SIZE);
1319
1320 if (unlikely(netif_msg_tx_done(sky2)))
1321 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1322 dev->name, done);
1323
1324 for (put = sky2->tx_cons; put != done; put = nxt) {
1325 struct tx_ring_info *re = sky2->tx_ring + put;
1326 struct sk_buff *skb = re->skb;
1327
1328 nxt = re->idx;
1329 BUG_ON(nxt >= TX_RING_SIZE);
1330 prefetch(sky2->tx_ring + nxt);
1331
1332 /* Check for partial status */
1333 if (tx_dist(put, done) < tx_dist(put, nxt))
1334 break;
1335
1336 skb = re->skb;
1337 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1338 skb_headlen(skb), PCI_DMA_TODEVICE);
1339
1340 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1341 struct tx_ring_info *fre;
1342 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1343 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1344 skb_shinfo(skb)->frags[i].size,
1345 PCI_DMA_TODEVICE);
1346 }
1347
1348 dev_kfree_skb_any(skb);
1349 }
1350
1351 sky2->tx_cons = put;
1352 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1353 netif_wake_queue(dev);
1354 }
1355
1356 /* Cleanup all untransmitted buffers, assume transmitter not running */
1357 static void sky2_tx_clean(struct sky2_port *sky2)
1358 {
1359 spin_lock_bh(&sky2->tx_lock);
1360 sky2_tx_complete(sky2, sky2->tx_prod);
1361 spin_unlock_bh(&sky2->tx_lock);
1362 }
1363
1364 /* Network shutdown */
1365 static int sky2_down(struct net_device *dev)
1366 {
1367 struct sky2_port *sky2 = netdev_priv(dev);
1368 struct sky2_hw *hw = sky2->hw;
1369 unsigned port = sky2->port;
1370 u16 ctrl;
1371
1372 /* Never really got started! */
1373 if (!sky2->tx_le)
1374 return 0;
1375
1376 if (netif_msg_ifdown(sky2))
1377 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1378
1379 /* Stop more packets from being queued */
1380 netif_stop_queue(dev);
1381
1382 /* Disable port IRQ */
1383 local_irq_disable();
1384 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1385 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1386 local_irq_enable();
1387
1388 flush_scheduled_work();
1389
1390 sky2_phy_reset(hw, port);
1391
1392 /* Stop transmitter */
1393 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1394 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1395
1396 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1397 RB_RST_SET | RB_DIS_OP_MD);
1398
1399 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1400 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1401 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1402
1403 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1404
1405 /* Workaround shared GMAC reset */
1406 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1407 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1408 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1409
1410 /* Disable Force Sync bit and Enable Alloc bit */
1411 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1412 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1413
1414 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1415 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1416 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1417
1418 /* Reset the PCI FIFO of the async Tx queue */
1419 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1420 BMU_RST_SET | BMU_FIFO_RST);
1421
1422 /* Reset the Tx prefetch units */
1423 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1424 PREF_UNIT_RST_SET);
1425
1426 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1427
1428 sky2_rx_stop(sky2);
1429
1430 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1431 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1432
1433 /* turn off LED's */
1434 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1435
1436 synchronize_irq(hw->pdev->irq);
1437
1438 sky2_tx_clean(sky2);
1439 sky2_rx_clean(sky2);
1440
1441 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1442 sky2->rx_le, sky2->rx_le_map);
1443 kfree(sky2->rx_ring);
1444
1445 pci_free_consistent(hw->pdev,
1446 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1447 sky2->tx_le, sky2->tx_le_map);
1448 kfree(sky2->tx_ring);
1449
1450 sky2->tx_le = NULL;
1451 sky2->rx_le = NULL;
1452
1453 sky2->rx_ring = NULL;
1454 sky2->tx_ring = NULL;
1455
1456 return 0;
1457 }
1458
1459 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1460 {
1461 if (!hw->copper)
1462 return SPEED_1000;
1463
1464 if (hw->chip_id == CHIP_ID_YUKON_FE)
1465 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1466
1467 switch (aux & PHY_M_PS_SPEED_MSK) {
1468 case PHY_M_PS_SPEED_1000:
1469 return SPEED_1000;
1470 case PHY_M_PS_SPEED_100:
1471 return SPEED_100;
1472 default:
1473 return SPEED_10;
1474 }
1475 }
1476
1477 static void sky2_link_up(struct sky2_port *sky2)
1478 {
1479 struct sky2_hw *hw = sky2->hw;
1480 unsigned port = sky2->port;
1481 u16 reg;
1482
1483 /* Enable Transmit FIFO Underrun */
1484 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1485
1486 reg = gma_read16(hw, port, GM_GP_CTRL);
1487 if (sky2->autoneg == AUTONEG_DISABLE) {
1488 reg |= GM_GPCR_AU_ALL_DIS;
1489
1490 /* Is write/read necessary? Copied from sky2_mac_init */
1491 gma_write16(hw, port, GM_GP_CTRL, reg);
1492 gma_read16(hw, port, GM_GP_CTRL);
1493
1494 switch (sky2->speed) {
1495 case SPEED_1000:
1496 reg &= ~GM_GPCR_SPEED_100;
1497 reg |= GM_GPCR_SPEED_1000;
1498 break;
1499 case SPEED_100:
1500 reg &= ~GM_GPCR_SPEED_1000;
1501 reg |= GM_GPCR_SPEED_100;
1502 break;
1503 case SPEED_10:
1504 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1505 break;
1506 }
1507 } else
1508 reg &= ~GM_GPCR_AU_ALL_DIS;
1509
1510 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1511 reg |= GM_GPCR_DUP_FULL;
1512
1513 /* enable Rx/Tx */
1514 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1515 gma_write16(hw, port, GM_GP_CTRL, reg);
1516 gma_read16(hw, port, GM_GP_CTRL);
1517
1518 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1519
1520 netif_carrier_on(sky2->netdev);
1521 netif_wake_queue(sky2->netdev);
1522
1523 /* Turn on link LED */
1524 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1525 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1526
1527 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1528 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1529
1530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1531 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1532 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1533 SPEED_10 ? 7 : 0) |
1534 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1535 SPEED_100 ? 7 : 0) |
1536 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1537 SPEED_1000 ? 7 : 0));
1538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1539 }
1540
1541 if (netif_msg_link(sky2))
1542 printk(KERN_INFO PFX
1543 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1544 sky2->netdev->name, sky2->speed,
1545 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1546 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1547 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1548 }
1549
1550 static void sky2_link_down(struct sky2_port *sky2)
1551 {
1552 struct sky2_hw *hw = sky2->hw;
1553 unsigned port = sky2->port;
1554 u16 reg;
1555
1556 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1557
1558 reg = gma_read16(hw, port, GM_GP_CTRL);
1559 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1560 gma_write16(hw, port, GM_GP_CTRL, reg);
1561 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1562
1563 if (sky2->rx_pause && !sky2->tx_pause) {
1564 /* restore Asymmetric Pause bit */
1565 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1566 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1567 | PHY_M_AN_ASP);
1568 }
1569
1570 netif_carrier_off(sky2->netdev);
1571 netif_stop_queue(sky2->netdev);
1572
1573 /* Turn on link LED */
1574 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1575
1576 if (netif_msg_link(sky2))
1577 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1578 sky2_phy_init(hw, port);
1579 }
1580
1581 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1582 {
1583 struct sky2_hw *hw = sky2->hw;
1584 unsigned port = sky2->port;
1585 u16 lpa;
1586
1587 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1588
1589 if (lpa & PHY_M_AN_RF) {
1590 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1591 return -1;
1592 }
1593
1594 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1595 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1596 printk(KERN_ERR PFX "%s: master/slave fault",
1597 sky2->netdev->name);
1598 return -1;
1599 }
1600
1601 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1602 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1603 sky2->netdev->name);
1604 return -1;
1605 }
1606
1607 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1608
1609 sky2->speed = sky2_phy_speed(hw, aux);
1610
1611 /* Pause bits are offset (9..8) */
1612 if (hw->chip_id == CHIP_ID_YUKON_XL)
1613 aux >>= 6;
1614
1615 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1616 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1617
1618 if ((sky2->tx_pause || sky2->rx_pause)
1619 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1620 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1621 else
1622 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1623
1624 return 0;
1625 }
1626
1627 /*
1628 * Interrupt from PHY are handled outside of interrupt context
1629 * because accessing phy registers requires spin wait which might
1630 * cause excess interrupt latency.
1631 */
1632 static void sky2_phy_task(void *arg)
1633 {
1634 struct sky2_port *sky2 = arg;
1635 struct sky2_hw *hw = sky2->hw;
1636 u16 istatus, phystat;
1637
1638 down(&sky2->phy_sema);
1639 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1640 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1641
1642 if (netif_msg_intr(sky2))
1643 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1644 sky2->netdev->name, istatus, phystat);
1645
1646 if (istatus & PHY_M_IS_AN_COMPL) {
1647 if (sky2_autoneg_done(sky2, phystat) == 0)
1648 sky2_link_up(sky2);
1649 goto out;
1650 }
1651
1652 if (istatus & PHY_M_IS_LSP_CHANGE)
1653 sky2->speed = sky2_phy_speed(hw, phystat);
1654
1655 if (istatus & PHY_M_IS_DUP_CHANGE)
1656 sky2->duplex =
1657 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1658
1659 if (istatus & PHY_M_IS_LST_CHANGE) {
1660 if (phystat & PHY_M_PS_LINK_UP)
1661 sky2_link_up(sky2);
1662 else
1663 sky2_link_down(sky2);
1664 }
1665 out:
1666 up(&sky2->phy_sema);
1667
1668 local_irq_disable();
1669 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1670 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1671 local_irq_enable();
1672 }
1673
1674
1675 /* Transmit timeout is only called if we are running, carries is up
1676 * and tx queue is full (stopped).
1677 */
1678 static void sky2_tx_timeout(struct net_device *dev)
1679 {
1680 struct sky2_port *sky2 = netdev_priv(dev);
1681 struct sky2_hw *hw = sky2->hw;
1682 unsigned txq = txqaddr[sky2->port];
1683 u16 ridx;
1684
1685 /* Maybe we just missed an status interrupt */
1686 spin_lock(&sky2->tx_lock);
1687 ridx = sky2_read16(hw,
1688 sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1689 sky2_tx_complete(sky2, ridx);
1690 spin_unlock(&sky2->tx_lock);
1691
1692 if (!netif_queue_stopped(dev)) {
1693 if (net_ratelimit())
1694 pr_info(PFX "transmit interrupt missed? recovered\n");
1695 return;
1696 }
1697
1698 if (netif_msg_timer(sky2))
1699 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1700
1701 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1702 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1703
1704 sky2_tx_clean(sky2);
1705
1706 sky2_qset(hw, txq);
1707 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1708 }
1709
1710
1711 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1712 /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1713 static inline unsigned sky2_buf_size(int mtu)
1714 {
1715 return roundup(mtu + ETH_HLEN + 4, 8);
1716 }
1717
1718 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1719 {
1720 struct sky2_port *sky2 = netdev_priv(dev);
1721 struct sky2_hw *hw = sky2->hw;
1722 int err;
1723 u16 ctl, mode;
1724
1725 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1726 return -EINVAL;
1727
1728 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1729 return -EINVAL;
1730
1731 if (!netif_running(dev)) {
1732 dev->mtu = new_mtu;
1733 return 0;
1734 }
1735
1736 sky2_write32(hw, B0_IMSK, 0);
1737
1738 dev->trans_start = jiffies; /* prevent tx timeout */
1739 netif_stop_queue(dev);
1740 netif_poll_disable(hw->dev[0]);
1741
1742 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1743 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1744 sky2_rx_stop(sky2);
1745 sky2_rx_clean(sky2);
1746
1747 dev->mtu = new_mtu;
1748 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1749 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1750 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1751
1752 if (dev->mtu > ETH_DATA_LEN)
1753 mode |= GM_SMOD_JUMBO_ENA;
1754
1755 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1756
1757 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1758
1759 err = sky2_rx_start(sky2);
1760 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1761
1762 if (err)
1763 dev_close(dev);
1764 else {
1765 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1766
1767 netif_poll_enable(hw->dev[0]);
1768 netif_wake_queue(dev);
1769 }
1770
1771 return err;
1772 }
1773
1774 /*
1775 * Receive one packet.
1776 * For small packets or errors, just reuse existing skb.
1777 * For larger packets, get new buffer.
1778 */
1779 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1780 u16 length, u32 status)
1781 {
1782 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1783 struct sk_buff *skb = NULL;
1784
1785 if (unlikely(netif_msg_rx_status(sky2)))
1786 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1787 sky2->netdev->name, sky2->rx_next, status, length);
1788
1789 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1790 prefetch(sky2->rx_ring + sky2->rx_next);
1791
1792 if (status & GMR_FS_ANY_ERR)
1793 goto error;
1794
1795 if (!(status & GMR_FS_RX_OK))
1796 goto resubmit;
1797
1798 if ((status >> 16) != length || length > sky2->rx_bufsize)
1799 goto oversize;
1800
1801 if (length < copybreak) {
1802 skb = alloc_skb(length + 2, GFP_ATOMIC);
1803 if (!skb)
1804 goto resubmit;
1805
1806 skb_reserve(skb, 2);
1807 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1808 length, PCI_DMA_FROMDEVICE);
1809 memcpy(skb->data, re->skb->data, length);
1810 skb->ip_summed = re->skb->ip_summed;
1811 skb->csum = re->skb->csum;
1812 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1813 length, PCI_DMA_FROMDEVICE);
1814 } else {
1815 struct sk_buff *nskb;
1816
1817 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1818 if (!nskb)
1819 goto resubmit;
1820
1821 skb = re->skb;
1822 re->skb = nskb;
1823 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1824 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1825 prefetch(skb->data);
1826
1827 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1828 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1829 }
1830
1831 skb_put(skb, length);
1832 resubmit:
1833 re->skb->ip_summed = CHECKSUM_NONE;
1834 sky2_rx_add(sky2, re->mapaddr);
1835
1836 /* Tell receiver about new buffers. */
1837 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1838 &sky2->rx_last_put, RX_LE_SIZE);
1839
1840 return skb;
1841
1842 oversize:
1843 ++sky2->net_stats.rx_over_errors;
1844 goto resubmit;
1845
1846 error:
1847 ++sky2->net_stats.rx_errors;
1848
1849 if (netif_msg_rx_err(sky2) && net_ratelimit())
1850 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1851 sky2->netdev->name, status, length);
1852
1853 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1854 sky2->net_stats.rx_length_errors++;
1855 if (status & GMR_FS_FRAGMENT)
1856 sky2->net_stats.rx_frame_errors++;
1857 if (status & GMR_FS_CRC_ERR)
1858 sky2->net_stats.rx_crc_errors++;
1859 if (status & GMR_FS_RX_FF_OV)
1860 sky2->net_stats.rx_fifo_errors++;
1861
1862 goto resubmit;
1863 }
1864
1865 /*
1866 * Check for transmit complete
1867 */
1868 #define TX_NO_STATUS 0xffff
1869
1870 static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1871 {
1872 if (last != TX_NO_STATUS) {
1873 struct net_device *dev = hw->dev[port];
1874 if (dev && netif_running(dev)) {
1875 struct sky2_port *sky2 = netdev_priv(dev);
1876
1877 spin_lock(&sky2->tx_lock);
1878 sky2_tx_complete(sky2, last);
1879 spin_unlock(&sky2->tx_lock);
1880 }
1881 }
1882 }
1883
1884 /*
1885 * Both ports share the same status interrupt, therefore there is only
1886 * one poll routine.
1887 */
1888 static int sky2_poll(struct net_device *dev0, int *budget)
1889 {
1890 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1891 unsigned int to_do = min(dev0->quota, *budget);
1892 unsigned int work_done = 0;
1893 u16 hwidx;
1894 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1895
1896 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1897
1898 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1899 BUG_ON(hwidx >= STATUS_RING_SIZE);
1900 rmb();
1901
1902 while (hwidx != hw->st_idx) {
1903 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1904 struct net_device *dev;
1905 struct sky2_port *sky2;
1906 struct sk_buff *skb;
1907 u32 status;
1908 u16 length;
1909
1910 le = hw->st_le + hw->st_idx;
1911 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1912 prefetch(hw->st_le + hw->st_idx);
1913
1914 BUG_ON(le->link >= 2);
1915 dev = hw->dev[le->link];
1916 if (dev == NULL || !netif_running(dev))
1917 continue;
1918
1919 sky2 = netdev_priv(dev);
1920 status = le32_to_cpu(le->status);
1921 length = le16_to_cpu(le->length);
1922
1923 switch (le->opcode & ~HW_OWNER) {
1924 case OP_RXSTAT:
1925 skb = sky2_receive(sky2, length, status);
1926 if (!skb)
1927 break;
1928
1929 skb->dev = dev;
1930 skb->protocol = eth_type_trans(skb, dev);
1931 dev->last_rx = jiffies;
1932
1933 #ifdef SKY2_VLAN_TAG_USED
1934 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1935 vlan_hwaccel_receive_skb(skb,
1936 sky2->vlgrp,
1937 be16_to_cpu(sky2->rx_tag));
1938 } else
1939 #endif
1940 netif_receive_skb(skb);
1941
1942 if (++work_done >= to_do)
1943 goto exit_loop;
1944 break;
1945
1946 #ifdef SKY2_VLAN_TAG_USED
1947 case OP_RXVLAN:
1948 sky2->rx_tag = length;
1949 break;
1950
1951 case OP_RXCHKSVLAN:
1952 sky2->rx_tag = length;
1953 /* fall through */
1954 #endif
1955 case OP_RXCHKS:
1956 skb = sky2->rx_ring[sky2->rx_next].skb;
1957 skb->ip_summed = CHECKSUM_HW;
1958 skb->csum = le16_to_cpu(status);
1959 break;
1960
1961 case OP_TXINDEXLE:
1962 /* TX index reports status for both ports */
1963 tx_done[0] = status & 0xffff;
1964 tx_done[1] = ((status >> 24) & 0xff)
1965 | (u16)(length & 0xf) << 8;
1966 break;
1967
1968 default:
1969 if (net_ratelimit())
1970 printk(KERN_WARNING PFX
1971 "unknown status opcode 0x%x\n", le->opcode);
1972 break;
1973 }
1974 }
1975
1976 exit_loop:
1977 sky2_tx_check(hw, 0, tx_done[0]);
1978 sky2_tx_check(hw, 1, tx_done[1]);
1979
1980 if (likely(work_done < to_do)) {
1981 /* need to restart TX timer */
1982 if (is_ec_a1(hw)) {
1983 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1984 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1985 }
1986
1987 netif_rx_complete(dev0);
1988 hw->intr_mask |= Y2_IS_STAT_BMU;
1989 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1990 return 0;
1991 } else {
1992 *budget -= work_done;
1993 dev0->quota -= work_done;
1994 return 1;
1995 }
1996 }
1997
1998 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1999 {
2000 struct net_device *dev = hw->dev[port];
2001
2002 if (net_ratelimit())
2003 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2004 dev->name, status);
2005
2006 if (status & Y2_IS_PAR_RD1) {
2007 if (net_ratelimit())
2008 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2009 dev->name);
2010 /* Clear IRQ */
2011 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2012 }
2013
2014 if (status & Y2_IS_PAR_WR1) {
2015 if (net_ratelimit())
2016 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2017 dev->name);
2018
2019 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2020 }
2021
2022 if (status & Y2_IS_PAR_MAC1) {
2023 if (net_ratelimit())
2024 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2025 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2026 }
2027
2028 if (status & Y2_IS_PAR_RX1) {
2029 if (net_ratelimit())
2030 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2031 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2032 }
2033
2034 if (status & Y2_IS_TCP_TXA1) {
2035 if (net_ratelimit())
2036 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2037 dev->name);
2038 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2039 }
2040 }
2041
2042 static void sky2_hw_intr(struct sky2_hw *hw)
2043 {
2044 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2045
2046 if (status & Y2_IS_TIST_OV)
2047 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2048
2049 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2050 u16 pci_err;
2051
2052 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
2053 if (net_ratelimit())
2054 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2055 pci_name(hw->pdev), pci_err);
2056
2057 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2058 pci_write_config_word(hw->pdev, PCI_STATUS,
2059 pci_err | PCI_STATUS_ERROR_BITS);
2060 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2061 }
2062
2063 if (status & Y2_IS_PCI_EXP) {
2064 /* PCI-Express uncorrectable Error occurred */
2065 u32 pex_err;
2066
2067 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
2068
2069 if (net_ratelimit())
2070 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2071 pci_name(hw->pdev), pex_err);
2072
2073 /* clear the interrupt */
2074 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2075 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2076 0xffffffffUL);
2077 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2078
2079 if (pex_err & PEX_FATAL_ERRORS) {
2080 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2081 hwmsk &= ~Y2_IS_PCI_EXP;
2082 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2083 }
2084 }
2085
2086 if (status & Y2_HWE_L1_MASK)
2087 sky2_hw_error(hw, 0, status);
2088 status >>= 8;
2089 if (status & Y2_HWE_L1_MASK)
2090 sky2_hw_error(hw, 1, status);
2091 }
2092
2093 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2094 {
2095 struct net_device *dev = hw->dev[port];
2096 struct sky2_port *sky2 = netdev_priv(dev);
2097 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2098
2099 if (netif_msg_intr(sky2))
2100 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2101 dev->name, status);
2102
2103 if (status & GM_IS_RX_FF_OR) {
2104 ++sky2->net_stats.rx_fifo_errors;
2105 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2106 }
2107
2108 if (status & GM_IS_TX_FF_UR) {
2109 ++sky2->net_stats.tx_fifo_errors;
2110 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2111 }
2112 }
2113
2114 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2115 {
2116 struct net_device *dev = hw->dev[port];
2117 struct sky2_port *sky2 = netdev_priv(dev);
2118
2119 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2120 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2121 schedule_work(&sky2->phy_task);
2122 }
2123
2124 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2125 {
2126 struct sky2_hw *hw = dev_id;
2127 struct net_device *dev0 = hw->dev[0];
2128 u32 status;
2129
2130 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2131 if (status == 0 || status == ~0)
2132 return IRQ_NONE;
2133
2134 if (status & Y2_IS_HW_ERR)
2135 sky2_hw_intr(hw);
2136
2137 /* Do NAPI for Rx and Tx status */
2138 if (status & Y2_IS_STAT_BMU) {
2139 hw->intr_mask &= ~Y2_IS_STAT_BMU;
2140 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2141
2142 if (likely(__netif_rx_schedule_prep(dev0))) {
2143 prefetch(&hw->st_le[hw->st_idx]);
2144 __netif_rx_schedule(dev0);
2145 }
2146 }
2147
2148 if (status & Y2_IS_IRQ_PHY1)
2149 sky2_phy_intr(hw, 0);
2150
2151 if (status & Y2_IS_IRQ_PHY2)
2152 sky2_phy_intr(hw, 1);
2153
2154 if (status & Y2_IS_IRQ_MAC1)
2155 sky2_mac_intr(hw, 0);
2156
2157 if (status & Y2_IS_IRQ_MAC2)
2158 sky2_mac_intr(hw, 1);
2159
2160 sky2_write32(hw, B0_Y2_SP_ICR, 2);
2161
2162 sky2_read32(hw, B0_IMSK);
2163
2164 return IRQ_HANDLED;
2165 }
2166
2167 #ifdef CONFIG_NET_POLL_CONTROLLER
2168 static void sky2_netpoll(struct net_device *dev)
2169 {
2170 struct sky2_port *sky2 = netdev_priv(dev);
2171
2172 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2173 }
2174 #endif
2175
2176 /* Chip internal frequency for clock calculations */
2177 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2178 {
2179 switch (hw->chip_id) {
2180 case CHIP_ID_YUKON_EC:
2181 case CHIP_ID_YUKON_EC_U:
2182 return 125; /* 125 Mhz */
2183 case CHIP_ID_YUKON_FE:
2184 return 100; /* 100 Mhz */
2185 default: /* YUKON_XL */
2186 return 156; /* 156 Mhz */
2187 }
2188 }
2189
2190 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2191 {
2192 return sky2_mhz(hw) * us;
2193 }
2194
2195 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2196 {
2197 return clk / sky2_mhz(hw);
2198 }
2199
2200
2201 static int sky2_reset(struct sky2_hw *hw)
2202 {
2203 u16 status;
2204 u8 t8, pmd_type;
2205 int i, err;
2206
2207 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2208
2209 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2210 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2211 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2212 pci_name(hw->pdev), hw->chip_id);
2213 return -EOPNOTSUPP;
2214 }
2215
2216 /* disable ASF */
2217 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2218 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2219 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2220 }
2221
2222 /* do a SW reset */
2223 sky2_write8(hw, B0_CTST, CS_RST_SET);
2224 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2225
2226 /* clear PCI errors, if any */
2227 err = pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2228 if (err)
2229 goto pci_err;
2230
2231 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2232 err = pci_write_config_word(hw->pdev, PCI_STATUS,
2233 status | PCI_STATUS_ERROR_BITS);
2234 if (err)
2235 goto pci_err;
2236
2237 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2238
2239 /* clear any PEX errors */
2240 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) {
2241 err = pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2242 0xffffffffUL);
2243 if (err)
2244 goto pci_err;
2245 }
2246
2247 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2248 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2249
2250 hw->ports = 1;
2251 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2252 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2253 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2254 ++hw->ports;
2255 }
2256 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2257
2258 sky2_set_power_state(hw, PCI_D0);
2259
2260 for (i = 0; i < hw->ports; i++) {
2261 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2262 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2263 }
2264
2265 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2266
2267 /* Clear I2C IRQ noise */
2268 sky2_write32(hw, B2_I2C_IRQ, 1);
2269
2270 /* turn off hardware timer (unused) */
2271 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2272 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2273
2274 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2275
2276 /* Turn off descriptor polling */
2277 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2278
2279 /* Turn off receive timestamp */
2280 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2281 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2282
2283 /* enable the Tx Arbiters */
2284 for (i = 0; i < hw->ports; i++)
2285 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2286
2287 /* Initialize ram interface */
2288 for (i = 0; i < hw->ports; i++) {
2289 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2290
2291 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2292 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2293 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2294 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2295 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2296 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2297 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2298 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2299 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2300 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2301 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2302 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2303 }
2304
2305 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2306
2307 for (i = 0; i < hw->ports; i++)
2308 sky2_phy_reset(hw, i);
2309
2310 memset(hw->st_le, 0, STATUS_LE_BYTES);
2311 hw->st_idx = 0;
2312
2313 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2314 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2315
2316 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2317 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2318
2319 /* Set the list last index */
2320 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2321
2322 /* These status setup values are copied from SysKonnect's driver */
2323 if (is_ec_a1(hw)) {
2324 /* WA for dev. #4.3 */
2325 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2326
2327 /* set Status-FIFO watermark */
2328 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2329
2330 /* set Status-FIFO ISR watermark */
2331 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2332 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
2333 } else {
2334 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2335 sky2_write8(hw, STAT_FIFO_WM, 16);
2336
2337 /* set Status-FIFO ISR watermark */
2338 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2339 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2340 else
2341 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2342
2343 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2344 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2345 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2346 }
2347
2348 /* enable status unit */
2349 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2350
2351 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2352 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2353 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2354
2355 return 0;
2356
2357 pci_err:
2358 /* This is to catch a BIOS bug workaround where
2359 * mmconfig table doesn't have other buses.
2360 */
2361 printk(KERN_ERR PFX "%s: can't access PCI config space\n",
2362 pci_name(hw->pdev));
2363 return err;
2364 }
2365
2366 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2367 {
2368 u32 modes;
2369 if (hw->copper) {
2370 modes = SUPPORTED_10baseT_Half
2371 | SUPPORTED_10baseT_Full
2372 | SUPPORTED_100baseT_Half
2373 | SUPPORTED_100baseT_Full
2374 | SUPPORTED_Autoneg | SUPPORTED_TP;
2375
2376 if (hw->chip_id != CHIP_ID_YUKON_FE)
2377 modes |= SUPPORTED_1000baseT_Half
2378 | SUPPORTED_1000baseT_Full;
2379 } else
2380 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2381 | SUPPORTED_Autoneg;
2382 return modes;
2383 }
2384
2385 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2386 {
2387 struct sky2_port *sky2 = netdev_priv(dev);
2388 struct sky2_hw *hw = sky2->hw;
2389
2390 ecmd->transceiver = XCVR_INTERNAL;
2391 ecmd->supported = sky2_supported_modes(hw);
2392 ecmd->phy_address = PHY_ADDR_MARV;
2393 if (hw->copper) {
2394 ecmd->supported = SUPPORTED_10baseT_Half
2395 | SUPPORTED_10baseT_Full
2396 | SUPPORTED_100baseT_Half
2397 | SUPPORTED_100baseT_Full
2398 | SUPPORTED_1000baseT_Half
2399 | SUPPORTED_1000baseT_Full
2400 | SUPPORTED_Autoneg | SUPPORTED_TP;
2401 ecmd->port = PORT_TP;
2402 } else
2403 ecmd->port = PORT_FIBRE;
2404
2405 ecmd->advertising = sky2->advertising;
2406 ecmd->autoneg = sky2->autoneg;
2407 ecmd->speed = sky2->speed;
2408 ecmd->duplex = sky2->duplex;
2409 return 0;
2410 }
2411
2412 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2413 {
2414 struct sky2_port *sky2 = netdev_priv(dev);
2415 const struct sky2_hw *hw = sky2->hw;
2416 u32 supported = sky2_supported_modes(hw);
2417
2418 if (ecmd->autoneg == AUTONEG_ENABLE) {
2419 ecmd->advertising = supported;
2420 sky2->duplex = -1;
2421 sky2->speed = -1;
2422 } else {
2423 u32 setting;
2424
2425 switch (ecmd->speed) {
2426 case SPEED_1000:
2427 if (ecmd->duplex == DUPLEX_FULL)
2428 setting = SUPPORTED_1000baseT_Full;
2429 else if (ecmd->duplex == DUPLEX_HALF)
2430 setting = SUPPORTED_1000baseT_Half;
2431 else
2432 return -EINVAL;
2433 break;
2434 case SPEED_100:
2435 if (ecmd->duplex == DUPLEX_FULL)
2436 setting = SUPPORTED_100baseT_Full;
2437 else if (ecmd->duplex == DUPLEX_HALF)
2438 setting = SUPPORTED_100baseT_Half;
2439 else
2440 return -EINVAL;
2441 break;
2442
2443 case SPEED_10:
2444 if (ecmd->duplex == DUPLEX_FULL)
2445 setting = SUPPORTED_10baseT_Full;
2446 else if (ecmd->duplex == DUPLEX_HALF)
2447 setting = SUPPORTED_10baseT_Half;
2448 else
2449 return -EINVAL;
2450 break;
2451 default:
2452 return -EINVAL;
2453 }
2454
2455 if ((setting & supported) == 0)
2456 return -EINVAL;
2457
2458 sky2->speed = ecmd->speed;
2459 sky2->duplex = ecmd->duplex;
2460 }
2461
2462 sky2->autoneg = ecmd->autoneg;
2463 sky2->advertising = ecmd->advertising;
2464
2465 if (netif_running(dev))
2466 sky2_phy_reinit(sky2);
2467
2468 return 0;
2469 }
2470
2471 static void sky2_get_drvinfo(struct net_device *dev,
2472 struct ethtool_drvinfo *info)
2473 {
2474 struct sky2_port *sky2 = netdev_priv(dev);
2475
2476 strcpy(info->driver, DRV_NAME);
2477 strcpy(info->version, DRV_VERSION);
2478 strcpy(info->fw_version, "N/A");
2479 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2480 }
2481
2482 static const struct sky2_stat {
2483 char name[ETH_GSTRING_LEN];
2484 u16 offset;
2485 } sky2_stats[] = {
2486 { "tx_bytes", GM_TXO_OK_HI },
2487 { "rx_bytes", GM_RXO_OK_HI },
2488 { "tx_broadcast", GM_TXF_BC_OK },
2489 { "rx_broadcast", GM_RXF_BC_OK },
2490 { "tx_multicast", GM_TXF_MC_OK },
2491 { "rx_multicast", GM_RXF_MC_OK },
2492 { "tx_unicast", GM_TXF_UC_OK },
2493 { "rx_unicast", GM_RXF_UC_OK },
2494 { "tx_mac_pause", GM_TXF_MPAUSE },
2495 { "rx_mac_pause", GM_RXF_MPAUSE },
2496 { "collisions", GM_TXF_SNG_COL },
2497 { "late_collision",GM_TXF_LAT_COL },
2498 { "aborted", GM_TXF_ABO_COL },
2499 { "multi_collisions", GM_TXF_MUL_COL },
2500 { "fifo_underrun", GM_TXE_FIFO_UR },
2501 { "fifo_overflow", GM_RXE_FIFO_OV },
2502 { "rx_toolong", GM_RXF_LNG_ERR },
2503 { "rx_jabber", GM_RXF_JAB_PKT },
2504 { "rx_runt", GM_RXE_FRAG },
2505 { "rx_too_long", GM_RXF_LNG_ERR },
2506 { "rx_fcs_error", GM_RXF_FCS_ERR },
2507 };
2508
2509 static u32 sky2_get_rx_csum(struct net_device *dev)
2510 {
2511 struct sky2_port *sky2 = netdev_priv(dev);
2512
2513 return sky2->rx_csum;
2514 }
2515
2516 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2517 {
2518 struct sky2_port *sky2 = netdev_priv(dev);
2519
2520 sky2->rx_csum = data;
2521
2522 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2523 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2524
2525 return 0;
2526 }
2527
2528 static u32 sky2_get_msglevel(struct net_device *netdev)
2529 {
2530 struct sky2_port *sky2 = netdev_priv(netdev);
2531 return sky2->msg_enable;
2532 }
2533
2534 static int sky2_nway_reset(struct net_device *dev)
2535 {
2536 struct sky2_port *sky2 = netdev_priv(dev);
2537
2538 if (sky2->autoneg != AUTONEG_ENABLE)
2539 return -EINVAL;
2540
2541 sky2_phy_reinit(sky2);
2542
2543 return 0;
2544 }
2545
2546 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2547 {
2548 struct sky2_hw *hw = sky2->hw;
2549 unsigned port = sky2->port;
2550 int i;
2551
2552 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2553 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2554 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2555 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2556
2557 for (i = 2; i < count; i++)
2558 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2559 }
2560
2561 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2562 {
2563 struct sky2_port *sky2 = netdev_priv(netdev);
2564 sky2->msg_enable = value;
2565 }
2566
2567 static int sky2_get_stats_count(struct net_device *dev)
2568 {
2569 return ARRAY_SIZE(sky2_stats);
2570 }
2571
2572 static void sky2_get_ethtool_stats(struct net_device *dev,
2573 struct ethtool_stats *stats, u64 * data)
2574 {
2575 struct sky2_port *sky2 = netdev_priv(dev);
2576
2577 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2578 }
2579
2580 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2581 {
2582 int i;
2583
2584 switch (stringset) {
2585 case ETH_SS_STATS:
2586 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2587 memcpy(data + i * ETH_GSTRING_LEN,
2588 sky2_stats[i].name, ETH_GSTRING_LEN);
2589 break;
2590 }
2591 }
2592
2593 /* Use hardware MIB variables for critical path statistics and
2594 * transmit feedback not reported at interrupt.
2595 * Other errors are accounted for in interrupt handler.
2596 */
2597 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2598 {
2599 struct sky2_port *sky2 = netdev_priv(dev);
2600 u64 data[13];
2601
2602 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2603
2604 sky2->net_stats.tx_bytes = data[0];
2605 sky2->net_stats.rx_bytes = data[1];
2606 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2607 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2608 sky2->net_stats.multicast = data[5] + data[7];
2609 sky2->net_stats.collisions = data[10];
2610 sky2->net_stats.tx_aborted_errors = data[12];
2611
2612 return &sky2->net_stats;
2613 }
2614
2615 static int sky2_set_mac_address(struct net_device *dev, void *p)
2616 {
2617 struct sky2_port *sky2 = netdev_priv(dev);
2618 struct sky2_hw *hw = sky2->hw;
2619 unsigned port = sky2->port;
2620 const struct sockaddr *addr = p;
2621
2622 if (!is_valid_ether_addr(addr->sa_data))
2623 return -EADDRNOTAVAIL;
2624
2625 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2626 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2627 dev->dev_addr, ETH_ALEN);
2628 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2629 dev->dev_addr, ETH_ALEN);
2630
2631 /* virtual address for data */
2632 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2633
2634 /* physical address: used for pause frames */
2635 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2636
2637 return 0;
2638 }
2639
2640 static void sky2_set_multicast(struct net_device *dev)
2641 {
2642 struct sky2_port *sky2 = netdev_priv(dev);
2643 struct sky2_hw *hw = sky2->hw;
2644 unsigned port = sky2->port;
2645 struct dev_mc_list *list = dev->mc_list;
2646 u16 reg;
2647 u8 filter[8];
2648
2649 memset(filter, 0, sizeof(filter));
2650
2651 reg = gma_read16(hw, port, GM_RX_CTRL);
2652 reg |= GM_RXCR_UCF_ENA;
2653
2654 if (dev->flags & IFF_PROMISC) /* promiscuous */
2655 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2656 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2657 memset(filter, 0xff, sizeof(filter));
2658 else if (dev->mc_count == 0) /* no multicast */
2659 reg &= ~GM_RXCR_MCF_ENA;
2660 else {
2661 int i;
2662 reg |= GM_RXCR_MCF_ENA;
2663
2664 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2665 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2666 filter[bit / 8] |= 1 << (bit % 8);
2667 }
2668 }
2669
2670 gma_write16(hw, port, GM_MC_ADDR_H1,
2671 (u16) filter[0] | ((u16) filter[1] << 8));
2672 gma_write16(hw, port, GM_MC_ADDR_H2,
2673 (u16) filter[2] | ((u16) filter[3] << 8));
2674 gma_write16(hw, port, GM_MC_ADDR_H3,
2675 (u16) filter[4] | ((u16) filter[5] << 8));
2676 gma_write16(hw, port, GM_MC_ADDR_H4,
2677 (u16) filter[6] | ((u16) filter[7] << 8));
2678
2679 gma_write16(hw, port, GM_RX_CTRL, reg);
2680 }
2681
2682 /* Can have one global because blinking is controlled by
2683 * ethtool and that is always under RTNL mutex
2684 */
2685 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2686 {
2687 u16 pg;
2688
2689 switch (hw->chip_id) {
2690 case CHIP_ID_YUKON_XL:
2691 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2692 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2693 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2694 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2695 PHY_M_LEDC_INIT_CTRL(7) |
2696 PHY_M_LEDC_STA1_CTRL(7) |
2697 PHY_M_LEDC_STA0_CTRL(7))
2698 : 0);
2699
2700 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2701 break;
2702
2703 default:
2704 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2705 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2706 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2707 PHY_M_LED_MO_10(MO_LED_ON) |
2708 PHY_M_LED_MO_100(MO_LED_ON) |
2709 PHY_M_LED_MO_1000(MO_LED_ON) |
2710 PHY_M_LED_MO_RX(MO_LED_ON)
2711 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2712 PHY_M_LED_MO_10(MO_LED_OFF) |
2713 PHY_M_LED_MO_100(MO_LED_OFF) |
2714 PHY_M_LED_MO_1000(MO_LED_OFF) |
2715 PHY_M_LED_MO_RX(MO_LED_OFF));
2716
2717 }
2718 }
2719
2720 /* blink LED's for finding board */
2721 static int sky2_phys_id(struct net_device *dev, u32 data)
2722 {
2723 struct sky2_port *sky2 = netdev_priv(dev);
2724 struct sky2_hw *hw = sky2->hw;
2725 unsigned port = sky2->port;
2726 u16 ledctrl, ledover = 0;
2727 long ms;
2728 int interrupted;
2729 int onoff = 1;
2730
2731 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2732 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2733 else
2734 ms = data * 1000;
2735
2736 /* save initial values */
2737 down(&sky2->phy_sema);
2738 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2739 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2740 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2741 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2742 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2743 } else {
2744 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2745 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2746 }
2747
2748 interrupted = 0;
2749 while (!interrupted && ms > 0) {
2750 sky2_led(hw, port, onoff);
2751 onoff = !onoff;
2752
2753 up(&sky2->phy_sema);
2754 interrupted = msleep_interruptible(250);
2755 down(&sky2->phy_sema);
2756
2757 ms -= 250;
2758 }
2759
2760 /* resume regularly scheduled programming */
2761 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2762 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2763 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2764 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2765 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2766 } else {
2767 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2768 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2769 }
2770 up(&sky2->phy_sema);
2771
2772 return 0;
2773 }
2774
2775 static void sky2_get_pauseparam(struct net_device *dev,
2776 struct ethtool_pauseparam *ecmd)
2777 {
2778 struct sky2_port *sky2 = netdev_priv(dev);
2779
2780 ecmd->tx_pause = sky2->tx_pause;
2781 ecmd->rx_pause = sky2->rx_pause;
2782 ecmd->autoneg = sky2->autoneg;
2783 }
2784
2785 static int sky2_set_pauseparam(struct net_device *dev,
2786 struct ethtool_pauseparam *ecmd)
2787 {
2788 struct sky2_port *sky2 = netdev_priv(dev);
2789 int err = 0;
2790
2791 sky2->autoneg = ecmd->autoneg;
2792 sky2->tx_pause = ecmd->tx_pause != 0;
2793 sky2->rx_pause = ecmd->rx_pause != 0;
2794
2795 sky2_phy_reinit(sky2);
2796
2797 return err;
2798 }
2799
2800 #ifdef CONFIG_PM
2801 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2802 {
2803 struct sky2_port *sky2 = netdev_priv(dev);
2804
2805 wol->supported = WAKE_MAGIC;
2806 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2807 }
2808
2809 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2810 {
2811 struct sky2_port *sky2 = netdev_priv(dev);
2812 struct sky2_hw *hw = sky2->hw;
2813
2814 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2815 return -EOPNOTSUPP;
2816
2817 sky2->wol = wol->wolopts == WAKE_MAGIC;
2818
2819 if (sky2->wol) {
2820 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2821
2822 sky2_write16(hw, WOL_CTRL_STAT,
2823 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2824 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2825 } else
2826 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2827
2828 return 0;
2829 }
2830 #endif
2831
2832 static int sky2_get_coalesce(struct net_device *dev,
2833 struct ethtool_coalesce *ecmd)
2834 {
2835 struct sky2_port *sky2 = netdev_priv(dev);
2836 struct sky2_hw *hw = sky2->hw;
2837
2838 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2839 ecmd->tx_coalesce_usecs = 0;
2840 else {
2841 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2842 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2843 }
2844 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2845
2846 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2847 ecmd->rx_coalesce_usecs = 0;
2848 else {
2849 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2850 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2851 }
2852 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2853
2854 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2855 ecmd->rx_coalesce_usecs_irq = 0;
2856 else {
2857 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2858 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2859 }
2860
2861 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2862
2863 return 0;
2864 }
2865
2866 /* Note: this affect both ports */
2867 static int sky2_set_coalesce(struct net_device *dev,
2868 struct ethtool_coalesce *ecmd)
2869 {
2870 struct sky2_port *sky2 = netdev_priv(dev);
2871 struct sky2_hw *hw = sky2->hw;
2872 const u32 tmin = sky2_clk2us(hw, 1);
2873 const u32 tmax = 5000;
2874
2875 if (ecmd->tx_coalesce_usecs != 0 &&
2876 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2877 return -EINVAL;
2878
2879 if (ecmd->rx_coalesce_usecs != 0 &&
2880 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2881 return -EINVAL;
2882
2883 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2884 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2885 return -EINVAL;
2886
2887 if (ecmd->tx_max_coalesced_frames > 0xffff)
2888 return -EINVAL;
2889 if (ecmd->rx_max_coalesced_frames > 0xff)
2890 return -EINVAL;
2891 if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2892 return -EINVAL;
2893
2894 if (ecmd->tx_coalesce_usecs == 0)
2895 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2896 else {
2897 sky2_write32(hw, STAT_TX_TIMER_INI,
2898 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2899 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2900 }
2901 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2902
2903 if (ecmd->rx_coalesce_usecs == 0)
2904 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2905 else {
2906 sky2_write32(hw, STAT_LEV_TIMER_INI,
2907 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2908 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2909 }
2910 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2911
2912 if (ecmd->rx_coalesce_usecs_irq == 0)
2913 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2914 else {
2915 sky2_write32(hw, STAT_ISR_TIMER_INI,
2916 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2917 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2918 }
2919 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2920 return 0;
2921 }
2922
2923 static void sky2_get_ringparam(struct net_device *dev,
2924 struct ethtool_ringparam *ering)
2925 {
2926 struct sky2_port *sky2 = netdev_priv(dev);
2927
2928 ering->rx_max_pending = RX_MAX_PENDING;
2929 ering->rx_mini_max_pending = 0;
2930 ering->rx_jumbo_max_pending = 0;
2931 ering->tx_max_pending = TX_RING_SIZE - 1;
2932
2933 ering->rx_pending = sky2->rx_pending;
2934 ering->rx_mini_pending = 0;
2935 ering->rx_jumbo_pending = 0;
2936 ering->tx_pending = sky2->tx_pending;
2937 }
2938
2939 static int sky2_set_ringparam(struct net_device *dev,
2940 struct ethtool_ringparam *ering)
2941 {
2942 struct sky2_port *sky2 = netdev_priv(dev);
2943 int err = 0;
2944
2945 if (ering->rx_pending > RX_MAX_PENDING ||
2946 ering->rx_pending < 8 ||
2947 ering->tx_pending < MAX_SKB_TX_LE ||
2948 ering->tx_pending > TX_RING_SIZE - 1)
2949 return -EINVAL;
2950
2951 if (netif_running(dev))
2952 sky2_down(dev);
2953
2954 sky2->rx_pending = ering->rx_pending;
2955 sky2->tx_pending = ering->tx_pending;
2956
2957 if (netif_running(dev)) {
2958 err = sky2_up(dev);
2959 if (err)
2960 dev_close(dev);
2961 else
2962 sky2_set_multicast(dev);
2963 }
2964
2965 return err;
2966 }
2967
2968 static int sky2_get_regs_len(struct net_device *dev)
2969 {
2970 return 0x4000;
2971 }
2972
2973 /*
2974 * Returns copy of control register region
2975 * Note: access to the RAM address register set will cause timeouts.
2976 */
2977 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2978 void *p)
2979 {
2980 const struct sky2_port *sky2 = netdev_priv(dev);
2981 const void __iomem *io = sky2->hw->regs;
2982
2983 BUG_ON(regs->len < B3_RI_WTO_R1);
2984 regs->version = 1;
2985 memset(p, 0, regs->len);
2986
2987 memcpy_fromio(p, io, B3_RAM_ADDR);
2988
2989 memcpy_fromio(p + B3_RI_WTO_R1,
2990 io + B3_RI_WTO_R1,
2991 regs->len - B3_RI_WTO_R1);
2992 }
2993
2994 static struct ethtool_ops sky2_ethtool_ops = {
2995 .get_settings = sky2_get_settings,
2996 .set_settings = sky2_set_settings,
2997 .get_drvinfo = sky2_get_drvinfo,
2998 .get_msglevel = sky2_get_msglevel,
2999 .set_msglevel = sky2_set_msglevel,
3000 .nway_reset = sky2_nway_reset,
3001 .get_regs_len = sky2_get_regs_len,
3002 .get_regs = sky2_get_regs,
3003 .get_link = ethtool_op_get_link,
3004 .get_sg = ethtool_op_get_sg,
3005 .set_sg = ethtool_op_set_sg,
3006 .get_tx_csum = ethtool_op_get_tx_csum,
3007 .set_tx_csum = ethtool_op_set_tx_csum,
3008 .get_tso = ethtool_op_get_tso,
3009 .set_tso = ethtool_op_set_tso,
3010 .get_rx_csum = sky2_get_rx_csum,
3011 .set_rx_csum = sky2_set_rx_csum,
3012 .get_strings = sky2_get_strings,
3013 .get_coalesce = sky2_get_coalesce,
3014 .set_coalesce = sky2_set_coalesce,
3015 .get_ringparam = sky2_get_ringparam,
3016 .set_ringparam = sky2_set_ringparam,
3017 .get_pauseparam = sky2_get_pauseparam,
3018 .set_pauseparam = sky2_set_pauseparam,
3019 #ifdef CONFIG_PM
3020 .get_wol = sky2_get_wol,
3021 .set_wol = sky2_set_wol,
3022 #endif
3023 .phys_id = sky2_phys_id,
3024 .get_stats_count = sky2_get_stats_count,
3025 .get_ethtool_stats = sky2_get_ethtool_stats,
3026 .get_perm_addr = ethtool_op_get_perm_addr,
3027 };
3028
3029 /* Initialize network device */
3030 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3031 unsigned port, int highmem)
3032 {
3033 struct sky2_port *sky2;
3034 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3035
3036 if (!dev) {
3037 printk(KERN_ERR "sky2 etherdev alloc failed");
3038 return NULL;
3039 }
3040
3041 SET_MODULE_OWNER(dev);
3042 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3043 dev->irq = hw->pdev->irq;
3044 dev->open = sky2_up;
3045 dev->stop = sky2_down;
3046 dev->do_ioctl = sky2_ioctl;
3047 dev->hard_start_xmit = sky2_xmit_frame;
3048 dev->get_stats = sky2_get_stats;
3049 dev->set_multicast_list = sky2_set_multicast;
3050 dev->set_mac_address = sky2_set_mac_address;
3051 dev->change_mtu = sky2_change_mtu;
3052 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3053 dev->tx_timeout = sky2_tx_timeout;
3054 dev->watchdog_timeo = TX_WATCHDOG;
3055 if (port == 0)
3056 dev->poll = sky2_poll;
3057 dev->weight = NAPI_WEIGHT;
3058 #ifdef CONFIG_NET_POLL_CONTROLLER
3059 dev->poll_controller = sky2_netpoll;
3060 #endif
3061
3062 sky2 = netdev_priv(dev);
3063 sky2->netdev = dev;
3064 sky2->hw = hw;
3065 sky2->msg_enable = netif_msg_init(debug, default_msg);
3066
3067 spin_lock_init(&sky2->tx_lock);
3068 /* Auto speed and flow control */
3069 sky2->autoneg = AUTONEG_ENABLE;
3070 sky2->tx_pause = 1;
3071 sky2->rx_pause = 1;
3072 sky2->duplex = -1;
3073 sky2->speed = -1;
3074 sky2->advertising = sky2_supported_modes(hw);
3075
3076 /* Receive checksum disabled for Yukon XL
3077 * because of observed problems with incorrect
3078 * values when multiple packets are received in one interrupt
3079 */
3080 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3081
3082 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
3083 init_MUTEX(&sky2->phy_sema);
3084 sky2->tx_pending = TX_DEF_PENDING;
3085 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
3086 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3087
3088 hw->dev[port] = dev;
3089
3090 sky2->port = port;
3091
3092 dev->features |= NETIF_F_LLTX;
3093 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3094 dev->features |= NETIF_F_TSO;
3095 if (highmem)
3096 dev->features |= NETIF_F_HIGHDMA;
3097 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3098
3099 #ifdef SKY2_VLAN_TAG_USED
3100 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3101 dev->vlan_rx_register = sky2_vlan_rx_register;
3102 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3103 #endif
3104
3105 /* read the mac address */
3106 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3107 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3108
3109 /* device is off until link detection */
3110 netif_carrier_off(dev);
3111 netif_stop_queue(dev);
3112
3113 return dev;
3114 }
3115
3116 static void __devinit sky2_show_addr(struct net_device *dev)
3117 {
3118 const struct sky2_port *sky2 = netdev_priv(dev);
3119
3120 if (netif_msg_probe(sky2))
3121 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3122 dev->name,
3123 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3124 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3125 }
3126
3127 /* Handle software interrupt used during MSI test */
3128 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3129 struct pt_regs *regs)
3130 {
3131 struct sky2_hw *hw = dev_id;
3132 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3133
3134 if (status == 0)
3135 return IRQ_NONE;
3136
3137 if (status & Y2_IS_IRQ_SW) {
3138 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3139 hw->msi = 1;
3140 }
3141 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3142
3143 sky2_read32(hw, B0_IMSK);
3144 return IRQ_HANDLED;
3145 }
3146
3147 /* Test interrupt path by forcing a a software IRQ */
3148 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3149 {
3150 struct pci_dev *pdev = hw->pdev;
3151 int i, err;
3152
3153 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3154
3155 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3156 if (err) {
3157 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3158 pci_name(pdev), pdev->irq);
3159 return err;
3160 }
3161
3162 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3163 wmb();
3164
3165 for (i = 0; i < 10; i++) {
3166 barrier();
3167 if (hw->msi)
3168 goto found;
3169 mdelay(1);
3170 }
3171
3172 err = -EOPNOTSUPP;
3173 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3174 found:
3175 sky2_write32(hw, B0_IMSK, 0);
3176
3177 free_irq(pdev->irq, hw);
3178
3179 return err;
3180 }
3181
3182 static int __devinit sky2_probe(struct pci_dev *pdev,
3183 const struct pci_device_id *ent)
3184 {
3185 struct net_device *dev, *dev1 = NULL;
3186 struct sky2_hw *hw;
3187 int err, pm_cap, using_dac = 0;
3188
3189 err = pci_enable_device(pdev);
3190 if (err) {
3191 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3192 pci_name(pdev));
3193 goto err_out;
3194 }
3195
3196 err = pci_request_regions(pdev, DRV_NAME);
3197 if (err) {
3198 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3199 pci_name(pdev));
3200 goto err_out;
3201 }
3202
3203 pci_set_master(pdev);
3204
3205 /* Find power-management capability. */
3206 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3207 if (pm_cap == 0) {
3208 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3209 "aborting.\n");
3210 err = -EIO;
3211 goto err_out_free_regions;
3212 }
3213
3214 if (sizeof(dma_addr_t) > sizeof(u32) &&
3215 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3216 using_dac = 1;
3217 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3218 if (err < 0) {
3219 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3220 "for consistent allocations\n", pci_name(pdev));
3221 goto err_out_free_regions;
3222 }
3223
3224 } else {
3225 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3226 if (err) {
3227 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3228 pci_name(pdev));
3229 goto err_out_free_regions;
3230 }
3231 }
3232
3233 #ifdef __BIG_ENDIAN
3234 /* byte swap descriptors in hardware */
3235 {
3236 u32 reg;
3237
3238 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3239 reg |= PCI_REV_DESC;
3240 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3241 }
3242 #endif
3243
3244 err = -ENOMEM;
3245 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3246 if (!hw) {
3247 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3248 pci_name(pdev));
3249 goto err_out_free_regions;
3250 }
3251
3252 hw->pdev = pdev;
3253
3254 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3255 if (!hw->regs) {
3256 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3257 pci_name(pdev));
3258 goto err_out_free_hw;
3259 }
3260 hw->pm_cap = pm_cap;
3261
3262 /* ring for status responses */
3263 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3264 &hw->st_dma);
3265 if (!hw->st_le)
3266 goto err_out_iounmap;
3267
3268 err = sky2_reset(hw);
3269 if (err)
3270 goto err_out_iounmap;
3271
3272 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3273 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3274 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3275 hw->chip_id, hw->chip_rev);
3276
3277 dev = sky2_init_netdev(hw, 0, using_dac);
3278 if (!dev)
3279 goto err_out_free_pci;
3280
3281 err = register_netdev(dev);
3282 if (err) {
3283 printk(KERN_ERR PFX "%s: cannot register net device\n",
3284 pci_name(pdev));
3285 goto err_out_free_netdev;
3286 }
3287
3288 sky2_show_addr(dev);
3289
3290 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3291 if (register_netdev(dev1) == 0)
3292 sky2_show_addr(dev1);
3293 else {
3294 /* Failure to register second port need not be fatal */
3295 printk(KERN_WARNING PFX
3296 "register of second port failed\n");
3297 hw->dev[1] = NULL;
3298 free_netdev(dev1);
3299 }
3300 }
3301
3302 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3303 err = sky2_test_msi(hw);
3304 if (err == -EOPNOTSUPP) {
3305 /* MSI test failed, go back to INTx mode */
3306 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3307 "switching to INTx mode. Please report this failure to "
3308 "the PCI maintainer and include system chipset information.\n",
3309 pci_name(pdev));
3310 pci_disable_msi(pdev);
3311 }
3312 else if (err)
3313 goto err_out_unregister;
3314 }
3315
3316 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ | SA_SAMPLE_RANDOM,
3317 DRV_NAME, hw);
3318 if (err) {
3319 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3320 pci_name(pdev), pdev->irq);
3321 goto err_out_unregister;
3322 }
3323
3324 hw->intr_mask = Y2_IS_BASE;
3325 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3326
3327 pci_set_drvdata(pdev, hw);
3328
3329 return 0;
3330
3331 err_out_unregister:
3332 if (hw->msi)
3333 pci_disable_msi(pdev);
3334 if (dev1) {
3335 unregister_netdev(dev1);
3336 free_netdev(dev1);
3337 }
3338 unregister_netdev(dev);
3339 err_out_free_netdev:
3340 free_netdev(dev);
3341 err_out_free_pci:
3342 sky2_write8(hw, B0_CTST, CS_RST_SET);
3343 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3344 err_out_iounmap:
3345 iounmap(hw->regs);
3346 err_out_free_hw:
3347 kfree(hw);
3348 err_out_free_regions:
3349 pci_release_regions(pdev);
3350 pci_disable_device(pdev);
3351 err_out:
3352 return err;
3353 }
3354
3355 static void __devexit sky2_remove(struct pci_dev *pdev)
3356 {
3357 struct sky2_hw *hw = pci_get_drvdata(pdev);
3358 struct net_device *dev0, *dev1;
3359
3360 if (!hw)
3361 return;
3362
3363 dev0 = hw->dev[0];
3364 dev1 = hw->dev[1];
3365 if (dev1)
3366 unregister_netdev(dev1);
3367 unregister_netdev(dev0);
3368
3369 sky2_write32(hw, B0_IMSK, 0);
3370 sky2_set_power_state(hw, PCI_D3hot);
3371 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3372 sky2_write8(hw, B0_CTST, CS_RST_SET);
3373 sky2_read8(hw, B0_CTST);
3374
3375 free_irq(pdev->irq, hw);
3376 if (hw->msi)
3377 pci_disable_msi(pdev);
3378 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3379 pci_release_regions(pdev);
3380 pci_disable_device(pdev);
3381
3382 if (dev1)
3383 free_netdev(dev1);
3384 free_netdev(dev0);
3385 iounmap(hw->regs);
3386 kfree(hw);
3387
3388 pci_set_drvdata(pdev, NULL);
3389 }
3390
3391 #ifdef CONFIG_PM
3392 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3393 {
3394 struct sky2_hw *hw = pci_get_drvdata(pdev);
3395 int i;
3396
3397 for (i = 0; i < 2; i++) {
3398 struct net_device *dev = hw->dev[i];
3399
3400 if (dev) {
3401 if (!netif_running(dev))
3402 continue;
3403
3404 sky2_down(dev);
3405 netif_device_detach(dev);
3406 }
3407 }
3408
3409 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3410 }
3411
3412 static int sky2_resume(struct pci_dev *pdev)
3413 {
3414 struct sky2_hw *hw = pci_get_drvdata(pdev);
3415 int i, err;
3416
3417 pci_restore_state(pdev);
3418 pci_enable_wake(pdev, PCI_D0, 0);
3419 err = sky2_set_power_state(hw, PCI_D0);
3420 if (err)
3421 goto out;
3422
3423 err = sky2_reset(hw);
3424 if (err)
3425 goto out;
3426
3427 for (i = 0; i < 2; i++) {
3428 struct net_device *dev = hw->dev[i];
3429 if (dev && netif_running(dev)) {
3430 netif_device_attach(dev);
3431 err = sky2_up(dev);
3432 if (err) {
3433 printk(KERN_ERR PFX "%s: could not up: %d\n",
3434 dev->name, err);
3435 dev_close(dev);
3436 break;
3437 }
3438 }
3439 }
3440 out:
3441 return err;
3442 }
3443 #endif
3444
3445 static struct pci_driver sky2_driver = {
3446 .name = DRV_NAME,
3447 .id_table = sky2_id_table,
3448 .probe = sky2_probe,
3449 .remove = __devexit_p(sky2_remove),
3450 #ifdef CONFIG_PM
3451 .suspend = sky2_suspend,
3452 .resume = sky2_resume,
3453 #endif
3454 };
3455
3456 static int __init sky2_init_module(void)
3457 {
3458 return pci_register_driver(&sky2_driver);
3459 }
3460
3461 static void __exit sky2_cleanup_module(void)
3462 {
3463 pci_unregister_driver(&sky2_driver);
3464 }
3465
3466 module_init(sky2_init_module);
3467 module_exit(sky2_cleanup_module);
3468
3469 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3470 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3471 MODULE_LICENSE("GPL");
3472 MODULE_VERSION(DRV_VERSION);
AMDTP streaming driver for the Linux FireWire stack (Juju)