arch/blackfin/mach-bf533/dma.c

   1 /*
   2  * File:         arch/blackfin/mach-bf533/dma.c
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:  This file contains the simple DMA Implementation for Blackfin
   8  *
   9  * Modified:
  10  *               Copyright 2004-2006 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29 #include <linux/module.h>
  30
  31 #include <asm/blackfin.h>
  32 #include <asm/dma.h>
  33
  34 struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
  35         (struct dma_register *) DMA0_NEXT_DESC_PTR,
  36         (struct dma_register *) DMA1_NEXT_DESC_PTR,
  37         (struct dma_register *) DMA2_NEXT_DESC_PTR,
  38         (struct dma_register *) DMA3_NEXT_DESC_PTR,
  39         (struct dma_register *) DMA4_NEXT_DESC_PTR,
  40         (struct dma_register *) DMA5_NEXT_DESC_PTR,
  41         (struct dma_register *) DMA6_NEXT_DESC_PTR,
  42         (struct dma_register *) DMA7_NEXT_DESC_PTR,
  43         (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
  44         (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
  45         (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
  46         (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
  47 };
  48 EXPORT_SYMBOL(dma_io_base_addr);
  49
  50 int channel2irq(unsigned int channel)
  51 {
  52         int ret_irq = -1;
  53
  54         switch (channel) {
  55         case CH_PPI:
  56                 ret_irq = IRQ_PPI;
  57                 break;
  58
  59         case CH_SPORT0_RX:
  60                 ret_irq = IRQ_SPORT0_RX;
  61                 break;
  62
  63         case CH_SPORT0_TX:
  64                 ret_irq = IRQ_SPORT0_TX;
  65                 break;
  66
  67         case CH_SPORT1_RX:
  68                 ret_irq = IRQ_SPORT1_RX;
  69                 break;
  70
  71         case CH_SPORT1_TX:
  72                 ret_irq = IRQ_SPORT1_TX;
  73                 break;
  74
  75         case CH_SPI:
  76                 ret_irq = IRQ_SPI;
  77                 break;
  78
  79         case CH_UART0_RX:
  80                 ret_irq = IRQ_UART0_RX;
  81                 break;
  82
  83         case CH_UART0_TX:
  84                 ret_irq = IRQ_UART0_TX;
  85                 break;
  86
  87         case CH_MEM_STREAM0_SRC:
  88         case CH_MEM_STREAM0_DEST:
  89                 ret_irq = IRQ_MEM_DMA0;
  90                 break;
  91
  92         case CH_MEM_STREAM1_SRC:
  93         case CH_MEM_STREAM1_DEST:
  94                 ret_irq = IRQ_MEM_DMA1;
  95                 break;
  96         }
  97         return ret_irq;
  98 }