2 drivers/net/tulip/media.c
4 Maintained by Jeff Garzik <jgarzik@pobox.com>
5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
17 #include <linux/kernel.h>
18 #include <linux/mii.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/pci.h>
25 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
26 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
27 "overclocking" issues or future 66Mhz PCI. */
28 #define mdio_delay() ioread32(mdio_addr)
30 /* Read and write the MII registers using software-generated serial
31 MDIO protocol. It is just different enough from the EEPROM protocol
32 to not share code. The maxium data clock rate is 2.5 Mhz. */
33 #define MDIO_SHIFT_CLK 0x10000
34 #define MDIO_DATA_WRITE0 0x00000
35 #define MDIO_DATA_WRITE1 0x20000
36 #define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */
37 #define MDIO_ENB_IN 0x40000
38 #define MDIO_DATA_READ 0x80000
40 static const unsigned char comet_miireg2offset
[32] = {
41 0xB4, 0xB8, 0xBC, 0xC0, 0xC4, 0xC8, 0xCC, 0, 0,0,0,0, 0,0,0,0,
42 0,0xD0,0,0, 0,0,0,0, 0,0,0,0, 0, 0xD4, 0xD8, 0xDC, };
45 /* MII transceiver control section.
46 Read and write the MII registers using software-generated serial
47 MDIO protocol. See the MII specifications or DP83840A data sheet
50 int tulip_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
52 struct tulip_private
*tp
= netdev_priv(dev
);
54 int read_cmd
= (0xf6 << 10) | ((phy_id
& 0x1f) << 5) | location
;
56 void __iomem
*ioaddr
= tp
->base_addr
;
57 void __iomem
*mdio_addr
= ioaddr
+ CSR9
;
63 if (tp
->chip_id
== COMET
&& phy_id
== 30) {
64 if (comet_miireg2offset
[location
])
65 return ioread32(ioaddr
+ comet_miireg2offset
[location
]);
69 spin_lock_irqsave(&tp
->mii_lock
, flags
);
70 if (tp
->chip_id
== LC82C168
) {
72 iowrite32(0x60020000 + (phy_id
<<23) + (location
<<18), ioaddr
+ 0xA0);
73 ioread32(ioaddr
+ 0xA0);
74 ioread32(ioaddr
+ 0xA0);
77 if ( ! ((retval
= ioread32(ioaddr
+ 0xA0)) & 0x80000000))
80 spin_unlock_irqrestore(&tp
->mii_lock
, flags
);
81 return retval
& 0xffff;
84 if(tp
->chip_id
== ULI526X
&& tp
->revision
>= 0x40) {
88 value
= ioread32(ioaddr
+ CSR9
);
89 iowrite32(value
& 0xFFEFFFFF, ioaddr
+ CSR9
);
91 value
= (phy_id
<< 21) | (location
<< 16) | 0x08000000;
92 iowrite32(value
, ioaddr
+ CSR10
);
96 if(ioread32(ioaddr
+ CSR10
) & 0x10000000)
99 retval
= ioread32(ioaddr
+ CSR10
);
100 spin_unlock_irqrestore(&tp
->mii_lock
, flags
);
101 return retval
& 0xFFFF;
103 /* Establish sync by sending at least 32 logic ones. */
104 for (i
= 32; i
>= 0; i
--) {
105 iowrite32(MDIO_ENB
| MDIO_DATA_WRITE1
, mdio_addr
);
107 iowrite32(MDIO_ENB
| MDIO_DATA_WRITE1
| MDIO_SHIFT_CLK
, mdio_addr
);
110 /* Shift the read command bits out. */
111 for (i
= 15; i
>= 0; i
--) {
112 int dataval
= (read_cmd
& (1 << i
)) ? MDIO_DATA_WRITE1
: 0;
114 iowrite32(MDIO_ENB
| dataval
, mdio_addr
);
116 iowrite32(MDIO_ENB
| dataval
| MDIO_SHIFT_CLK
, mdio_addr
);
119 /* Read the two transition, 16 data, and wire-idle bits. */
120 for (i
= 19; i
> 0; i
--) {
121 iowrite32(MDIO_ENB_IN
, mdio_addr
);
123 retval
= (retval
<< 1) | ((ioread32(mdio_addr
) & MDIO_DATA_READ
) ? 1 : 0);
124 iowrite32(MDIO_ENB_IN
| MDIO_SHIFT_CLK
, mdio_addr
);
128 spin_unlock_irqrestore(&tp
->mii_lock
, flags
);
129 return (retval
>>1) & 0xffff;
132 void tulip_mdio_write(struct net_device
*dev
, int phy_id
, int location
, int val
)
134 struct tulip_private
*tp
= netdev_priv(dev
);
136 int cmd
= (0x5002 << 16) | ((phy_id
& 0x1f) << 23) | (location
<<18) | (val
& 0xffff);
137 void __iomem
*ioaddr
= tp
->base_addr
;
138 void __iomem
*mdio_addr
= ioaddr
+ CSR9
;
141 if (location
& ~0x1f)
144 if (tp
->chip_id
== COMET
&& phy_id
== 30) {
145 if (comet_miireg2offset
[location
])
146 iowrite32(val
, ioaddr
+ comet_miireg2offset
[location
]);
150 spin_lock_irqsave(&tp
->mii_lock
, flags
);
151 if (tp
->chip_id
== LC82C168
) {
153 iowrite32(cmd
, ioaddr
+ 0xA0);
156 if ( ! (ioread32(ioaddr
+ 0xA0) & 0x80000000))
159 spin_unlock_irqrestore(&tp
->mii_lock
, flags
);
162 if (tp
->chip_id
== ULI526X
&& tp
->revision
>= 0x40) {
166 value
= ioread32(ioaddr
+ CSR9
);
167 iowrite32(value
& 0xFFEFFFFF, ioaddr
+ CSR9
);
169 value
= (phy_id
<< 21) | (location
<< 16) | 0x04000000 | (val
& 0xFFFF);
170 iowrite32(value
, ioaddr
+ CSR10
);
173 if (ioread32(ioaddr
+ CSR10
) & 0x10000000)
176 spin_unlock_irqrestore(&tp
->mii_lock
, flags
);
180 /* Establish sync by sending 32 logic ones. */
181 for (i
= 32; i
>= 0; i
--) {
182 iowrite32(MDIO_ENB
| MDIO_DATA_WRITE1
, mdio_addr
);
184 iowrite32(MDIO_ENB
| MDIO_DATA_WRITE1
| MDIO_SHIFT_CLK
, mdio_addr
);
187 /* Shift the command bits out. */
188 for (i
= 31; i
>= 0; i
--) {
189 int dataval
= (cmd
& (1 << i
)) ? MDIO_DATA_WRITE1
: 0;
190 iowrite32(MDIO_ENB
| dataval
, mdio_addr
);
192 iowrite32(MDIO_ENB
| dataval
| MDIO_SHIFT_CLK
, mdio_addr
);
195 /* Clear out extra bits. */
196 for (i
= 2; i
> 0; i
--) {
197 iowrite32(MDIO_ENB_IN
, mdio_addr
);
199 iowrite32(MDIO_ENB_IN
| MDIO_SHIFT_CLK
, mdio_addr
);
203 spin_unlock_irqrestore(&tp
->mii_lock
, flags
);
207 /* Set up the transceiver control registers for the selected media type. */
208 void tulip_select_media(struct net_device
*dev
, int startup
)
210 struct tulip_private
*tp
= netdev_priv(dev
);
211 void __iomem
*ioaddr
= tp
->base_addr
;
212 struct mediatable
*mtable
= tp
->mtable
;
217 struct medialeaf
*mleaf
= &mtable
->mleaf
[tp
->cur_index
];
218 unsigned char *p
= mleaf
->leafdata
;
219 switch (mleaf
->type
) {
220 case 0: /* 21140 non-MII xcvr. */
222 printk(KERN_DEBUG
"%s: Using a 21140 non-MII transceiver"
223 " with control setting %2.2x.\n",
227 iowrite32(mtable
->csr12dir
| 0x100, ioaddr
+ CSR12
);
228 iowrite32(p
[1], ioaddr
+ CSR12
);
229 new_csr6
= 0x02000000 | ((p
[2] & 0x71) << 18);
233 u32 csr13val
, csr14val
, csr15dir
, csr15val
;
234 for (i
= 0; i
< 5; i
++)
235 setup
[i
] = get_u16(&p
[i
*2 + 1]);
237 dev
->if_port
= p
[0] & MEDIA_MASK
;
238 if (tulip_media_cap
[dev
->if_port
] & MediaAlwaysFD
)
241 if (startup
&& mtable
->has_reset
) {
242 struct medialeaf
*rleaf
= &mtable
->mleaf
[mtable
->has_reset
];
243 unsigned char *rst
= rleaf
->leafdata
;
245 printk(KERN_DEBUG
"%s: Resetting the transceiver.\n",
247 for (i
= 0; i
< rst
[0]; i
++)
248 iowrite32(get_u16(rst
+ 1 + (i
<<1)) << 16, ioaddr
+ CSR15
);
251 printk(KERN_DEBUG
"%s: 21143 non-MII %s transceiver control "
253 dev
->name
, medianame
[dev
->if_port
], setup
[0], setup
[1]);
254 if (p
[0] & 0x40) { /* SIA (CSR13-15) setup values are provided. */
257 csr15dir
= (setup
[3]<<16) | setup
[2];
258 csr15val
= (setup
[4]<<16) | setup
[2];
259 iowrite32(0, ioaddr
+ CSR13
);
260 iowrite32(csr14val
, ioaddr
+ CSR14
);
261 iowrite32(csr15dir
, ioaddr
+ CSR15
); /* Direction */
262 iowrite32(csr15val
, ioaddr
+ CSR15
); /* Data */
263 iowrite32(csr13val
, ioaddr
+ CSR13
);
267 csr15dir
= (setup
[0]<<16) | 0x0008;
268 csr15val
= (setup
[1]<<16) | 0x0008;
269 if (dev
->if_port
<= 4)
270 csr14val
= t21142_csr14
[dev
->if_port
];
272 iowrite32(0, ioaddr
+ CSR13
);
273 iowrite32(csr14val
, ioaddr
+ CSR14
);
275 iowrite32(csr15dir
, ioaddr
+ CSR15
); /* Direction */
276 iowrite32(csr15val
, ioaddr
+ CSR15
); /* Data */
277 if (startup
) iowrite32(csr13val
, ioaddr
+ CSR13
);
280 printk(KERN_DEBUG
"%s: Setting CSR15 to %8.8x/%8.8x.\n",
281 dev
->name
, csr15dir
, csr15val
);
282 if (mleaf
->type
== 4)
283 new_csr6
= 0x82020000 | ((setup
[2] & 0x71) << 18);
285 new_csr6
= 0x82420000;
290 int init_length
= p
[1];
291 u16
*misc_info
, tmp_info
;
294 new_csr6
= 0x020E0000;
295 if (mleaf
->type
== 3) { /* 21142 */
296 u16
*init_sequence
= (u16
*)(p
+2);
297 u16
*reset_sequence
= &((u16
*)(p
+3))[init_length
];
298 int reset_length
= p
[2 + init_length
*2];
299 misc_info
= reset_sequence
+ reset_length
;
301 for (i
= 0; i
< reset_length
; i
++)
302 iowrite32(get_u16(&reset_sequence
[i
]) << 16, ioaddr
+ CSR15
);
303 for (i
= 0; i
< init_length
; i
++)
304 iowrite32(get_u16(&init_sequence
[i
]) << 16, ioaddr
+ CSR15
);
306 u8
*init_sequence
= p
+ 2;
307 u8
*reset_sequence
= p
+ 3 + init_length
;
308 int reset_length
= p
[2 + init_length
];
309 misc_info
= (u16
*)(reset_sequence
+ reset_length
);
311 iowrite32(mtable
->csr12dir
| 0x100, ioaddr
+ CSR12
);
312 for (i
= 0; i
< reset_length
; i
++)
313 iowrite32(reset_sequence
[i
], ioaddr
+ CSR12
);
315 for (i
= 0; i
< init_length
; i
++)
316 iowrite32(init_sequence
[i
], ioaddr
+ CSR12
);
318 tmp_info
= get_u16(&misc_info
[1]);
320 tp
->advertising
[phy_num
] = tmp_info
| 1;
321 if (tmp_info
&& startup
< 2) {
322 if (tp
->mii_advertise
== 0)
323 tp
->mii_advertise
= tp
->advertising
[phy_num
];
325 printk(KERN_DEBUG
"%s: Advertising %4.4x on MII %d.\n",
326 dev
->name
, tp
->mii_advertise
, tp
->phys
[phy_num
]);
327 tulip_mdio_write(dev
, tp
->phys
[phy_num
], 4, tp
->mii_advertise
);
334 new_csr6
= 0; /* FIXME */
336 for (i
= 0; i
< 5; i
++)
337 setup
[i
] = get_u16(&p
[i
*2 + 1]);
339 if (startup
&& mtable
->has_reset
) {
340 struct medialeaf
*rleaf
= &mtable
->mleaf
[mtable
->has_reset
];
341 unsigned char *rst
= rleaf
->leafdata
;
343 printk(KERN_DEBUG
"%s: Resetting the transceiver.\n",
345 for (i
= 0; i
< rst
[0]; i
++)
346 iowrite32(get_u16(rst
+ 1 + (i
<<1)) << 16, ioaddr
+ CSR15
);
352 printk(KERN_DEBUG
"%s: Invalid media table selection %d.\n",
353 dev
->name
, mleaf
->type
);
354 new_csr6
= 0x020E0000;
357 printk(KERN_DEBUG
"%s: Using media type %s, CSR12 is %2.2x.\n",
358 dev
->name
, medianame
[dev
->if_port
],
359 ioread32(ioaddr
+ CSR12
) & 0xff);
360 } else if (tp
->chip_id
== LC82C168
) {
361 if (startup
&& ! tp
->medialock
)
362 dev
->if_port
= tp
->mii_cnt
? 11 : 0;
364 printk(KERN_DEBUG
"%s: PNIC PHY status is %3.3x, media %s.\n",
365 dev
->name
, ioread32(ioaddr
+ 0xB8), medianame
[dev
->if_port
]);
367 new_csr6
= 0x810C0000;
368 iowrite32(0x0001, ioaddr
+ CSR15
);
369 iowrite32(0x0201B07A, ioaddr
+ 0xB8);
370 } else if (startup
) {
371 /* Start with 10mbps to do autonegotiation. */
372 iowrite32(0x32, ioaddr
+ CSR12
);
373 new_csr6
= 0x00420000;
374 iowrite32(0x0001B078, ioaddr
+ 0xB8);
375 iowrite32(0x0201B078, ioaddr
+ 0xB8);
376 } else if (dev
->if_port
== 3 || dev
->if_port
== 5) {
377 iowrite32(0x33, ioaddr
+ CSR12
);
378 new_csr6
= 0x01860000;
379 /* Trigger autonegotiation. */
380 iowrite32(startup
? 0x0201F868 : 0x0001F868, ioaddr
+ 0xB8);
382 iowrite32(0x32, ioaddr
+ CSR12
);
383 new_csr6
= 0x00420000;
384 iowrite32(0x1F078, ioaddr
+ 0xB8);
386 } else { /* Unknown chip type with no media table. */
387 if (tp
->default_port
== 0)
388 dev
->if_port
= tp
->mii_cnt
? 11 : 3;
389 if (tulip_media_cap
[dev
->if_port
] & MediaIsMII
) {
390 new_csr6
= 0x020E0000;
391 } else if (tulip_media_cap
[dev
->if_port
] & MediaIsFx
) {
392 new_csr6
= 0x02860000;
394 new_csr6
= 0x03860000;
396 printk(KERN_DEBUG
"%s: No media description table, assuming "
397 "%s transceiver, CSR12 %2.2x.\n",
398 dev
->name
, medianame
[dev
->if_port
],
399 ioread32(ioaddr
+ CSR12
));
402 tp
->csr6
= new_csr6
| (tp
->csr6
& 0xfdff) | (tp
->full_duplex
? 0x0200 : 0);
407 Check the MII negotiated duplex and change the CSR6 setting if
409 Return 0 if everything is OK.
410 Return < 0 if the transceiver is missing or has no link beat.
412 int tulip_check_duplex(struct net_device
*dev
)
414 struct tulip_private
*tp
= netdev_priv(dev
);
415 unsigned int bmsr
, lpa
, negotiated
, new_csr6
;
417 bmsr
= tulip_mdio_read(dev
, tp
->phys
[0], MII_BMSR
);
418 lpa
= tulip_mdio_read(dev
, tp
->phys
[0], MII_LPA
);
420 printk(KERN_INFO
"%s: MII status %4.4x, Link partner report "
421 "%4.4x.\n", dev
->name
, bmsr
, lpa
);
424 if ((bmsr
& BMSR_LSTATUS
) == 0) {
425 int new_bmsr
= tulip_mdio_read(dev
, tp
->phys
[0], MII_BMSR
);
426 if ((new_bmsr
& BMSR_LSTATUS
) == 0) {
428 printk(KERN_INFO
"%s: No link beat on the MII interface,"
429 " status %4.4x.\n", dev
->name
, new_bmsr
);
433 negotiated
= lpa
& tp
->advertising
[0];
434 tp
->full_duplex
= mii_duplex(tp
->full_duplex_lock
, negotiated
);
438 if (negotiated
& LPA_100
) new_csr6
&= ~TxThreshold
;
439 else new_csr6
|= TxThreshold
;
440 if (tp
->full_duplex
) new_csr6
|= FullDuplex
;
441 else new_csr6
&= ~FullDuplex
;
443 if (new_csr6
!= tp
->csr6
) {
445 tulip_restart_rxtx(tp
);
448 printk(KERN_INFO
"%s: Setting %s-duplex based on MII"
449 "#%d link partner capability of %4.4x.\n",
450 dev
->name
, tp
->full_duplex
? "full" : "half",
458 void __devinit
tulip_find_mii (struct net_device
*dev
, int board_idx
)
460 struct tulip_private
*tp
= netdev_priv(dev
);
461 int phyn
, phy_idx
= 0;
464 unsigned int to_advert
, new_bmcr
, ane_switch
;
466 /* Find the connected MII xcvrs.
467 Doing this in open() would allow detecting external xcvrs later,
468 but takes much time. */
469 for (phyn
= 1; phyn
<= 32 && phy_idx
< sizeof (tp
->phys
); phyn
++) {
470 int phy
= phyn
& 0x1f;
471 int mii_status
= tulip_mdio_read (dev
, phy
, MII_BMSR
);
472 if ((mii_status
& 0x8301) == 0x8001 ||
473 ((mii_status
& BMSR_100BASE4
) == 0
474 && (mii_status
& 0x7800) != 0)) {
475 /* preserve Becker logic, gain indentation level */
480 mii_reg0
= tulip_mdio_read (dev
, phy
, MII_BMCR
);
481 mii_advert
= tulip_mdio_read (dev
, phy
, MII_ADVERTISE
);
484 /* if not advertising at all, gen an
485 * advertising value from the capability
488 if ((mii_advert
& ADVERTISE_ALL
) == 0) {
489 unsigned int tmpadv
= tulip_mdio_read (dev
, phy
, MII_BMSR
);
490 mii_advert
= ((tmpadv
>> 6) & 0x3e0) | 1;
493 if (tp
->mii_advertise
) {
494 tp
->advertising
[phy_idx
] =
495 to_advert
= tp
->mii_advertise
;
496 } else if (tp
->advertising
[phy_idx
]) {
497 to_advert
= tp
->advertising
[phy_idx
];
499 tp
->advertising
[phy_idx
] =
501 to_advert
= mii_advert
;
504 tp
->phys
[phy_idx
++] = phy
;
506 printk (KERN_INFO
"tulip%d: MII transceiver #%d "
507 "config %4.4x status %4.4x advertising %4.4x.\n",
508 board_idx
, phy
, mii_reg0
, mii_status
, mii_advert
);
510 /* Fixup for DLink with miswired PHY. */
511 if (mii_advert
!= to_advert
) {
512 printk (KERN_DEBUG
"tulip%d: Advertising %4.4x on PHY %d,"
513 " previously advertising %4.4x.\n",
514 board_idx
, to_advert
, phy
, mii_advert
);
515 tulip_mdio_write (dev
, phy
, 4, to_advert
);
518 /* Enable autonegotiation: some boards default to off. */
519 if (tp
->default_port
== 0) {
520 new_bmcr
= mii_reg0
| BMCR_ANENABLE
;
521 if (new_bmcr
!= mii_reg0
) {
522 new_bmcr
|= BMCR_ANRESTART
;
526 /* ...or disable nway, if forcing media */
528 new_bmcr
= mii_reg0
& ~BMCR_ANENABLE
;
529 if (new_bmcr
!= mii_reg0
)
533 /* clear out bits we never want at this point */
534 new_bmcr
&= ~(BMCR_CTST
| BMCR_FULLDPLX
| BMCR_ISOLATE
|
535 BMCR_PDOWN
| BMCR_SPEED100
| BMCR_LOOPBACK
|
539 new_bmcr
|= BMCR_FULLDPLX
;
540 if (tulip_media_cap
[tp
->default_port
] & MediaIs100
)
541 new_bmcr
|= BMCR_SPEED100
;
543 if (new_bmcr
!= mii_reg0
) {
544 /* some phys need the ANE switch to
545 * happen before forced media settings
546 * will "take." However, we write the
547 * same value twice in order not to
548 * confuse the sane phys.
551 tulip_mdio_write (dev
, phy
, MII_BMCR
, new_bmcr
);
554 tulip_mdio_write (dev
, phy
, MII_BMCR
, new_bmcr
);
557 tp
->mii_cnt
= phy_idx
;
558 if (tp
->mtable
&& tp
->mtable
->has_mii
&& phy_idx
== 0) {
559 printk (KERN_INFO
"tulip%d: ***WARNING***: No MII transceiver found!\n",