include/asm-powerpc/irq.h

   1 #ifdef __KERNEL__
   2 #ifndef _ASM_POWERPC_IRQ_H
   3 #define _ASM_POWERPC_IRQ_H
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/config.h>
  13 #include <linux/threads.h>
  14 #include <linux/list.h>
  15 #include <linux/radix-tree.h>
  16
  17 #include <asm/types.h>
  18 #include <asm/atomic.h>
  19
  20
  21 #define get_irq_desc(irq) (&irq_desc[(irq)])
  22
  23 /* Define a way to iterate across irqs. */
  24 #define for_each_irq(i) \
  25         for ((i) = 0; (i) < NR_IRQS; ++(i))
  26
  27 extern atomic_t ppc_n_lost_interrupts;
  28
  29 #ifdef CONFIG_PPC_MERGE
  30
  31 /* This number is used when no interrupt has been assigned */
  32 #define NO_IRQ                  (0)
  33
  34 /* This is a special irq number to return from get_irq() to tell that
  35  * no interrupt happened _and_ ignore it (don't count it as bad). Some
  36  * platforms like iSeries rely on that.
  37  */
  38 #define NO_IRQ_IGNORE           ((unsigned int)-1)
  39
  40 /* Total number of virq in the platform (make it a CONFIG_* option ? */
  41 #define NR_IRQS         512
  42
  43 /* Number of irqs reserved for the legacy controller */
  44 #define NUM_ISA_INTERRUPTS      16
  45
  46 /* This type is the placeholder for a hardware interrupt number. It has to
  47  * be big enough to enclose whatever representation is used by a given
  48  * platform.
  49  */
  50 typedef unsigned long irq_hw_number_t;
  51
  52 /* Interrupt controller "host" data structure. This could be defined as a
  53  * irq domain controller. That is, it handles the mapping between hardware
  54  * and virtual interrupt numbers for a given interrupt domain. The host
  55  * structure is generally created by the PIC code for a given PIC instance
  56  * (though a host can cover more than one PIC if they have a flat number
  57  * model). It's the host callbacks that are responsible for setting the
  58  * irq_chip on a given irq_desc after it's been mapped.
  59  *
  60  * The host code and data structures are fairly agnostic to the fact that
  61  * we use an open firmware device-tree. We do have references to struct
  62  * device_node in two places: in irq_find_host() to find the host matching
  63  * a given interrupt controller node, and of course as an argument to its
  64  * counterpart host->ops->match() callback. However, those are treated as
  65  * generic pointers by the core and the fact that it's actually a device-node
  66  * pointer is purely a convention between callers and implementation. This
  67  * code could thus be used on other architectures by replacing those two
  68  * by some sort of arch-specific void * "token" used to identify interrupt
  69  * controllers.
  70  */
  71 struct irq_host;
  72 struct radix_tree_root;
  73
  74 /* Functions below are provided by the host and called whenever a new mapping
  75  * is created or an old mapping is disposed. The host can then proceed to
  76  * whatever internal data structures management is required. It also needs
  77  * to setup the irq_desc when returning from map().
  78  */
  79 struct irq_host_ops {
  80         /* Match an interrupt controller device node to a host, returns
  81          * 1 on a match
  82          */
  83         int (*match)(struct irq_host *h, struct device_node *node);
  84
  85         /* Create or update a mapping between a virtual irq number and a hw
  86          * irq number. This is called only once for a given mapping.
  87          */
  88         int (*map)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
  89
  90         /* Dispose of such a mapping */
  91         void (*unmap)(struct irq_host *h, unsigned int virq);
  92
  93         /* Translate device-tree interrupt specifier from raw format coming
  94          * from the firmware to a irq_hw_number_t (interrupt line number) and
  95          * type (sense) that can be passed to set_irq_type(). In the absence
  96          * of this callback, irq_create_of_mapping() and irq_of_parse_and_map()
  97          * will return the hw number in the first cell and IRQ_TYPE_NONE for
  98          * the type (which amount to keeping whatever default value the
  99          * interrupt controller has for that line)
 100          */
 101         int (*xlate)(struct irq_host *h, struct device_node *ctrler,
 102                      u32 *intspec, unsigned int intsize,
 103                      irq_hw_number_t *out_hwirq, unsigned int *out_type);
 104 };
 105
 106 struct irq_host {
 107         struct list_head        link;
 108
 109         /* type of reverse mapping technique */
 110         unsigned int            revmap_type;
 111 #define IRQ_HOST_MAP_LEGACY     0 /* legacy 8259, gets irqs 1..15 */
 112 #define IRQ_HOST_MAP_NOMAP      1 /* no fast reverse mapping */
 113 #define IRQ_HOST_MAP_LINEAR     2 /* linear map of interrupts */
 114 #define IRQ_HOST_MAP_TREE       3 /* radix tree */
 115         union {
 116                 struct {
 117                         unsigned int size;
 118                         unsigned int *revmap;
 119                 } linear;
 120                 struct radix_tree_root tree;
 121         } revmap_data;
 122         struct irq_host_ops     *ops;
 123         void                    *host_data;
 124         irq_hw_number_t         inval_irq;
 125 };
 126
 127 /* The main irq map itself is an array of NR_IRQ entries containing the
 128  * associate host and irq number. An entry with a host of NULL is free.
 129  * An entry can be allocated if it's free, the allocator always then sets
 130  * hwirq first to the host's invalid irq number and then fills ops.
 131  */
 132 struct irq_map_entry {
 133         irq_hw_number_t hwirq;
 134         struct irq_host *host;
 135 };
 136
 137 extern struct irq_map_entry irq_map[NR_IRQS];
 138
 139
 140 /***
 141  * irq_alloc_host - Allocate a new irq_host data structure
 142  * @node: device-tree node of the interrupt controller
 143  * @revmap_type: type of reverse mapping to use
 144  * @revmap_arg: for IRQ_HOST_MAP_LINEAR linear only: size of the map
 145  * @ops: map/unmap host callbacks
 146  * @inval_irq: provide a hw number in that host space that is always invalid
 147  *
 148  * Allocates and initialize and irq_host structure. Note that in the case of
 149  * IRQ_HOST_MAP_LEGACY, the map() callback will be called before this returns
 150  * for all legacy interrupts except 0 (which is always the invalid irq for
 151  * a legacy controller). For a IRQ_HOST_MAP_LINEAR, the map is allocated by
 152  * this call as well. For a IRQ_HOST_MAP_TREE, the radix tree will be allocated
 153  * later during boot automatically (the reverse mapping will use the slow path
 154  * until that happens).
 155  */
 156 extern struct irq_host *irq_alloc_host(unsigned int revmap_type,
 157                                        unsigned int revmap_arg,
 158                                        struct irq_host_ops *ops,
 159                                        irq_hw_number_t inval_irq);
 160
 161
 162 /***
 163  * irq_find_host - Locates a host for a given device node
 164  * @node: device-tree node of the interrupt controller
 165  */
 166 extern struct irq_host *irq_find_host(struct device_node *node);
 167
 168
 169 /***
 170  * irq_set_default_host - Set a "default" host
 171  * @host: default host pointer
 172  *
 173  * For convenience, it's possible to set a "default" host that will be used
 174  * whenever NULL is passed to irq_create_mapping(). It makes life easier for
 175  * platforms that want to manipulate a few hard coded interrupt numbers that
 176  * aren't properly represented in the device-tree.
 177  */
 178 extern void irq_set_default_host(struct irq_host *host);
 179
 180
 181 /***
 182  * irq_set_virq_count - Set the maximum number of virt irqs
 183  * @count: number of linux virtual irqs, capped with NR_IRQS
 184  *
 185  * This is mainly for use by platforms like iSeries who want to program
 186  * the virtual irq number in the controller to avoid the reverse mapping
 187  */
 188 extern void irq_set_virq_count(unsigned int count);
 189
 190
 191 /***
 192  * irq_create_mapping - Map a hardware interrupt into linux virq space
 193  * @host: host owning this hardware interrupt or NULL for default host
 194  * @hwirq: hardware irq number in that host space
 195  *
 196  * Only one mapping per hardware interrupt is permitted. Returns a linux
 197  * virq number.
 198  * If the sense/trigger is to be specified, set_irq_type() should be called
 199  * on the number returned from that call.
 200  */
 201 extern unsigned int irq_create_mapping(struct irq_host *host,
 202                                        irq_hw_number_t hwirq);
 203
 204
 205 /***
 206  * irq_dispose_mapping - Unmap an interrupt
 207  * @virq: linux virq number of the interrupt to unmap
 208  */
 209 extern void irq_dispose_mapping(unsigned int virq);
 210
 211 /***
 212  * irq_find_mapping - Find a linux virq from an hw irq number.
 213  * @host: host owning this hardware interrupt
 214  * @hwirq: hardware irq number in that host space
 215  *
 216  * This is a slow path, for use by generic code. It's expected that an
 217  * irq controller implementation directly calls the appropriate low level
 218  * mapping function.
 219  */
 220 extern unsigned int irq_find_mapping(struct irq_host *host,
 221                                      irq_hw_number_t hwirq);
 222
 223
 224 /***
 225  * irq_radix_revmap - Find a linux virq from a hw irq number.
 226  * @host: host owning this hardware interrupt
 227  * @hwirq: hardware irq number in that host space
 228  *
 229  * This is a fast path, for use by irq controller code that uses radix tree
 230  * revmaps
 231  */
 232 extern unsigned int irq_radix_revmap(struct irq_host *host,
 233                                      irq_hw_number_t hwirq);
 234
 235 /***
 236  * irq_linear_revmap - Find a linux virq from a hw irq number.
 237  * @host: host owning this hardware interrupt
 238  * @hwirq: hardware irq number in that host space
 239  *
 240  * This is a fast path, for use by irq controller code that uses linear
 241  * revmaps. It does fallback to the slow path if the revmap doesn't exist
 242  * yet and will create the revmap entry with appropriate locking
 243  */
 244
 245 extern unsigned int irq_linear_revmap(struct irq_host *host,
 246                                       irq_hw_number_t hwirq);
 247
 248
 249
 250 /***
 251  * irq_alloc_virt - Allocate virtual irq numbers
 252  * @host: host owning these new virtual irqs
 253  * @count: number of consecutive numbers to allocate
 254  * @hint: pass a hint number, the allocator will try to use a 1:1 mapping
 255  *
 256  * This is a low level function that is used internally by irq_create_mapping()
 257  * and that can be used by some irq controllers implementations for things
 258  * like allocating ranges of numbers for MSIs. The revmaps are left untouched.
 259  */
 260 extern unsigned int irq_alloc_virt(struct irq_host *host,
 261                                    unsigned int count,
 262                                    unsigned int hint);
 263
 264 /***
 265  * irq_free_virt - Free virtual irq numbers
 266  * @virq: virtual irq number of the first interrupt to free
 267  * @count: number of interrupts to free
 268  *
 269  * This function is the opposite of irq_alloc_virt. It will not clear reverse
 270  * maps, this should be done previously by unmap'ing the interrupt. In fact,
 271  * all interrupts covered by the range being freed should have been unmapped
 272  * prior to calling this.
 273  */
 274 extern void irq_free_virt(unsigned int virq, unsigned int count);
 275
 276
 277 /* -- OF helpers -- */
 278
 279 /* irq_create_of_mapping - Map a hardware interrupt into linux virq space
 280  * @controller: Device node of the interrupt controller
 281  * @inspec: Interrupt specifier from the device-tree
 282  * @intsize: Size of the interrupt specifier from the device-tree
 283  *
 284  * This function is identical to irq_create_mapping except that it takes
 285  * as input informations straight from the device-tree (typically the results
 286  * of the of_irq_map_*() functions.
 287  */
 288 extern unsigned int irq_create_of_mapping(struct device_node *controller,
 289                                           u32 *intspec, unsigned int intsize);
 290
 291
 292 /* irq_of_parse_and_map - Parse nad Map an interrupt into linux virq space
 293  * @device: Device node of the device whose interrupt is to be mapped
 294  * @index: Index of the interrupt to map
 295  *
 296  * This function is a wrapper that chains of_irq_map_one() and
 297  * irq_create_of_mapping() to make things easier to callers
 298  */
 299 extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index);
 300
 301 /* -- End OF helpers -- */
 302
 303 /***
 304  * irq_early_init - Init irq remapping subsystem
 305  */
 306 extern void irq_early_init(void);
 307
 308 static __inline__ int irq_canonicalize(int irq)
 309 {
 310         return irq;
 311 }
 312
 313
 314 #else /* CONFIG_PPC_MERGE */
 315
 316 /* This number is used when no interrupt has been assigned */
 317 #define NO_IRQ                  (-1)
 318 #define NO_IRQ_IGNORE           (-2)
 319
 320
 321 /*
 322  * These constants are used for passing information about interrupt
 323  * signal polarity and level/edge sensing to the low-level PIC chip
 324  * drivers.
 325  */
 326 #define IRQ_SENSE_MASK          0x1
 327 #define IRQ_SENSE_LEVEL         0x1     /* interrupt on active level */
 328 #define IRQ_SENSE_EDGE          0x0     /* interrupt triggered by edge */
 329
 330 #define IRQ_POLARITY_MASK       0x2
 331 #define IRQ_POLARITY_POSITIVE   0x2     /* high level or low->high edge */
 332 #define IRQ_POLARITY_NEGATIVE   0x0     /* low level or high->low edge */
 333
 334
 335 #if defined(CONFIG_40x)
 336 #include <asm/ibm4xx.h>
 337
 338 #ifndef NR_BOARD_IRQS
 339 #define NR_BOARD_IRQS 0
 340 #endif
 341
 342 #ifndef UIC_WIDTH /* Number of interrupts per device */
 343 #define UIC_WIDTH 32
 344 #endif
 345
 346 #ifndef NR_UICS /* number  of UIC devices */
 347 #define NR_UICS 1
 348 #endif
 349
 350 #if defined (CONFIG_403)
 351 /*
 352  * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
 353  * 32 possible interrupts, a majority of which are not implemented on
 354  * all cores. There are six configurable, external interrupt pins and
 355  * there are eight internal interrupts for the on-chip serial port
 356  * (SPU), DMA controller, and JTAG controller.
 357  *
 358  */
 359
 360 #define NR_AIC_IRQS 32
 361 #define NR_IRQS  (NR_AIC_IRQS + NR_BOARD_IRQS)
 362
 363 #elif !defined (CONFIG_403)
 364
 365 /*
 366  *  The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
 367  * possible interrupts as well. There are seven, configurable external
 368  * interrupt pins and there are 17 internal interrupts for the on-chip
 369  * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
 370  *
 371  */
 372
 373
 374 #define NR_UIC_IRQS UIC_WIDTH
 375 #define NR_IRQS         ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
 376 #endif
 377
 378 #elif defined(CONFIG_44x)
 379 #include <asm/ibm44x.h>
 380
 381 #define NR_UIC_IRQS     32
 382 #define NR_IRQS         ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
 383
 384 #elif defined(CONFIG_8xx)
 385
 386 /* Now include the board configuration specific associations.
 387 */
 388 #include <asm/mpc8xx.h>
 389
 390 /* The MPC8xx cores have 16 possible interrupts.  There are eight
 391  * possible level sensitive interrupts assigned and generated internally
 392  * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
 393  * There are eight external interrupts (IRQs) that can be configured
 394  * as either level or edge sensitive.
 395  *
 396  * On some implementations, there is also the possibility of an 8259
 397  * through the PCI and PCI-ISA bridges.
 398  *
 399  * We are "flattening" the interrupt vectors of the cascaded CPM
 400  * and 8259 interrupt controllers so that we can uniquely identify
 401  * any interrupt source with a single integer.
 402  */
 403 #define NR_SIU_INTS     16
 404 #define NR_CPM_INTS     32
 405 #ifndef NR_8259_INTS
 406 #define NR_8259_INTS 0
 407 #endif
 408
 409 #define SIU_IRQ_OFFSET          0
 410 #define CPM_IRQ_OFFSET          (SIU_IRQ_OFFSET + NR_SIU_INTS)
 411 #define I8259_IRQ_OFFSET        (CPM_IRQ_OFFSET + NR_CPM_INTS)
 412
 413 #define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
 414
 415 /* These values must be zero-based and map 1:1 with the SIU configuration.
 416  * They are used throughout the 8xx I/O subsystem to generate
 417  * interrupt masks, flags, and other control patterns.  This is why the
 418  * current kernel assumption of the 8259 as the base controller is such
 419  * a pain in the butt.
 420  */
 421 #define SIU_IRQ0        (0)     /* Highest priority */
 422 #define SIU_LEVEL0      (1)
 423 #define SIU_IRQ1        (2)
 424 #define SIU_LEVEL1      (3)
 425 #define SIU_IRQ2        (4)
 426 #define SIU_LEVEL2      (5)
 427 #define SIU_IRQ3        (6)
 428 #define SIU_LEVEL3      (7)
 429 #define SIU_IRQ4        (8)
 430 #define SIU_LEVEL4      (9)
 431 #define SIU_IRQ5        (10)
 432 #define SIU_LEVEL5      (11)
 433 #define SIU_IRQ6        (12)
 434 #define SIU_LEVEL6      (13)
 435 #define SIU_IRQ7        (14)
 436 #define SIU_LEVEL7      (15)
 437
 438 #define MPC8xx_INT_FEC1         SIU_LEVEL1
 439 #define MPC8xx_INT_FEC2         SIU_LEVEL3
 440
 441 #define MPC8xx_INT_SCC1         (CPM_IRQ_OFFSET + CPMVEC_SCC1)
 442 #define MPC8xx_INT_SCC2         (CPM_IRQ_OFFSET + CPMVEC_SCC2)
 443 #define MPC8xx_INT_SCC3         (CPM_IRQ_OFFSET + CPMVEC_SCC3)
 444 #define MPC8xx_INT_SCC4         (CPM_IRQ_OFFSET + CPMVEC_SCC4)
 445 #define MPC8xx_INT_SMC1         (CPM_IRQ_OFFSET + CPMVEC_SMC1)
 446 #define MPC8xx_INT_SMC2         (CPM_IRQ_OFFSET + CPMVEC_SMC2)
 447
 448 /* The internal interrupts we can configure as we see fit.
 449  * My personal preference is CPM at level 2, which puts it above the
 450  * MBX PCI/ISA/IDE interrupts.
 451  */
 452 #ifndef PIT_INTERRUPT
 453 #define PIT_INTERRUPT           SIU_LEVEL0
 454 #endif
 455 #ifndef CPM_INTERRUPT
 456 #define CPM_INTERRUPT           SIU_LEVEL2
 457 #endif
 458 #ifndef PCMCIA_INTERRUPT
 459 #define PCMCIA_INTERRUPT        SIU_LEVEL6
 460 #endif
 461 #ifndef DEC_INTERRUPT
 462 #define DEC_INTERRUPT           SIU_LEVEL7
 463 #endif
 464
 465 /* Some internal interrupt registers use an 8-bit mask for the interrupt
 466  * level instead of a number.
 467  */
 468 #define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
 469
 470 #elif defined(CONFIG_83xx)
 471 #include <asm/mpc83xx.h>
 472
 473 #define NR_IRQS (NR_IPIC_INTS)
 474
 475 #elif defined(CONFIG_85xx)
 476 /* Now include the board configuration specific associations.
 477 */
 478 #include <asm/mpc85xx.h>
 479
 480 /* The MPC8548 openpic has 48 internal interrupts and 12 external
 481  * interrupts.
 482  *
 483  * We are "flattening" the interrupt vectors of the cascaded CPM
 484  * so that we can uniquely identify any interrupt source with a
 485  * single integer.
 486  */
 487 #define NR_CPM_INTS     64
 488 #define NR_EPIC_INTS    60
 489 #ifndef NR_8259_INTS
 490 #define NR_8259_INTS    0
 491 #endif
 492 #define NUM_8259_INTERRUPTS NR_8259_INTS
 493
 494 #ifndef CPM_IRQ_OFFSET
 495 #define CPM_IRQ_OFFSET  0
 496 #endif
 497
 498 #define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
 499
 500 /* Internal IRQs on MPC85xx OpenPIC */
 501
 502 #ifndef MPC85xx_OPENPIC_IRQ_OFFSET
 503 #ifdef CONFIG_CPM2
 504 #define MPC85xx_OPENPIC_IRQ_OFFSET      (CPM_IRQ_OFFSET + NR_CPM_INTS)
 505 #else
 506 #define MPC85xx_OPENPIC_IRQ_OFFSET      0
 507 #endif
 508 #endif
 509
 510 /* Not all of these exist on all MPC85xx implementations */
 511 #define MPC85xx_IRQ_L2CACHE     ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
 512 #define MPC85xx_IRQ_ECM         ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
 513 #define MPC85xx_IRQ_DDR         ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
 514 #define MPC85xx_IRQ_LBIU        ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
 515 #define MPC85xx_IRQ_DMA0        ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
 516 #define MPC85xx_IRQ_DMA1        ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
 517 #define MPC85xx_IRQ_DMA2        ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
 518 #define MPC85xx_IRQ_DMA3        ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
 519 #define MPC85xx_IRQ_PCI1        ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
 520 #define MPC85xx_IRQ_PCI2        ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
 521 #define MPC85xx_IRQ_RIO_ERROR   ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
 522 #define MPC85xx_IRQ_RIO_BELL    (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
 523 #define MPC85xx_IRQ_RIO_TX      (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
 524 #define MPC85xx_IRQ_RIO_RX      (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
 525 #define MPC85xx_IRQ_TSEC1_TX    (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
 526 #define MPC85xx_IRQ_TSEC1_RX    (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
 527 #define MPC85xx_IRQ_TSEC3_TX    (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
 528 #define MPC85xx_IRQ_TSEC3_RX    (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
 529 #define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
 530 #define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
 531 #define MPC85xx_IRQ_TSEC2_TX    (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
 532 #define MPC85xx_IRQ_TSEC2_RX    (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
 533 #define MPC85xx_IRQ_TSEC4_TX    (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
 534 #define MPC85xx_IRQ_TSEC4_RX    (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
 535 #define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
 536 #define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
 537 #define MPC85xx_IRQ_FEC         (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
 538 #define MPC85xx_IRQ_DUART       (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
 539 #define MPC85xx_IRQ_IIC1        (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
 540 #define MPC85xx_IRQ_PERFMON     (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
 541 #define MPC85xx_IRQ_SEC2        (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
 542 #define MPC85xx_IRQ_CPM         (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
 543
 544 /* The 12 external interrupt lines */
 545 #define MPC85xx_IRQ_EXT0        (48 + MPC85xx_OPENPIC_IRQ_OFFSET)
 546 #define MPC85xx_IRQ_EXT1        (49 + MPC85xx_OPENPIC_IRQ_OFFSET)
 547 #define MPC85xx_IRQ_EXT2        (50 + MPC85xx_OPENPIC_IRQ_OFFSET)
 548 #define MPC85xx_IRQ_EXT3        (51 + MPC85xx_OPENPIC_IRQ_OFFSET)
 549 #define MPC85xx_IRQ_EXT4        (52 + MPC85xx_OPENPIC_IRQ_OFFSET)
 550 #define MPC85xx_IRQ_EXT5        (53 + MPC85xx_OPENPIC_IRQ_OFFSET)
 551 #define MPC85xx_IRQ_EXT6        (54 + MPC85xx_OPENPIC_IRQ_OFFSET)
 552 #define MPC85xx_IRQ_EXT7        (55 + MPC85xx_OPENPIC_IRQ_OFFSET)
 553 #define MPC85xx_IRQ_EXT8        (56 + MPC85xx_OPENPIC_IRQ_OFFSET)
 554 #define MPC85xx_IRQ_EXT9        (57 + MPC85xx_OPENPIC_IRQ_OFFSET)
 555 #define MPC85xx_IRQ_EXT10       (58 + MPC85xx_OPENPIC_IRQ_OFFSET)
 556 #define MPC85xx_IRQ_EXT11       (59 + MPC85xx_OPENPIC_IRQ_OFFSET)
 557
 558 /* CPM related interrupts */
 559 #define SIU_INT_ERROR           ((uint)0x00+CPM_IRQ_OFFSET)
 560 #define SIU_INT_I2C             ((uint)0x01+CPM_IRQ_OFFSET)
 561 #define SIU_INT_SPI             ((uint)0x02+CPM_IRQ_OFFSET)
 562 #define SIU_INT_RISC            ((uint)0x03+CPM_IRQ_OFFSET)
 563 #define SIU_INT_SMC1            ((uint)0x04+CPM_IRQ_OFFSET)
 564 #define SIU_INT_SMC2            ((uint)0x05+CPM_IRQ_OFFSET)
 565 #define SIU_INT_USB             ((uint)0x0b+CPM_IRQ_OFFSET)
 566 #define SIU_INT_TIMER1          ((uint)0x0c+CPM_IRQ_OFFSET)
 567 #define SIU_INT_TIMER2          ((uint)0x0d+CPM_IRQ_OFFSET)
 568 #define SIU_INT_TIMER3          ((uint)0x0e+CPM_IRQ_OFFSET)
 569 #define SIU_INT_TIMER4          ((uint)0x0f+CPM_IRQ_OFFSET)
 570 #define SIU_INT_FCC1            ((uint)0x20+CPM_IRQ_OFFSET)
 571 #define SIU_INT_FCC2            ((uint)0x21+CPM_IRQ_OFFSET)
 572 #define SIU_INT_FCC3            ((uint)0x22+CPM_IRQ_OFFSET)
 573 #define SIU_INT_MCC1            ((uint)0x24+CPM_IRQ_OFFSET)
 574 #define SIU_INT_MCC2            ((uint)0x25+CPM_IRQ_OFFSET)
 575 #define SIU_INT_SCC1            ((uint)0x28+CPM_IRQ_OFFSET)
 576 #define SIU_INT_SCC2            ((uint)0x29+CPM_IRQ_OFFSET)
 577 #define SIU_INT_SCC3            ((uint)0x2a+CPM_IRQ_OFFSET)
 578 #define SIU_INT_SCC4            ((uint)0x2b+CPM_IRQ_OFFSET)
 579 #define SIU_INT_PC15            ((uint)0x30+CPM_IRQ_OFFSET)
 580 #define SIU_INT_PC14            ((uint)0x31+CPM_IRQ_OFFSET)
 581 #define SIU_INT_PC13            ((uint)0x32+CPM_IRQ_OFFSET)
 582 #define SIU_INT_PC12            ((uint)0x33+CPM_IRQ_OFFSET)
 583 #define SIU_INT_PC11            ((uint)0x34+CPM_IRQ_OFFSET)
 584 #define SIU_INT_PC10            ((uint)0x35+CPM_IRQ_OFFSET)
 585 #define SIU_INT_PC9             ((uint)0x36+CPM_IRQ_OFFSET)
 586 #define SIU_INT_PC8             ((uint)0x37+CPM_IRQ_OFFSET)
 587 #define SIU_INT_PC7             ((uint)0x38+CPM_IRQ_OFFSET)
 588 #define SIU_INT_PC6             ((uint)0x39+CPM_IRQ_OFFSET)
 589 #define SIU_INT_PC5             ((uint)0x3a+CPM_IRQ_OFFSET)
 590 #define SIU_INT_PC4             ((uint)0x3b+CPM_IRQ_OFFSET)
 591 #define SIU_INT_PC3             ((uint)0x3c+CPM_IRQ_OFFSET)
 592 #define SIU_INT_PC2             ((uint)0x3d+CPM_IRQ_OFFSET)
 593 #define SIU_INT_PC1             ((uint)0x3e+CPM_IRQ_OFFSET)
 594 #define SIU_INT_PC0             ((uint)0x3f+CPM_IRQ_OFFSET)
 595
 596 #elif defined(CONFIG_PPC_86xx)
 597 #include <asm/mpc86xx.h>
 598
 599 #define NR_EPIC_INTS 48
 600 #ifndef NR_8259_INTS
 601 #define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */
 602 #endif
 603 #define NUM_8259_INTERRUPTS NR_8259_INTS
 604
 605 #ifndef I8259_OFFSET
 606 #define I8259_OFFSET 0
 607 #endif
 608
 609 #define NR_IRQS 256
 610
 611 /* Internal IRQs on MPC86xx OpenPIC */
 612
 613 #ifndef MPC86xx_OPENPIC_IRQ_OFFSET
 614 #define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
 615 #endif
 616
 617 /* The 48 internal sources */
 618 #define MPC86xx_IRQ_NULL        ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET)
 619 #define MPC86xx_IRQ_MCM         ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET)
 620 #define MPC86xx_IRQ_DDR         ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET)
 621 #define MPC86xx_IRQ_LBC         ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET)
 622 #define MPC86xx_IRQ_DMA0        ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET)
 623 #define MPC86xx_IRQ_DMA1        ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET)
 624 #define MPC86xx_IRQ_DMA2        ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET)
 625 #define MPC86xx_IRQ_DMA3        ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET)
 626
 627 /* no 10,11 */
 628 #define MPC86xx_IRQ_UART2       (12 + MPC86xx_OPENPIC_IRQ_OFFSET)
 629 #define MPC86xx_IRQ_TSEC1_TX    (13 + MPC86xx_OPENPIC_IRQ_OFFSET)
 630 #define MPC86xx_IRQ_TSEC1_RX    (14 + MPC86xx_OPENPIC_IRQ_OFFSET)
 631 #define MPC86xx_IRQ_TSEC3_TX    (15 + MPC86xx_OPENPIC_IRQ_OFFSET)
 632 #define MPC86xx_IRQ_TSEC3_RX    (16 + MPC86xx_OPENPIC_IRQ_OFFSET)
 633 #define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET)
 634 #define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET)
 635 #define MPC86xx_IRQ_TSEC2_TX    (19 + MPC86xx_OPENPIC_IRQ_OFFSET)
 636 #define MPC86xx_IRQ_TSEC2_RX    (20 + MPC86xx_OPENPIC_IRQ_OFFSET)
 637 #define MPC86xx_IRQ_TSEC4_TX    (21 + MPC86xx_OPENPIC_IRQ_OFFSET)
 638 #define MPC86xx_IRQ_TSEC4_RX    (22 + MPC86xx_OPENPIC_IRQ_OFFSET)
 639 #define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET)
 640 #define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET)
 641 /* no 25 */
 642 #define MPC86xx_IRQ_UART1       (26 + MPC86xx_OPENPIC_IRQ_OFFSET)
 643 #define MPC86xx_IRQ_IIC         (27 + MPC86xx_OPENPIC_IRQ_OFFSET)
 644 #define MPC86xx_IRQ_PERFMON       (28 + MPC86xx_OPENPIC_IRQ_OFFSET)
 645 /* no 29,30,31 */
 646 #define MPC86xx_IRQ_SRIO_ERROR    (32 + MPC86xx_OPENPIC_IRQ_OFFSET)
 647 #define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET)
 648 #define MPC86xx_IRQ_SRIO_IN_BELL  (34 + MPC86xx_OPENPIC_IRQ_OFFSET)
 649 /* no 35,36 */
 650 #define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET)
 651 #define MPC86xx_IRQ_SRIO_IN_MSG1  (38 + MPC86xx_OPENPIC_IRQ_OFFSET)
 652 #define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET)
 653 #define MPC86xx_IRQ_SRIO_IN_MSG2  (40 + MPC86xx_OPENPIC_IRQ_OFFSET)
 654
 655 /* The 12 external interrupt lines */
 656 #define MPC86xx_IRQ_EXT_BASE    48
 657 #define MPC86xx_IRQ_EXT0        (0 + MPC86xx_IRQ_EXT_BASE \
 658                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 659 #define MPC86xx_IRQ_EXT1        (1 + MPC86xx_IRQ_EXT_BASE \
 660                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 661 #define MPC86xx_IRQ_EXT2        (2 + MPC86xx_IRQ_EXT_BASE \
 662                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 663 #define MPC86xx_IRQ_EXT3        (3 + MPC86xx_IRQ_EXT_BASE \
 664                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 665 #define MPC86xx_IRQ_EXT4        (4 + MPC86xx_IRQ_EXT_BASE \
 666                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 667 #define MPC86xx_IRQ_EXT5        (5 + MPC86xx_IRQ_EXT_BASE \
 668                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 669 #define MPC86xx_IRQ_EXT6        (6 + MPC86xx_IRQ_EXT_BASE \
 670                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 671 #define MPC86xx_IRQ_EXT7        (7 + MPC86xx_IRQ_EXT_BASE \
 672                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 673 #define MPC86xx_IRQ_EXT8        (8 + MPC86xx_IRQ_EXT_BASE \
 674                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 675 #define MPC86xx_IRQ_EXT9        (9 + MPC86xx_IRQ_EXT_BASE \
 676                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 677 #define MPC86xx_IRQ_EXT10       (10 + MPC86xx_IRQ_EXT_BASE \
 678                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 679 #define MPC86xx_IRQ_EXT11       (11 + MPC86xx_IRQ_EXT_BASE \
 680                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 681
 682 #else /* CONFIG_40x + CONFIG_8xx */
 683 /*
 684  * this is the # irq's for all ppc arch's (pmac/chrp/prep)
 685  * so it is the max of them all
 686  */
 687 #define NR_IRQS                 256
 688 #define __DO_IRQ_CANON  1
 689
 690 #ifndef CONFIG_8260
 691
 692 #define NUM_8259_INTERRUPTS     16
 693
 694 #else /* CONFIG_8260 */
 695
 696 /* The 8260 has an internal interrupt controller with a maximum of
 697  * 64 IRQs.  We will use NR_IRQs from above since it is large enough.
 698  * Don't be confused by the 8260 documentation where they list an
 699  * "interrupt number" and "interrupt vector".  We are only interested
 700  * in the interrupt vector.  There are "reserved" holes where the
 701  * vector number increases, but the interrupt number in the table does not.
 702  * (Document errata updates have fixed this...make sure you have up to
 703  * date processor documentation -- Dan).
 704  */
 705
 706 #ifndef CPM_IRQ_OFFSET
 707 #define CPM_IRQ_OFFSET  0
 708 #endif
 709
 710 #define NR_CPM_INTS     64
 711
 712 #define SIU_INT_ERROR           ((uint)0x00 + CPM_IRQ_OFFSET)
 713 #define SIU_INT_I2C             ((uint)0x01 + CPM_IRQ_OFFSET)
 714 #define SIU_INT_SPI             ((uint)0x02 + CPM_IRQ_OFFSET)
 715 #define SIU_INT_RISC            ((uint)0x03 + CPM_IRQ_OFFSET)
 716 #define SIU_INT_SMC1            ((uint)0x04 + CPM_IRQ_OFFSET)
 717 #define SIU_INT_SMC2            ((uint)0x05 + CPM_IRQ_OFFSET)
 718 #define SIU_INT_IDMA1           ((uint)0x06 + CPM_IRQ_OFFSET)
 719 #define SIU_INT_IDMA2           ((uint)0x07 + CPM_IRQ_OFFSET)
 720 #define SIU_INT_IDMA3           ((uint)0x08 + CPM_IRQ_OFFSET)
 721 #define SIU_INT_IDMA4           ((uint)0x09 + CPM_IRQ_OFFSET)
 722 #define SIU_INT_SDMA            ((uint)0x0a + CPM_IRQ_OFFSET)
 723 #define SIU_INT_USB             ((uint)0x0b + CPM_IRQ_OFFSET)
 724 #define SIU_INT_TIMER1          ((uint)0x0c + CPM_IRQ_OFFSET)
 725 #define SIU_INT_TIMER2          ((uint)0x0d + CPM_IRQ_OFFSET)
 726 #define SIU_INT_TIMER3          ((uint)0x0e + CPM_IRQ_OFFSET)
 727 #define SIU_INT_TIMER4          ((uint)0x0f + CPM_IRQ_OFFSET)
 728 #define SIU_INT_TMCNT           ((uint)0x10 + CPM_IRQ_OFFSET)
 729 #define SIU_INT_PIT             ((uint)0x11 + CPM_IRQ_OFFSET)
 730 #define SIU_INT_PCI             ((uint)0x12 + CPM_IRQ_OFFSET)
 731 #define SIU_INT_IRQ1            ((uint)0x13 + CPM_IRQ_OFFSET)
 732 #define SIU_INT_IRQ2            ((uint)0x14 + CPM_IRQ_OFFSET)
 733 #define SIU_INT_IRQ3            ((uint)0x15 + CPM_IRQ_OFFSET)
 734 #define SIU_INT_IRQ4            ((uint)0x16 + CPM_IRQ_OFFSET)
 735 #define SIU_INT_IRQ5            ((uint)0x17 + CPM_IRQ_OFFSET)
 736 #define SIU_INT_IRQ6            ((uint)0x18 + CPM_IRQ_OFFSET)
 737 #define SIU_INT_IRQ7            ((uint)0x19 + CPM_IRQ_OFFSET)
 738 #define SIU_INT_FCC1            ((uint)0x20 + CPM_IRQ_OFFSET)
 739 #define SIU_INT_FCC2            ((uint)0x21 + CPM_IRQ_OFFSET)
 740 #define SIU_INT_FCC3            ((uint)0x22 + CPM_IRQ_OFFSET)
 741 #define SIU_INT_MCC1            ((uint)0x24 + CPM_IRQ_OFFSET)
 742 #define SIU_INT_MCC2            ((uint)0x25 + CPM_IRQ_OFFSET)
 743 #define SIU_INT_SCC1            ((uint)0x28 + CPM_IRQ_OFFSET)
 744 #define SIU_INT_SCC2            ((uint)0x29 + CPM_IRQ_OFFSET)
 745 #define SIU_INT_SCC3            ((uint)0x2a + CPM_IRQ_OFFSET)
 746 #define SIU_INT_SCC4            ((uint)0x2b + CPM_IRQ_OFFSET)
 747 #define SIU_INT_PC15            ((uint)0x30 + CPM_IRQ_OFFSET)
 748 #define SIU_INT_PC14            ((uint)0x31 + CPM_IRQ_OFFSET)
 749 #define SIU_INT_PC13            ((uint)0x32 + CPM_IRQ_OFFSET)
 750 #define SIU_INT_PC12            ((uint)0x33 + CPM_IRQ_OFFSET)
 751 #define SIU_INT_PC11            ((uint)0x34 + CPM_IRQ_OFFSET)
 752 #define SIU_INT_PC10            ((uint)0x35 + CPM_IRQ_OFFSET)
 753 #define SIU_INT_PC9             ((uint)0x36 + CPM_IRQ_OFFSET)
 754 #define SIU_INT_PC8             ((uint)0x37 + CPM_IRQ_OFFSET)
 755 #define SIU_INT_PC7             ((uint)0x38 + CPM_IRQ_OFFSET)
 756 #define SIU_INT_PC6             ((uint)0x39 + CPM_IRQ_OFFSET)
 757 #define SIU_INT_PC5             ((uint)0x3a + CPM_IRQ_OFFSET)
 758 #define SIU_INT_PC4             ((uint)0x3b + CPM_IRQ_OFFSET)
 759 #define SIU_INT_PC3             ((uint)0x3c + CPM_IRQ_OFFSET)
 760 #define SIU_INT_PC2             ((uint)0x3d + CPM_IRQ_OFFSET)
 761 #define SIU_INT_PC1             ((uint)0x3e + CPM_IRQ_OFFSET)
 762 #define SIU_INT_PC0             ((uint)0x3f + CPM_IRQ_OFFSET)
 763
 764 #endif /* CONFIG_8260 */
 765
 766 #endif /* Whatever way too big #ifdef */
 767
 768 #define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
 769 /* pedantic: these are long because they are used with set_bit --RR */
 770 extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
 771
 772 /*
 773  * Because many systems have two overlapping names spaces for
 774  * interrupts (ISA and XICS for example), and the ISA interrupts
 775  * have historically not been easy to renumber, we allow ISA
 776  * interrupts to take values 0 - 15, and shift up the remaining
 777  * interrupts by 0x10.
 778  */
 779 #define NUM_ISA_INTERRUPTS      0x10
 780 extern int __irq_offset_value;
 781
 782 static inline int irq_offset_up(int irq)
 783 {
 784         return(irq + __irq_offset_value);
 785 }
 786
 787 static inline int irq_offset_down(int irq)
 788 {
 789         return(irq - __irq_offset_value);
 790 }
 791
 792 static inline int irq_offset_value(void)
 793 {
 794         return __irq_offset_value;
 795 }
 796
 797 #ifdef __DO_IRQ_CANON
 798 extern int ppc_do_canonicalize_irqs;
 799 #else
 800 #define ppc_do_canonicalize_irqs        0
 801 #endif
 802
 803 static __inline__ int irq_canonicalize(int irq)
 804 {
 805         if (ppc_do_canonicalize_irqs && irq == 2)
 806                 irq = 9;
 807         return irq;
 808 }
 809 #endif /* CONFIG_PPC_MERGE */
 810
 811 extern int distribute_irqs;
 812
 813 struct irqaction;
 814 struct pt_regs;
 815
 816 #define __ARCH_HAS_DO_SOFTIRQ
 817
 818 extern void __do_softirq(void);
 819
 820 #ifdef CONFIG_IRQSTACKS
 821 /*
 822  * Per-cpu stacks for handling hard and soft interrupts.
 823  */
 824 extern struct thread_info *hardirq_ctx[NR_CPUS];
 825 extern struct thread_info *softirq_ctx[NR_CPUS];
 826
 827 extern void irq_ctx_init(void);
 828 extern void call_do_softirq(struct thread_info *tp);
 829 extern int call_handle_irq(int irq, void *p1, void *p2,
 830                            struct thread_info *tp, void *func);
 831 #else
 832 #define irq_ctx_init()
 833
 834 #endif /* CONFIG_IRQSTACKS */
 835
 836 extern void do_IRQ(struct pt_regs *regs);
 837
 838 #endif /* _ASM_IRQ_H */
 839 #endif /* __KERNEL__ */